1 /* 2 * 3 * 4 * Copyright (C) 2005 Mike Isely <isely@pobox.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * 19 */ 20 21 #include <linux/errno.h> 22 #include <linux/string.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/firmware.h> 26 #include <linux/videodev2.h> 27 #include <media/v4l2-common.h> 28 #include <media/tuner.h> 29 #include "pvrusb2.h" 30 #include "pvrusb2-std.h" 31 #include "pvrusb2-util.h" 32 #include "pvrusb2-hdw.h" 33 #include "pvrusb2-i2c-core.h" 34 #include "pvrusb2-eeprom.h" 35 #include "pvrusb2-hdw-internal.h" 36 #include "pvrusb2-encoder.h" 37 #include "pvrusb2-debug.h" 38 #include "pvrusb2-fx2-cmd.h" 39 #include "pvrusb2-wm8775.h" 40 #include "pvrusb2-video-v4l.h" 41 #include "pvrusb2-cx2584x-v4l.h" 42 #include "pvrusb2-cs53l32a.h" 43 #include "pvrusb2-audio.h" 44 45 #define TV_MIN_FREQ 55250000L 46 #define TV_MAX_FREQ 850000000L 47 48 /* This defines a minimum interval that the decoder must remain quiet 49 before we are allowed to start it running. */ 50 #define TIME_MSEC_DECODER_WAIT 50 51 52 /* This defines a minimum interval that the decoder must be allowed to run 53 before we can safely begin using its streaming output. */ 54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300 55 56 /* This defines a minimum interval that the encoder must remain quiet 57 before we are allowed to configure it. */ 58 #define TIME_MSEC_ENCODER_WAIT 50 59 60 /* This defines the minimum interval that the encoder must successfully run 61 before we consider that the encoder has run at least once since its 62 firmware has been loaded. This measurement is in important for cases 63 where we can't do something until we know that the encoder has been run 64 at least once. */ 65 #define TIME_MSEC_ENCODER_OK 250 66 67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL}; 68 static DEFINE_MUTEX(pvr2_unit_mtx); 69 70 static int ctlchg; 71 static int procreload; 72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 }; 73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; 74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; 75 static int init_pause_msec; 76 77 module_param(ctlchg, int, S_IRUGO|S_IWUSR); 78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value"); 79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR); 80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay"); 81 module_param(procreload, int, S_IRUGO|S_IWUSR); 82 MODULE_PARM_DESC(procreload, 83 "Attempt init failure recovery with firmware reload"); 84 module_param_array(tuner, int, NULL, 0444); 85 MODULE_PARM_DESC(tuner,"specify installed tuner type"); 86 module_param_array(video_std, int, NULL, 0444); 87 MODULE_PARM_DESC(video_std,"specify initial video standard"); 88 module_param_array(tolerance, int, NULL, 0444); 89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance"); 90 91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */ 92 static int default_tv_freq = 61250000L; 93 /* 104.3 MHz, a usable FM station for my area */ 94 static int default_radio_freq = 104300000L; 95 96 module_param_named(tv_freq, default_tv_freq, int, 0444); 97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency"); 98 module_param_named(radio_freq, default_radio_freq, int, 0444); 99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency"); 100 101 #define PVR2_CTL_WRITE_ENDPOINT 0x01 102 #define PVR2_CTL_READ_ENDPOINT 0x81 103 104 #define PVR2_GPIO_IN 0x9008 105 #define PVR2_GPIO_OUT 0x900c 106 #define PVR2_GPIO_DIR 0x9020 107 108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__) 109 110 #define PVR2_FIRMWARE_ENDPOINT 0x02 111 112 /* size of a firmware chunk */ 113 #define FIRMWARE_CHUNK_SIZE 0x2000 114 115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *, 116 struct v4l2_subdev *); 117 118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = { 119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update, 120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update, 121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update, 122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update, 123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update, 124 }; 125 126 static const char *module_names[] = { 127 [PVR2_CLIENT_ID_MSP3400] = "msp3400", 128 [PVR2_CLIENT_ID_CX25840] = "cx25840", 129 [PVR2_CLIENT_ID_SAA7115] = "saa7115", 130 [PVR2_CLIENT_ID_TUNER] = "tuner", 131 [PVR2_CLIENT_ID_DEMOD] = "tuner", 132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a", 133 [PVR2_CLIENT_ID_WM8775] = "wm8775", 134 }; 135 136 137 static const unsigned char *module_i2c_addresses[] = { 138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63", 139 [PVR2_CLIENT_ID_DEMOD] = "\x43", 140 [PVR2_CLIENT_ID_MSP3400] = "\x40", 141 [PVR2_CLIENT_ID_SAA7115] = "\x21", 142 [PVR2_CLIENT_ID_WM8775] = "\x1b", 143 [PVR2_CLIENT_ID_CX25840] = "\x44", 144 [PVR2_CLIENT_ID_CS53L32A] = "\x11", 145 }; 146 147 148 static const char *ir_scheme_names[] = { 149 [PVR2_IR_SCHEME_NONE] = "none", 150 [PVR2_IR_SCHEME_29XXX] = "29xxx", 151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)", 152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)", 153 [PVR2_IR_SCHEME_ZILOG] = "Zilog", 154 }; 155 156 157 /* Define the list of additional controls we'll dynamically construct based 158 on query of the cx2341x module. */ 159 struct pvr2_mpeg_ids { 160 const char *strid; 161 int id; 162 }; 163 static const struct pvr2_mpeg_ids mpeg_ids[] = { 164 { 165 .strid = "audio_layer", 166 .id = V4L2_CID_MPEG_AUDIO_ENCODING, 167 },{ 168 .strid = "audio_bitrate", 169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE, 170 },{ 171 /* Already using audio_mode elsewhere :-( */ 172 .strid = "mpeg_audio_mode", 173 .id = V4L2_CID_MPEG_AUDIO_MODE, 174 },{ 175 .strid = "mpeg_audio_mode_extension", 176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION, 177 },{ 178 .strid = "audio_emphasis", 179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS, 180 },{ 181 .strid = "audio_crc", 182 .id = V4L2_CID_MPEG_AUDIO_CRC, 183 },{ 184 .strid = "video_aspect", 185 .id = V4L2_CID_MPEG_VIDEO_ASPECT, 186 },{ 187 .strid = "video_b_frames", 188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES, 189 },{ 190 .strid = "video_gop_size", 191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE, 192 },{ 193 .strid = "video_gop_closure", 194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, 195 },{ 196 .strid = "video_bitrate_mode", 197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE, 198 },{ 199 .strid = "video_bitrate", 200 .id = V4L2_CID_MPEG_VIDEO_BITRATE, 201 },{ 202 .strid = "video_bitrate_peak", 203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, 204 },{ 205 .strid = "video_temporal_decimation", 206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION, 207 },{ 208 .strid = "stream_type", 209 .id = V4L2_CID_MPEG_STREAM_TYPE, 210 },{ 211 .strid = "video_spatial_filter_mode", 212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE, 213 },{ 214 .strid = "video_spatial_filter", 215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER, 216 },{ 217 .strid = "video_luma_spatial_filter_type", 218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE, 219 },{ 220 .strid = "video_chroma_spatial_filter_type", 221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE, 222 },{ 223 .strid = "video_temporal_filter_mode", 224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE, 225 },{ 226 .strid = "video_temporal_filter", 227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER, 228 },{ 229 .strid = "video_median_filter_type", 230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE, 231 },{ 232 .strid = "video_luma_median_filter_top", 233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP, 234 },{ 235 .strid = "video_luma_median_filter_bottom", 236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM, 237 },{ 238 .strid = "video_chroma_median_filter_top", 239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP, 240 },{ 241 .strid = "video_chroma_median_filter_bottom", 242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM, 243 } 244 }; 245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids) 246 247 248 static const char *control_values_srate[] = { 249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz", 250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz", 251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz", 252 }; 253 254 255 256 static const char *control_values_input[] = { 257 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/ 258 [PVR2_CVAL_INPUT_DTV] = "dtv", 259 [PVR2_CVAL_INPUT_RADIO] = "radio", 260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video", 261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite", 262 }; 263 264 265 static const char *control_values_audiomode[] = { 266 [V4L2_TUNER_MODE_MONO] = "Mono", 267 [V4L2_TUNER_MODE_STEREO] = "Stereo", 268 [V4L2_TUNER_MODE_LANG1] = "Lang1", 269 [V4L2_TUNER_MODE_LANG2] = "Lang2", 270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2", 271 }; 272 273 274 static const char *control_values_hsm[] = { 275 [PVR2_CVAL_HSM_FAIL] = "Fail", 276 [PVR2_CVAL_HSM_HIGH] = "High", 277 [PVR2_CVAL_HSM_FULL] = "Full", 278 }; 279 280 281 static const char *pvr2_state_names[] = { 282 [PVR2_STATE_NONE] = "none", 283 [PVR2_STATE_DEAD] = "dead", 284 [PVR2_STATE_COLD] = "cold", 285 [PVR2_STATE_WARM] = "warm", 286 [PVR2_STATE_ERROR] = "error", 287 [PVR2_STATE_READY] = "ready", 288 [PVR2_STATE_RUN] = "run", 289 }; 290 291 292 struct pvr2_fx2cmd_descdef { 293 unsigned char id; 294 unsigned char *desc; 295 }; 296 297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = { 298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"}, 299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"}, 300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"}, 301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"}, 302 {FX2CMD_REG_WRITE, "write encoder register"}, 303 {FX2CMD_REG_READ, "read encoder register"}, 304 {FX2CMD_MEMSEL, "encoder memsel"}, 305 {FX2CMD_I2C_WRITE, "i2c write"}, 306 {FX2CMD_I2C_READ, "i2c read"}, 307 {FX2CMD_GET_USB_SPEED, "get USB speed"}, 308 {FX2CMD_STREAMING_ON, "stream on"}, 309 {FX2CMD_STREAMING_OFF, "stream off"}, 310 {FX2CMD_FWPOST1, "fwpost1"}, 311 {FX2CMD_POWER_OFF, "power off"}, 312 {FX2CMD_POWER_ON, "power on"}, 313 {FX2CMD_DEEP_RESET, "deep reset"}, 314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"}, 315 {FX2CMD_GET_IR_CODE, "get IR code"}, 316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"}, 317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"}, 318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"}, 319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"}, 320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"}, 321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"}, 322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"}, 323 }; 324 325 326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v); 327 static void pvr2_hdw_state_sched(struct pvr2_hdw *); 328 static int pvr2_hdw_state_eval(struct pvr2_hdw *); 329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long); 330 static void pvr2_hdw_worker_poll(struct work_struct *work); 331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state); 332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *); 333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *); 334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl); 335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw); 336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw); 337 static void pvr2_hdw_quiescent_timeout(unsigned long); 338 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long); 339 static void pvr2_hdw_encoder_wait_timeout(unsigned long); 340 static void pvr2_hdw_encoder_run_timeout(unsigned long); 341 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32); 342 static int pvr2_send_request_ex(struct pvr2_hdw *hdw, 343 unsigned int timeout,int probe_fl, 344 void *write_data,unsigned int write_len, 345 void *read_data,unsigned int read_len); 346 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw); 347 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw); 348 349 static void trace_stbit(const char *name,int val) 350 { 351 pvr2_trace(PVR2_TRACE_STBITS, 352 "State bit %s <-- %s", 353 name,(val ? "true" : "false")); 354 } 355 356 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp) 357 { 358 struct pvr2_hdw *hdw = cptr->hdw; 359 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) { 360 *vp = hdw->freqTable[hdw->freqProgSlot-1]; 361 } else { 362 *vp = 0; 363 } 364 return 0; 365 } 366 367 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v) 368 { 369 struct pvr2_hdw *hdw = cptr->hdw; 370 unsigned int slotId = hdw->freqProgSlot; 371 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) { 372 hdw->freqTable[slotId-1] = v; 373 /* Handle side effects correctly - if we're tuned to this 374 slot, then forgot the slot id relation since the stored 375 frequency has been changed. */ 376 if (hdw->freqSelector) { 377 if (hdw->freqSlotRadio == slotId) { 378 hdw->freqSlotRadio = 0; 379 } 380 } else { 381 if (hdw->freqSlotTelevision == slotId) { 382 hdw->freqSlotTelevision = 0; 383 } 384 } 385 } 386 return 0; 387 } 388 389 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp) 390 { 391 *vp = cptr->hdw->freqProgSlot; 392 return 0; 393 } 394 395 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v) 396 { 397 struct pvr2_hdw *hdw = cptr->hdw; 398 if ((v >= 0) && (v <= FREQTABLE_SIZE)) { 399 hdw->freqProgSlot = v; 400 } 401 return 0; 402 } 403 404 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp) 405 { 406 struct pvr2_hdw *hdw = cptr->hdw; 407 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision; 408 return 0; 409 } 410 411 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId) 412 { 413 unsigned freq = 0; 414 struct pvr2_hdw *hdw = cptr->hdw; 415 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0; 416 if (slotId > 0) { 417 freq = hdw->freqTable[slotId-1]; 418 if (!freq) return 0; 419 pvr2_hdw_set_cur_freq(hdw,freq); 420 } 421 if (hdw->freqSelector) { 422 hdw->freqSlotRadio = slotId; 423 } else { 424 hdw->freqSlotTelevision = slotId; 425 } 426 return 0; 427 } 428 429 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp) 430 { 431 *vp = pvr2_hdw_get_cur_freq(cptr->hdw); 432 return 0; 433 } 434 435 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr) 436 { 437 return cptr->hdw->freqDirty != 0; 438 } 439 440 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr) 441 { 442 cptr->hdw->freqDirty = 0; 443 } 444 445 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v) 446 { 447 pvr2_hdw_set_cur_freq(cptr->hdw,v); 448 return 0; 449 } 450 451 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left) 452 { 453 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 454 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 455 if (stat != 0) { 456 return stat; 457 } 458 *left = cap->bounds.left; 459 return 0; 460 } 461 462 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left) 463 { 464 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 465 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 466 if (stat != 0) { 467 return stat; 468 } 469 *left = cap->bounds.left; 470 if (cap->bounds.width > cptr->hdw->cropw_val) { 471 *left += cap->bounds.width - cptr->hdw->cropw_val; 472 } 473 return 0; 474 } 475 476 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top) 477 { 478 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 479 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 480 if (stat != 0) { 481 return stat; 482 } 483 *top = cap->bounds.top; 484 return 0; 485 } 486 487 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top) 488 { 489 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 490 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 491 if (stat != 0) { 492 return stat; 493 } 494 *top = cap->bounds.top; 495 if (cap->bounds.height > cptr->hdw->croph_val) { 496 *top += cap->bounds.height - cptr->hdw->croph_val; 497 } 498 return 0; 499 } 500 501 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width) 502 { 503 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 504 int stat, bleftend, cleft; 505 506 stat = pvr2_hdw_check_cropcap(cptr->hdw); 507 if (stat != 0) { 508 return stat; 509 } 510 bleftend = cap->bounds.left+cap->bounds.width; 511 cleft = cptr->hdw->cropl_val; 512 513 *width = cleft < bleftend ? bleftend-cleft : 0; 514 return 0; 515 } 516 517 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height) 518 { 519 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 520 int stat, btopend, ctop; 521 522 stat = pvr2_hdw_check_cropcap(cptr->hdw); 523 if (stat != 0) { 524 return stat; 525 } 526 btopend = cap->bounds.top+cap->bounds.height; 527 ctop = cptr->hdw->cropt_val; 528 529 *height = ctop < btopend ? btopend-ctop : 0; 530 return 0; 531 } 532 533 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val) 534 { 535 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 536 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 537 if (stat != 0) { 538 return stat; 539 } 540 *val = cap->bounds.left; 541 return 0; 542 } 543 544 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val) 545 { 546 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 547 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 548 if (stat != 0) { 549 return stat; 550 } 551 *val = cap->bounds.top; 552 return 0; 553 } 554 555 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val) 556 { 557 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 558 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 559 if (stat != 0) { 560 return stat; 561 } 562 *val = cap->bounds.width; 563 return 0; 564 } 565 566 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val) 567 { 568 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 569 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 570 if (stat != 0) { 571 return stat; 572 } 573 *val = cap->bounds.height; 574 return 0; 575 } 576 577 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val) 578 { 579 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 580 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 581 if (stat != 0) { 582 return stat; 583 } 584 *val = cap->defrect.left; 585 return 0; 586 } 587 588 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val) 589 { 590 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 591 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 592 if (stat != 0) { 593 return stat; 594 } 595 *val = cap->defrect.top; 596 return 0; 597 } 598 599 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val) 600 { 601 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 602 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 603 if (stat != 0) { 604 return stat; 605 } 606 *val = cap->defrect.width; 607 return 0; 608 } 609 610 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val) 611 { 612 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 613 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 614 if (stat != 0) { 615 return stat; 616 } 617 *val = cap->defrect.height; 618 return 0; 619 } 620 621 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val) 622 { 623 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 624 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 625 if (stat != 0) { 626 return stat; 627 } 628 *val = cap->pixelaspect.numerator; 629 return 0; 630 } 631 632 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val) 633 { 634 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 635 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 636 if (stat != 0) { 637 return stat; 638 } 639 *val = cap->pixelaspect.denominator; 640 return 0; 641 } 642 643 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp) 644 { 645 /* Actual maximum depends on the video standard in effect. */ 646 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) { 647 *vp = 480; 648 } else { 649 *vp = 576; 650 } 651 return 0; 652 } 653 654 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp) 655 { 656 /* Actual minimum depends on device digitizer type. */ 657 if (cptr->hdw->hdw_desc->flag_has_cx25840) { 658 *vp = 75; 659 } else { 660 *vp = 17; 661 } 662 return 0; 663 } 664 665 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp) 666 { 667 *vp = cptr->hdw->input_val; 668 return 0; 669 } 670 671 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v) 672 { 673 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0; 674 } 675 676 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v) 677 { 678 return pvr2_hdw_set_input(cptr->hdw,v); 679 } 680 681 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr) 682 { 683 return cptr->hdw->input_dirty != 0; 684 } 685 686 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr) 687 { 688 cptr->hdw->input_dirty = 0; 689 } 690 691 692 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp) 693 { 694 unsigned long fv; 695 struct pvr2_hdw *hdw = cptr->hdw; 696 if (hdw->tuner_signal_stale) { 697 pvr2_hdw_status_poll(hdw); 698 } 699 fv = hdw->tuner_signal_info.rangehigh; 700 if (!fv) { 701 /* Safety fallback */ 702 *vp = TV_MAX_FREQ; 703 return 0; 704 } 705 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 706 fv = (fv * 125) / 2; 707 } else { 708 fv = fv * 62500; 709 } 710 *vp = fv; 711 return 0; 712 } 713 714 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp) 715 { 716 unsigned long fv; 717 struct pvr2_hdw *hdw = cptr->hdw; 718 if (hdw->tuner_signal_stale) { 719 pvr2_hdw_status_poll(hdw); 720 } 721 fv = hdw->tuner_signal_info.rangelow; 722 if (!fv) { 723 /* Safety fallback */ 724 *vp = TV_MIN_FREQ; 725 return 0; 726 } 727 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 728 fv = (fv * 125) / 2; 729 } else { 730 fv = fv * 62500; 731 } 732 *vp = fv; 733 return 0; 734 } 735 736 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr) 737 { 738 return cptr->hdw->enc_stale != 0; 739 } 740 741 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr) 742 { 743 cptr->hdw->enc_stale = 0; 744 cptr->hdw->enc_unsafe_stale = 0; 745 } 746 747 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp) 748 { 749 int ret; 750 struct v4l2_ext_controls cs; 751 struct v4l2_ext_control c1; 752 memset(&cs,0,sizeof(cs)); 753 memset(&c1,0,sizeof(c1)); 754 cs.controls = &c1; 755 cs.count = 1; 756 c1.id = cptr->info->v4l_id; 757 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs, 758 VIDIOC_G_EXT_CTRLS); 759 if (ret) return ret; 760 *vp = c1.value; 761 return 0; 762 } 763 764 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v) 765 { 766 int ret; 767 struct pvr2_hdw *hdw = cptr->hdw; 768 struct v4l2_ext_controls cs; 769 struct v4l2_ext_control c1; 770 memset(&cs,0,sizeof(cs)); 771 memset(&c1,0,sizeof(c1)); 772 cs.controls = &c1; 773 cs.count = 1; 774 c1.id = cptr->info->v4l_id; 775 c1.value = v; 776 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, 777 hdw->state_encoder_run, &cs, 778 VIDIOC_S_EXT_CTRLS); 779 if (ret == -EBUSY) { 780 /* Oops. cx2341x is telling us it's not safe to change 781 this control while we're capturing. Make a note of this 782 fact so that the pipeline will be stopped the next time 783 controls are committed. Then go on ahead and store this 784 change anyway. */ 785 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, 786 0, &cs, 787 VIDIOC_S_EXT_CTRLS); 788 if (!ret) hdw->enc_unsafe_stale = !0; 789 } 790 if (ret) return ret; 791 hdw->enc_stale = !0; 792 return 0; 793 } 794 795 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr) 796 { 797 struct v4l2_queryctrl qctrl; 798 struct pvr2_ctl_info *info; 799 qctrl.id = cptr->info->v4l_id; 800 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl); 801 /* Strip out the const so we can adjust a function pointer. It's 802 OK to do this here because we know this is a dynamically created 803 control, so the underlying storage for the info pointer is (a) 804 private to us, and (b) not in read-only storage. Either we do 805 this or we significantly complicate the underlying control 806 implementation. */ 807 info = (struct pvr2_ctl_info *)(cptr->info); 808 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) { 809 if (info->set_value) { 810 info->set_value = NULL; 811 } 812 } else { 813 if (!(info->set_value)) { 814 info->set_value = ctrl_cx2341x_set; 815 } 816 } 817 return qctrl.flags; 818 } 819 820 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp) 821 { 822 *vp = cptr->hdw->state_pipeline_req; 823 return 0; 824 } 825 826 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp) 827 { 828 *vp = cptr->hdw->master_state; 829 return 0; 830 } 831 832 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp) 833 { 834 int result = pvr2_hdw_is_hsm(cptr->hdw); 835 *vp = PVR2_CVAL_HSM_FULL; 836 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL; 837 if (result) *vp = PVR2_CVAL_HSM_HIGH; 838 return 0; 839 } 840 841 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp) 842 { 843 *vp = pvr2_hdw_get_detected_std(cptr->hdw); 844 return 0; 845 } 846 847 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp) 848 { 849 *vp = cptr->hdw->std_mask_avail; 850 return 0; 851 } 852 853 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v) 854 { 855 struct pvr2_hdw *hdw = cptr->hdw; 856 v4l2_std_id ns; 857 ns = hdw->std_mask_avail; 858 ns = (ns & ~m) | (v & m); 859 if (ns == hdw->std_mask_avail) return 0; 860 hdw->std_mask_avail = ns; 861 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; 862 return 0; 863 } 864 865 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val, 866 char *bufPtr,unsigned int bufSize, 867 unsigned int *len) 868 { 869 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val); 870 return 0; 871 } 872 873 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr, 874 const char *bufPtr,unsigned int bufSize, 875 int *mskp,int *valp) 876 { 877 int ret; 878 v4l2_std_id id; 879 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize); 880 if (ret < 0) return ret; 881 if (mskp) *mskp = id; 882 if (valp) *valp = id; 883 return 0; 884 } 885 886 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp) 887 { 888 *vp = cptr->hdw->std_mask_cur; 889 return 0; 890 } 891 892 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v) 893 { 894 struct pvr2_hdw *hdw = cptr->hdw; 895 v4l2_std_id ns; 896 ns = hdw->std_mask_cur; 897 ns = (ns & ~m) | (v & m); 898 if (ns == hdw->std_mask_cur) return 0; 899 hdw->std_mask_cur = ns; 900 hdw->std_dirty = !0; 901 return 0; 902 } 903 904 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr) 905 { 906 return cptr->hdw->std_dirty != 0; 907 } 908 909 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr) 910 { 911 cptr->hdw->std_dirty = 0; 912 } 913 914 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp) 915 { 916 struct pvr2_hdw *hdw = cptr->hdw; 917 pvr2_hdw_status_poll(hdw); 918 *vp = hdw->tuner_signal_info.signal; 919 return 0; 920 } 921 922 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp) 923 { 924 int val = 0; 925 unsigned int subchan; 926 struct pvr2_hdw *hdw = cptr->hdw; 927 pvr2_hdw_status_poll(hdw); 928 subchan = hdw->tuner_signal_info.rxsubchans; 929 if (subchan & V4L2_TUNER_SUB_MONO) { 930 val |= (1 << V4L2_TUNER_MODE_MONO); 931 } 932 if (subchan & V4L2_TUNER_SUB_STEREO) { 933 val |= (1 << V4L2_TUNER_MODE_STEREO); 934 } 935 if (subchan & V4L2_TUNER_SUB_LANG1) { 936 val |= (1 << V4L2_TUNER_MODE_LANG1); 937 } 938 if (subchan & V4L2_TUNER_SUB_LANG2) { 939 val |= (1 << V4L2_TUNER_MODE_LANG2); 940 } 941 *vp = val; 942 return 0; 943 } 944 945 946 #define DEFINT(vmin,vmax) \ 947 .type = pvr2_ctl_int, \ 948 .def.type_int.min_value = vmin, \ 949 .def.type_int.max_value = vmax 950 951 #define DEFENUM(tab) \ 952 .type = pvr2_ctl_enum, \ 953 .def.type_enum.count = ARRAY_SIZE(tab), \ 954 .def.type_enum.value_names = tab 955 956 #define DEFBOOL \ 957 .type = pvr2_ctl_bool 958 959 #define DEFMASK(msk,tab) \ 960 .type = pvr2_ctl_bitmask, \ 961 .def.type_bitmask.valid_bits = msk, \ 962 .def.type_bitmask.bit_names = tab 963 964 #define DEFREF(vname) \ 965 .set_value = ctrl_set_##vname, \ 966 .get_value = ctrl_get_##vname, \ 967 .is_dirty = ctrl_isdirty_##vname, \ 968 .clear_dirty = ctrl_cleardirty_##vname 969 970 971 #define VCREATE_FUNCS(vname) \ 972 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \ 973 {*vp = cptr->hdw->vname##_val; return 0;} \ 974 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \ 975 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \ 976 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \ 977 {return cptr->hdw->vname##_dirty != 0;} \ 978 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \ 979 {cptr->hdw->vname##_dirty = 0;} 980 981 VCREATE_FUNCS(brightness) 982 VCREATE_FUNCS(contrast) 983 VCREATE_FUNCS(saturation) 984 VCREATE_FUNCS(hue) 985 VCREATE_FUNCS(volume) 986 VCREATE_FUNCS(balance) 987 VCREATE_FUNCS(bass) 988 VCREATE_FUNCS(treble) 989 VCREATE_FUNCS(mute) 990 VCREATE_FUNCS(cropl) 991 VCREATE_FUNCS(cropt) 992 VCREATE_FUNCS(cropw) 993 VCREATE_FUNCS(croph) 994 VCREATE_FUNCS(audiomode) 995 VCREATE_FUNCS(res_hor) 996 VCREATE_FUNCS(res_ver) 997 VCREATE_FUNCS(srate) 998 999 /* Table definition of all controls which can be manipulated */ 1000 static const struct pvr2_ctl_info control_defs[] = { 1001 { 1002 .v4l_id = V4L2_CID_BRIGHTNESS, 1003 .desc = "Brightness", 1004 .name = "brightness", 1005 .default_value = 128, 1006 DEFREF(brightness), 1007 DEFINT(0,255), 1008 },{ 1009 .v4l_id = V4L2_CID_CONTRAST, 1010 .desc = "Contrast", 1011 .name = "contrast", 1012 .default_value = 68, 1013 DEFREF(contrast), 1014 DEFINT(0,127), 1015 },{ 1016 .v4l_id = V4L2_CID_SATURATION, 1017 .desc = "Saturation", 1018 .name = "saturation", 1019 .default_value = 64, 1020 DEFREF(saturation), 1021 DEFINT(0,127), 1022 },{ 1023 .v4l_id = V4L2_CID_HUE, 1024 .desc = "Hue", 1025 .name = "hue", 1026 .default_value = 0, 1027 DEFREF(hue), 1028 DEFINT(-128,127), 1029 },{ 1030 .v4l_id = V4L2_CID_AUDIO_VOLUME, 1031 .desc = "Volume", 1032 .name = "volume", 1033 .default_value = 62000, 1034 DEFREF(volume), 1035 DEFINT(0,65535), 1036 },{ 1037 .v4l_id = V4L2_CID_AUDIO_BALANCE, 1038 .desc = "Balance", 1039 .name = "balance", 1040 .default_value = 0, 1041 DEFREF(balance), 1042 DEFINT(-32768,32767), 1043 },{ 1044 .v4l_id = V4L2_CID_AUDIO_BASS, 1045 .desc = "Bass", 1046 .name = "bass", 1047 .default_value = 0, 1048 DEFREF(bass), 1049 DEFINT(-32768,32767), 1050 },{ 1051 .v4l_id = V4L2_CID_AUDIO_TREBLE, 1052 .desc = "Treble", 1053 .name = "treble", 1054 .default_value = 0, 1055 DEFREF(treble), 1056 DEFINT(-32768,32767), 1057 },{ 1058 .v4l_id = V4L2_CID_AUDIO_MUTE, 1059 .desc = "Mute", 1060 .name = "mute", 1061 .default_value = 0, 1062 DEFREF(mute), 1063 DEFBOOL, 1064 }, { 1065 .desc = "Capture crop left margin", 1066 .name = "crop_left", 1067 .internal_id = PVR2_CID_CROPL, 1068 .default_value = 0, 1069 DEFREF(cropl), 1070 DEFINT(-129, 340), 1071 .get_min_value = ctrl_cropl_min_get, 1072 .get_max_value = ctrl_cropl_max_get, 1073 .get_def_value = ctrl_get_cropcapdl, 1074 }, { 1075 .desc = "Capture crop top margin", 1076 .name = "crop_top", 1077 .internal_id = PVR2_CID_CROPT, 1078 .default_value = 0, 1079 DEFREF(cropt), 1080 DEFINT(-35, 544), 1081 .get_min_value = ctrl_cropt_min_get, 1082 .get_max_value = ctrl_cropt_max_get, 1083 .get_def_value = ctrl_get_cropcapdt, 1084 }, { 1085 .desc = "Capture crop width", 1086 .name = "crop_width", 1087 .internal_id = PVR2_CID_CROPW, 1088 .default_value = 720, 1089 DEFREF(cropw), 1090 DEFINT(0, 864), 1091 .get_max_value = ctrl_cropw_max_get, 1092 .get_def_value = ctrl_get_cropcapdw, 1093 }, { 1094 .desc = "Capture crop height", 1095 .name = "crop_height", 1096 .internal_id = PVR2_CID_CROPH, 1097 .default_value = 480, 1098 DEFREF(croph), 1099 DEFINT(0, 576), 1100 .get_max_value = ctrl_croph_max_get, 1101 .get_def_value = ctrl_get_cropcapdh, 1102 }, { 1103 .desc = "Capture capability pixel aspect numerator", 1104 .name = "cropcap_pixel_numerator", 1105 .internal_id = PVR2_CID_CROPCAPPAN, 1106 .get_value = ctrl_get_cropcappan, 1107 }, { 1108 .desc = "Capture capability pixel aspect denominator", 1109 .name = "cropcap_pixel_denominator", 1110 .internal_id = PVR2_CID_CROPCAPPAD, 1111 .get_value = ctrl_get_cropcappad, 1112 }, { 1113 .desc = "Capture capability bounds top", 1114 .name = "cropcap_bounds_top", 1115 .internal_id = PVR2_CID_CROPCAPBT, 1116 .get_value = ctrl_get_cropcapbt, 1117 }, { 1118 .desc = "Capture capability bounds left", 1119 .name = "cropcap_bounds_left", 1120 .internal_id = PVR2_CID_CROPCAPBL, 1121 .get_value = ctrl_get_cropcapbl, 1122 }, { 1123 .desc = "Capture capability bounds width", 1124 .name = "cropcap_bounds_width", 1125 .internal_id = PVR2_CID_CROPCAPBW, 1126 .get_value = ctrl_get_cropcapbw, 1127 }, { 1128 .desc = "Capture capability bounds height", 1129 .name = "cropcap_bounds_height", 1130 .internal_id = PVR2_CID_CROPCAPBH, 1131 .get_value = ctrl_get_cropcapbh, 1132 },{ 1133 .desc = "Video Source", 1134 .name = "input", 1135 .internal_id = PVR2_CID_INPUT, 1136 .default_value = PVR2_CVAL_INPUT_TV, 1137 .check_value = ctrl_check_input, 1138 DEFREF(input), 1139 DEFENUM(control_values_input), 1140 },{ 1141 .desc = "Audio Mode", 1142 .name = "audio_mode", 1143 .internal_id = PVR2_CID_AUDIOMODE, 1144 .default_value = V4L2_TUNER_MODE_STEREO, 1145 DEFREF(audiomode), 1146 DEFENUM(control_values_audiomode), 1147 },{ 1148 .desc = "Horizontal capture resolution", 1149 .name = "resolution_hor", 1150 .internal_id = PVR2_CID_HRES, 1151 .default_value = 720, 1152 DEFREF(res_hor), 1153 DEFINT(19,720), 1154 },{ 1155 .desc = "Vertical capture resolution", 1156 .name = "resolution_ver", 1157 .internal_id = PVR2_CID_VRES, 1158 .default_value = 480, 1159 DEFREF(res_ver), 1160 DEFINT(17,576), 1161 /* Hook in check for video standard and adjust maximum 1162 depending on the standard. */ 1163 .get_max_value = ctrl_vres_max_get, 1164 .get_min_value = ctrl_vres_min_get, 1165 },{ 1166 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ, 1167 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000, 1168 .desc = "Audio Sampling Frequency", 1169 .name = "srate", 1170 DEFREF(srate), 1171 DEFENUM(control_values_srate), 1172 },{ 1173 .desc = "Tuner Frequency (Hz)", 1174 .name = "frequency", 1175 .internal_id = PVR2_CID_FREQUENCY, 1176 .default_value = 0, 1177 .set_value = ctrl_freq_set, 1178 .get_value = ctrl_freq_get, 1179 .is_dirty = ctrl_freq_is_dirty, 1180 .clear_dirty = ctrl_freq_clear_dirty, 1181 DEFINT(0,0), 1182 /* Hook in check for input value (tv/radio) and adjust 1183 max/min values accordingly */ 1184 .get_max_value = ctrl_freq_max_get, 1185 .get_min_value = ctrl_freq_min_get, 1186 },{ 1187 .desc = "Channel", 1188 .name = "channel", 1189 .set_value = ctrl_channel_set, 1190 .get_value = ctrl_channel_get, 1191 DEFINT(0,FREQTABLE_SIZE), 1192 },{ 1193 .desc = "Channel Program Frequency", 1194 .name = "freq_table_value", 1195 .set_value = ctrl_channelfreq_set, 1196 .get_value = ctrl_channelfreq_get, 1197 DEFINT(0,0), 1198 /* Hook in check for input value (tv/radio) and adjust 1199 max/min values accordingly */ 1200 .get_max_value = ctrl_freq_max_get, 1201 .get_min_value = ctrl_freq_min_get, 1202 },{ 1203 .desc = "Channel Program ID", 1204 .name = "freq_table_channel", 1205 .set_value = ctrl_channelprog_set, 1206 .get_value = ctrl_channelprog_get, 1207 DEFINT(0,FREQTABLE_SIZE), 1208 },{ 1209 .desc = "Streaming Enabled", 1210 .name = "streaming_enabled", 1211 .get_value = ctrl_streamingenabled_get, 1212 DEFBOOL, 1213 },{ 1214 .desc = "USB Speed", 1215 .name = "usb_speed", 1216 .get_value = ctrl_hsm_get, 1217 DEFENUM(control_values_hsm), 1218 },{ 1219 .desc = "Master State", 1220 .name = "master_state", 1221 .get_value = ctrl_masterstate_get, 1222 DEFENUM(pvr2_state_names), 1223 },{ 1224 .desc = "Signal Present", 1225 .name = "signal_present", 1226 .get_value = ctrl_signal_get, 1227 DEFINT(0,65535), 1228 },{ 1229 .desc = "Audio Modes Present", 1230 .name = "audio_modes_present", 1231 .get_value = ctrl_audio_modes_present_get, 1232 /* For this type we "borrow" the V4L2_TUNER_MODE enum from 1233 v4l. Nothing outside of this module cares about this, 1234 but I reuse it in order to also reuse the 1235 control_values_audiomode string table. */ 1236 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)| 1237 (1 << V4L2_TUNER_MODE_STEREO)| 1238 (1 << V4L2_TUNER_MODE_LANG1)| 1239 (1 << V4L2_TUNER_MODE_LANG2)), 1240 control_values_audiomode), 1241 },{ 1242 .desc = "Video Standards Available Mask", 1243 .name = "video_standard_mask_available", 1244 .internal_id = PVR2_CID_STDAVAIL, 1245 .skip_init = !0, 1246 .get_value = ctrl_stdavail_get, 1247 .set_value = ctrl_stdavail_set, 1248 .val_to_sym = ctrl_std_val_to_sym, 1249 .sym_to_val = ctrl_std_sym_to_val, 1250 .type = pvr2_ctl_bitmask, 1251 },{ 1252 .desc = "Video Standards In Use Mask", 1253 .name = "video_standard_mask_active", 1254 .internal_id = PVR2_CID_STDCUR, 1255 .skip_init = !0, 1256 .get_value = ctrl_stdcur_get, 1257 .set_value = ctrl_stdcur_set, 1258 .is_dirty = ctrl_stdcur_is_dirty, 1259 .clear_dirty = ctrl_stdcur_clear_dirty, 1260 .val_to_sym = ctrl_std_val_to_sym, 1261 .sym_to_val = ctrl_std_sym_to_val, 1262 .type = pvr2_ctl_bitmask, 1263 },{ 1264 .desc = "Video Standards Detected Mask", 1265 .name = "video_standard_mask_detected", 1266 .internal_id = PVR2_CID_STDDETECT, 1267 .skip_init = !0, 1268 .get_value = ctrl_stddetect_get, 1269 .val_to_sym = ctrl_std_val_to_sym, 1270 .sym_to_val = ctrl_std_sym_to_val, 1271 .type = pvr2_ctl_bitmask, 1272 } 1273 }; 1274 1275 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs) 1276 1277 1278 const char *pvr2_config_get_name(enum pvr2_config cfg) 1279 { 1280 switch (cfg) { 1281 case pvr2_config_empty: return "empty"; 1282 case pvr2_config_mpeg: return "mpeg"; 1283 case pvr2_config_vbi: return "vbi"; 1284 case pvr2_config_pcm: return "pcm"; 1285 case pvr2_config_rawvideo: return "raw video"; 1286 } 1287 return "<unknown>"; 1288 } 1289 1290 1291 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw) 1292 { 1293 return hdw->usb_dev; 1294 } 1295 1296 1297 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw) 1298 { 1299 return hdw->serial_number; 1300 } 1301 1302 1303 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw) 1304 { 1305 return hdw->bus_info; 1306 } 1307 1308 1309 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw) 1310 { 1311 return hdw->identifier; 1312 } 1313 1314 1315 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw) 1316 { 1317 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio; 1318 } 1319 1320 /* Set the currently tuned frequency and account for all possible 1321 driver-core side effects of this action. */ 1322 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val) 1323 { 1324 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 1325 if (hdw->freqSelector) { 1326 /* Swing over to radio frequency selection */ 1327 hdw->freqSelector = 0; 1328 hdw->freqDirty = !0; 1329 } 1330 if (hdw->freqValRadio != val) { 1331 hdw->freqValRadio = val; 1332 hdw->freqSlotRadio = 0; 1333 hdw->freqDirty = !0; 1334 } 1335 } else { 1336 if (!(hdw->freqSelector)) { 1337 /* Swing over to television frequency selection */ 1338 hdw->freqSelector = 1; 1339 hdw->freqDirty = !0; 1340 } 1341 if (hdw->freqValTelevision != val) { 1342 hdw->freqValTelevision = val; 1343 hdw->freqSlotTelevision = 0; 1344 hdw->freqDirty = !0; 1345 } 1346 } 1347 } 1348 1349 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw) 1350 { 1351 return hdw->unit_number; 1352 } 1353 1354 1355 /* Attempt to locate one of the given set of files. Messages are logged 1356 appropriate to what has been found. The return value will be 0 or 1357 greater on success (it will be the index of the file name found) and 1358 fw_entry will be filled in. Otherwise a negative error is returned on 1359 failure. If the return value is -ENOENT then no viable firmware file 1360 could be located. */ 1361 static int pvr2_locate_firmware(struct pvr2_hdw *hdw, 1362 const struct firmware **fw_entry, 1363 const char *fwtypename, 1364 unsigned int fwcount, 1365 const char *fwnames[]) 1366 { 1367 unsigned int idx; 1368 int ret = -EINVAL; 1369 for (idx = 0; idx < fwcount; idx++) { 1370 ret = request_firmware(fw_entry, 1371 fwnames[idx], 1372 &hdw->usb_dev->dev); 1373 if (!ret) { 1374 trace_firmware("Located %s firmware: %s;" 1375 " uploading...", 1376 fwtypename, 1377 fwnames[idx]); 1378 return idx; 1379 } 1380 if (ret == -ENOENT) continue; 1381 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1382 "request_firmware fatal error with code=%d",ret); 1383 return ret; 1384 } 1385 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1386 "***WARNING***" 1387 " Device %s firmware" 1388 " seems to be missing.", 1389 fwtypename); 1390 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1391 "Did you install the pvrusb2 firmware files" 1392 " in their proper location?"); 1393 if (fwcount == 1) { 1394 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1395 "request_firmware unable to locate %s file %s", 1396 fwtypename,fwnames[0]); 1397 } else { 1398 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1399 "request_firmware unable to locate" 1400 " one of the following %s files:", 1401 fwtypename); 1402 for (idx = 0; idx < fwcount; idx++) { 1403 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1404 "request_firmware: Failed to find %s", 1405 fwnames[idx]); 1406 } 1407 } 1408 return ret; 1409 } 1410 1411 1412 /* 1413 * pvr2_upload_firmware1(). 1414 * 1415 * Send the 8051 firmware to the device. After the upload, arrange for 1416 * device to re-enumerate. 1417 * 1418 * NOTE : the pointer to the firmware data given by request_firmware() 1419 * is not suitable for an usb transaction. 1420 * 1421 */ 1422 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw) 1423 { 1424 const struct firmware *fw_entry = NULL; 1425 void *fw_ptr; 1426 unsigned int pipe; 1427 unsigned int fwsize; 1428 int ret; 1429 u16 address; 1430 1431 if (!hdw->hdw_desc->fx2_firmware.cnt) { 1432 hdw->fw1_state = FW1_STATE_OK; 1433 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1434 "Connected device type defines" 1435 " no firmware to upload; ignoring firmware"); 1436 return -ENOTTY; 1437 } 1438 1439 hdw->fw1_state = FW1_STATE_FAILED; // default result 1440 1441 trace_firmware("pvr2_upload_firmware1"); 1442 1443 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller", 1444 hdw->hdw_desc->fx2_firmware.cnt, 1445 hdw->hdw_desc->fx2_firmware.lst); 1446 if (ret < 0) { 1447 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING; 1448 return ret; 1449 } 1450 1451 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f)); 1452 1453 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); 1454 fwsize = fw_entry->size; 1455 1456 if ((fwsize != 0x2000) && 1457 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) { 1458 if (hdw->hdw_desc->flag_fx2_16kb) { 1459 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1460 "Wrong fx2 firmware size" 1461 " (expected 8192 or 16384, got %u)", 1462 fwsize); 1463 } else { 1464 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1465 "Wrong fx2 firmware size" 1466 " (expected 8192, got %u)", 1467 fwsize); 1468 } 1469 release_firmware(fw_entry); 1470 return -ENOMEM; 1471 } 1472 1473 fw_ptr = kmalloc(0x800, GFP_KERNEL); 1474 if (fw_ptr == NULL){ 1475 release_firmware(fw_entry); 1476 return -ENOMEM; 1477 } 1478 1479 /* We have to hold the CPU during firmware upload. */ 1480 pvr2_hdw_cpureset_assert(hdw,1); 1481 1482 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes 1483 chunk. */ 1484 1485 ret = 0; 1486 for (address = 0; address < fwsize; address += 0x800) { 1487 memcpy(fw_ptr, fw_entry->data + address, 0x800); 1488 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address, 1489 0, fw_ptr, 0x800, HZ); 1490 } 1491 1492 trace_firmware("Upload done, releasing device's CPU"); 1493 1494 /* Now release the CPU. It will disconnect and reconnect later. */ 1495 pvr2_hdw_cpureset_assert(hdw,0); 1496 1497 kfree(fw_ptr); 1498 release_firmware(fw_entry); 1499 1500 trace_firmware("Upload done (%d bytes sent)",ret); 1501 1502 /* We should have written fwsize bytes */ 1503 if (ret == fwsize) { 1504 hdw->fw1_state = FW1_STATE_RELOAD; 1505 return 0; 1506 } 1507 1508 return -EIO; 1509 } 1510 1511 1512 /* 1513 * pvr2_upload_firmware2() 1514 * 1515 * This uploads encoder firmware on endpoint 2. 1516 * 1517 */ 1518 1519 int pvr2_upload_firmware2(struct pvr2_hdw *hdw) 1520 { 1521 const struct firmware *fw_entry = NULL; 1522 void *fw_ptr; 1523 unsigned int pipe, fw_len, fw_done, bcnt, icnt; 1524 int actual_length; 1525 int ret = 0; 1526 int fwidx; 1527 static const char *fw_files[] = { 1528 CX2341X_FIRM_ENC_FILENAME, 1529 }; 1530 1531 if (hdw->hdw_desc->flag_skip_cx23416_firmware) { 1532 return 0; 1533 } 1534 1535 trace_firmware("pvr2_upload_firmware2"); 1536 1537 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder", 1538 ARRAY_SIZE(fw_files), fw_files); 1539 if (ret < 0) return ret; 1540 fwidx = ret; 1541 ret = 0; 1542 /* Since we're about to completely reinitialize the encoder, 1543 invalidate our cached copy of its configuration state. Next 1544 time we configure the encoder, then we'll fully configure it. */ 1545 hdw->enc_cur_valid = 0; 1546 1547 /* Encoder is about to be reset so note that as far as we're 1548 concerned now, the encoder has never been run. */ 1549 del_timer_sync(&hdw->encoder_run_timer); 1550 if (hdw->state_encoder_runok) { 1551 hdw->state_encoder_runok = 0; 1552 trace_stbit("state_encoder_runok",hdw->state_encoder_runok); 1553 } 1554 1555 /* First prepare firmware loading */ 1556 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/ 1557 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/ 1558 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ 1559 ret |= pvr2_hdw_cmd_deep_reset(hdw); 1560 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/ 1561 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/ 1562 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ 1563 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/ 1564 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/ 1565 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/ 1566 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/ 1567 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/ 1568 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/ 1569 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ 1570 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ 1571 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ 1572 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1); 1573 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); 1574 1575 if (ret) { 1576 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1577 "firmware2 upload prep failed, ret=%d",ret); 1578 release_firmware(fw_entry); 1579 goto done; 1580 } 1581 1582 /* Now send firmware */ 1583 1584 fw_len = fw_entry->size; 1585 1586 if (fw_len % sizeof(u32)) { 1587 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1588 "size of %s firmware" 1589 " must be a multiple of %zu bytes", 1590 fw_files[fwidx],sizeof(u32)); 1591 release_firmware(fw_entry); 1592 ret = -EINVAL; 1593 goto done; 1594 } 1595 1596 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL); 1597 if (fw_ptr == NULL){ 1598 release_firmware(fw_entry); 1599 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1600 "failed to allocate memory for firmware2 upload"); 1601 ret = -ENOMEM; 1602 goto done; 1603 } 1604 1605 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT); 1606 1607 fw_done = 0; 1608 for (fw_done = 0; fw_done < fw_len;) { 1609 bcnt = fw_len - fw_done; 1610 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE; 1611 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt); 1612 /* Usbsnoop log shows that we must swap bytes... */ 1613 /* Some background info: The data being swapped here is a 1614 firmware image destined for the mpeg encoder chip that 1615 lives at the other end of a USB endpoint. The encoder 1616 chip always talks in 32 bit chunks and its storage is 1617 organized into 32 bit words. However from the file 1618 system to the encoder chip everything is purely a byte 1619 stream. The firmware file's contents are always 32 bit 1620 swapped from what the encoder expects. Thus the need 1621 always exists to swap the bytes regardless of the endian 1622 type of the host processor and therefore swab32() makes 1623 the most sense. */ 1624 for (icnt = 0; icnt < bcnt/4 ; icnt++) 1625 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]); 1626 1627 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt, 1628 &actual_length, HZ); 1629 ret |= (actual_length != bcnt); 1630 if (ret) break; 1631 fw_done += bcnt; 1632 } 1633 1634 trace_firmware("upload of %s : %i / %i ", 1635 fw_files[fwidx],fw_done,fw_len); 1636 1637 kfree(fw_ptr); 1638 release_firmware(fw_entry); 1639 1640 if (ret) { 1641 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1642 "firmware2 upload transfer failure"); 1643 goto done; 1644 } 1645 1646 /* Finish upload */ 1647 1648 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ 1649 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ 1650 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); 1651 1652 if (ret) { 1653 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1654 "firmware2 upload post-proc failure"); 1655 } 1656 1657 done: 1658 if (hdw->hdw_desc->signal_routing_scheme == 1659 PVR2_ROUTING_SCHEME_GOTVIEW) { 1660 /* Ensure that GPIO 11 is set to output for GOTVIEW 1661 hardware. */ 1662 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); 1663 } 1664 return ret; 1665 } 1666 1667 1668 static const char *pvr2_get_state_name(unsigned int st) 1669 { 1670 if (st < ARRAY_SIZE(pvr2_state_names)) { 1671 return pvr2_state_names[st]; 1672 } 1673 return "???"; 1674 } 1675 1676 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl) 1677 { 1678 /* Even though we really only care about the video decoder chip at 1679 this point, we'll broadcast stream on/off to all sub-devices 1680 anyway, just in case somebody else wants to hear the 1681 command... */ 1682 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s", 1683 (enablefl ? "on" : "off")); 1684 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl); 1685 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl); 1686 if (hdw->decoder_client_id) { 1687 /* We get here if the encoder has been noticed. Otherwise 1688 we'll issue a warning to the user (which should 1689 normally never happen). */ 1690 return 0; 1691 } 1692 if (!hdw->flag_decoder_missed) { 1693 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1694 "WARNING: No decoder present"); 1695 hdw->flag_decoder_missed = !0; 1696 trace_stbit("flag_decoder_missed", 1697 hdw->flag_decoder_missed); 1698 } 1699 return -EIO; 1700 } 1701 1702 1703 int pvr2_hdw_get_state(struct pvr2_hdw *hdw) 1704 { 1705 return hdw->master_state; 1706 } 1707 1708 1709 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw) 1710 { 1711 if (!hdw->flag_tripped) return 0; 1712 hdw->flag_tripped = 0; 1713 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1714 "Clearing driver error statuss"); 1715 return !0; 1716 } 1717 1718 1719 int pvr2_hdw_untrip(struct pvr2_hdw *hdw) 1720 { 1721 int fl; 1722 LOCK_TAKE(hdw->big_lock); do { 1723 fl = pvr2_hdw_untrip_unlocked(hdw); 1724 } while (0); LOCK_GIVE(hdw->big_lock); 1725 if (fl) pvr2_hdw_state_sched(hdw); 1726 return 0; 1727 } 1728 1729 1730 1731 1732 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw) 1733 { 1734 return hdw->state_pipeline_req != 0; 1735 } 1736 1737 1738 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag) 1739 { 1740 int ret,st; 1741 LOCK_TAKE(hdw->big_lock); do { 1742 pvr2_hdw_untrip_unlocked(hdw); 1743 if ((!enable_flag) != !(hdw->state_pipeline_req)) { 1744 hdw->state_pipeline_req = enable_flag != 0; 1745 pvr2_trace(PVR2_TRACE_START_STOP, 1746 "/*--TRACE_STREAM--*/ %s", 1747 enable_flag ? "enable" : "disable"); 1748 } 1749 pvr2_hdw_state_sched(hdw); 1750 } while (0); LOCK_GIVE(hdw->big_lock); 1751 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret; 1752 if (enable_flag) { 1753 while ((st = hdw->master_state) != PVR2_STATE_RUN) { 1754 if (st != PVR2_STATE_READY) return -EIO; 1755 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret; 1756 } 1757 } 1758 return 0; 1759 } 1760 1761 1762 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config) 1763 { 1764 int fl; 1765 LOCK_TAKE(hdw->big_lock); 1766 if ((fl = (hdw->desired_stream_type != config)) != 0) { 1767 hdw->desired_stream_type = config; 1768 hdw->state_pipeline_config = 0; 1769 trace_stbit("state_pipeline_config", 1770 hdw->state_pipeline_config); 1771 pvr2_hdw_state_sched(hdw); 1772 } 1773 LOCK_GIVE(hdw->big_lock); 1774 if (fl) return 0; 1775 return pvr2_hdw_wait(hdw,0); 1776 } 1777 1778 1779 static int get_default_tuner_type(struct pvr2_hdw *hdw) 1780 { 1781 int unit_number = hdw->unit_number; 1782 int tp = -1; 1783 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1784 tp = tuner[unit_number]; 1785 } 1786 if (tp < 0) return -EINVAL; 1787 hdw->tuner_type = tp; 1788 hdw->tuner_updated = !0; 1789 return 0; 1790 } 1791 1792 1793 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw) 1794 { 1795 int unit_number = hdw->unit_number; 1796 int tp = 0; 1797 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1798 tp = video_std[unit_number]; 1799 if (tp) return tp; 1800 } 1801 return 0; 1802 } 1803 1804 1805 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw) 1806 { 1807 int unit_number = hdw->unit_number; 1808 int tp = 0; 1809 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1810 tp = tolerance[unit_number]; 1811 } 1812 return tp; 1813 } 1814 1815 1816 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw) 1817 { 1818 /* Try a harmless request to fetch the eeprom's address over 1819 endpoint 1. See what happens. Only the full FX2 image can 1820 respond to this. If this probe fails then likely the FX2 1821 firmware needs be loaded. */ 1822 int result; 1823 LOCK_TAKE(hdw->ctl_lock); do { 1824 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; 1825 result = pvr2_send_request_ex(hdw,HZ*1,!0, 1826 hdw->cmd_buffer,1, 1827 hdw->cmd_buffer,1); 1828 if (result < 0) break; 1829 } while(0); LOCK_GIVE(hdw->ctl_lock); 1830 if (result) { 1831 pvr2_trace(PVR2_TRACE_INIT, 1832 "Probe of device endpoint 1 result status %d", 1833 result); 1834 } else { 1835 pvr2_trace(PVR2_TRACE_INIT, 1836 "Probe of device endpoint 1 succeeded"); 1837 } 1838 return result == 0; 1839 } 1840 1841 struct pvr2_std_hack { 1842 v4l2_std_id pat; /* Pattern to match */ 1843 v4l2_std_id msk; /* Which bits we care about */ 1844 v4l2_std_id std; /* What additional standards or default to set */ 1845 }; 1846 1847 /* This data structure labels specific combinations of standards from 1848 tveeprom that we'll try to recognize. If we recognize one, then assume 1849 a specified default standard to use. This is here because tveeprom only 1850 tells us about available standards not the intended default standard (if 1851 any) for the device in question. We guess the default based on what has 1852 been reported as available. Note that this is only for guessing a 1853 default - which can always be overridden explicitly - and if the user 1854 has otherwise named a default then that default will always be used in 1855 place of this table. */ 1856 static const struct pvr2_std_hack std_eeprom_maps[] = { 1857 { /* PAL(B/G) */ 1858 .pat = V4L2_STD_B|V4L2_STD_GH, 1859 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G, 1860 }, 1861 { /* NTSC(M) */ 1862 .pat = V4L2_STD_MN, 1863 .std = V4L2_STD_NTSC_M, 1864 }, 1865 { /* PAL(I) */ 1866 .pat = V4L2_STD_PAL_I, 1867 .std = V4L2_STD_PAL_I, 1868 }, 1869 { /* SECAM(L/L') */ 1870 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, 1871 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, 1872 }, 1873 { /* PAL(D/D1/K) */ 1874 .pat = V4L2_STD_DK, 1875 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K, 1876 }, 1877 }; 1878 1879 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw) 1880 { 1881 char buf[40]; 1882 unsigned int bcnt; 1883 v4l2_std_id std1,std2,std3; 1884 1885 std1 = get_default_standard(hdw); 1886 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask; 1887 1888 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom); 1889 pvr2_trace(PVR2_TRACE_STD, 1890 "Supported video standard(s) reported available" 1891 " in hardware: %.*s", 1892 bcnt,buf); 1893 1894 hdw->std_mask_avail = hdw->std_mask_eeprom; 1895 1896 std2 = (std1|std3) & ~hdw->std_mask_avail; 1897 if (std2) { 1898 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2); 1899 pvr2_trace(PVR2_TRACE_STD, 1900 "Expanding supported video standards" 1901 " to include: %.*s", 1902 bcnt,buf); 1903 hdw->std_mask_avail |= std2; 1904 } 1905 1906 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; 1907 1908 if (std1) { 1909 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1); 1910 pvr2_trace(PVR2_TRACE_STD, 1911 "Initial video standard forced to %.*s", 1912 bcnt,buf); 1913 hdw->std_mask_cur = std1; 1914 hdw->std_dirty = !0; 1915 return; 1916 } 1917 if (std3) { 1918 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3); 1919 pvr2_trace(PVR2_TRACE_STD, 1920 "Initial video standard" 1921 " (determined by device type): %.*s",bcnt,buf); 1922 hdw->std_mask_cur = std3; 1923 hdw->std_dirty = !0; 1924 return; 1925 } 1926 1927 { 1928 unsigned int idx; 1929 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) { 1930 if (std_eeprom_maps[idx].msk ? 1931 ((std_eeprom_maps[idx].pat ^ 1932 hdw->std_mask_eeprom) & 1933 std_eeprom_maps[idx].msk) : 1934 (std_eeprom_maps[idx].pat != 1935 hdw->std_mask_eeprom)) continue; 1936 bcnt = pvr2_std_id_to_str(buf,sizeof(buf), 1937 std_eeprom_maps[idx].std); 1938 pvr2_trace(PVR2_TRACE_STD, 1939 "Initial video standard guessed as %.*s", 1940 bcnt,buf); 1941 hdw->std_mask_cur = std_eeprom_maps[idx].std; 1942 hdw->std_dirty = !0; 1943 return; 1944 } 1945 } 1946 1947 } 1948 1949 1950 static unsigned int pvr2_copy_i2c_addr_list( 1951 unsigned short *dst, const unsigned char *src, 1952 unsigned int dst_max) 1953 { 1954 unsigned int cnt = 0; 1955 if (!src) return 0; 1956 while (src[cnt] && (cnt + 1) < dst_max) { 1957 dst[cnt] = src[cnt]; 1958 cnt++; 1959 } 1960 dst[cnt] = I2C_CLIENT_END; 1961 return cnt; 1962 } 1963 1964 1965 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw) 1966 { 1967 /* 1968 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness 1969 for cx25840 causes that module to correctly set up its video 1970 scaling. This is really a problem in the cx25840 module itself, 1971 but we work around it here. The problem has not been seen in 1972 ivtv because there VBI is supported and set up. We don't do VBI 1973 here (at least not yet) and thus we never attempted to even set 1974 it up. 1975 */ 1976 struct v4l2_format fmt; 1977 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) { 1978 /* We're not using a cx25840 so don't enable the hack */ 1979 return; 1980 } 1981 1982 pvr2_trace(PVR2_TRACE_INIT, 1983 "Module ID %u:" 1984 " Executing cx25840 VBI hack", 1985 hdw->decoder_client_id); 1986 memset(&fmt, 0, sizeof(fmt)); 1987 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE; 1988 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525; 1989 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525; 1990 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id, 1991 vbi, s_sliced_fmt, &fmt.fmt.sliced); 1992 } 1993 1994 1995 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw, 1996 const struct pvr2_device_client_desc *cd) 1997 { 1998 const char *fname; 1999 unsigned char mid; 2000 struct v4l2_subdev *sd; 2001 unsigned int i2ccnt; 2002 const unsigned char *p; 2003 /* Arbitrary count - max # i2c addresses we will probe */ 2004 unsigned short i2caddr[25]; 2005 2006 mid = cd->module_id; 2007 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL; 2008 if (!fname) { 2009 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2010 "Module ID %u for device %s has no name?" 2011 " The driver might have a configuration problem.", 2012 mid, 2013 hdw->hdw_desc->description); 2014 return -EINVAL; 2015 } 2016 pvr2_trace(PVR2_TRACE_INIT, 2017 "Module ID %u (%s) for device %s being loaded...", 2018 mid, fname, 2019 hdw->hdw_desc->description); 2020 2021 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list, 2022 ARRAY_SIZE(i2caddr)); 2023 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ? 2024 module_i2c_addresses[mid] : NULL) != NULL)) { 2025 /* Second chance: Try default i2c address list */ 2026 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p, 2027 ARRAY_SIZE(i2caddr)); 2028 if (i2ccnt) { 2029 pvr2_trace(PVR2_TRACE_INIT, 2030 "Module ID %u:" 2031 " Using default i2c address list", 2032 mid); 2033 } 2034 } 2035 2036 if (!i2ccnt) { 2037 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2038 "Module ID %u (%s) for device %s:" 2039 " No i2c addresses." 2040 " The driver might have a configuration problem.", 2041 mid, fname, hdw->hdw_desc->description); 2042 return -EINVAL; 2043 } 2044 2045 if (i2ccnt == 1) { 2046 pvr2_trace(PVR2_TRACE_INIT, 2047 "Module ID %u:" 2048 " Setting up with specified i2c address 0x%x", 2049 mid, i2caddr[0]); 2050 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, 2051 fname, i2caddr[0], NULL); 2052 } else { 2053 pvr2_trace(PVR2_TRACE_INIT, 2054 "Module ID %u:" 2055 " Setting up with address probe list", 2056 mid); 2057 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, 2058 fname, 0, i2caddr); 2059 } 2060 2061 if (!sd) { 2062 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2063 "Module ID %u (%s) for device %s failed to load." 2064 " Possible missing sub-device kernel module or" 2065 " initialization failure within module.", 2066 mid, fname, hdw->hdw_desc->description); 2067 return -EIO; 2068 } 2069 2070 /* Tag this sub-device instance with the module ID we know about. 2071 In other places we'll use that tag to determine if the instance 2072 requires special handling. */ 2073 sd->grp_id = mid; 2074 2075 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname); 2076 2077 2078 /* client-specific setup... */ 2079 switch (mid) { 2080 case PVR2_CLIENT_ID_CX25840: 2081 case PVR2_CLIENT_ID_SAA7115: 2082 hdw->decoder_client_id = mid; 2083 break; 2084 default: break; 2085 } 2086 2087 return 0; 2088 } 2089 2090 2091 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw) 2092 { 2093 unsigned int idx; 2094 const struct pvr2_string_table *cm; 2095 const struct pvr2_device_client_table *ct; 2096 int okFl = !0; 2097 2098 cm = &hdw->hdw_desc->client_modules; 2099 for (idx = 0; idx < cm->cnt; idx++) { 2100 request_module(cm->lst[idx]); 2101 } 2102 2103 ct = &hdw->hdw_desc->client_table; 2104 for (idx = 0; idx < ct->cnt; idx++) { 2105 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0; 2106 } 2107 if (!okFl) { 2108 hdw->flag_modulefail = !0; 2109 pvr2_hdw_render_useless(hdw); 2110 } 2111 } 2112 2113 2114 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw) 2115 { 2116 int ret; 2117 unsigned int idx; 2118 struct pvr2_ctrl *cptr; 2119 int reloadFl = 0; 2120 if (hdw->hdw_desc->fx2_firmware.cnt) { 2121 if (!reloadFl) { 2122 reloadFl = 2123 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints 2124 == 0); 2125 if (reloadFl) { 2126 pvr2_trace(PVR2_TRACE_INIT, 2127 "USB endpoint config looks strange" 2128 "; possibly firmware needs to be" 2129 " loaded"); 2130 } 2131 } 2132 if (!reloadFl) { 2133 reloadFl = !pvr2_hdw_check_firmware(hdw); 2134 if (reloadFl) { 2135 pvr2_trace(PVR2_TRACE_INIT, 2136 "Check for FX2 firmware failed" 2137 "; possibly firmware needs to be" 2138 " loaded"); 2139 } 2140 } 2141 if (reloadFl) { 2142 if (pvr2_upload_firmware1(hdw) != 0) { 2143 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2144 "Failure uploading firmware1"); 2145 } 2146 return; 2147 } 2148 } 2149 hdw->fw1_state = FW1_STATE_OK; 2150 2151 if (!pvr2_hdw_dev_ok(hdw)) return; 2152 2153 hdw->force_dirty = !0; 2154 2155 if (!hdw->hdw_desc->flag_no_powerup) { 2156 pvr2_hdw_cmd_powerup(hdw); 2157 if (!pvr2_hdw_dev_ok(hdw)) return; 2158 } 2159 2160 /* Take the IR chip out of reset, if appropriate */ 2161 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) { 2162 pvr2_issue_simple_cmd(hdw, 2163 FX2CMD_HCW_ZILOG_RESET | 2164 (1 << 8) | 2165 ((0) << 16)); 2166 } 2167 2168 // This step MUST happen after the earlier powerup step. 2169 pvr2_i2c_core_init(hdw); 2170 if (!pvr2_hdw_dev_ok(hdw)) return; 2171 2172 pvr2_hdw_load_modules(hdw); 2173 if (!pvr2_hdw_dev_ok(hdw)) return; 2174 2175 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw); 2176 2177 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { 2178 cptr = hdw->controls + idx; 2179 if (cptr->info->skip_init) continue; 2180 if (!cptr->info->set_value) continue; 2181 cptr->info->set_value(cptr,~0,cptr->info->default_value); 2182 } 2183 2184 pvr2_hdw_cx25840_vbi_hack(hdw); 2185 2186 /* Set up special default values for the television and radio 2187 frequencies here. It's not really important what these defaults 2188 are, but I set them to something usable in the Chicago area just 2189 to make driver testing a little easier. */ 2190 2191 hdw->freqValTelevision = default_tv_freq; 2192 hdw->freqValRadio = default_radio_freq; 2193 2194 // Do not use pvr2_reset_ctl_endpoints() here. It is not 2195 // thread-safe against the normal pvr2_send_request() mechanism. 2196 // (We should make it thread safe). 2197 2198 if (hdw->hdw_desc->flag_has_hauppauge_rom) { 2199 ret = pvr2_hdw_get_eeprom_addr(hdw); 2200 if (!pvr2_hdw_dev_ok(hdw)) return; 2201 if (ret < 0) { 2202 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2203 "Unable to determine location of eeprom," 2204 " skipping"); 2205 } else { 2206 hdw->eeprom_addr = ret; 2207 pvr2_eeprom_analyze(hdw); 2208 if (!pvr2_hdw_dev_ok(hdw)) return; 2209 } 2210 } else { 2211 hdw->tuner_type = hdw->hdw_desc->default_tuner_type; 2212 hdw->tuner_updated = !0; 2213 hdw->std_mask_eeprom = V4L2_STD_ALL; 2214 } 2215 2216 if (hdw->serial_number) { 2217 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2218 "sn-%lu", hdw->serial_number); 2219 } else if (hdw->unit_number >= 0) { 2220 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2221 "unit-%c", 2222 hdw->unit_number + 'a'); 2223 } else { 2224 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2225 "unit-??"); 2226 } 2227 hdw->identifier[idx] = 0; 2228 2229 pvr2_hdw_setup_std(hdw); 2230 2231 if (!get_default_tuner_type(hdw)) { 2232 pvr2_trace(PVR2_TRACE_INIT, 2233 "pvr2_hdw_setup: Tuner type overridden to %d", 2234 hdw->tuner_type); 2235 } 2236 2237 2238 if (!pvr2_hdw_dev_ok(hdw)) return; 2239 2240 if (hdw->hdw_desc->signal_routing_scheme == 2241 PVR2_ROUTING_SCHEME_GOTVIEW) { 2242 /* Ensure that GPIO 11 is set to output for GOTVIEW 2243 hardware. */ 2244 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); 2245 } 2246 2247 pvr2_hdw_commit_setup(hdw); 2248 2249 hdw->vid_stream = pvr2_stream_create(); 2250 if (!pvr2_hdw_dev_ok(hdw)) return; 2251 pvr2_trace(PVR2_TRACE_INIT, 2252 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream); 2253 if (hdw->vid_stream) { 2254 idx = get_default_error_tolerance(hdw); 2255 if (idx) { 2256 pvr2_trace(PVR2_TRACE_INIT, 2257 "pvr2_hdw_setup: video stream %p" 2258 " setting tolerance %u", 2259 hdw->vid_stream,idx); 2260 } 2261 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev, 2262 PVR2_VID_ENDPOINT,idx); 2263 } 2264 2265 if (!pvr2_hdw_dev_ok(hdw)) return; 2266 2267 hdw->flag_init_ok = !0; 2268 2269 pvr2_hdw_state_sched(hdw); 2270 } 2271 2272 2273 /* Set up the structure and attempt to put the device into a usable state. 2274 This can be a time-consuming operation, which is why it is not done 2275 internally as part of the create() step. */ 2276 static void pvr2_hdw_setup(struct pvr2_hdw *hdw) 2277 { 2278 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw); 2279 do { 2280 pvr2_hdw_setup_low(hdw); 2281 pvr2_trace(PVR2_TRACE_INIT, 2282 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d", 2283 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok); 2284 if (pvr2_hdw_dev_ok(hdw)) { 2285 if (hdw->flag_init_ok) { 2286 pvr2_trace( 2287 PVR2_TRACE_INFO, 2288 "Device initialization" 2289 " completed successfully."); 2290 break; 2291 } 2292 if (hdw->fw1_state == FW1_STATE_RELOAD) { 2293 pvr2_trace( 2294 PVR2_TRACE_INFO, 2295 "Device microcontroller firmware" 2296 " (re)loaded; it should now reset" 2297 " and reconnect."); 2298 break; 2299 } 2300 pvr2_trace( 2301 PVR2_TRACE_ERROR_LEGS, 2302 "Device initialization was not successful."); 2303 if (hdw->fw1_state == FW1_STATE_MISSING) { 2304 pvr2_trace( 2305 PVR2_TRACE_ERROR_LEGS, 2306 "Giving up since device" 2307 " microcontroller firmware" 2308 " appears to be missing."); 2309 break; 2310 } 2311 } 2312 if (hdw->flag_modulefail) { 2313 pvr2_trace( 2314 PVR2_TRACE_ERROR_LEGS, 2315 "***WARNING*** pvrusb2 driver initialization" 2316 " failed due to the failure of one or more" 2317 " sub-device kernel modules."); 2318 pvr2_trace( 2319 PVR2_TRACE_ERROR_LEGS, 2320 "You need to resolve the failing condition" 2321 " before this driver can function. There" 2322 " should be some earlier messages giving more" 2323 " information about the problem."); 2324 break; 2325 } 2326 if (procreload) { 2327 pvr2_trace( 2328 PVR2_TRACE_ERROR_LEGS, 2329 "Attempting pvrusb2 recovery by reloading" 2330 " primary firmware."); 2331 pvr2_trace( 2332 PVR2_TRACE_ERROR_LEGS, 2333 "If this works, device should disconnect" 2334 " and reconnect in a sane state."); 2335 hdw->fw1_state = FW1_STATE_UNKNOWN; 2336 pvr2_upload_firmware1(hdw); 2337 } else { 2338 pvr2_trace( 2339 PVR2_TRACE_ERROR_LEGS, 2340 "***WARNING*** pvrusb2 device hardware" 2341 " appears to be jammed" 2342 " and I can't clear it."); 2343 pvr2_trace( 2344 PVR2_TRACE_ERROR_LEGS, 2345 "You might need to power cycle" 2346 " the pvrusb2 device" 2347 " in order to recover."); 2348 } 2349 } while (0); 2350 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw); 2351 } 2352 2353 2354 /* Perform second stage initialization. Set callback pointer first so that 2355 we can avoid a possible initialization race (if the kernel thread runs 2356 before the callback has been set). */ 2357 int pvr2_hdw_initialize(struct pvr2_hdw *hdw, 2358 void (*callback_func)(void *), 2359 void *callback_data) 2360 { 2361 LOCK_TAKE(hdw->big_lock); do { 2362 if (hdw->flag_disconnected) { 2363 /* Handle a race here: If we're already 2364 disconnected by this point, then give up. If we 2365 get past this then we'll remain connected for 2366 the duration of initialization since the entire 2367 initialization sequence is now protected by the 2368 big_lock. */ 2369 break; 2370 } 2371 hdw->state_data = callback_data; 2372 hdw->state_func = callback_func; 2373 pvr2_hdw_setup(hdw); 2374 } while (0); LOCK_GIVE(hdw->big_lock); 2375 return hdw->flag_init_ok; 2376 } 2377 2378 2379 /* Create, set up, and return a structure for interacting with the 2380 underlying hardware. */ 2381 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf, 2382 const struct usb_device_id *devid) 2383 { 2384 unsigned int idx,cnt1,cnt2,m; 2385 struct pvr2_hdw *hdw = NULL; 2386 int valid_std_mask; 2387 struct pvr2_ctrl *cptr; 2388 struct usb_device *usb_dev; 2389 const struct pvr2_device_desc *hdw_desc; 2390 __u8 ifnum; 2391 struct v4l2_queryctrl qctrl; 2392 struct pvr2_ctl_info *ciptr; 2393 2394 usb_dev = interface_to_usbdev(intf); 2395 2396 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info); 2397 2398 if (hdw_desc == NULL) { 2399 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:" 2400 " No device description pointer," 2401 " unable to continue."); 2402 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type," 2403 " please contact Mike Isely <isely@pobox.com>" 2404 " to get it included in the driver\n"); 2405 goto fail; 2406 } 2407 2408 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL); 2409 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"", 2410 hdw,hdw_desc->description); 2411 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s", 2412 hdw_desc->description); 2413 if (hdw_desc->flag_is_experimental) { 2414 pvr2_trace(PVR2_TRACE_INFO, "**********"); 2415 pvr2_trace(PVR2_TRACE_INFO, 2416 "WARNING: Support for this device (%s) is" 2417 " experimental.", hdw_desc->description); 2418 pvr2_trace(PVR2_TRACE_INFO, 2419 "Important functionality might not be" 2420 " entirely working."); 2421 pvr2_trace(PVR2_TRACE_INFO, 2422 "Please consider contacting the driver author to" 2423 " help with further stabilization of the driver."); 2424 pvr2_trace(PVR2_TRACE_INFO, "**********"); 2425 } 2426 if (!hdw) goto fail; 2427 2428 setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 2429 (unsigned long)hdw); 2430 2431 setup_timer(&hdw->decoder_stabilization_timer, 2432 pvr2_hdw_decoder_stabilization_timeout, 2433 (unsigned long)hdw); 2434 2435 setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout, 2436 (unsigned long)hdw); 2437 2438 setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 2439 (unsigned long)hdw); 2440 2441 hdw->master_state = PVR2_STATE_DEAD; 2442 2443 init_waitqueue_head(&hdw->state_wait_data); 2444 2445 hdw->tuner_signal_stale = !0; 2446 cx2341x_fill_defaults(&hdw->enc_ctl_state); 2447 2448 /* Calculate which inputs are OK */ 2449 m = 0; 2450 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV; 2451 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) { 2452 m |= 1 << PVR2_CVAL_INPUT_DTV; 2453 } 2454 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO; 2455 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE; 2456 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO; 2457 hdw->input_avail_mask = m; 2458 hdw->input_allowed_mask = hdw->input_avail_mask; 2459 2460 /* If not a hybrid device, pathway_state never changes. So 2461 initialize it here to what it should forever be. */ 2462 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) { 2463 hdw->pathway_state = PVR2_PATHWAY_ANALOG; 2464 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) { 2465 hdw->pathway_state = PVR2_PATHWAY_DIGITAL; 2466 } 2467 2468 hdw->control_cnt = CTRLDEF_COUNT; 2469 hdw->control_cnt += MPEGDEF_COUNT; 2470 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt, 2471 GFP_KERNEL); 2472 if (!hdw->controls) goto fail; 2473 hdw->hdw_desc = hdw_desc; 2474 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme; 2475 for (idx = 0; idx < hdw->control_cnt; idx++) { 2476 cptr = hdw->controls + idx; 2477 cptr->hdw = hdw; 2478 } 2479 for (idx = 0; idx < 32; idx++) { 2480 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx]; 2481 } 2482 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { 2483 cptr = hdw->controls + idx; 2484 cptr->info = control_defs+idx; 2485 } 2486 2487 /* Ensure that default input choice is a valid one. */ 2488 m = hdw->input_avail_mask; 2489 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) { 2490 if (!((1 << idx) & m)) continue; 2491 hdw->input_val = idx; 2492 break; 2493 } 2494 2495 /* Define and configure additional controls from cx2341x module. */ 2496 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT, 2497 sizeof(*(hdw->mpeg_ctrl_info)), 2498 GFP_KERNEL); 2499 if (!hdw->mpeg_ctrl_info) goto fail; 2500 for (idx = 0; idx < MPEGDEF_COUNT; idx++) { 2501 cptr = hdw->controls + idx + CTRLDEF_COUNT; 2502 ciptr = &(hdw->mpeg_ctrl_info[idx].info); 2503 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc; 2504 ciptr->name = mpeg_ids[idx].strid; 2505 ciptr->v4l_id = mpeg_ids[idx].id; 2506 ciptr->skip_init = !0; 2507 ciptr->get_value = ctrl_cx2341x_get; 2508 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags; 2509 ciptr->is_dirty = ctrl_cx2341x_is_dirty; 2510 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty; 2511 qctrl.id = ciptr->v4l_id; 2512 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl); 2513 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) { 2514 ciptr->set_value = ctrl_cx2341x_set; 2515 } 2516 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name, 2517 PVR2_CTLD_INFO_DESC_SIZE); 2518 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0; 2519 ciptr->default_value = qctrl.default_value; 2520 switch (qctrl.type) { 2521 default: 2522 case V4L2_CTRL_TYPE_INTEGER: 2523 ciptr->type = pvr2_ctl_int; 2524 ciptr->def.type_int.min_value = qctrl.minimum; 2525 ciptr->def.type_int.max_value = qctrl.maximum; 2526 break; 2527 case V4L2_CTRL_TYPE_BOOLEAN: 2528 ciptr->type = pvr2_ctl_bool; 2529 break; 2530 case V4L2_CTRL_TYPE_MENU: 2531 ciptr->type = pvr2_ctl_enum; 2532 ciptr->def.type_enum.value_names = 2533 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state, 2534 ciptr->v4l_id); 2535 for (cnt1 = 0; 2536 ciptr->def.type_enum.value_names[cnt1] != NULL; 2537 cnt1++) { } 2538 ciptr->def.type_enum.count = cnt1; 2539 break; 2540 } 2541 cptr->info = ciptr; 2542 } 2543 2544 // Initialize control data regarding video standard masks 2545 valid_std_mask = pvr2_std_get_usable(); 2546 for (idx = 0; idx < 32; idx++) { 2547 if (!(valid_std_mask & (1 << idx))) continue; 2548 cnt1 = pvr2_std_id_to_str( 2549 hdw->std_mask_names[idx], 2550 sizeof(hdw->std_mask_names[idx])-1, 2551 1 << idx); 2552 hdw->std_mask_names[idx][cnt1] = 0; 2553 } 2554 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL); 2555 if (cptr) { 2556 memcpy(&hdw->std_info_avail,cptr->info, 2557 sizeof(hdw->std_info_avail)); 2558 cptr->info = &hdw->std_info_avail; 2559 hdw->std_info_avail.def.type_bitmask.bit_names = 2560 hdw->std_mask_ptrs; 2561 hdw->std_info_avail.def.type_bitmask.valid_bits = 2562 valid_std_mask; 2563 } 2564 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR); 2565 if (cptr) { 2566 memcpy(&hdw->std_info_cur,cptr->info, 2567 sizeof(hdw->std_info_cur)); 2568 cptr->info = &hdw->std_info_cur; 2569 hdw->std_info_cur.def.type_bitmask.bit_names = 2570 hdw->std_mask_ptrs; 2571 hdw->std_info_cur.def.type_bitmask.valid_bits = 2572 valid_std_mask; 2573 } 2574 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT); 2575 if (cptr) { 2576 memcpy(&hdw->std_info_detect,cptr->info, 2577 sizeof(hdw->std_info_detect)); 2578 cptr->info = &hdw->std_info_detect; 2579 hdw->std_info_detect.def.type_bitmask.bit_names = 2580 hdw->std_mask_ptrs; 2581 hdw->std_info_detect.def.type_bitmask.valid_bits = 2582 valid_std_mask; 2583 } 2584 2585 hdw->cropcap_stale = !0; 2586 hdw->eeprom_addr = -1; 2587 hdw->unit_number = -1; 2588 hdw->v4l_minor_number_video = -1; 2589 hdw->v4l_minor_number_vbi = -1; 2590 hdw->v4l_minor_number_radio = -1; 2591 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); 2592 if (!hdw->ctl_write_buffer) goto fail; 2593 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); 2594 if (!hdw->ctl_read_buffer) goto fail; 2595 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL); 2596 if (!hdw->ctl_write_urb) goto fail; 2597 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL); 2598 if (!hdw->ctl_read_urb) goto fail; 2599 2600 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) { 2601 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2602 "Error registering with v4l core, giving up"); 2603 goto fail; 2604 } 2605 mutex_lock(&pvr2_unit_mtx); 2606 do { 2607 for (idx = 0; idx < PVR_NUM; idx++) { 2608 if (unit_pointers[idx]) continue; 2609 hdw->unit_number = idx; 2610 unit_pointers[idx] = hdw; 2611 break; 2612 } 2613 } while (0); 2614 mutex_unlock(&pvr2_unit_mtx); 2615 2616 cnt1 = 0; 2617 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2"); 2618 cnt1 += cnt2; 2619 if (hdw->unit_number >= 0) { 2620 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c", 2621 ('a' + hdw->unit_number)); 2622 cnt1 += cnt2; 2623 } 2624 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1; 2625 hdw->name[cnt1] = 0; 2626 2627 hdw->workqueue = create_singlethread_workqueue(hdw->name); 2628 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll); 2629 2630 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s", 2631 hdw->unit_number,hdw->name); 2632 2633 hdw->tuner_type = -1; 2634 hdw->flag_ok = !0; 2635 2636 hdw->usb_intf = intf; 2637 hdw->usb_dev = usb_dev; 2638 2639 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info)); 2640 2641 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber; 2642 usb_set_interface(hdw->usb_dev,ifnum,0); 2643 2644 mutex_init(&hdw->ctl_lock_mutex); 2645 mutex_init(&hdw->big_lock_mutex); 2646 2647 return hdw; 2648 fail: 2649 if (hdw) { 2650 del_timer_sync(&hdw->quiescent_timer); 2651 del_timer_sync(&hdw->decoder_stabilization_timer); 2652 del_timer_sync(&hdw->encoder_run_timer); 2653 del_timer_sync(&hdw->encoder_wait_timer); 2654 if (hdw->workqueue) { 2655 flush_workqueue(hdw->workqueue); 2656 destroy_workqueue(hdw->workqueue); 2657 hdw->workqueue = NULL; 2658 } 2659 usb_free_urb(hdw->ctl_read_urb); 2660 usb_free_urb(hdw->ctl_write_urb); 2661 kfree(hdw->ctl_read_buffer); 2662 kfree(hdw->ctl_write_buffer); 2663 kfree(hdw->controls); 2664 kfree(hdw->mpeg_ctrl_info); 2665 kfree(hdw); 2666 } 2667 return NULL; 2668 } 2669 2670 2671 /* Remove _all_ associations between this driver and the underlying USB 2672 layer. */ 2673 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw) 2674 { 2675 if (hdw->flag_disconnected) return; 2676 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw); 2677 if (hdw->ctl_read_urb) { 2678 usb_kill_urb(hdw->ctl_read_urb); 2679 usb_free_urb(hdw->ctl_read_urb); 2680 hdw->ctl_read_urb = NULL; 2681 } 2682 if (hdw->ctl_write_urb) { 2683 usb_kill_urb(hdw->ctl_write_urb); 2684 usb_free_urb(hdw->ctl_write_urb); 2685 hdw->ctl_write_urb = NULL; 2686 } 2687 if (hdw->ctl_read_buffer) { 2688 kfree(hdw->ctl_read_buffer); 2689 hdw->ctl_read_buffer = NULL; 2690 } 2691 if (hdw->ctl_write_buffer) { 2692 kfree(hdw->ctl_write_buffer); 2693 hdw->ctl_write_buffer = NULL; 2694 } 2695 hdw->flag_disconnected = !0; 2696 /* If we don't do this, then there will be a dangling struct device 2697 reference to our disappearing device persisting inside the V4L 2698 core... */ 2699 v4l2_device_disconnect(&hdw->v4l2_dev); 2700 hdw->usb_dev = NULL; 2701 hdw->usb_intf = NULL; 2702 pvr2_hdw_render_useless(hdw); 2703 } 2704 2705 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev) 2706 { 2707 vdev->v4l2_dev = &hdw->v4l2_dev; 2708 } 2709 2710 /* Destroy hardware interaction structure */ 2711 void pvr2_hdw_destroy(struct pvr2_hdw *hdw) 2712 { 2713 if (!hdw) return; 2714 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw); 2715 if (hdw->workqueue) { 2716 flush_workqueue(hdw->workqueue); 2717 destroy_workqueue(hdw->workqueue); 2718 hdw->workqueue = NULL; 2719 } 2720 del_timer_sync(&hdw->quiescent_timer); 2721 del_timer_sync(&hdw->decoder_stabilization_timer); 2722 del_timer_sync(&hdw->encoder_run_timer); 2723 del_timer_sync(&hdw->encoder_wait_timer); 2724 if (hdw->fw_buffer) { 2725 kfree(hdw->fw_buffer); 2726 hdw->fw_buffer = NULL; 2727 } 2728 if (hdw->vid_stream) { 2729 pvr2_stream_destroy(hdw->vid_stream); 2730 hdw->vid_stream = NULL; 2731 } 2732 pvr2_i2c_core_done(hdw); 2733 v4l2_device_unregister(&hdw->v4l2_dev); 2734 pvr2_hdw_remove_usb_stuff(hdw); 2735 mutex_lock(&pvr2_unit_mtx); 2736 do { 2737 if ((hdw->unit_number >= 0) && 2738 (hdw->unit_number < PVR_NUM) && 2739 (unit_pointers[hdw->unit_number] == hdw)) { 2740 unit_pointers[hdw->unit_number] = NULL; 2741 } 2742 } while (0); 2743 mutex_unlock(&pvr2_unit_mtx); 2744 kfree(hdw->controls); 2745 kfree(hdw->mpeg_ctrl_info); 2746 kfree(hdw); 2747 } 2748 2749 2750 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw) 2751 { 2752 return (hdw && hdw->flag_ok); 2753 } 2754 2755 2756 /* Called when hardware has been unplugged */ 2757 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw) 2758 { 2759 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw); 2760 LOCK_TAKE(hdw->big_lock); 2761 LOCK_TAKE(hdw->ctl_lock); 2762 pvr2_hdw_remove_usb_stuff(hdw); 2763 LOCK_GIVE(hdw->ctl_lock); 2764 LOCK_GIVE(hdw->big_lock); 2765 } 2766 2767 2768 /* Get the number of defined controls */ 2769 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw) 2770 { 2771 return hdw->control_cnt; 2772 } 2773 2774 2775 /* Retrieve a control handle given its index (0..count-1) */ 2776 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw, 2777 unsigned int idx) 2778 { 2779 if (idx >= hdw->control_cnt) return NULL; 2780 return hdw->controls + idx; 2781 } 2782 2783 2784 /* Retrieve a control handle given its index (0..count-1) */ 2785 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw, 2786 unsigned int ctl_id) 2787 { 2788 struct pvr2_ctrl *cptr; 2789 unsigned int idx; 2790 int i; 2791 2792 /* This could be made a lot more efficient, but for now... */ 2793 for (idx = 0; idx < hdw->control_cnt; idx++) { 2794 cptr = hdw->controls + idx; 2795 i = cptr->info->internal_id; 2796 if (i && (i == ctl_id)) return cptr; 2797 } 2798 return NULL; 2799 } 2800 2801 2802 /* Given a V4L ID, retrieve the control structure associated with it. */ 2803 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id) 2804 { 2805 struct pvr2_ctrl *cptr; 2806 unsigned int idx; 2807 int i; 2808 2809 /* This could be made a lot more efficient, but for now... */ 2810 for (idx = 0; idx < hdw->control_cnt; idx++) { 2811 cptr = hdw->controls + idx; 2812 i = cptr->info->v4l_id; 2813 if (i && (i == ctl_id)) return cptr; 2814 } 2815 return NULL; 2816 } 2817 2818 2819 /* Given a V4L ID for its immediate predecessor, retrieve the control 2820 structure associated with it. */ 2821 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw, 2822 unsigned int ctl_id) 2823 { 2824 struct pvr2_ctrl *cptr,*cp2; 2825 unsigned int idx; 2826 int i; 2827 2828 /* This could be made a lot more efficient, but for now... */ 2829 cp2 = NULL; 2830 for (idx = 0; idx < hdw->control_cnt; idx++) { 2831 cptr = hdw->controls + idx; 2832 i = cptr->info->v4l_id; 2833 if (!i) continue; 2834 if (i <= ctl_id) continue; 2835 if (cp2 && (cp2->info->v4l_id < i)) continue; 2836 cp2 = cptr; 2837 } 2838 return cp2; 2839 return NULL; 2840 } 2841 2842 2843 static const char *get_ctrl_typename(enum pvr2_ctl_type tp) 2844 { 2845 switch (tp) { 2846 case pvr2_ctl_int: return "integer"; 2847 case pvr2_ctl_enum: return "enum"; 2848 case pvr2_ctl_bool: return "boolean"; 2849 case pvr2_ctl_bitmask: return "bitmask"; 2850 } 2851 return ""; 2852 } 2853 2854 2855 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id, 2856 const char *name, int val) 2857 { 2858 struct v4l2_control ctrl; 2859 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val); 2860 memset(&ctrl, 0, sizeof(ctrl)); 2861 ctrl.id = id; 2862 ctrl.value = val; 2863 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl); 2864 } 2865 2866 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \ 2867 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \ 2868 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \ 2869 } 2870 2871 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw) 2872 { 2873 v4l2_std_id std; 2874 std = (v4l2_std_id)hdw->std_mask_avail; 2875 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2876 video, querystd, &std); 2877 return std; 2878 } 2879 2880 /* Execute whatever commands are required to update the state of all the 2881 sub-devices so that they match our current control values. */ 2882 static void pvr2_subdev_update(struct pvr2_hdw *hdw) 2883 { 2884 struct v4l2_subdev *sd; 2885 unsigned int id; 2886 pvr2_subdev_update_func fp; 2887 2888 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update..."); 2889 2890 if (hdw->tuner_updated || hdw->force_dirty) { 2891 struct tuner_setup setup; 2892 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)", 2893 hdw->tuner_type); 2894 if (((int)(hdw->tuner_type)) >= 0) { 2895 memset(&setup, 0, sizeof(setup)); 2896 setup.addr = ADDR_UNSET; 2897 setup.type = hdw->tuner_type; 2898 setup.mode_mask = T_RADIO | T_ANALOG_TV; 2899 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2900 tuner, s_type_addr, &setup); 2901 } 2902 } 2903 2904 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) { 2905 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard"); 2906 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 2907 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2908 tuner, s_radio); 2909 } else { 2910 v4l2_std_id vs; 2911 vs = hdw->std_mask_cur; 2912 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2913 video, s_std, vs); 2914 pvr2_hdw_cx25840_vbi_hack(hdw); 2915 } 2916 hdw->tuner_signal_stale = !0; 2917 hdw->cropcap_stale = !0; 2918 } 2919 2920 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness); 2921 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast); 2922 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation); 2923 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue); 2924 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute); 2925 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume); 2926 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance); 2927 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass); 2928 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble); 2929 2930 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) { 2931 struct v4l2_tuner vt; 2932 memset(&vt, 0, sizeof(vt)); 2933 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ? 2934 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; 2935 vt.audmode = hdw->audiomode_val; 2936 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt); 2937 } 2938 2939 if (hdw->freqDirty || hdw->force_dirty) { 2940 unsigned long fv; 2941 struct v4l2_frequency freq; 2942 fv = pvr2_hdw_get_cur_freq(hdw); 2943 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv); 2944 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw); 2945 memset(&freq, 0, sizeof(freq)); 2946 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 2947 /* ((fv * 1000) / 62500) */ 2948 freq.frequency = (fv * 2) / 125; 2949 } else { 2950 freq.frequency = fv / 62500; 2951 } 2952 /* tuner-core currently doesn't seem to care about this, but 2953 let's set it anyway for completeness. */ 2954 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 2955 freq.type = V4L2_TUNER_RADIO; 2956 } else { 2957 freq.type = V4L2_TUNER_ANALOG_TV; 2958 } 2959 freq.tuner = 0; 2960 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, 2961 s_frequency, &freq); 2962 } 2963 2964 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) { 2965 struct v4l2_subdev_format format = { 2966 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 2967 }; 2968 2969 format.format.width = hdw->res_hor_val; 2970 format.format.height = hdw->res_ver_val; 2971 format.format.code = MEDIA_BUS_FMT_FIXED; 2972 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)", 2973 format.format.width, format.format.height); 2974 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt, 2975 NULL, &format); 2976 } 2977 2978 if (hdw->srate_dirty || hdw->force_dirty) { 2979 u32 val; 2980 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d", 2981 hdw->srate_val); 2982 switch (hdw->srate_val) { 2983 default: 2984 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000: 2985 val = 48000; 2986 break; 2987 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100: 2988 val = 44100; 2989 break; 2990 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000: 2991 val = 32000; 2992 break; 2993 } 2994 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2995 audio, s_clock_freq, val); 2996 } 2997 2998 /* Unable to set crop parameters; there is apparently no equivalent 2999 for VIDIOC_S_CROP */ 3000 3001 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) { 3002 id = sd->grp_id; 3003 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue; 3004 fp = pvr2_module_update_functions[id]; 3005 if (!fp) continue; 3006 (*fp)(hdw, sd); 3007 } 3008 3009 if (hdw->tuner_signal_stale || hdw->cropcap_stale) { 3010 pvr2_hdw_status_poll(hdw); 3011 } 3012 } 3013 3014 3015 /* Figure out if we need to commit control changes. If so, mark internal 3016 state flags to indicate this fact and return true. Otherwise do nothing 3017 else and return false. */ 3018 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw) 3019 { 3020 unsigned int idx; 3021 struct pvr2_ctrl *cptr; 3022 int value; 3023 int commit_flag = hdw->force_dirty; 3024 char buf[100]; 3025 unsigned int bcnt,ccnt; 3026 3027 for (idx = 0; idx < hdw->control_cnt; idx++) { 3028 cptr = hdw->controls + idx; 3029 if (!cptr->info->is_dirty) continue; 3030 if (!cptr->info->is_dirty(cptr)) continue; 3031 commit_flag = !0; 3032 3033 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue; 3034 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ", 3035 cptr->info->name); 3036 value = 0; 3037 cptr->info->get_value(cptr,&value); 3038 pvr2_ctrl_value_to_sym_internal(cptr,~0,value, 3039 buf+bcnt, 3040 sizeof(buf)-bcnt,&ccnt); 3041 bcnt += ccnt; 3042 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>", 3043 get_ctrl_typename(cptr->info->type)); 3044 pvr2_trace(PVR2_TRACE_CTL, 3045 "/*--TRACE_COMMIT--*/ %.*s", 3046 bcnt,buf); 3047 } 3048 3049 if (!commit_flag) { 3050 /* Nothing has changed */ 3051 return 0; 3052 } 3053 3054 hdw->state_pipeline_config = 0; 3055 trace_stbit("state_pipeline_config",hdw->state_pipeline_config); 3056 pvr2_hdw_state_sched(hdw); 3057 3058 return !0; 3059 } 3060 3061 3062 /* Perform all operations needed to commit all control changes. This must 3063 be performed in synchronization with the pipeline state and is thus 3064 expected to be called as part of the driver's worker thread. Return 3065 true if commit successful, otherwise return false to indicate that 3066 commit isn't possible at this time. */ 3067 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw) 3068 { 3069 unsigned int idx; 3070 struct pvr2_ctrl *cptr; 3071 int disruptive_change; 3072 3073 if (hdw->input_dirty && hdw->state_pathway_ok && 3074 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ? 3075 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) != 3076 hdw->pathway_state)) { 3077 /* Change of mode being asked for... */ 3078 hdw->state_pathway_ok = 0; 3079 trace_stbit("state_pathway_ok", hdw->state_pathway_ok); 3080 } 3081 if (!hdw->state_pathway_ok) { 3082 /* Can't commit anything until pathway is ok. */ 3083 return 0; 3084 } 3085 3086 /* Handle some required side effects when the video standard is 3087 changed.... */ 3088 if (hdw->std_dirty) { 3089 int nvres; 3090 int gop_size; 3091 if (hdw->std_mask_cur & V4L2_STD_525_60) { 3092 nvres = 480; 3093 gop_size = 15; 3094 } else { 3095 nvres = 576; 3096 gop_size = 12; 3097 } 3098 /* Rewrite the vertical resolution to be appropriate to the 3099 video standard that has been selected. */ 3100 if (nvres != hdw->res_ver_val) { 3101 hdw->res_ver_val = nvres; 3102 hdw->res_ver_dirty = !0; 3103 } 3104 /* Rewrite the GOP size to be appropriate to the video 3105 standard that has been selected. */ 3106 if (gop_size != hdw->enc_ctl_state.video_gop_size) { 3107 struct v4l2_ext_controls cs; 3108 struct v4l2_ext_control c1; 3109 memset(&cs, 0, sizeof(cs)); 3110 memset(&c1, 0, sizeof(c1)); 3111 cs.controls = &c1; 3112 cs.count = 1; 3113 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE; 3114 c1.value = gop_size; 3115 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs, 3116 VIDIOC_S_EXT_CTRLS); 3117 } 3118 } 3119 3120 /* The broadcast decoder can only scale down, so if 3121 * res_*_dirty && crop window < output format ==> enlarge crop. 3122 * 3123 * The mpeg encoder receives fields of res_hor_val dots and 3124 * res_ver_val halflines. Limits: hor<=720, ver<=576. 3125 */ 3126 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) { 3127 hdw->cropw_val = hdw->res_hor_val; 3128 hdw->cropw_dirty = !0; 3129 } else if (hdw->cropw_dirty) { 3130 hdw->res_hor_dirty = !0; /* must rescale */ 3131 hdw->res_hor_val = min(720, hdw->cropw_val); 3132 } 3133 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) { 3134 hdw->croph_val = hdw->res_ver_val; 3135 hdw->croph_dirty = !0; 3136 } else if (hdw->croph_dirty) { 3137 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576; 3138 hdw->res_ver_dirty = !0; 3139 hdw->res_ver_val = min(nvres, hdw->croph_val); 3140 } 3141 3142 /* If any of the below has changed, then we can't do the update 3143 while the pipeline is running. Pipeline must be paused first 3144 and decoder -> encoder connection be made quiescent before we 3145 can proceed. */ 3146 disruptive_change = 3147 (hdw->std_dirty || 3148 hdw->enc_unsafe_stale || 3149 hdw->srate_dirty || 3150 hdw->res_ver_dirty || 3151 hdw->res_hor_dirty || 3152 hdw->cropw_dirty || 3153 hdw->croph_dirty || 3154 hdw->input_dirty || 3155 (hdw->active_stream_type != hdw->desired_stream_type)); 3156 if (disruptive_change && !hdw->state_pipeline_idle) { 3157 /* Pipeline is not idle; we can't proceed. Arrange to 3158 cause pipeline to stop so that we can try this again 3159 later.... */ 3160 hdw->state_pipeline_pause = !0; 3161 return 0; 3162 } 3163 3164 if (hdw->srate_dirty) { 3165 /* Write new sample rate into control structure since 3166 * the master copy is stale. We must track srate 3167 * separate from the mpeg control structure because 3168 * other logic also uses this value. */ 3169 struct v4l2_ext_controls cs; 3170 struct v4l2_ext_control c1; 3171 memset(&cs,0,sizeof(cs)); 3172 memset(&c1,0,sizeof(c1)); 3173 cs.controls = &c1; 3174 cs.count = 1; 3175 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ; 3176 c1.value = hdw->srate_val; 3177 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS); 3178 } 3179 3180 if (hdw->active_stream_type != hdw->desired_stream_type) { 3181 /* Handle any side effects of stream config here */ 3182 hdw->active_stream_type = hdw->desired_stream_type; 3183 } 3184 3185 if (hdw->hdw_desc->signal_routing_scheme == 3186 PVR2_ROUTING_SCHEME_GOTVIEW) { 3187 u32 b; 3188 /* Handle GOTVIEW audio switching */ 3189 pvr2_hdw_gpio_get_out(hdw,&b); 3190 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 3191 /* Set GPIO 11 */ 3192 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0); 3193 } else { 3194 /* Clear GPIO 11 */ 3195 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0); 3196 } 3197 } 3198 3199 /* Check and update state for all sub-devices. */ 3200 pvr2_subdev_update(hdw); 3201 3202 hdw->tuner_updated = 0; 3203 hdw->force_dirty = 0; 3204 for (idx = 0; idx < hdw->control_cnt; idx++) { 3205 cptr = hdw->controls + idx; 3206 if (!cptr->info->clear_dirty) continue; 3207 cptr->info->clear_dirty(cptr); 3208 } 3209 3210 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) && 3211 hdw->state_encoder_run) { 3212 /* If encoder isn't running or it can't be touched, then 3213 this will get worked out later when we start the 3214 encoder. */ 3215 if (pvr2_encoder_adjust(hdw) < 0) return !0; 3216 } 3217 3218 hdw->state_pipeline_config = !0; 3219 /* Hardware state may have changed in a way to cause the cropping 3220 capabilities to have changed. So mark it stale, which will 3221 cause a later re-fetch. */ 3222 trace_stbit("state_pipeline_config",hdw->state_pipeline_config); 3223 return !0; 3224 } 3225 3226 3227 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw) 3228 { 3229 int fl; 3230 LOCK_TAKE(hdw->big_lock); 3231 fl = pvr2_hdw_commit_setup(hdw); 3232 LOCK_GIVE(hdw->big_lock); 3233 if (!fl) return 0; 3234 return pvr2_hdw_wait(hdw,0); 3235 } 3236 3237 3238 static void pvr2_hdw_worker_poll(struct work_struct *work) 3239 { 3240 int fl = 0; 3241 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll); 3242 LOCK_TAKE(hdw->big_lock); do { 3243 fl = pvr2_hdw_state_eval(hdw); 3244 } while (0); LOCK_GIVE(hdw->big_lock); 3245 if (fl && hdw->state_func) { 3246 hdw->state_func(hdw->state_data); 3247 } 3248 } 3249 3250 3251 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state) 3252 { 3253 return wait_event_interruptible( 3254 hdw->state_wait_data, 3255 (hdw->state_stale == 0) && 3256 (!state || (hdw->master_state != state))); 3257 } 3258 3259 3260 /* Return name for this driver instance */ 3261 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw) 3262 { 3263 return hdw->name; 3264 } 3265 3266 3267 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw) 3268 { 3269 return hdw->hdw_desc->description; 3270 } 3271 3272 3273 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw) 3274 { 3275 return hdw->hdw_desc->shortname; 3276 } 3277 3278 3279 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw) 3280 { 3281 int result; 3282 LOCK_TAKE(hdw->ctl_lock); do { 3283 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED; 3284 result = pvr2_send_request(hdw, 3285 hdw->cmd_buffer,1, 3286 hdw->cmd_buffer,1); 3287 if (result < 0) break; 3288 result = (hdw->cmd_buffer[0] != 0); 3289 } while(0); LOCK_GIVE(hdw->ctl_lock); 3290 return result; 3291 } 3292 3293 3294 /* Execute poll of tuner status */ 3295 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw) 3296 { 3297 LOCK_TAKE(hdw->big_lock); do { 3298 pvr2_hdw_status_poll(hdw); 3299 } while (0); LOCK_GIVE(hdw->big_lock); 3300 } 3301 3302 3303 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw) 3304 { 3305 if (!hdw->cropcap_stale) { 3306 return 0; 3307 } 3308 pvr2_hdw_status_poll(hdw); 3309 if (hdw->cropcap_stale) { 3310 return -EIO; 3311 } 3312 return 0; 3313 } 3314 3315 3316 /* Return information about cropping capabilities */ 3317 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp) 3318 { 3319 int stat = 0; 3320 LOCK_TAKE(hdw->big_lock); 3321 stat = pvr2_hdw_check_cropcap(hdw); 3322 if (!stat) { 3323 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info)); 3324 } 3325 LOCK_GIVE(hdw->big_lock); 3326 return stat; 3327 } 3328 3329 3330 /* Return information about the tuner */ 3331 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp) 3332 { 3333 LOCK_TAKE(hdw->big_lock); do { 3334 if (hdw->tuner_signal_stale) { 3335 pvr2_hdw_status_poll(hdw); 3336 } 3337 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner)); 3338 } while (0); LOCK_GIVE(hdw->big_lock); 3339 return 0; 3340 } 3341 3342 3343 /* Get handle to video output stream */ 3344 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp) 3345 { 3346 return hp->vid_stream; 3347 } 3348 3349 3350 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw) 3351 { 3352 int nr = pvr2_hdw_get_unit_number(hdw); 3353 LOCK_TAKE(hdw->big_lock); 3354 do { 3355 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr); 3356 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status); 3357 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:"); 3358 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2"); 3359 pvr2_hdw_state_log_state(hdw); 3360 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr); 3361 } while (0); 3362 LOCK_GIVE(hdw->big_lock); 3363 } 3364 3365 3366 /* Grab EEPROM contents, needed for direct method. */ 3367 #define EEPROM_SIZE 8192 3368 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__) 3369 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw) 3370 { 3371 struct i2c_msg msg[2]; 3372 u8 *eeprom; 3373 u8 iadd[2]; 3374 u8 addr; 3375 u16 eepromSize; 3376 unsigned int offs; 3377 int ret; 3378 int mode16 = 0; 3379 unsigned pcnt,tcnt; 3380 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL); 3381 if (!eeprom) { 3382 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3383 "Failed to allocate memory" 3384 " required to read eeprom"); 3385 return NULL; 3386 } 3387 3388 trace_eeprom("Value for eeprom addr from controller was 0x%x", 3389 hdw->eeprom_addr); 3390 addr = hdw->eeprom_addr; 3391 /* Seems that if the high bit is set, then the *real* eeprom 3392 address is shifted right now bit position (noticed this in 3393 newer PVR USB2 hardware) */ 3394 if (addr & 0x80) addr >>= 1; 3395 3396 /* FX2 documentation states that a 16bit-addressed eeprom is 3397 expected if the I2C address is an odd number (yeah, this is 3398 strange but it's what they do) */ 3399 mode16 = (addr & 1); 3400 eepromSize = (mode16 ? EEPROM_SIZE : 256); 3401 trace_eeprom("Examining %d byte eeprom at location 0x%x" 3402 " using %d bit addressing",eepromSize,addr, 3403 mode16 ? 16 : 8); 3404 3405 msg[0].addr = addr; 3406 msg[0].flags = 0; 3407 msg[0].len = mode16 ? 2 : 1; 3408 msg[0].buf = iadd; 3409 msg[1].addr = addr; 3410 msg[1].flags = I2C_M_RD; 3411 3412 /* We have to do the actual eeprom data fetch ourselves, because 3413 (1) we're only fetching part of the eeprom, and (2) if we were 3414 getting the whole thing our I2C driver can't grab it in one 3415 pass - which is what tveeprom is otherwise going to attempt */ 3416 memset(eeprom,0,EEPROM_SIZE); 3417 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) { 3418 pcnt = 16; 3419 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt; 3420 offs = tcnt + (eepromSize - EEPROM_SIZE); 3421 if (mode16) { 3422 iadd[0] = offs >> 8; 3423 iadd[1] = offs; 3424 } else { 3425 iadd[0] = offs; 3426 } 3427 msg[1].len = pcnt; 3428 msg[1].buf = eeprom+tcnt; 3429 if ((ret = i2c_transfer(&hdw->i2c_adap, 3430 msg,ARRAY_SIZE(msg))) != 2) { 3431 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3432 "eeprom fetch set offs err=%d",ret); 3433 kfree(eeprom); 3434 return NULL; 3435 } 3436 } 3437 return eeprom; 3438 } 3439 3440 3441 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, 3442 int mode, 3443 int enable_flag) 3444 { 3445 int ret; 3446 u16 address; 3447 unsigned int pipe; 3448 LOCK_TAKE(hdw->big_lock); do { 3449 if ((hdw->fw_buffer == NULL) == !enable_flag) break; 3450 3451 if (!enable_flag) { 3452 pvr2_trace(PVR2_TRACE_FIRMWARE, 3453 "Cleaning up after CPU firmware fetch"); 3454 kfree(hdw->fw_buffer); 3455 hdw->fw_buffer = NULL; 3456 hdw->fw_size = 0; 3457 if (hdw->fw_cpu_flag) { 3458 /* Now release the CPU. It will disconnect 3459 and reconnect later. */ 3460 pvr2_hdw_cpureset_assert(hdw,0); 3461 } 3462 break; 3463 } 3464 3465 hdw->fw_cpu_flag = (mode != 2); 3466 if (hdw->fw_cpu_flag) { 3467 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000; 3468 pvr2_trace(PVR2_TRACE_FIRMWARE, 3469 "Preparing to suck out CPU firmware" 3470 " (size=%u)", hdw->fw_size); 3471 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL); 3472 if (!hdw->fw_buffer) { 3473 hdw->fw_size = 0; 3474 break; 3475 } 3476 3477 /* We have to hold the CPU during firmware upload. */ 3478 pvr2_hdw_cpureset_assert(hdw,1); 3479 3480 /* download the firmware from address 0000-1fff in 2048 3481 (=0x800) bytes chunk. */ 3482 3483 pvr2_trace(PVR2_TRACE_FIRMWARE, 3484 "Grabbing CPU firmware"); 3485 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0); 3486 for(address = 0; address < hdw->fw_size; 3487 address += 0x800) { 3488 ret = usb_control_msg(hdw->usb_dev,pipe, 3489 0xa0,0xc0, 3490 address,0, 3491 hdw->fw_buffer+address, 3492 0x800,HZ); 3493 if (ret < 0) break; 3494 } 3495 3496 pvr2_trace(PVR2_TRACE_FIRMWARE, 3497 "Done grabbing CPU firmware"); 3498 } else { 3499 pvr2_trace(PVR2_TRACE_FIRMWARE, 3500 "Sucking down EEPROM contents"); 3501 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw); 3502 if (!hdw->fw_buffer) { 3503 pvr2_trace(PVR2_TRACE_FIRMWARE, 3504 "EEPROM content suck failed."); 3505 break; 3506 } 3507 hdw->fw_size = EEPROM_SIZE; 3508 pvr2_trace(PVR2_TRACE_FIRMWARE, 3509 "Done sucking down EEPROM contents"); 3510 } 3511 3512 } while (0); LOCK_GIVE(hdw->big_lock); 3513 } 3514 3515 3516 /* Return true if we're in a mode for retrieval CPU firmware */ 3517 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw) 3518 { 3519 return hdw->fw_buffer != NULL; 3520 } 3521 3522 3523 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs, 3524 char *buf,unsigned int cnt) 3525 { 3526 int ret = -EINVAL; 3527 LOCK_TAKE(hdw->big_lock); do { 3528 if (!buf) break; 3529 if (!cnt) break; 3530 3531 if (!hdw->fw_buffer) { 3532 ret = -EIO; 3533 break; 3534 } 3535 3536 if (offs >= hdw->fw_size) { 3537 pvr2_trace(PVR2_TRACE_FIRMWARE, 3538 "Read firmware data offs=%d EOF", 3539 offs); 3540 ret = 0; 3541 break; 3542 } 3543 3544 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs; 3545 3546 memcpy(buf,hdw->fw_buffer+offs,cnt); 3547 3548 pvr2_trace(PVR2_TRACE_FIRMWARE, 3549 "Read firmware data offs=%d cnt=%d", 3550 offs,cnt); 3551 ret = cnt; 3552 } while (0); LOCK_GIVE(hdw->big_lock); 3553 3554 return ret; 3555 } 3556 3557 3558 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw, 3559 enum pvr2_v4l_type index) 3560 { 3561 switch (index) { 3562 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video; 3563 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi; 3564 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio; 3565 default: return -1; 3566 } 3567 } 3568 3569 3570 /* Store a v4l minor device number */ 3571 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw, 3572 enum pvr2_v4l_type index,int v) 3573 { 3574 switch (index) { 3575 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break; 3576 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break; 3577 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break; 3578 default: break; 3579 } 3580 } 3581 3582 3583 static void pvr2_ctl_write_complete(struct urb *urb) 3584 { 3585 struct pvr2_hdw *hdw = urb->context; 3586 hdw->ctl_write_pend_flag = 0; 3587 if (hdw->ctl_read_pend_flag) return; 3588 complete(&hdw->ctl_done); 3589 } 3590 3591 3592 static void pvr2_ctl_read_complete(struct urb *urb) 3593 { 3594 struct pvr2_hdw *hdw = urb->context; 3595 hdw->ctl_read_pend_flag = 0; 3596 if (hdw->ctl_write_pend_flag) return; 3597 complete(&hdw->ctl_done); 3598 } 3599 3600 3601 static void pvr2_ctl_timeout(unsigned long data) 3602 { 3603 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 3604 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 3605 hdw->ctl_timeout_flag = !0; 3606 if (hdw->ctl_write_pend_flag) 3607 usb_unlink_urb(hdw->ctl_write_urb); 3608 if (hdw->ctl_read_pend_flag) 3609 usb_unlink_urb(hdw->ctl_read_urb); 3610 } 3611 } 3612 3613 3614 /* Issue a command and get a response from the device. This extended 3615 version includes a probe flag (which if set means that device errors 3616 should not be logged or treated as fatal) and a timeout in jiffies. 3617 This can be used to non-lethally probe the health of endpoint 1. */ 3618 static int pvr2_send_request_ex(struct pvr2_hdw *hdw, 3619 unsigned int timeout,int probe_fl, 3620 void *write_data,unsigned int write_len, 3621 void *read_data,unsigned int read_len) 3622 { 3623 unsigned int idx; 3624 int status = 0; 3625 struct timer_list timer; 3626 if (!hdw->ctl_lock_held) { 3627 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3628 "Attempted to execute control transfer" 3629 " without lock!!"); 3630 return -EDEADLK; 3631 } 3632 if (!hdw->flag_ok && !probe_fl) { 3633 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3634 "Attempted to execute control transfer" 3635 " when device not ok"); 3636 return -EIO; 3637 } 3638 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) { 3639 if (!probe_fl) { 3640 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3641 "Attempted to execute control transfer" 3642 " when USB is disconnected"); 3643 } 3644 return -ENOTTY; 3645 } 3646 3647 /* Ensure that we have sane parameters */ 3648 if (!write_data) write_len = 0; 3649 if (!read_data) read_len = 0; 3650 if (write_len > PVR2_CTL_BUFFSIZE) { 3651 pvr2_trace( 3652 PVR2_TRACE_ERROR_LEGS, 3653 "Attempted to execute %d byte" 3654 " control-write transfer (limit=%d)", 3655 write_len,PVR2_CTL_BUFFSIZE); 3656 return -EINVAL; 3657 } 3658 if (read_len > PVR2_CTL_BUFFSIZE) { 3659 pvr2_trace( 3660 PVR2_TRACE_ERROR_LEGS, 3661 "Attempted to execute %d byte" 3662 " control-read transfer (limit=%d)", 3663 write_len,PVR2_CTL_BUFFSIZE); 3664 return -EINVAL; 3665 } 3666 if ((!write_len) && (!read_len)) { 3667 pvr2_trace( 3668 PVR2_TRACE_ERROR_LEGS, 3669 "Attempted to execute null control transfer?"); 3670 return -EINVAL; 3671 } 3672 3673 3674 hdw->cmd_debug_state = 1; 3675 if (write_len && write_data) 3676 hdw->cmd_debug_code = ((unsigned char *)write_data)[0]; 3677 else 3678 hdw->cmd_debug_code = 0; 3679 hdw->cmd_debug_write_len = write_len; 3680 hdw->cmd_debug_read_len = read_len; 3681 3682 /* Initialize common stuff */ 3683 init_completion(&hdw->ctl_done); 3684 hdw->ctl_timeout_flag = 0; 3685 hdw->ctl_write_pend_flag = 0; 3686 hdw->ctl_read_pend_flag = 0; 3687 setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw); 3688 timer.expires = jiffies + timeout; 3689 3690 if (write_len && write_data) { 3691 hdw->cmd_debug_state = 2; 3692 /* Transfer write data to internal buffer */ 3693 for (idx = 0; idx < write_len; idx++) { 3694 hdw->ctl_write_buffer[idx] = 3695 ((unsigned char *)write_data)[idx]; 3696 } 3697 /* Initiate a write request */ 3698 usb_fill_bulk_urb(hdw->ctl_write_urb, 3699 hdw->usb_dev, 3700 usb_sndbulkpipe(hdw->usb_dev, 3701 PVR2_CTL_WRITE_ENDPOINT), 3702 hdw->ctl_write_buffer, 3703 write_len, 3704 pvr2_ctl_write_complete, 3705 hdw); 3706 hdw->ctl_write_urb->actual_length = 0; 3707 hdw->ctl_write_pend_flag = !0; 3708 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL); 3709 if (status < 0) { 3710 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3711 "Failed to submit write-control" 3712 " URB status=%d",status); 3713 hdw->ctl_write_pend_flag = 0; 3714 goto done; 3715 } 3716 } 3717 3718 if (read_len) { 3719 hdw->cmd_debug_state = 3; 3720 memset(hdw->ctl_read_buffer,0x43,read_len); 3721 /* Initiate a read request */ 3722 usb_fill_bulk_urb(hdw->ctl_read_urb, 3723 hdw->usb_dev, 3724 usb_rcvbulkpipe(hdw->usb_dev, 3725 PVR2_CTL_READ_ENDPOINT), 3726 hdw->ctl_read_buffer, 3727 read_len, 3728 pvr2_ctl_read_complete, 3729 hdw); 3730 hdw->ctl_read_urb->actual_length = 0; 3731 hdw->ctl_read_pend_flag = !0; 3732 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL); 3733 if (status < 0) { 3734 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3735 "Failed to submit read-control" 3736 " URB status=%d",status); 3737 hdw->ctl_read_pend_flag = 0; 3738 goto done; 3739 } 3740 } 3741 3742 /* Start timer */ 3743 add_timer(&timer); 3744 3745 /* Now wait for all I/O to complete */ 3746 hdw->cmd_debug_state = 4; 3747 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 3748 wait_for_completion(&hdw->ctl_done); 3749 } 3750 hdw->cmd_debug_state = 5; 3751 3752 /* Stop timer */ 3753 del_timer_sync(&timer); 3754 3755 hdw->cmd_debug_state = 6; 3756 status = 0; 3757 3758 if (hdw->ctl_timeout_flag) { 3759 status = -ETIMEDOUT; 3760 if (!probe_fl) { 3761 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3762 "Timed out control-write"); 3763 } 3764 goto done; 3765 } 3766 3767 if (write_len) { 3768 /* Validate results of write request */ 3769 if ((hdw->ctl_write_urb->status != 0) && 3770 (hdw->ctl_write_urb->status != -ENOENT) && 3771 (hdw->ctl_write_urb->status != -ESHUTDOWN) && 3772 (hdw->ctl_write_urb->status != -ECONNRESET)) { 3773 /* USB subsystem is reporting some kind of failure 3774 on the write */ 3775 status = hdw->ctl_write_urb->status; 3776 if (!probe_fl) { 3777 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3778 "control-write URB failure," 3779 " status=%d", 3780 status); 3781 } 3782 goto done; 3783 } 3784 if (hdw->ctl_write_urb->actual_length < write_len) { 3785 /* Failed to write enough data */ 3786 status = -EIO; 3787 if (!probe_fl) { 3788 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3789 "control-write URB short," 3790 " expected=%d got=%d", 3791 write_len, 3792 hdw->ctl_write_urb->actual_length); 3793 } 3794 goto done; 3795 } 3796 } 3797 if (read_len && read_data) { 3798 /* Validate results of read request */ 3799 if ((hdw->ctl_read_urb->status != 0) && 3800 (hdw->ctl_read_urb->status != -ENOENT) && 3801 (hdw->ctl_read_urb->status != -ESHUTDOWN) && 3802 (hdw->ctl_read_urb->status != -ECONNRESET)) { 3803 /* USB subsystem is reporting some kind of failure 3804 on the read */ 3805 status = hdw->ctl_read_urb->status; 3806 if (!probe_fl) { 3807 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3808 "control-read URB failure," 3809 " status=%d", 3810 status); 3811 } 3812 goto done; 3813 } 3814 if (hdw->ctl_read_urb->actual_length < read_len) { 3815 /* Failed to read enough data */ 3816 status = -EIO; 3817 if (!probe_fl) { 3818 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3819 "control-read URB short," 3820 " expected=%d got=%d", 3821 read_len, 3822 hdw->ctl_read_urb->actual_length); 3823 } 3824 goto done; 3825 } 3826 /* Transfer retrieved data out from internal buffer */ 3827 for (idx = 0; idx < read_len; idx++) { 3828 ((unsigned char *)read_data)[idx] = 3829 hdw->ctl_read_buffer[idx]; 3830 } 3831 } 3832 3833 done: 3834 3835 hdw->cmd_debug_state = 0; 3836 if ((status < 0) && (!probe_fl)) { 3837 pvr2_hdw_render_useless(hdw); 3838 } 3839 return status; 3840 } 3841 3842 3843 int pvr2_send_request(struct pvr2_hdw *hdw, 3844 void *write_data,unsigned int write_len, 3845 void *read_data,unsigned int read_len) 3846 { 3847 return pvr2_send_request_ex(hdw,HZ*4,0, 3848 write_data,write_len, 3849 read_data,read_len); 3850 } 3851 3852 3853 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode) 3854 { 3855 int ret; 3856 unsigned int cnt = 1; 3857 unsigned int args = 0; 3858 LOCK_TAKE(hdw->ctl_lock); 3859 hdw->cmd_buffer[0] = cmdcode & 0xffu; 3860 args = (cmdcode >> 8) & 0xffu; 3861 args = (args > 2) ? 2 : args; 3862 if (args) { 3863 cnt += args; 3864 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu; 3865 if (args > 1) { 3866 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu; 3867 } 3868 } 3869 if (pvrusb2_debug & PVR2_TRACE_INIT) { 3870 unsigned int idx; 3871 unsigned int ccnt,bcnt; 3872 char tbuf[50]; 3873 cmdcode &= 0xffu; 3874 bcnt = 0; 3875 ccnt = scnprintf(tbuf+bcnt, 3876 sizeof(tbuf)-bcnt, 3877 "Sending FX2 command 0x%x",cmdcode); 3878 bcnt += ccnt; 3879 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) { 3880 if (pvr2_fx2cmd_desc[idx].id == cmdcode) { 3881 ccnt = scnprintf(tbuf+bcnt, 3882 sizeof(tbuf)-bcnt, 3883 " \"%s\"", 3884 pvr2_fx2cmd_desc[idx].desc); 3885 bcnt += ccnt; 3886 break; 3887 } 3888 } 3889 if (args) { 3890 ccnt = scnprintf(tbuf+bcnt, 3891 sizeof(tbuf)-bcnt, 3892 " (%u",hdw->cmd_buffer[1]); 3893 bcnt += ccnt; 3894 if (args > 1) { 3895 ccnt = scnprintf(tbuf+bcnt, 3896 sizeof(tbuf)-bcnt, 3897 ",%u",hdw->cmd_buffer[2]); 3898 bcnt += ccnt; 3899 } 3900 ccnt = scnprintf(tbuf+bcnt, 3901 sizeof(tbuf)-bcnt, 3902 ")"); 3903 bcnt += ccnt; 3904 } 3905 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf); 3906 } 3907 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0); 3908 LOCK_GIVE(hdw->ctl_lock); 3909 return ret; 3910 } 3911 3912 3913 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data) 3914 { 3915 int ret; 3916 3917 LOCK_TAKE(hdw->ctl_lock); 3918 3919 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */ 3920 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data); 3921 hdw->cmd_buffer[5] = 0; 3922 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; 3923 hdw->cmd_buffer[7] = reg & 0xff; 3924 3925 3926 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0); 3927 3928 LOCK_GIVE(hdw->ctl_lock); 3929 3930 return ret; 3931 } 3932 3933 3934 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data) 3935 { 3936 int ret = 0; 3937 3938 LOCK_TAKE(hdw->ctl_lock); 3939 3940 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */ 3941 hdw->cmd_buffer[1] = 0; 3942 hdw->cmd_buffer[2] = 0; 3943 hdw->cmd_buffer[3] = 0; 3944 hdw->cmd_buffer[4] = 0; 3945 hdw->cmd_buffer[5] = 0; 3946 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; 3947 hdw->cmd_buffer[7] = reg & 0xff; 3948 3949 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4); 3950 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0); 3951 3952 LOCK_GIVE(hdw->ctl_lock); 3953 3954 return ret; 3955 } 3956 3957 3958 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw) 3959 { 3960 if (!hdw->flag_ok) return; 3961 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3962 "Device being rendered inoperable"); 3963 if (hdw->vid_stream) { 3964 pvr2_stream_setup(hdw->vid_stream,NULL,0,0); 3965 } 3966 hdw->flag_ok = 0; 3967 trace_stbit("flag_ok",hdw->flag_ok); 3968 pvr2_hdw_state_sched(hdw); 3969 } 3970 3971 3972 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw) 3973 { 3974 int ret; 3975 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset..."); 3976 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL); 3977 if (ret == 0) { 3978 ret = usb_reset_device(hdw->usb_dev); 3979 usb_unlock_device(hdw->usb_dev); 3980 } else { 3981 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3982 "Failed to lock USB device ret=%d",ret); 3983 } 3984 if (init_pause_msec) { 3985 pvr2_trace(PVR2_TRACE_INFO, 3986 "Waiting %u msec for hardware to settle", 3987 init_pause_msec); 3988 msleep(init_pause_msec); 3989 } 3990 3991 } 3992 3993 3994 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val) 3995 { 3996 char *da; 3997 unsigned int pipe; 3998 int ret; 3999 4000 if (!hdw->usb_dev) return; 4001 4002 da = kmalloc(16, GFP_KERNEL); 4003 4004 if (da == NULL) { 4005 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 4006 "Unable to allocate memory to control CPU reset"); 4007 return; 4008 } 4009 4010 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val); 4011 4012 da[0] = val ? 0x01 : 0x00; 4013 4014 /* Write the CPUCS register on the 8051. The lsb of the register 4015 is the reset bit; a 1 asserts reset while a 0 clears it. */ 4016 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); 4017 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ); 4018 if (ret < 0) { 4019 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 4020 "cpureset_assert(%d) error=%d",val,ret); 4021 pvr2_hdw_render_useless(hdw); 4022 } 4023 4024 kfree(da); 4025 } 4026 4027 4028 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw) 4029 { 4030 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET); 4031 } 4032 4033 4034 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw) 4035 { 4036 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON); 4037 } 4038 4039 4040 4041 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw) 4042 { 4043 pvr2_trace(PVR2_TRACE_INIT, 4044 "Requesting decoder reset"); 4045 if (hdw->decoder_client_id) { 4046 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id, 4047 core, reset, 0); 4048 pvr2_hdw_cx25840_vbi_hack(hdw); 4049 return 0; 4050 } 4051 pvr2_trace(PVR2_TRACE_INIT, 4052 "Unable to reset decoder: nothing attached"); 4053 return -ENOTTY; 4054 } 4055 4056 4057 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff) 4058 { 4059 hdw->flag_ok = !0; 4060 return pvr2_issue_simple_cmd(hdw, 4061 FX2CMD_HCW_DEMOD_RESETIN | 4062 (1 << 8) | 4063 ((onoff ? 1 : 0) << 16)); 4064 } 4065 4066 4067 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff) 4068 { 4069 hdw->flag_ok = !0; 4070 return pvr2_issue_simple_cmd(hdw,(onoff ? 4071 FX2CMD_ONAIR_DTV_POWER_ON : 4072 FX2CMD_ONAIR_DTV_POWER_OFF)); 4073 } 4074 4075 4076 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw, 4077 int onoff) 4078 { 4079 return pvr2_issue_simple_cmd(hdw,(onoff ? 4080 FX2CMD_ONAIR_DTV_STREAMING_ON : 4081 FX2CMD_ONAIR_DTV_STREAMING_OFF)); 4082 } 4083 4084 4085 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl) 4086 { 4087 int cmode; 4088 /* Compare digital/analog desired setting with current setting. If 4089 they don't match, fix it... */ 4090 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG); 4091 if (cmode == hdw->pathway_state) { 4092 /* They match; nothing to do */ 4093 return; 4094 } 4095 4096 switch (hdw->hdw_desc->digital_control_scheme) { 4097 case PVR2_DIGITAL_SCHEME_HAUPPAUGE: 4098 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl); 4099 if (cmode == PVR2_PATHWAY_ANALOG) { 4100 /* If moving to analog mode, also force the decoder 4101 to reset. If no decoder is attached, then it's 4102 ok to ignore this because if/when the decoder 4103 attaches, it will reset itself at that time. */ 4104 pvr2_hdw_cmd_decoder_reset(hdw); 4105 } 4106 break; 4107 case PVR2_DIGITAL_SCHEME_ONAIR: 4108 /* Supposedly we should always have the power on whether in 4109 digital or analog mode. But for now do what appears to 4110 work... */ 4111 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl); 4112 break; 4113 default: break; 4114 } 4115 4116 pvr2_hdw_untrip_unlocked(hdw); 4117 hdw->pathway_state = cmode; 4118 } 4119 4120 4121 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff) 4122 { 4123 /* change some GPIO data 4124 * 4125 * note: bit d7 of dir appears to control the LED, 4126 * so we shut it off here. 4127 * 4128 */ 4129 if (onoff) { 4130 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481); 4131 } else { 4132 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401); 4133 } 4134 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000); 4135 } 4136 4137 4138 typedef void (*led_method_func)(struct pvr2_hdw *,int); 4139 4140 static led_method_func led_methods[] = { 4141 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge, 4142 }; 4143 4144 4145 /* Toggle LED */ 4146 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff) 4147 { 4148 unsigned int scheme_id; 4149 led_method_func fp; 4150 4151 if ((!onoff) == (!hdw->led_on)) return; 4152 4153 hdw->led_on = onoff != 0; 4154 4155 scheme_id = hdw->hdw_desc->led_scheme; 4156 if (scheme_id < ARRAY_SIZE(led_methods)) { 4157 fp = led_methods[scheme_id]; 4158 } else { 4159 fp = NULL; 4160 } 4161 4162 if (fp) (*fp)(hdw,onoff); 4163 } 4164 4165 4166 /* Stop / start video stream transport */ 4167 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl) 4168 { 4169 int ret; 4170 4171 /* If we're in analog mode, then just issue the usual analog 4172 command. */ 4173 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4174 return pvr2_issue_simple_cmd(hdw, 4175 (runFl ? 4176 FX2CMD_STREAMING_ON : 4177 FX2CMD_STREAMING_OFF)); 4178 /*Note: Not reached */ 4179 } 4180 4181 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) { 4182 /* Whoops, we don't know what mode we're in... */ 4183 return -EINVAL; 4184 } 4185 4186 /* To get here we have to be in digital mode. The mechanism here 4187 is unfortunately different for different vendors. So we switch 4188 on the device's digital scheme attribute in order to figure out 4189 what to do. */ 4190 switch (hdw->hdw_desc->digital_control_scheme) { 4191 case PVR2_DIGITAL_SCHEME_HAUPPAUGE: 4192 return pvr2_issue_simple_cmd(hdw, 4193 (runFl ? 4194 FX2CMD_HCW_DTV_STREAMING_ON : 4195 FX2CMD_HCW_DTV_STREAMING_OFF)); 4196 case PVR2_DIGITAL_SCHEME_ONAIR: 4197 ret = pvr2_issue_simple_cmd(hdw, 4198 (runFl ? 4199 FX2CMD_STREAMING_ON : 4200 FX2CMD_STREAMING_OFF)); 4201 if (ret) return ret; 4202 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl); 4203 default: 4204 return -EINVAL; 4205 } 4206 } 4207 4208 4209 /* Evaluate whether or not state_pathway_ok can change */ 4210 static int state_eval_pathway_ok(struct pvr2_hdw *hdw) 4211 { 4212 if (hdw->state_pathway_ok) { 4213 /* Nothing to do if pathway is already ok */ 4214 return 0; 4215 } 4216 if (!hdw->state_pipeline_idle) { 4217 /* Not allowed to change anything if pipeline is not idle */ 4218 return 0; 4219 } 4220 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV); 4221 hdw->state_pathway_ok = !0; 4222 trace_stbit("state_pathway_ok",hdw->state_pathway_ok); 4223 return !0; 4224 } 4225 4226 4227 /* Evaluate whether or not state_encoder_ok can change */ 4228 static int state_eval_encoder_ok(struct pvr2_hdw *hdw) 4229 { 4230 if (hdw->state_encoder_ok) return 0; 4231 if (hdw->flag_tripped) return 0; 4232 if (hdw->state_encoder_run) return 0; 4233 if (hdw->state_encoder_config) return 0; 4234 if (hdw->state_decoder_run) return 0; 4235 if (hdw->state_usbstream_run) return 0; 4236 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) { 4237 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0; 4238 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) { 4239 return 0; 4240 } 4241 4242 if (pvr2_upload_firmware2(hdw) < 0) { 4243 hdw->flag_tripped = !0; 4244 trace_stbit("flag_tripped",hdw->flag_tripped); 4245 return !0; 4246 } 4247 hdw->state_encoder_ok = !0; 4248 trace_stbit("state_encoder_ok",hdw->state_encoder_ok); 4249 return !0; 4250 } 4251 4252 4253 /* Evaluate whether or not state_encoder_config can change */ 4254 static int state_eval_encoder_config(struct pvr2_hdw *hdw) 4255 { 4256 if (hdw->state_encoder_config) { 4257 if (hdw->state_encoder_ok) { 4258 if (hdw->state_pipeline_req && 4259 !hdw->state_pipeline_pause) return 0; 4260 } 4261 hdw->state_encoder_config = 0; 4262 hdw->state_encoder_waitok = 0; 4263 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); 4264 /* paranoia - solve race if timer just completed */ 4265 del_timer_sync(&hdw->encoder_wait_timer); 4266 } else { 4267 if (!hdw->state_pathway_ok || 4268 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || 4269 !hdw->state_encoder_ok || 4270 !hdw->state_pipeline_idle || 4271 hdw->state_pipeline_pause || 4272 !hdw->state_pipeline_req || 4273 !hdw->state_pipeline_config) { 4274 /* We must reset the enforced wait interval if 4275 anything has happened that might have disturbed 4276 the encoder. This should be a rare case. */ 4277 if (timer_pending(&hdw->encoder_wait_timer)) { 4278 del_timer_sync(&hdw->encoder_wait_timer); 4279 } 4280 if (hdw->state_encoder_waitok) { 4281 /* Must clear the state - therefore we did 4282 something to a state bit and must also 4283 return true. */ 4284 hdw->state_encoder_waitok = 0; 4285 trace_stbit("state_encoder_waitok", 4286 hdw->state_encoder_waitok); 4287 return !0; 4288 } 4289 return 0; 4290 } 4291 if (!hdw->state_encoder_waitok) { 4292 if (!timer_pending(&hdw->encoder_wait_timer)) { 4293 /* waitok flag wasn't set and timer isn't 4294 running. Check flag once more to avoid 4295 a race then start the timer. This is 4296 the point when we measure out a minimal 4297 quiet interval before doing something to 4298 the encoder. */ 4299 if (!hdw->state_encoder_waitok) { 4300 hdw->encoder_wait_timer.expires = 4301 jiffies + msecs_to_jiffies( 4302 TIME_MSEC_ENCODER_WAIT); 4303 add_timer(&hdw->encoder_wait_timer); 4304 } 4305 } 4306 /* We can't continue until we know we have been 4307 quiet for the interval measured by this 4308 timer. */ 4309 return 0; 4310 } 4311 pvr2_encoder_configure(hdw); 4312 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0; 4313 } 4314 trace_stbit("state_encoder_config",hdw->state_encoder_config); 4315 return !0; 4316 } 4317 4318 4319 /* Return true if the encoder should not be running. */ 4320 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw) 4321 { 4322 if (!hdw->state_encoder_ok) { 4323 /* Encoder isn't healthy at the moment, so stop it. */ 4324 return !0; 4325 } 4326 if (!hdw->state_pathway_ok) { 4327 /* Mode is not understood at the moment (i.e. it wants to 4328 change), so encoder must be stopped. */ 4329 return !0; 4330 } 4331 4332 switch (hdw->pathway_state) { 4333 case PVR2_PATHWAY_ANALOG: 4334 if (!hdw->state_decoder_run) { 4335 /* We're in analog mode and the decoder is not 4336 running; thus the encoder should be stopped as 4337 well. */ 4338 return !0; 4339 } 4340 break; 4341 case PVR2_PATHWAY_DIGITAL: 4342 if (hdw->state_encoder_runok) { 4343 /* This is a funny case. We're in digital mode so 4344 really the encoder should be stopped. However 4345 if it really is running, only kill it after 4346 runok has been set. This gives a chance for the 4347 onair quirk to function (encoder must run 4348 briefly first, at least once, before onair 4349 digital streaming can work). */ 4350 return !0; 4351 } 4352 break; 4353 default: 4354 /* Unknown mode; so encoder should be stopped. */ 4355 return !0; 4356 } 4357 4358 /* If we get here, we haven't found a reason to stop the 4359 encoder. */ 4360 return 0; 4361 } 4362 4363 4364 /* Return true if the encoder should be running. */ 4365 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw) 4366 { 4367 if (!hdw->state_encoder_ok) { 4368 /* Don't run the encoder if it isn't healthy... */ 4369 return 0; 4370 } 4371 if (!hdw->state_pathway_ok) { 4372 /* Don't run the encoder if we don't (yet) know what mode 4373 we need to be in... */ 4374 return 0; 4375 } 4376 4377 switch (hdw->pathway_state) { 4378 case PVR2_PATHWAY_ANALOG: 4379 if (hdw->state_decoder_run && hdw->state_decoder_ready) { 4380 /* In analog mode, if the decoder is running, then 4381 run the encoder. */ 4382 return !0; 4383 } 4384 break; 4385 case PVR2_PATHWAY_DIGITAL: 4386 if ((hdw->hdw_desc->digital_control_scheme == 4387 PVR2_DIGITAL_SCHEME_ONAIR) && 4388 !hdw->state_encoder_runok) { 4389 /* This is a quirk. OnAir hardware won't stream 4390 digital until the encoder has been run at least 4391 once, for a minimal period of time (empiricially 4392 measured to be 1/4 second). So if we're on 4393 OnAir hardware and the encoder has never been 4394 run at all, then start the encoder. Normal 4395 state machine logic in the driver will 4396 automatically handle the remaining bits. */ 4397 return !0; 4398 } 4399 break; 4400 default: 4401 /* For completeness (unknown mode; encoder won't run ever) */ 4402 break; 4403 } 4404 /* If we get here, then we haven't found any reason to run the 4405 encoder, so don't run it. */ 4406 return 0; 4407 } 4408 4409 4410 /* Evaluate whether or not state_encoder_run can change */ 4411 static int state_eval_encoder_run(struct pvr2_hdw *hdw) 4412 { 4413 if (hdw->state_encoder_run) { 4414 if (!state_check_disable_encoder_run(hdw)) return 0; 4415 if (hdw->state_encoder_ok) { 4416 del_timer_sync(&hdw->encoder_run_timer); 4417 if (pvr2_encoder_stop(hdw) < 0) return !0; 4418 } 4419 hdw->state_encoder_run = 0; 4420 } else { 4421 if (!state_check_enable_encoder_run(hdw)) return 0; 4422 if (pvr2_encoder_start(hdw) < 0) return !0; 4423 hdw->state_encoder_run = !0; 4424 if (!hdw->state_encoder_runok) { 4425 hdw->encoder_run_timer.expires = jiffies + 4426 msecs_to_jiffies(TIME_MSEC_ENCODER_OK); 4427 add_timer(&hdw->encoder_run_timer); 4428 } 4429 } 4430 trace_stbit("state_encoder_run",hdw->state_encoder_run); 4431 return !0; 4432 } 4433 4434 4435 /* Timeout function for quiescent timer. */ 4436 static void pvr2_hdw_quiescent_timeout(unsigned long data) 4437 { 4438 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4439 hdw->state_decoder_quiescent = !0; 4440 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); 4441 hdw->state_stale = !0; 4442 queue_work(hdw->workqueue,&hdw->workpoll); 4443 } 4444 4445 4446 /* Timeout function for decoder stabilization timer. */ 4447 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data) 4448 { 4449 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4450 hdw->state_decoder_ready = !0; 4451 trace_stbit("state_decoder_ready", hdw->state_decoder_ready); 4452 hdw->state_stale = !0; 4453 queue_work(hdw->workqueue, &hdw->workpoll); 4454 } 4455 4456 4457 /* Timeout function for encoder wait timer. */ 4458 static void pvr2_hdw_encoder_wait_timeout(unsigned long data) 4459 { 4460 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4461 hdw->state_encoder_waitok = !0; 4462 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); 4463 hdw->state_stale = !0; 4464 queue_work(hdw->workqueue,&hdw->workpoll); 4465 } 4466 4467 4468 /* Timeout function for encoder run timer. */ 4469 static void pvr2_hdw_encoder_run_timeout(unsigned long data) 4470 { 4471 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4472 if (!hdw->state_encoder_runok) { 4473 hdw->state_encoder_runok = !0; 4474 trace_stbit("state_encoder_runok",hdw->state_encoder_runok); 4475 hdw->state_stale = !0; 4476 queue_work(hdw->workqueue,&hdw->workpoll); 4477 } 4478 } 4479 4480 4481 /* Evaluate whether or not state_decoder_run can change */ 4482 static int state_eval_decoder_run(struct pvr2_hdw *hdw) 4483 { 4484 if (hdw->state_decoder_run) { 4485 if (hdw->state_encoder_ok) { 4486 if (hdw->state_pipeline_req && 4487 !hdw->state_pipeline_pause && 4488 hdw->state_pathway_ok) return 0; 4489 } 4490 if (!hdw->flag_decoder_missed) { 4491 pvr2_decoder_enable(hdw,0); 4492 } 4493 hdw->state_decoder_quiescent = 0; 4494 hdw->state_decoder_run = 0; 4495 /* paranoia - solve race if timer(s) just completed */ 4496 del_timer_sync(&hdw->quiescent_timer); 4497 /* Kill the stabilization timer, in case we're killing the 4498 encoder before the previous stabilization interval has 4499 been properly timed. */ 4500 del_timer_sync(&hdw->decoder_stabilization_timer); 4501 hdw->state_decoder_ready = 0; 4502 } else { 4503 if (!hdw->state_decoder_quiescent) { 4504 if (!timer_pending(&hdw->quiescent_timer)) { 4505 /* We don't do something about the 4506 quiescent timer until right here because 4507 we also want to catch cases where the 4508 decoder was already not running (like 4509 after initialization) as opposed to 4510 knowing that we had just stopped it. 4511 The second flag check is here to cover a 4512 race - the timer could have run and set 4513 this flag just after the previous check 4514 but before we did the pending check. */ 4515 if (!hdw->state_decoder_quiescent) { 4516 hdw->quiescent_timer.expires = 4517 jiffies + msecs_to_jiffies( 4518 TIME_MSEC_DECODER_WAIT); 4519 add_timer(&hdw->quiescent_timer); 4520 } 4521 } 4522 /* Don't allow decoder to start again until it has 4523 been quiesced first. This little detail should 4524 hopefully further stabilize the encoder. */ 4525 return 0; 4526 } 4527 if (!hdw->state_pathway_ok || 4528 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || 4529 !hdw->state_pipeline_req || 4530 hdw->state_pipeline_pause || 4531 !hdw->state_pipeline_config || 4532 !hdw->state_encoder_config || 4533 !hdw->state_encoder_ok) return 0; 4534 del_timer_sync(&hdw->quiescent_timer); 4535 if (hdw->flag_decoder_missed) return 0; 4536 if (pvr2_decoder_enable(hdw,!0) < 0) return 0; 4537 hdw->state_decoder_quiescent = 0; 4538 hdw->state_decoder_ready = 0; 4539 hdw->state_decoder_run = !0; 4540 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) { 4541 hdw->decoder_stabilization_timer.expires = 4542 jiffies + msecs_to_jiffies( 4543 TIME_MSEC_DECODER_STABILIZATION_WAIT); 4544 add_timer(&hdw->decoder_stabilization_timer); 4545 } else { 4546 hdw->state_decoder_ready = !0; 4547 } 4548 } 4549 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); 4550 trace_stbit("state_decoder_run",hdw->state_decoder_run); 4551 trace_stbit("state_decoder_ready", hdw->state_decoder_ready); 4552 return !0; 4553 } 4554 4555 4556 /* Evaluate whether or not state_usbstream_run can change */ 4557 static int state_eval_usbstream_run(struct pvr2_hdw *hdw) 4558 { 4559 if (hdw->state_usbstream_run) { 4560 int fl = !0; 4561 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4562 fl = (hdw->state_encoder_ok && 4563 hdw->state_encoder_run); 4564 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && 4565 (hdw->hdw_desc->flag_digital_requires_cx23416)) { 4566 fl = hdw->state_encoder_ok; 4567 } 4568 if (fl && 4569 hdw->state_pipeline_req && 4570 !hdw->state_pipeline_pause && 4571 hdw->state_pathway_ok) { 4572 return 0; 4573 } 4574 pvr2_hdw_cmd_usbstream(hdw,0); 4575 hdw->state_usbstream_run = 0; 4576 } else { 4577 if (!hdw->state_pipeline_req || 4578 hdw->state_pipeline_pause || 4579 !hdw->state_pathway_ok) return 0; 4580 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4581 if (!hdw->state_encoder_ok || 4582 !hdw->state_encoder_run) return 0; 4583 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && 4584 (hdw->hdw_desc->flag_digital_requires_cx23416)) { 4585 if (!hdw->state_encoder_ok) return 0; 4586 if (hdw->state_encoder_run) return 0; 4587 if (hdw->hdw_desc->digital_control_scheme == 4588 PVR2_DIGITAL_SCHEME_ONAIR) { 4589 /* OnAir digital receivers won't stream 4590 unless the analog encoder has run first. 4591 Why? I have no idea. But don't even 4592 try until we know the analog side is 4593 known to have run. */ 4594 if (!hdw->state_encoder_runok) return 0; 4595 } 4596 } 4597 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0; 4598 hdw->state_usbstream_run = !0; 4599 } 4600 trace_stbit("state_usbstream_run",hdw->state_usbstream_run); 4601 return !0; 4602 } 4603 4604 4605 /* Attempt to configure pipeline, if needed */ 4606 static int state_eval_pipeline_config(struct pvr2_hdw *hdw) 4607 { 4608 if (hdw->state_pipeline_config || 4609 hdw->state_pipeline_pause) return 0; 4610 pvr2_hdw_commit_execute(hdw); 4611 return !0; 4612 } 4613 4614 4615 /* Update pipeline idle and pipeline pause tracking states based on other 4616 inputs. This must be called whenever the other relevant inputs have 4617 changed. */ 4618 static int state_update_pipeline_state(struct pvr2_hdw *hdw) 4619 { 4620 unsigned int st; 4621 int updatedFl = 0; 4622 /* Update pipeline state */ 4623 st = !(hdw->state_encoder_run || 4624 hdw->state_decoder_run || 4625 hdw->state_usbstream_run || 4626 (!hdw->state_decoder_quiescent)); 4627 if (!st != !hdw->state_pipeline_idle) { 4628 hdw->state_pipeline_idle = st; 4629 updatedFl = !0; 4630 } 4631 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) { 4632 hdw->state_pipeline_pause = 0; 4633 updatedFl = !0; 4634 } 4635 return updatedFl; 4636 } 4637 4638 4639 typedef int (*state_eval_func)(struct pvr2_hdw *); 4640 4641 /* Set of functions to be run to evaluate various states in the driver. */ 4642 static const state_eval_func eval_funcs[] = { 4643 state_eval_pathway_ok, 4644 state_eval_pipeline_config, 4645 state_eval_encoder_ok, 4646 state_eval_encoder_config, 4647 state_eval_decoder_run, 4648 state_eval_encoder_run, 4649 state_eval_usbstream_run, 4650 }; 4651 4652 4653 /* Process various states and return true if we did anything interesting. */ 4654 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw) 4655 { 4656 unsigned int i; 4657 int state_updated = 0; 4658 int check_flag; 4659 4660 if (!hdw->state_stale) return 0; 4661 if ((hdw->fw1_state != FW1_STATE_OK) || 4662 !hdw->flag_ok) { 4663 hdw->state_stale = 0; 4664 return !0; 4665 } 4666 /* This loop is the heart of the entire driver. It keeps trying to 4667 evaluate various bits of driver state until nothing changes for 4668 one full iteration. Each "bit of state" tracks some global 4669 aspect of the driver, e.g. whether decoder should run, if 4670 pipeline is configured, usb streaming is on, etc. We separately 4671 evaluate each of those questions based on other driver state to 4672 arrive at the correct running configuration. */ 4673 do { 4674 check_flag = 0; 4675 state_update_pipeline_state(hdw); 4676 /* Iterate over each bit of state */ 4677 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) { 4678 if ((*eval_funcs[i])(hdw)) { 4679 check_flag = !0; 4680 state_updated = !0; 4681 state_update_pipeline_state(hdw); 4682 } 4683 } 4684 } while (check_flag && hdw->flag_ok); 4685 hdw->state_stale = 0; 4686 trace_stbit("state_stale",hdw->state_stale); 4687 return state_updated; 4688 } 4689 4690 4691 static unsigned int print_input_mask(unsigned int msk, 4692 char *buf,unsigned int acnt) 4693 { 4694 unsigned int idx,ccnt; 4695 unsigned int tcnt = 0; 4696 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) { 4697 if (!((1 << idx) & msk)) continue; 4698 ccnt = scnprintf(buf+tcnt, 4699 acnt-tcnt, 4700 "%s%s", 4701 (tcnt ? ", " : ""), 4702 control_values_input[idx]); 4703 tcnt += ccnt; 4704 } 4705 return tcnt; 4706 } 4707 4708 4709 static const char *pvr2_pathway_state_name(int id) 4710 { 4711 switch (id) { 4712 case PVR2_PATHWAY_ANALOG: return "analog"; 4713 case PVR2_PATHWAY_DIGITAL: return "digital"; 4714 default: return "unknown"; 4715 } 4716 } 4717 4718 4719 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which, 4720 char *buf,unsigned int acnt) 4721 { 4722 switch (which) { 4723 case 0: 4724 return scnprintf( 4725 buf,acnt, 4726 "driver:%s%s%s%s%s <mode=%s>", 4727 (hdw->flag_ok ? " <ok>" : " <fail>"), 4728 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"), 4729 (hdw->flag_disconnected ? " <disconnected>" : 4730 " <connected>"), 4731 (hdw->flag_tripped ? " <tripped>" : ""), 4732 (hdw->flag_decoder_missed ? " <no decoder>" : ""), 4733 pvr2_pathway_state_name(hdw->pathway_state)); 4734 4735 case 1: 4736 return scnprintf( 4737 buf,acnt, 4738 "pipeline:%s%s%s%s", 4739 (hdw->state_pipeline_idle ? " <idle>" : ""), 4740 (hdw->state_pipeline_config ? 4741 " <configok>" : " <stale>"), 4742 (hdw->state_pipeline_req ? " <req>" : ""), 4743 (hdw->state_pipeline_pause ? " <pause>" : "")); 4744 case 2: 4745 return scnprintf( 4746 buf,acnt, 4747 "worker:%s%s%s%s%s%s%s", 4748 (hdw->state_decoder_run ? 4749 (hdw->state_decoder_ready ? 4750 "<decode:run>" : " <decode:start>") : 4751 (hdw->state_decoder_quiescent ? 4752 "" : " <decode:stop>")), 4753 (hdw->state_decoder_quiescent ? 4754 " <decode:quiescent>" : ""), 4755 (hdw->state_encoder_ok ? 4756 "" : " <encode:init>"), 4757 (hdw->state_encoder_run ? 4758 (hdw->state_encoder_runok ? 4759 " <encode:run>" : 4760 " <encode:firstrun>") : 4761 (hdw->state_encoder_runok ? 4762 " <encode:stop>" : 4763 " <encode:virgin>")), 4764 (hdw->state_encoder_config ? 4765 " <encode:configok>" : 4766 (hdw->state_encoder_waitok ? 4767 "" : " <encode:waitok>")), 4768 (hdw->state_usbstream_run ? 4769 " <usb:run>" : " <usb:stop>"), 4770 (hdw->state_pathway_ok ? 4771 " <pathway:ok>" : "")); 4772 case 3: 4773 return scnprintf( 4774 buf,acnt, 4775 "state: %s", 4776 pvr2_get_state_name(hdw->master_state)); 4777 case 4: { 4778 unsigned int tcnt = 0; 4779 unsigned int ccnt; 4780 4781 ccnt = scnprintf(buf, 4782 acnt, 4783 "Hardware supported inputs: "); 4784 tcnt += ccnt; 4785 tcnt += print_input_mask(hdw->input_avail_mask, 4786 buf+tcnt, 4787 acnt-tcnt); 4788 if (hdw->input_avail_mask != hdw->input_allowed_mask) { 4789 ccnt = scnprintf(buf+tcnt, 4790 acnt-tcnt, 4791 "; allowed inputs: "); 4792 tcnt += ccnt; 4793 tcnt += print_input_mask(hdw->input_allowed_mask, 4794 buf+tcnt, 4795 acnt-tcnt); 4796 } 4797 return tcnt; 4798 } 4799 case 5: { 4800 struct pvr2_stream_stats stats; 4801 if (!hdw->vid_stream) break; 4802 pvr2_stream_get_stats(hdw->vid_stream, 4803 &stats, 4804 0); 4805 return scnprintf( 4806 buf,acnt, 4807 "Bytes streamed=%u" 4808 " URBs: queued=%u idle=%u ready=%u" 4809 " processed=%u failed=%u", 4810 stats.bytes_processed, 4811 stats.buffers_in_queue, 4812 stats.buffers_in_idle, 4813 stats.buffers_in_ready, 4814 stats.buffers_processed, 4815 stats.buffers_failed); 4816 } 4817 case 6: { 4818 unsigned int id = hdw->ir_scheme_active; 4819 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id, 4820 (id >= ARRAY_SIZE(ir_scheme_names) ? 4821 "?" : ir_scheme_names[id])); 4822 } 4823 default: break; 4824 } 4825 return 0; 4826 } 4827 4828 4829 /* Generate report containing info about attached sub-devices and attached 4830 i2c clients, including an indication of which attached i2c clients are 4831 actually sub-devices. */ 4832 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw, 4833 char *buf, unsigned int acnt) 4834 { 4835 struct v4l2_subdev *sd; 4836 unsigned int tcnt = 0; 4837 unsigned int ccnt; 4838 struct i2c_client *client; 4839 const char *p; 4840 unsigned int id; 4841 4842 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n"); 4843 tcnt += ccnt; 4844 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) { 4845 id = sd->grp_id; 4846 p = NULL; 4847 if (id < ARRAY_SIZE(module_names)) p = module_names[id]; 4848 if (p) { 4849 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p); 4850 tcnt += ccnt; 4851 } else { 4852 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4853 " (unknown id=%u):", id); 4854 tcnt += ccnt; 4855 } 4856 client = v4l2_get_subdevdata(sd); 4857 if (client) { 4858 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4859 " %s @ %02x\n", client->name, 4860 client->addr); 4861 tcnt += ccnt; 4862 } else { 4863 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4864 " no i2c client\n"); 4865 tcnt += ccnt; 4866 } 4867 } 4868 return tcnt; 4869 } 4870 4871 4872 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw, 4873 char *buf,unsigned int acnt) 4874 { 4875 unsigned int bcnt,ccnt,idx; 4876 bcnt = 0; 4877 LOCK_TAKE(hdw->big_lock); 4878 for (idx = 0; ; idx++) { 4879 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt); 4880 if (!ccnt) break; 4881 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4882 if (!acnt) break; 4883 buf[0] = '\n'; ccnt = 1; 4884 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4885 } 4886 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt); 4887 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4888 LOCK_GIVE(hdw->big_lock); 4889 return bcnt; 4890 } 4891 4892 4893 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw) 4894 { 4895 char buf[256]; 4896 unsigned int idx, ccnt; 4897 unsigned int lcnt, ucnt; 4898 4899 for (idx = 0; ; idx++) { 4900 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf)); 4901 if (!ccnt) break; 4902 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf); 4903 } 4904 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf)); 4905 if (ccnt >= sizeof(buf)) 4906 ccnt = sizeof(buf); 4907 4908 ucnt = 0; 4909 while (ucnt < ccnt) { 4910 lcnt = 0; 4911 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) { 4912 lcnt++; 4913 } 4914 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt); 4915 ucnt += lcnt + 1; 4916 } 4917 } 4918 4919 4920 /* Evaluate and update the driver's current state, taking various actions 4921 as appropriate for the update. */ 4922 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw) 4923 { 4924 unsigned int st; 4925 int state_updated = 0; 4926 int callback_flag = 0; 4927 int analog_mode; 4928 4929 pvr2_trace(PVR2_TRACE_STBITS, 4930 "Drive state check START"); 4931 if (pvrusb2_debug & PVR2_TRACE_STBITS) { 4932 pvr2_hdw_state_log_state(hdw); 4933 } 4934 4935 /* Process all state and get back over disposition */ 4936 state_updated = pvr2_hdw_state_update(hdw); 4937 4938 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL); 4939 4940 /* Update master state based upon all other states. */ 4941 if (!hdw->flag_ok) { 4942 st = PVR2_STATE_DEAD; 4943 } else if (hdw->fw1_state != FW1_STATE_OK) { 4944 st = PVR2_STATE_COLD; 4945 } else if ((analog_mode || 4946 hdw->hdw_desc->flag_digital_requires_cx23416) && 4947 !hdw->state_encoder_ok) { 4948 st = PVR2_STATE_WARM; 4949 } else if (hdw->flag_tripped || 4950 (analog_mode && hdw->flag_decoder_missed)) { 4951 st = PVR2_STATE_ERROR; 4952 } else if (hdw->state_usbstream_run && 4953 (!analog_mode || 4954 (hdw->state_encoder_run && hdw->state_decoder_run))) { 4955 st = PVR2_STATE_RUN; 4956 } else { 4957 st = PVR2_STATE_READY; 4958 } 4959 if (hdw->master_state != st) { 4960 pvr2_trace(PVR2_TRACE_STATE, 4961 "Device state change from %s to %s", 4962 pvr2_get_state_name(hdw->master_state), 4963 pvr2_get_state_name(st)); 4964 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN); 4965 hdw->master_state = st; 4966 state_updated = !0; 4967 callback_flag = !0; 4968 } 4969 if (state_updated) { 4970 /* Trigger anyone waiting on any state changes here. */ 4971 wake_up(&hdw->state_wait_data); 4972 } 4973 4974 if (pvrusb2_debug & PVR2_TRACE_STBITS) { 4975 pvr2_hdw_state_log_state(hdw); 4976 } 4977 pvr2_trace(PVR2_TRACE_STBITS, 4978 "Drive state check DONE callback=%d",callback_flag); 4979 4980 return callback_flag; 4981 } 4982 4983 4984 /* Cause kernel thread to check / update driver state */ 4985 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw) 4986 { 4987 if (hdw->state_stale) return; 4988 hdw->state_stale = !0; 4989 trace_stbit("state_stale",hdw->state_stale); 4990 queue_work(hdw->workqueue,&hdw->workpoll); 4991 } 4992 4993 4994 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp) 4995 { 4996 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp); 4997 } 4998 4999 5000 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp) 5001 { 5002 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp); 5003 } 5004 5005 5006 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp) 5007 { 5008 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp); 5009 } 5010 5011 5012 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val) 5013 { 5014 u32 cval,nval; 5015 int ret; 5016 if (~msk) { 5017 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval); 5018 if (ret) return ret; 5019 nval = (cval & ~msk) | (val & msk); 5020 pvr2_trace(PVR2_TRACE_GPIO, 5021 "GPIO direction changing 0x%x:0x%x" 5022 " from 0x%x to 0x%x", 5023 msk,val,cval,nval); 5024 } else { 5025 nval = val; 5026 pvr2_trace(PVR2_TRACE_GPIO, 5027 "GPIO direction changing to 0x%x",nval); 5028 } 5029 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval); 5030 } 5031 5032 5033 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val) 5034 { 5035 u32 cval,nval; 5036 int ret; 5037 if (~msk) { 5038 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval); 5039 if (ret) return ret; 5040 nval = (cval & ~msk) | (val & msk); 5041 pvr2_trace(PVR2_TRACE_GPIO, 5042 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x", 5043 msk,val,cval,nval); 5044 } else { 5045 nval = val; 5046 pvr2_trace(PVR2_TRACE_GPIO, 5047 "GPIO output changing to 0x%x",nval); 5048 } 5049 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval); 5050 } 5051 5052 5053 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw) 5054 { 5055 struct v4l2_tuner *vtp = &hdw->tuner_signal_info; 5056 memset(vtp, 0, sizeof(*vtp)); 5057 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ? 5058 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; 5059 hdw->tuner_signal_stale = 0; 5060 /* Note: There apparently is no replacement for VIDIOC_CROPCAP 5061 using v4l2-subdev - therefore we can't support that AT ALL right 5062 now. (Of course, no sub-drivers seem to implement it either. 5063 But now it's a a chicken and egg problem...) */ 5064 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp); 5065 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll" 5066 " type=%u strength=%u audio=0x%x cap=0x%x" 5067 " low=%u hi=%u", 5068 vtp->type, 5069 vtp->signal, vtp->rxsubchans, vtp->capability, 5070 vtp->rangelow, vtp->rangehigh); 5071 5072 /* We have to do this to avoid getting into constant polling if 5073 there's nobody to answer a poll of cropcap info. */ 5074 hdw->cropcap_stale = 0; 5075 } 5076 5077 5078 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw) 5079 { 5080 return hdw->input_avail_mask; 5081 } 5082 5083 5084 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw) 5085 { 5086 return hdw->input_allowed_mask; 5087 } 5088 5089 5090 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v) 5091 { 5092 if (hdw->input_val != v) { 5093 hdw->input_val = v; 5094 hdw->input_dirty = !0; 5095 } 5096 5097 /* Handle side effects - if we switch to a mode that needs the RF 5098 tuner, then select the right frequency choice as well and mark 5099 it dirty. */ 5100 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 5101 hdw->freqSelector = 0; 5102 hdw->freqDirty = !0; 5103 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) || 5104 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) { 5105 hdw->freqSelector = 1; 5106 hdw->freqDirty = !0; 5107 } 5108 return 0; 5109 } 5110 5111 5112 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw, 5113 unsigned int change_mask, 5114 unsigned int change_val) 5115 { 5116 int ret = 0; 5117 unsigned int nv,m,idx; 5118 LOCK_TAKE(hdw->big_lock); 5119 do { 5120 nv = hdw->input_allowed_mask & ~change_mask; 5121 nv |= (change_val & change_mask); 5122 nv &= hdw->input_avail_mask; 5123 if (!nv) { 5124 /* No legal modes left; return error instead. */ 5125 ret = -EPERM; 5126 break; 5127 } 5128 hdw->input_allowed_mask = nv; 5129 if ((1 << hdw->input_val) & hdw->input_allowed_mask) { 5130 /* Current mode is still in the allowed mask, so 5131 we're done. */ 5132 break; 5133 } 5134 /* Select and switch to a mode that is still in the allowed 5135 mask */ 5136 if (!hdw->input_allowed_mask) { 5137 /* Nothing legal; give up */ 5138 break; 5139 } 5140 m = hdw->input_allowed_mask; 5141 for (idx = 0; idx < (sizeof(m) << 3); idx++) { 5142 if (!((1 << idx) & m)) continue; 5143 pvr2_hdw_set_input(hdw,idx); 5144 break; 5145 } 5146 } while (0); 5147 LOCK_GIVE(hdw->big_lock); 5148 return ret; 5149 } 5150 5151 5152 /* Find I2C address of eeprom */ 5153 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw) 5154 { 5155 int result; 5156 LOCK_TAKE(hdw->ctl_lock); do { 5157 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; 5158 result = pvr2_send_request(hdw, 5159 hdw->cmd_buffer,1, 5160 hdw->cmd_buffer,1); 5161 if (result < 0) break; 5162 result = hdw->cmd_buffer[0]; 5163 } while(0); LOCK_GIVE(hdw->ctl_lock); 5164 return result; 5165 } 5166