1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *
4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
5  */
6 
7 #include <linux/errno.h>
8 #include <linux/string.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/firmware.h>
12 #include <linux/videodev2.h>
13 #include <media/v4l2-common.h>
14 #include <media/tuner.h>
15 #include "pvrusb2.h"
16 #include "pvrusb2-std.h"
17 #include "pvrusb2-util.h"
18 #include "pvrusb2-hdw.h"
19 #include "pvrusb2-i2c-core.h"
20 #include "pvrusb2-eeprom.h"
21 #include "pvrusb2-hdw-internal.h"
22 #include "pvrusb2-encoder.h"
23 #include "pvrusb2-debug.h"
24 #include "pvrusb2-fx2-cmd.h"
25 #include "pvrusb2-wm8775.h"
26 #include "pvrusb2-video-v4l.h"
27 #include "pvrusb2-cx2584x-v4l.h"
28 #include "pvrusb2-cs53l32a.h"
29 #include "pvrusb2-audio.h"
30 
31 #define TV_MIN_FREQ     55250000L
32 #define TV_MAX_FREQ    850000000L
33 
34 /* This defines a minimum interval that the decoder must remain quiet
35    before we are allowed to start it running. */
36 #define TIME_MSEC_DECODER_WAIT 50
37 
38 /* This defines a minimum interval that the decoder must be allowed to run
39    before we can safely begin using its streaming output. */
40 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
41 
42 /* This defines a minimum interval that the encoder must remain quiet
43    before we are allowed to configure it. */
44 #define TIME_MSEC_ENCODER_WAIT 50
45 
46 /* This defines the minimum interval that the encoder must successfully run
47    before we consider that the encoder has run at least once since its
48    firmware has been loaded.  This measurement is in important for cases
49    where we can't do something until we know that the encoder has been run
50    at least once. */
51 #define TIME_MSEC_ENCODER_OK 250
52 
53 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
54 static DEFINE_MUTEX(pvr2_unit_mtx);
55 
56 static int ctlchg;
57 static int procreload;
58 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
59 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
60 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
61 static int init_pause_msec;
62 
63 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
65 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
66 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
67 module_param(procreload, int, S_IRUGO|S_IWUSR);
68 MODULE_PARM_DESC(procreload,
69 		 "Attempt init failure recovery with firmware reload");
70 module_param_array(tuner,    int, NULL, 0444);
71 MODULE_PARM_DESC(tuner,"specify installed tuner type");
72 module_param_array(video_std,    int, NULL, 0444);
73 MODULE_PARM_DESC(video_std,"specify initial video standard");
74 module_param_array(tolerance,    int, NULL, 0444);
75 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
76 
77 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
78 static int default_tv_freq    = 61250000L;
79 /* 104.3 MHz, a usable FM station for my area */
80 static int default_radio_freq = 104300000L;
81 
82 module_param_named(tv_freq, default_tv_freq, int, 0444);
83 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
84 module_param_named(radio_freq, default_radio_freq, int, 0444);
85 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
86 
87 #define PVR2_CTL_WRITE_ENDPOINT  0x01
88 #define PVR2_CTL_READ_ENDPOINT   0x81
89 
90 #define PVR2_GPIO_IN 0x9008
91 #define PVR2_GPIO_OUT 0x900c
92 #define PVR2_GPIO_DIR 0x9020
93 
94 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
95 
96 #define PVR2_FIRMWARE_ENDPOINT   0x02
97 
98 /* size of a firmware chunk */
99 #define FIRMWARE_CHUNK_SIZE 0x2000
100 
101 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
102 					struct v4l2_subdev *);
103 
104 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
105 	[PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
106 	[PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
107 	[PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
108 	[PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
109 	[PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
110 };
111 
112 static const char *module_names[] = {
113 	[PVR2_CLIENT_ID_MSP3400] = "msp3400",
114 	[PVR2_CLIENT_ID_CX25840] = "cx25840",
115 	[PVR2_CLIENT_ID_SAA7115] = "saa7115",
116 	[PVR2_CLIENT_ID_TUNER] = "tuner",
117 	[PVR2_CLIENT_ID_DEMOD] = "tuner",
118 	[PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
119 	[PVR2_CLIENT_ID_WM8775] = "wm8775",
120 };
121 
122 
123 static const unsigned char *module_i2c_addresses[] = {
124 	[PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
125 	[PVR2_CLIENT_ID_DEMOD] = "\x43",
126 	[PVR2_CLIENT_ID_MSP3400] = "\x40",
127 	[PVR2_CLIENT_ID_SAA7115] = "\x21",
128 	[PVR2_CLIENT_ID_WM8775] = "\x1b",
129 	[PVR2_CLIENT_ID_CX25840] = "\x44",
130 	[PVR2_CLIENT_ID_CS53L32A] = "\x11",
131 };
132 
133 
134 static const char *ir_scheme_names[] = {
135 	[PVR2_IR_SCHEME_NONE] = "none",
136 	[PVR2_IR_SCHEME_29XXX] = "29xxx",
137 	[PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
138 	[PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
139 	[PVR2_IR_SCHEME_ZILOG] = "Zilog",
140 };
141 
142 
143 /* Define the list of additional controls we'll dynamically construct based
144    on query of the cx2341x module. */
145 struct pvr2_mpeg_ids {
146 	const char *strid;
147 	int id;
148 };
149 static const struct pvr2_mpeg_ids mpeg_ids[] = {
150 	{
151 		.strid = "audio_layer",
152 		.id = V4L2_CID_MPEG_AUDIO_ENCODING,
153 	},{
154 		.strid = "audio_bitrate",
155 		.id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
156 	},{
157 		/* Already using audio_mode elsewhere :-( */
158 		.strid = "mpeg_audio_mode",
159 		.id = V4L2_CID_MPEG_AUDIO_MODE,
160 	},{
161 		.strid = "mpeg_audio_mode_extension",
162 		.id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
163 	},{
164 		.strid = "audio_emphasis",
165 		.id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
166 	},{
167 		.strid = "audio_crc",
168 		.id = V4L2_CID_MPEG_AUDIO_CRC,
169 	},{
170 		.strid = "video_aspect",
171 		.id = V4L2_CID_MPEG_VIDEO_ASPECT,
172 	},{
173 		.strid = "video_b_frames",
174 		.id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
175 	},{
176 		.strid = "video_gop_size",
177 		.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
178 	},{
179 		.strid = "video_gop_closure",
180 		.id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
181 	},{
182 		.strid = "video_bitrate_mode",
183 		.id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
184 	},{
185 		.strid = "video_bitrate",
186 		.id = V4L2_CID_MPEG_VIDEO_BITRATE,
187 	},{
188 		.strid = "video_bitrate_peak",
189 		.id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
190 	},{
191 		.strid = "video_temporal_decimation",
192 		.id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
193 	},{
194 		.strid = "stream_type",
195 		.id = V4L2_CID_MPEG_STREAM_TYPE,
196 	},{
197 		.strid = "video_spatial_filter_mode",
198 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
199 	},{
200 		.strid = "video_spatial_filter",
201 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
202 	},{
203 		.strid = "video_luma_spatial_filter_type",
204 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
205 	},{
206 		.strid = "video_chroma_spatial_filter_type",
207 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
208 	},{
209 		.strid = "video_temporal_filter_mode",
210 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
211 	},{
212 		.strid = "video_temporal_filter",
213 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
214 	},{
215 		.strid = "video_median_filter_type",
216 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
217 	},{
218 		.strid = "video_luma_median_filter_top",
219 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
220 	},{
221 		.strid = "video_luma_median_filter_bottom",
222 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
223 	},{
224 		.strid = "video_chroma_median_filter_top",
225 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
226 	},{
227 		.strid = "video_chroma_median_filter_bottom",
228 		.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
229 	}
230 };
231 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
232 
233 
234 static const char *control_values_srate[] = {
235 	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
236 	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
237 	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
238 };
239 
240 
241 
242 static const char *control_values_input[] = {
243 	[PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
244 	[PVR2_CVAL_INPUT_DTV]       = "dtv",
245 	[PVR2_CVAL_INPUT_RADIO]     = "radio",
246 	[PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
247 	[PVR2_CVAL_INPUT_COMPOSITE] = "composite",
248 };
249 
250 
251 static const char *control_values_audiomode[] = {
252 	[V4L2_TUNER_MODE_MONO]   = "Mono",
253 	[V4L2_TUNER_MODE_STEREO] = "Stereo",
254 	[V4L2_TUNER_MODE_LANG1]  = "Lang1",
255 	[V4L2_TUNER_MODE_LANG2]  = "Lang2",
256 	[V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
257 };
258 
259 
260 static const char *control_values_hsm[] = {
261 	[PVR2_CVAL_HSM_FAIL] = "Fail",
262 	[PVR2_CVAL_HSM_HIGH] = "High",
263 	[PVR2_CVAL_HSM_FULL] = "Full",
264 };
265 
266 
267 static const char *pvr2_state_names[] = {
268 	[PVR2_STATE_NONE] =    "none",
269 	[PVR2_STATE_DEAD] =    "dead",
270 	[PVR2_STATE_COLD] =    "cold",
271 	[PVR2_STATE_WARM] =    "warm",
272 	[PVR2_STATE_ERROR] =   "error",
273 	[PVR2_STATE_READY] =   "ready",
274 	[PVR2_STATE_RUN] =     "run",
275 };
276 
277 
278 struct pvr2_fx2cmd_descdef {
279 	unsigned char id;
280 	unsigned char *desc;
281 };
282 
283 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
284 	{FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
285 	{FX2CMD_MEM_READ_DWORD, "read encoder dword"},
286 	{FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
287 	{FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
288 	{FX2CMD_REG_WRITE, "write encoder register"},
289 	{FX2CMD_REG_READ, "read encoder register"},
290 	{FX2CMD_MEMSEL, "encoder memsel"},
291 	{FX2CMD_I2C_WRITE, "i2c write"},
292 	{FX2CMD_I2C_READ, "i2c read"},
293 	{FX2CMD_GET_USB_SPEED, "get USB speed"},
294 	{FX2CMD_STREAMING_ON, "stream on"},
295 	{FX2CMD_STREAMING_OFF, "stream off"},
296 	{FX2CMD_FWPOST1, "fwpost1"},
297 	{FX2CMD_POWER_OFF, "power off"},
298 	{FX2CMD_POWER_ON, "power on"},
299 	{FX2CMD_DEEP_RESET, "deep reset"},
300 	{FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
301 	{FX2CMD_GET_IR_CODE, "get IR code"},
302 	{FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
303 	{FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
304 	{FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
305 	{FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
306 	{FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
307 	{FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
308 	{FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
309 	{FX2CMD_HCW_DEMOD_RESET_PIN, "hcw demod reset pin"},
310 	{FX2CMD_HCW_MAKO_SLEEP_PIN, "hcw mako sleep pin"},
311 };
312 
313 
314 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
315 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
316 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
317 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
318 static void pvr2_hdw_worker_poll(struct work_struct *work);
319 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
320 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
321 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
322 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
323 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
324 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
325 static void pvr2_hdw_quiescent_timeout(struct timer_list *);
326 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *);
327 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *);
328 static void pvr2_hdw_encoder_run_timeout(struct timer_list *);
329 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
330 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
331 				unsigned int timeout,int probe_fl,
332 				void *write_data,unsigned int write_len,
333 				void *read_data,unsigned int read_len);
334 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
335 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
336 
337 static void trace_stbit(const char *name,int val)
338 {
339 	pvr2_trace(PVR2_TRACE_STBITS,
340 		   "State bit %s <-- %s",
341 		   name,(val ? "true" : "false"));
342 }
343 
344 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
345 {
346 	struct pvr2_hdw *hdw = cptr->hdw;
347 	if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
348 		*vp = hdw->freqTable[hdw->freqProgSlot-1];
349 	} else {
350 		*vp = 0;
351 	}
352 	return 0;
353 }
354 
355 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
356 {
357 	struct pvr2_hdw *hdw = cptr->hdw;
358 	unsigned int slotId = hdw->freqProgSlot;
359 	if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
360 		hdw->freqTable[slotId-1] = v;
361 		/* Handle side effects correctly - if we're tuned to this
362 		   slot, then forgot the slot id relation since the stored
363 		   frequency has been changed. */
364 		if (hdw->freqSelector) {
365 			if (hdw->freqSlotRadio == slotId) {
366 				hdw->freqSlotRadio = 0;
367 			}
368 		} else {
369 			if (hdw->freqSlotTelevision == slotId) {
370 				hdw->freqSlotTelevision = 0;
371 			}
372 		}
373 	}
374 	return 0;
375 }
376 
377 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
378 {
379 	*vp = cptr->hdw->freqProgSlot;
380 	return 0;
381 }
382 
383 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
384 {
385 	struct pvr2_hdw *hdw = cptr->hdw;
386 	if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
387 		hdw->freqProgSlot = v;
388 	}
389 	return 0;
390 }
391 
392 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
393 {
394 	struct pvr2_hdw *hdw = cptr->hdw;
395 	*vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
396 	return 0;
397 }
398 
399 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
400 {
401 	unsigned freq = 0;
402 	struct pvr2_hdw *hdw = cptr->hdw;
403 	if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
404 	if (slotId > 0) {
405 		freq = hdw->freqTable[slotId-1];
406 		if (!freq) return 0;
407 		pvr2_hdw_set_cur_freq(hdw,freq);
408 	}
409 	if (hdw->freqSelector) {
410 		hdw->freqSlotRadio = slotId;
411 	} else {
412 		hdw->freqSlotTelevision = slotId;
413 	}
414 	return 0;
415 }
416 
417 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
418 {
419 	*vp = pvr2_hdw_get_cur_freq(cptr->hdw);
420 	return 0;
421 }
422 
423 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
424 {
425 	return cptr->hdw->freqDirty != 0;
426 }
427 
428 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
429 {
430 	cptr->hdw->freqDirty = 0;
431 }
432 
433 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
434 {
435 	pvr2_hdw_set_cur_freq(cptr->hdw,v);
436 	return 0;
437 }
438 
439 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
440 {
441 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
442 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
443 	if (stat != 0) {
444 		return stat;
445 	}
446 	*left = cap->bounds.left;
447 	return 0;
448 }
449 
450 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
451 {
452 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
453 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
454 	if (stat != 0) {
455 		return stat;
456 	}
457 	*left = cap->bounds.left;
458 	if (cap->bounds.width > cptr->hdw->cropw_val) {
459 		*left += cap->bounds.width - cptr->hdw->cropw_val;
460 	}
461 	return 0;
462 }
463 
464 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
465 {
466 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
467 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
468 	if (stat != 0) {
469 		return stat;
470 	}
471 	*top = cap->bounds.top;
472 	return 0;
473 }
474 
475 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
476 {
477 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
478 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
479 	if (stat != 0) {
480 		return stat;
481 	}
482 	*top = cap->bounds.top;
483 	if (cap->bounds.height > cptr->hdw->croph_val) {
484 		*top += cap->bounds.height - cptr->hdw->croph_val;
485 	}
486 	return 0;
487 }
488 
489 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
490 {
491 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
492 	int stat, bleftend, cleft;
493 
494 	stat = pvr2_hdw_check_cropcap(cptr->hdw);
495 	if (stat != 0) {
496 		return stat;
497 	}
498 	bleftend = cap->bounds.left+cap->bounds.width;
499 	cleft = cptr->hdw->cropl_val;
500 
501 	*width = cleft < bleftend ? bleftend-cleft : 0;
502 	return 0;
503 }
504 
505 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
506 {
507 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
508 	int stat, btopend, ctop;
509 
510 	stat = pvr2_hdw_check_cropcap(cptr->hdw);
511 	if (stat != 0) {
512 		return stat;
513 	}
514 	btopend = cap->bounds.top+cap->bounds.height;
515 	ctop = cptr->hdw->cropt_val;
516 
517 	*height = ctop < btopend ? btopend-ctop : 0;
518 	return 0;
519 }
520 
521 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
522 {
523 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
524 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
525 	if (stat != 0) {
526 		return stat;
527 	}
528 	*val = cap->bounds.left;
529 	return 0;
530 }
531 
532 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
533 {
534 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
535 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
536 	if (stat != 0) {
537 		return stat;
538 	}
539 	*val = cap->bounds.top;
540 	return 0;
541 }
542 
543 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
544 {
545 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
546 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
547 	if (stat != 0) {
548 		return stat;
549 	}
550 	*val = cap->bounds.width;
551 	return 0;
552 }
553 
554 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
555 {
556 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
557 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
558 	if (stat != 0) {
559 		return stat;
560 	}
561 	*val = cap->bounds.height;
562 	return 0;
563 }
564 
565 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
566 {
567 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
568 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
569 	if (stat != 0) {
570 		return stat;
571 	}
572 	*val = cap->defrect.left;
573 	return 0;
574 }
575 
576 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
577 {
578 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
579 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
580 	if (stat != 0) {
581 		return stat;
582 	}
583 	*val = cap->defrect.top;
584 	return 0;
585 }
586 
587 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
588 {
589 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
590 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
591 	if (stat != 0) {
592 		return stat;
593 	}
594 	*val = cap->defrect.width;
595 	return 0;
596 }
597 
598 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
599 {
600 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
601 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
602 	if (stat != 0) {
603 		return stat;
604 	}
605 	*val = cap->defrect.height;
606 	return 0;
607 }
608 
609 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
610 {
611 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
612 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
613 	if (stat != 0) {
614 		return stat;
615 	}
616 	*val = cap->pixelaspect.numerator;
617 	return 0;
618 }
619 
620 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
621 {
622 	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
623 	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
624 	if (stat != 0) {
625 		return stat;
626 	}
627 	*val = cap->pixelaspect.denominator;
628 	return 0;
629 }
630 
631 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
632 {
633 	/* Actual maximum depends on the video standard in effect. */
634 	if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
635 		*vp = 480;
636 	} else {
637 		*vp = 576;
638 	}
639 	return 0;
640 }
641 
642 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
643 {
644 	/* Actual minimum depends on device digitizer type. */
645 	if (cptr->hdw->hdw_desc->flag_has_cx25840) {
646 		*vp = 75;
647 	} else {
648 		*vp = 17;
649 	}
650 	return 0;
651 }
652 
653 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
654 {
655 	*vp = cptr->hdw->input_val;
656 	return 0;
657 }
658 
659 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
660 {
661 	if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
662 		return 0;
663 	return ((1UL << v) & cptr->hdw->input_allowed_mask) != 0;
664 }
665 
666 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
667 {
668 	return pvr2_hdw_set_input(cptr->hdw,v);
669 }
670 
671 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
672 {
673 	return cptr->hdw->input_dirty != 0;
674 }
675 
676 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
677 {
678 	cptr->hdw->input_dirty = 0;
679 }
680 
681 
682 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
683 {
684 	unsigned long fv;
685 	struct pvr2_hdw *hdw = cptr->hdw;
686 	if (hdw->tuner_signal_stale) {
687 		pvr2_hdw_status_poll(hdw);
688 	}
689 	fv = hdw->tuner_signal_info.rangehigh;
690 	if (!fv) {
691 		/* Safety fallback */
692 		*vp = TV_MAX_FREQ;
693 		return 0;
694 	}
695 	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
696 		fv = (fv * 125) / 2;
697 	} else {
698 		fv = fv * 62500;
699 	}
700 	*vp = fv;
701 	return 0;
702 }
703 
704 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
705 {
706 	unsigned long fv;
707 	struct pvr2_hdw *hdw = cptr->hdw;
708 	if (hdw->tuner_signal_stale) {
709 		pvr2_hdw_status_poll(hdw);
710 	}
711 	fv = hdw->tuner_signal_info.rangelow;
712 	if (!fv) {
713 		/* Safety fallback */
714 		*vp = TV_MIN_FREQ;
715 		return 0;
716 	}
717 	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
718 		fv = (fv * 125) / 2;
719 	} else {
720 		fv = fv * 62500;
721 	}
722 	*vp = fv;
723 	return 0;
724 }
725 
726 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
727 {
728 	return cptr->hdw->enc_stale != 0;
729 }
730 
731 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
732 {
733 	cptr->hdw->enc_stale = 0;
734 	cptr->hdw->enc_unsafe_stale = 0;
735 }
736 
737 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
738 {
739 	int ret;
740 	struct v4l2_ext_controls cs;
741 	struct v4l2_ext_control c1;
742 	memset(&cs,0,sizeof(cs));
743 	memset(&c1,0,sizeof(c1));
744 	cs.controls = &c1;
745 	cs.count = 1;
746 	c1.id = cptr->info->v4l_id;
747 	ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
748 				VIDIOC_G_EXT_CTRLS);
749 	if (ret) return ret;
750 	*vp = c1.value;
751 	return 0;
752 }
753 
754 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
755 {
756 	int ret;
757 	struct pvr2_hdw *hdw = cptr->hdw;
758 	struct v4l2_ext_controls cs;
759 	struct v4l2_ext_control c1;
760 	memset(&cs,0,sizeof(cs));
761 	memset(&c1,0,sizeof(c1));
762 	cs.controls = &c1;
763 	cs.count = 1;
764 	c1.id = cptr->info->v4l_id;
765 	c1.value = v;
766 	ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
767 				hdw->state_encoder_run, &cs,
768 				VIDIOC_S_EXT_CTRLS);
769 	if (ret == -EBUSY) {
770 		/* Oops.  cx2341x is telling us it's not safe to change
771 		   this control while we're capturing.  Make a note of this
772 		   fact so that the pipeline will be stopped the next time
773 		   controls are committed.  Then go on ahead and store this
774 		   change anyway. */
775 		ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
776 					0, &cs,
777 					VIDIOC_S_EXT_CTRLS);
778 		if (!ret) hdw->enc_unsafe_stale = !0;
779 	}
780 	if (ret) return ret;
781 	hdw->enc_stale = !0;
782 	return 0;
783 }
784 
785 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
786 {
787 	struct v4l2_queryctrl qctrl = {};
788 	struct pvr2_ctl_info *info;
789 	qctrl.id = cptr->info->v4l_id;
790 	cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
791 	/* Strip out the const so we can adjust a function pointer.  It's
792 	   OK to do this here because we know this is a dynamically created
793 	   control, so the underlying storage for the info pointer is (a)
794 	   private to us, and (b) not in read-only storage.  Either we do
795 	   this or we significantly complicate the underlying control
796 	   implementation. */
797 	info = (struct pvr2_ctl_info *)(cptr->info);
798 	if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
799 		if (info->set_value) {
800 			info->set_value = NULL;
801 		}
802 	} else {
803 		if (!(info->set_value)) {
804 			info->set_value = ctrl_cx2341x_set;
805 		}
806 	}
807 	return qctrl.flags;
808 }
809 
810 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
811 {
812 	*vp = cptr->hdw->state_pipeline_req;
813 	return 0;
814 }
815 
816 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
817 {
818 	*vp = cptr->hdw->master_state;
819 	return 0;
820 }
821 
822 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
823 {
824 	int result = pvr2_hdw_is_hsm(cptr->hdw);
825 	*vp = PVR2_CVAL_HSM_FULL;
826 	if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
827 	if (result) *vp = PVR2_CVAL_HSM_HIGH;
828 	return 0;
829 }
830 
831 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
832 {
833 	*vp = pvr2_hdw_get_detected_std(cptr->hdw);
834 	return 0;
835 }
836 
837 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
838 {
839 	*vp = cptr->hdw->std_mask_avail;
840 	return 0;
841 }
842 
843 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
844 {
845 	struct pvr2_hdw *hdw = cptr->hdw;
846 	v4l2_std_id ns;
847 	ns = hdw->std_mask_avail;
848 	ns = (ns & ~m) | (v & m);
849 	if (ns == hdw->std_mask_avail) return 0;
850 	hdw->std_mask_avail = ns;
851 	hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
852 	return 0;
853 }
854 
855 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
856 			       char *bufPtr,unsigned int bufSize,
857 			       unsigned int *len)
858 {
859 	*len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
860 	return 0;
861 }
862 
863 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
864 			       const char *bufPtr,unsigned int bufSize,
865 			       int *mskp,int *valp)
866 {
867 	v4l2_std_id id;
868 	if (!pvr2_std_str_to_id(&id, bufPtr, bufSize))
869 		return -EINVAL;
870 	if (mskp) *mskp = id;
871 	if (valp) *valp = id;
872 	return 0;
873 }
874 
875 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
876 {
877 	*vp = cptr->hdw->std_mask_cur;
878 	return 0;
879 }
880 
881 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
882 {
883 	struct pvr2_hdw *hdw = cptr->hdw;
884 	v4l2_std_id ns;
885 	ns = hdw->std_mask_cur;
886 	ns = (ns & ~m) | (v & m);
887 	if (ns == hdw->std_mask_cur) return 0;
888 	hdw->std_mask_cur = ns;
889 	hdw->std_dirty = !0;
890 	return 0;
891 }
892 
893 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
894 {
895 	return cptr->hdw->std_dirty != 0;
896 }
897 
898 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
899 {
900 	cptr->hdw->std_dirty = 0;
901 }
902 
903 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
904 {
905 	struct pvr2_hdw *hdw = cptr->hdw;
906 	pvr2_hdw_status_poll(hdw);
907 	*vp = hdw->tuner_signal_info.signal;
908 	return 0;
909 }
910 
911 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
912 {
913 	int val = 0;
914 	unsigned int subchan;
915 	struct pvr2_hdw *hdw = cptr->hdw;
916 	pvr2_hdw_status_poll(hdw);
917 	subchan = hdw->tuner_signal_info.rxsubchans;
918 	if (subchan & V4L2_TUNER_SUB_MONO) {
919 		val |= (1 << V4L2_TUNER_MODE_MONO);
920 	}
921 	if (subchan & V4L2_TUNER_SUB_STEREO) {
922 		val |= (1 << V4L2_TUNER_MODE_STEREO);
923 	}
924 	if (subchan & V4L2_TUNER_SUB_LANG1) {
925 		val |= (1 << V4L2_TUNER_MODE_LANG1);
926 	}
927 	if (subchan & V4L2_TUNER_SUB_LANG2) {
928 		val |= (1 << V4L2_TUNER_MODE_LANG2);
929 	}
930 	*vp = val;
931 	return 0;
932 }
933 
934 
935 #define DEFINT(vmin,vmax) \
936 	.type = pvr2_ctl_int, \
937 	.def.type_int.min_value = vmin, \
938 	.def.type_int.max_value = vmax
939 
940 #define DEFENUM(tab) \
941 	.type = pvr2_ctl_enum, \
942 	.def.type_enum.count = ARRAY_SIZE(tab), \
943 	.def.type_enum.value_names = tab
944 
945 #define DEFBOOL \
946 	.type = pvr2_ctl_bool
947 
948 #define DEFMASK(msk,tab) \
949 	.type = pvr2_ctl_bitmask, \
950 	.def.type_bitmask.valid_bits = msk, \
951 	.def.type_bitmask.bit_names = tab
952 
953 #define DEFREF(vname) \
954 	.set_value = ctrl_set_##vname, \
955 	.get_value = ctrl_get_##vname, \
956 	.is_dirty = ctrl_isdirty_##vname, \
957 	.clear_dirty = ctrl_cleardirty_##vname
958 
959 
960 #define VCREATE_FUNCS(vname) \
961 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
962 {*vp = cptr->hdw->vname##_val; return 0;} \
963 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
964 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
965 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
966 {return cptr->hdw->vname##_dirty != 0;} \
967 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
968 {cptr->hdw->vname##_dirty = 0;}
969 
970 VCREATE_FUNCS(brightness)
971 VCREATE_FUNCS(contrast)
972 VCREATE_FUNCS(saturation)
973 VCREATE_FUNCS(hue)
974 VCREATE_FUNCS(volume)
975 VCREATE_FUNCS(balance)
976 VCREATE_FUNCS(bass)
977 VCREATE_FUNCS(treble)
978 VCREATE_FUNCS(mute)
979 VCREATE_FUNCS(cropl)
980 VCREATE_FUNCS(cropt)
981 VCREATE_FUNCS(cropw)
982 VCREATE_FUNCS(croph)
983 VCREATE_FUNCS(audiomode)
984 VCREATE_FUNCS(res_hor)
985 VCREATE_FUNCS(res_ver)
986 VCREATE_FUNCS(srate)
987 
988 /* Table definition of all controls which can be manipulated */
989 static const struct pvr2_ctl_info control_defs[] = {
990 	{
991 		.v4l_id = V4L2_CID_BRIGHTNESS,
992 		.desc = "Brightness",
993 		.name = "brightness",
994 		.default_value = 128,
995 		DEFREF(brightness),
996 		DEFINT(0,255),
997 	},{
998 		.v4l_id = V4L2_CID_CONTRAST,
999 		.desc = "Contrast",
1000 		.name = "contrast",
1001 		.default_value = 68,
1002 		DEFREF(contrast),
1003 		DEFINT(0,127),
1004 	},{
1005 		.v4l_id = V4L2_CID_SATURATION,
1006 		.desc = "Saturation",
1007 		.name = "saturation",
1008 		.default_value = 64,
1009 		DEFREF(saturation),
1010 		DEFINT(0,127),
1011 	},{
1012 		.v4l_id = V4L2_CID_HUE,
1013 		.desc = "Hue",
1014 		.name = "hue",
1015 		.default_value = 0,
1016 		DEFREF(hue),
1017 		DEFINT(-128,127),
1018 	},{
1019 		.v4l_id = V4L2_CID_AUDIO_VOLUME,
1020 		.desc = "Volume",
1021 		.name = "volume",
1022 		.default_value = 62000,
1023 		DEFREF(volume),
1024 		DEFINT(0,65535),
1025 	},{
1026 		.v4l_id = V4L2_CID_AUDIO_BALANCE,
1027 		.desc = "Balance",
1028 		.name = "balance",
1029 		.default_value = 0,
1030 		DEFREF(balance),
1031 		DEFINT(-32768,32767),
1032 	},{
1033 		.v4l_id = V4L2_CID_AUDIO_BASS,
1034 		.desc = "Bass",
1035 		.name = "bass",
1036 		.default_value = 0,
1037 		DEFREF(bass),
1038 		DEFINT(-32768,32767),
1039 	},{
1040 		.v4l_id = V4L2_CID_AUDIO_TREBLE,
1041 		.desc = "Treble",
1042 		.name = "treble",
1043 		.default_value = 0,
1044 		DEFREF(treble),
1045 		DEFINT(-32768,32767),
1046 	},{
1047 		.v4l_id = V4L2_CID_AUDIO_MUTE,
1048 		.desc = "Mute",
1049 		.name = "mute",
1050 		.default_value = 0,
1051 		DEFREF(mute),
1052 		DEFBOOL,
1053 	}, {
1054 		.desc = "Capture crop left margin",
1055 		.name = "crop_left",
1056 		.internal_id = PVR2_CID_CROPL,
1057 		.default_value = 0,
1058 		DEFREF(cropl),
1059 		DEFINT(-129, 340),
1060 		.get_min_value = ctrl_cropl_min_get,
1061 		.get_max_value = ctrl_cropl_max_get,
1062 		.get_def_value = ctrl_get_cropcapdl,
1063 	}, {
1064 		.desc = "Capture crop top margin",
1065 		.name = "crop_top",
1066 		.internal_id = PVR2_CID_CROPT,
1067 		.default_value = 0,
1068 		DEFREF(cropt),
1069 		DEFINT(-35, 544),
1070 		.get_min_value = ctrl_cropt_min_get,
1071 		.get_max_value = ctrl_cropt_max_get,
1072 		.get_def_value = ctrl_get_cropcapdt,
1073 	}, {
1074 		.desc = "Capture crop width",
1075 		.name = "crop_width",
1076 		.internal_id = PVR2_CID_CROPW,
1077 		.default_value = 720,
1078 		DEFREF(cropw),
1079 		DEFINT(0, 864),
1080 		.get_max_value = ctrl_cropw_max_get,
1081 		.get_def_value = ctrl_get_cropcapdw,
1082 	}, {
1083 		.desc = "Capture crop height",
1084 		.name = "crop_height",
1085 		.internal_id = PVR2_CID_CROPH,
1086 		.default_value = 480,
1087 		DEFREF(croph),
1088 		DEFINT(0, 576),
1089 		.get_max_value = ctrl_croph_max_get,
1090 		.get_def_value = ctrl_get_cropcapdh,
1091 	}, {
1092 		.desc = "Capture capability pixel aspect numerator",
1093 		.name = "cropcap_pixel_numerator",
1094 		.internal_id = PVR2_CID_CROPCAPPAN,
1095 		.get_value = ctrl_get_cropcappan,
1096 	}, {
1097 		.desc = "Capture capability pixel aspect denominator",
1098 		.name = "cropcap_pixel_denominator",
1099 		.internal_id = PVR2_CID_CROPCAPPAD,
1100 		.get_value = ctrl_get_cropcappad,
1101 	}, {
1102 		.desc = "Capture capability bounds top",
1103 		.name = "cropcap_bounds_top",
1104 		.internal_id = PVR2_CID_CROPCAPBT,
1105 		.get_value = ctrl_get_cropcapbt,
1106 	}, {
1107 		.desc = "Capture capability bounds left",
1108 		.name = "cropcap_bounds_left",
1109 		.internal_id = PVR2_CID_CROPCAPBL,
1110 		.get_value = ctrl_get_cropcapbl,
1111 	}, {
1112 		.desc = "Capture capability bounds width",
1113 		.name = "cropcap_bounds_width",
1114 		.internal_id = PVR2_CID_CROPCAPBW,
1115 		.get_value = ctrl_get_cropcapbw,
1116 	}, {
1117 		.desc = "Capture capability bounds height",
1118 		.name = "cropcap_bounds_height",
1119 		.internal_id = PVR2_CID_CROPCAPBH,
1120 		.get_value = ctrl_get_cropcapbh,
1121 	},{
1122 		.desc = "Video Source",
1123 		.name = "input",
1124 		.internal_id = PVR2_CID_INPUT,
1125 		.default_value = PVR2_CVAL_INPUT_TV,
1126 		.check_value = ctrl_check_input,
1127 		DEFREF(input),
1128 		DEFENUM(control_values_input),
1129 	},{
1130 		.desc = "Audio Mode",
1131 		.name = "audio_mode",
1132 		.internal_id = PVR2_CID_AUDIOMODE,
1133 		.default_value = V4L2_TUNER_MODE_STEREO,
1134 		DEFREF(audiomode),
1135 		DEFENUM(control_values_audiomode),
1136 	},{
1137 		.desc = "Horizontal capture resolution",
1138 		.name = "resolution_hor",
1139 		.internal_id = PVR2_CID_HRES,
1140 		.default_value = 720,
1141 		DEFREF(res_hor),
1142 		DEFINT(19,720),
1143 	},{
1144 		.desc = "Vertical capture resolution",
1145 		.name = "resolution_ver",
1146 		.internal_id = PVR2_CID_VRES,
1147 		.default_value = 480,
1148 		DEFREF(res_ver),
1149 		DEFINT(17,576),
1150 		/* Hook in check for video standard and adjust maximum
1151 		   depending on the standard. */
1152 		.get_max_value = ctrl_vres_max_get,
1153 		.get_min_value = ctrl_vres_min_get,
1154 	},{
1155 		.v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1156 		.default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1157 		.desc = "Audio Sampling Frequency",
1158 		.name = "srate",
1159 		DEFREF(srate),
1160 		DEFENUM(control_values_srate),
1161 	},{
1162 		.desc = "Tuner Frequency (Hz)",
1163 		.name = "frequency",
1164 		.internal_id = PVR2_CID_FREQUENCY,
1165 		.default_value = 0,
1166 		.set_value = ctrl_freq_set,
1167 		.get_value = ctrl_freq_get,
1168 		.is_dirty = ctrl_freq_is_dirty,
1169 		.clear_dirty = ctrl_freq_clear_dirty,
1170 		DEFINT(0,0),
1171 		/* Hook in check for input value (tv/radio) and adjust
1172 		   max/min values accordingly */
1173 		.get_max_value = ctrl_freq_max_get,
1174 		.get_min_value = ctrl_freq_min_get,
1175 	},{
1176 		.desc = "Channel",
1177 		.name = "channel",
1178 		.set_value = ctrl_channel_set,
1179 		.get_value = ctrl_channel_get,
1180 		DEFINT(0,FREQTABLE_SIZE),
1181 	},{
1182 		.desc = "Channel Program Frequency",
1183 		.name = "freq_table_value",
1184 		.set_value = ctrl_channelfreq_set,
1185 		.get_value = ctrl_channelfreq_get,
1186 		DEFINT(0,0),
1187 		/* Hook in check for input value (tv/radio) and adjust
1188 		   max/min values accordingly */
1189 		.get_max_value = ctrl_freq_max_get,
1190 		.get_min_value = ctrl_freq_min_get,
1191 	},{
1192 		.desc = "Channel Program ID",
1193 		.name = "freq_table_channel",
1194 		.set_value = ctrl_channelprog_set,
1195 		.get_value = ctrl_channelprog_get,
1196 		DEFINT(0,FREQTABLE_SIZE),
1197 	},{
1198 		.desc = "Streaming Enabled",
1199 		.name = "streaming_enabled",
1200 		.get_value = ctrl_streamingenabled_get,
1201 		DEFBOOL,
1202 	},{
1203 		.desc = "USB Speed",
1204 		.name = "usb_speed",
1205 		.get_value = ctrl_hsm_get,
1206 		DEFENUM(control_values_hsm),
1207 	},{
1208 		.desc = "Master State",
1209 		.name = "master_state",
1210 		.get_value = ctrl_masterstate_get,
1211 		DEFENUM(pvr2_state_names),
1212 	},{
1213 		.desc = "Signal Present",
1214 		.name = "signal_present",
1215 		.get_value = ctrl_signal_get,
1216 		DEFINT(0,65535),
1217 	},{
1218 		.desc = "Audio Modes Present",
1219 		.name = "audio_modes_present",
1220 		.get_value = ctrl_audio_modes_present_get,
1221 		/* For this type we "borrow" the V4L2_TUNER_MODE enum from
1222 		   v4l.  Nothing outside of this module cares about this,
1223 		   but I reuse it in order to also reuse the
1224 		   control_values_audiomode string table. */
1225 		DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1226 			 (1 << V4L2_TUNER_MODE_STEREO)|
1227 			 (1 << V4L2_TUNER_MODE_LANG1)|
1228 			 (1 << V4L2_TUNER_MODE_LANG2)),
1229 			control_values_audiomode),
1230 	},{
1231 		.desc = "Video Standards Available Mask",
1232 		.name = "video_standard_mask_available",
1233 		.internal_id = PVR2_CID_STDAVAIL,
1234 		.skip_init = !0,
1235 		.get_value = ctrl_stdavail_get,
1236 		.set_value = ctrl_stdavail_set,
1237 		.val_to_sym = ctrl_std_val_to_sym,
1238 		.sym_to_val = ctrl_std_sym_to_val,
1239 		.type = pvr2_ctl_bitmask,
1240 	},{
1241 		.desc = "Video Standards In Use Mask",
1242 		.name = "video_standard_mask_active",
1243 		.internal_id = PVR2_CID_STDCUR,
1244 		.skip_init = !0,
1245 		.get_value = ctrl_stdcur_get,
1246 		.set_value = ctrl_stdcur_set,
1247 		.is_dirty = ctrl_stdcur_is_dirty,
1248 		.clear_dirty = ctrl_stdcur_clear_dirty,
1249 		.val_to_sym = ctrl_std_val_to_sym,
1250 		.sym_to_val = ctrl_std_sym_to_val,
1251 		.type = pvr2_ctl_bitmask,
1252 	},{
1253 		.desc = "Video Standards Detected Mask",
1254 		.name = "video_standard_mask_detected",
1255 		.internal_id = PVR2_CID_STDDETECT,
1256 		.skip_init = !0,
1257 		.get_value = ctrl_stddetect_get,
1258 		.val_to_sym = ctrl_std_val_to_sym,
1259 		.sym_to_val = ctrl_std_sym_to_val,
1260 		.type = pvr2_ctl_bitmask,
1261 	}
1262 };
1263 
1264 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1265 
1266 
1267 const char *pvr2_config_get_name(enum pvr2_config cfg)
1268 {
1269 	switch (cfg) {
1270 	case pvr2_config_empty: return "empty";
1271 	case pvr2_config_mpeg: return "mpeg";
1272 	case pvr2_config_vbi: return "vbi";
1273 	case pvr2_config_pcm: return "pcm";
1274 	case pvr2_config_rawvideo: return "raw video";
1275 	}
1276 	return "<unknown>";
1277 }
1278 
1279 
1280 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1281 {
1282 	return hdw->usb_dev;
1283 }
1284 
1285 
1286 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1287 {
1288 	return hdw->serial_number;
1289 }
1290 
1291 
1292 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1293 {
1294 	return hdw->bus_info;
1295 }
1296 
1297 
1298 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1299 {
1300 	return hdw->identifier;
1301 }
1302 
1303 
1304 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1305 {
1306 	return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1307 }
1308 
1309 /* Set the currently tuned frequency and account for all possible
1310    driver-core side effects of this action. */
1311 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1312 {
1313 	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1314 		if (hdw->freqSelector) {
1315 			/* Swing over to radio frequency selection */
1316 			hdw->freqSelector = 0;
1317 			hdw->freqDirty = !0;
1318 		}
1319 		if (hdw->freqValRadio != val) {
1320 			hdw->freqValRadio = val;
1321 			hdw->freqSlotRadio = 0;
1322 			hdw->freqDirty = !0;
1323 		}
1324 	} else {
1325 		if (!(hdw->freqSelector)) {
1326 			/* Swing over to television frequency selection */
1327 			hdw->freqSelector = 1;
1328 			hdw->freqDirty = !0;
1329 		}
1330 		if (hdw->freqValTelevision != val) {
1331 			hdw->freqValTelevision = val;
1332 			hdw->freqSlotTelevision = 0;
1333 			hdw->freqDirty = !0;
1334 		}
1335 	}
1336 }
1337 
1338 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1339 {
1340 	return hdw->unit_number;
1341 }
1342 
1343 
1344 /* Attempt to locate one of the given set of files.  Messages are logged
1345    appropriate to what has been found.  The return value will be 0 or
1346    greater on success (it will be the index of the file name found) and
1347    fw_entry will be filled in.  Otherwise a negative error is returned on
1348    failure.  If the return value is -ENOENT then no viable firmware file
1349    could be located. */
1350 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1351 				const struct firmware **fw_entry,
1352 				const char *fwtypename,
1353 				unsigned int fwcount,
1354 				const char *fwnames[])
1355 {
1356 	unsigned int idx;
1357 	int ret = -EINVAL;
1358 	for (idx = 0; idx < fwcount; idx++) {
1359 		ret = request_firmware(fw_entry,
1360 				       fwnames[idx],
1361 				       &hdw->usb_dev->dev);
1362 		if (!ret) {
1363 			trace_firmware("Located %s firmware: %s; uploading...",
1364 				       fwtypename,
1365 				       fwnames[idx]);
1366 			return idx;
1367 		}
1368 		if (ret == -ENOENT) continue;
1369 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1370 			   "request_firmware fatal error with code=%d",ret);
1371 		return ret;
1372 	}
1373 	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374 		   "***WARNING*** Device %s firmware seems to be missing.",
1375 		   fwtypename);
1376 	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1377 		   "Did you install the pvrusb2 firmware files in their proper location?");
1378 	if (fwcount == 1) {
1379 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1380 			   "request_firmware unable to locate %s file %s",
1381 			   fwtypename,fwnames[0]);
1382 	} else {
1383 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1384 			   "request_firmware unable to locate one of the following %s files:",
1385 			   fwtypename);
1386 		for (idx = 0; idx < fwcount; idx++) {
1387 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1388 				   "request_firmware: Failed to find %s",
1389 				   fwnames[idx]);
1390 		}
1391 	}
1392 	return ret;
1393 }
1394 
1395 
1396 /*
1397  * pvr2_upload_firmware1().
1398  *
1399  * Send the 8051 firmware to the device.  After the upload, arrange for
1400  * device to re-enumerate.
1401  *
1402  * NOTE : the pointer to the firmware data given by request_firmware()
1403  * is not suitable for an usb transaction.
1404  *
1405  */
1406 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1407 {
1408 	const struct firmware *fw_entry = NULL;
1409 	void  *fw_ptr;
1410 	unsigned int pipe;
1411 	unsigned int fwsize;
1412 	int ret;
1413 	u16 address;
1414 
1415 	if (!hdw->hdw_desc->fx2_firmware.cnt) {
1416 		hdw->fw1_state = FW1_STATE_OK;
1417 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418 			   "Connected device type defines no firmware to upload; ignoring firmware");
1419 		return -ENOTTY;
1420 	}
1421 
1422 	hdw->fw1_state = FW1_STATE_FAILED; // default result
1423 
1424 	trace_firmware("pvr2_upload_firmware1");
1425 
1426 	ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1427 				   hdw->hdw_desc->fx2_firmware.cnt,
1428 				   hdw->hdw_desc->fx2_firmware.lst);
1429 	if (ret < 0) {
1430 		if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1431 		return ret;
1432 	}
1433 
1434 	usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1435 
1436 	pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1437 	fwsize = fw_entry->size;
1438 
1439 	if ((fwsize != 0x2000) &&
1440 	    (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1441 		if (hdw->hdw_desc->flag_fx2_16kb) {
1442 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1443 				   "Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
1444 				   fwsize);
1445 		} else {
1446 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1447 				   "Wrong fx2 firmware size (expected 8192, got %u)",
1448 				   fwsize);
1449 		}
1450 		release_firmware(fw_entry);
1451 		return -ENOMEM;
1452 	}
1453 
1454 	fw_ptr = kmalloc(0x800, GFP_KERNEL);
1455 	if (fw_ptr == NULL){
1456 		release_firmware(fw_entry);
1457 		return -ENOMEM;
1458 	}
1459 
1460 	/* We have to hold the CPU during firmware upload. */
1461 	pvr2_hdw_cpureset_assert(hdw,1);
1462 
1463 	/* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1464 	   chunk. */
1465 
1466 	ret = 0;
1467 	for (address = 0; address < fwsize; address += 0x800) {
1468 		memcpy(fw_ptr, fw_entry->data + address, 0x800);
1469 		ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1470 				       0, fw_ptr, 0x800, HZ);
1471 	}
1472 
1473 	trace_firmware("Upload done, releasing device's CPU");
1474 
1475 	/* Now release the CPU.  It will disconnect and reconnect later. */
1476 	pvr2_hdw_cpureset_assert(hdw,0);
1477 
1478 	kfree(fw_ptr);
1479 	release_firmware(fw_entry);
1480 
1481 	trace_firmware("Upload done (%d bytes sent)",ret);
1482 
1483 	/* We should have written fwsize bytes */
1484 	if (ret == fwsize) {
1485 		hdw->fw1_state = FW1_STATE_RELOAD;
1486 		return 0;
1487 	}
1488 
1489 	return -EIO;
1490 }
1491 
1492 
1493 /*
1494  * pvr2_upload_firmware2()
1495  *
1496  * This uploads encoder firmware on endpoint 2.
1497  *
1498  */
1499 
1500 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1501 {
1502 	const struct firmware *fw_entry = NULL;
1503 	void  *fw_ptr;
1504 	unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1505 	int actual_length;
1506 	int ret = 0;
1507 	int fwidx;
1508 	static const char *fw_files[] = {
1509 		CX2341X_FIRM_ENC_FILENAME,
1510 	};
1511 
1512 	if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1513 		return 0;
1514 	}
1515 
1516 	trace_firmware("pvr2_upload_firmware2");
1517 
1518 	ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1519 				   ARRAY_SIZE(fw_files), fw_files);
1520 	if (ret < 0) return ret;
1521 	fwidx = ret;
1522 	ret = 0;
1523 	/* Since we're about to completely reinitialize the encoder,
1524 	   invalidate our cached copy of its configuration state.  Next
1525 	   time we configure the encoder, then we'll fully configure it. */
1526 	hdw->enc_cur_valid = 0;
1527 
1528 	/* Encoder is about to be reset so note that as far as we're
1529 	   concerned now, the encoder has never been run. */
1530 	del_timer_sync(&hdw->encoder_run_timer);
1531 	if (hdw->state_encoder_runok) {
1532 		hdw->state_encoder_runok = 0;
1533 		trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1534 	}
1535 
1536 	/* First prepare firmware loading */
1537 	ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1538 	ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1539 	ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1540 	ret |= pvr2_hdw_cmd_deep_reset(hdw);
1541 	ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1542 	ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1543 	ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1544 	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1545 	ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1546 	ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1547 	ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1548 	ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1549 	ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1550 	ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1551 	ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1552 	ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1553 	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1554 	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1555 
1556 	if (ret) {
1557 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1558 			   "firmware2 upload prep failed, ret=%d",ret);
1559 		release_firmware(fw_entry);
1560 		goto done;
1561 	}
1562 
1563 	/* Now send firmware */
1564 
1565 	fw_len = fw_entry->size;
1566 
1567 	if (fw_len % sizeof(u32)) {
1568 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1569 			   "size of %s firmware must be a multiple of %zu bytes",
1570 			   fw_files[fwidx],sizeof(u32));
1571 		release_firmware(fw_entry);
1572 		ret = -EINVAL;
1573 		goto done;
1574 	}
1575 
1576 	fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577 	if (fw_ptr == NULL){
1578 		release_firmware(fw_entry);
1579 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580 			   "failed to allocate memory for firmware2 upload");
1581 		ret = -ENOMEM;
1582 		goto done;
1583 	}
1584 
1585 	pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1586 
1587 	fw_done = 0;
1588 	for (fw_done = 0; fw_done < fw_len;) {
1589 		bcnt = fw_len - fw_done;
1590 		if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591 		memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592 		/* Usbsnoop log shows that we must swap bytes... */
1593 		/* Some background info: The data being swapped here is a
1594 		   firmware image destined for the mpeg encoder chip that
1595 		   lives at the other end of a USB endpoint.  The encoder
1596 		   chip always talks in 32 bit chunks and its storage is
1597 		   organized into 32 bit words.  However from the file
1598 		   system to the encoder chip everything is purely a byte
1599 		   stream.  The firmware file's contents are always 32 bit
1600 		   swapped from what the encoder expects.  Thus the need
1601 		   always exists to swap the bytes regardless of the endian
1602 		   type of the host processor and therefore swab32() makes
1603 		   the most sense. */
1604 		for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605 			((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1606 
1607 		ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1608 				    &actual_length, HZ);
1609 		ret |= (actual_length != bcnt);
1610 		if (ret) break;
1611 		fw_done += bcnt;
1612 	}
1613 
1614 	trace_firmware("upload of %s : %i / %i ",
1615 		       fw_files[fwidx],fw_done,fw_len);
1616 
1617 	kfree(fw_ptr);
1618 	release_firmware(fw_entry);
1619 
1620 	if (ret) {
1621 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622 			   "firmware2 upload transfer failure");
1623 		goto done;
1624 	}
1625 
1626 	/* Finish upload */
1627 
1628 	ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629 	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630 	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1631 
1632 	if (ret) {
1633 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634 			   "firmware2 upload post-proc failure");
1635 	}
1636 
1637  done:
1638 	if (hdw->hdw_desc->signal_routing_scheme ==
1639 	    PVR2_ROUTING_SCHEME_GOTVIEW) {
1640 		/* Ensure that GPIO 11 is set to output for GOTVIEW
1641 		   hardware. */
1642 		pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1643 	}
1644 	return ret;
1645 }
1646 
1647 
1648 static const char *pvr2_get_state_name(unsigned int st)
1649 {
1650 	if (st < ARRAY_SIZE(pvr2_state_names)) {
1651 		return pvr2_state_names[st];
1652 	}
1653 	return "???";
1654 }
1655 
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1657 {
1658 	/* Even though we really only care about the video decoder chip at
1659 	   this point, we'll broadcast stream on/off to all sub-devices
1660 	   anyway, just in case somebody else wants to hear the
1661 	   command... */
1662 	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1663 		   (enablefl ? "on" : "off"));
1664 	v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1665 	v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1666 	if (hdw->decoder_client_id) {
1667 		/* We get here if the encoder has been noticed.  Otherwise
1668 		   we'll issue a warning to the user (which should
1669 		   normally never happen). */
1670 		return 0;
1671 	}
1672 	if (!hdw->flag_decoder_missed) {
1673 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1674 			   "***WARNING*** No decoder present");
1675 		hdw->flag_decoder_missed = !0;
1676 		trace_stbit("flag_decoder_missed",
1677 			    hdw->flag_decoder_missed);
1678 	}
1679 	return -EIO;
1680 }
1681 
1682 
1683 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1684 {
1685 	return hdw->master_state;
1686 }
1687 
1688 
1689 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1690 {
1691 	if (!hdw->flag_tripped) return 0;
1692 	hdw->flag_tripped = 0;
1693 	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694 		   "Clearing driver error status");
1695 	return !0;
1696 }
1697 
1698 
1699 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1700 {
1701 	int fl;
1702 	LOCK_TAKE(hdw->big_lock); do {
1703 		fl = pvr2_hdw_untrip_unlocked(hdw);
1704 	} while (0); LOCK_GIVE(hdw->big_lock);
1705 	if (fl) pvr2_hdw_state_sched(hdw);
1706 	return 0;
1707 }
1708 
1709 
1710 
1711 
1712 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1713 {
1714 	return hdw->state_pipeline_req != 0;
1715 }
1716 
1717 
1718 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1719 {
1720 	int ret,st;
1721 	LOCK_TAKE(hdw->big_lock); do {
1722 		pvr2_hdw_untrip_unlocked(hdw);
1723 		if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1724 			hdw->state_pipeline_req = enable_flag != 0;
1725 			pvr2_trace(PVR2_TRACE_START_STOP,
1726 				   "/*--TRACE_STREAM--*/ %s",
1727 				   enable_flag ? "enable" : "disable");
1728 		}
1729 		pvr2_hdw_state_sched(hdw);
1730 	} while (0); LOCK_GIVE(hdw->big_lock);
1731 	if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1732 	if (enable_flag) {
1733 		while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1734 			if (st != PVR2_STATE_READY) return -EIO;
1735 			if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1736 		}
1737 	}
1738 	return 0;
1739 }
1740 
1741 
1742 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1743 {
1744 	int fl;
1745 	LOCK_TAKE(hdw->big_lock);
1746 	if ((fl = (hdw->desired_stream_type != config)) != 0) {
1747 		hdw->desired_stream_type = config;
1748 		hdw->state_pipeline_config = 0;
1749 		trace_stbit("state_pipeline_config",
1750 			    hdw->state_pipeline_config);
1751 		pvr2_hdw_state_sched(hdw);
1752 	}
1753 	LOCK_GIVE(hdw->big_lock);
1754 	if (fl) return 0;
1755 	return pvr2_hdw_wait(hdw,0);
1756 }
1757 
1758 
1759 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1760 {
1761 	int unit_number = hdw->unit_number;
1762 	int tp = -1;
1763 	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1764 		tp = tuner[unit_number];
1765 	}
1766 	if (tp < 0) return -EINVAL;
1767 	hdw->tuner_type = tp;
1768 	hdw->tuner_updated = !0;
1769 	return 0;
1770 }
1771 
1772 
1773 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1774 {
1775 	int unit_number = hdw->unit_number;
1776 	int tp = 0;
1777 	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1778 		tp = video_std[unit_number];
1779 		if (tp) return tp;
1780 	}
1781 	return 0;
1782 }
1783 
1784 
1785 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1786 {
1787 	int unit_number = hdw->unit_number;
1788 	int tp = 0;
1789 	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1790 		tp = tolerance[unit_number];
1791 	}
1792 	return tp;
1793 }
1794 
1795 
1796 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1797 {
1798 	/* Try a harmless request to fetch the eeprom's address over
1799 	   endpoint 1.  See what happens.  Only the full FX2 image can
1800 	   respond to this.  If this probe fails then likely the FX2
1801 	   firmware needs be loaded. */
1802 	int result;
1803 	LOCK_TAKE(hdw->ctl_lock); do {
1804 		hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1805 		result = pvr2_send_request_ex(hdw,HZ*1,!0,
1806 					   hdw->cmd_buffer,1,
1807 					   hdw->cmd_buffer,1);
1808 		if (result < 0) break;
1809 	} while(0); LOCK_GIVE(hdw->ctl_lock);
1810 	if (result) {
1811 		pvr2_trace(PVR2_TRACE_INIT,
1812 			   "Probe of device endpoint 1 result status %d",
1813 			   result);
1814 	} else {
1815 		pvr2_trace(PVR2_TRACE_INIT,
1816 			   "Probe of device endpoint 1 succeeded");
1817 	}
1818 	return result == 0;
1819 }
1820 
1821 struct pvr2_std_hack {
1822 	v4l2_std_id pat;  /* Pattern to match */
1823 	v4l2_std_id msk;  /* Which bits we care about */
1824 	v4l2_std_id std;  /* What additional standards or default to set */
1825 };
1826 
1827 /* This data structure labels specific combinations of standards from
1828    tveeprom that we'll try to recognize.  If we recognize one, then assume
1829    a specified default standard to use.  This is here because tveeprom only
1830    tells us about available standards not the intended default standard (if
1831    any) for the device in question.  We guess the default based on what has
1832    been reported as available.  Note that this is only for guessing a
1833    default - which can always be overridden explicitly - and if the user
1834    has otherwise named a default then that default will always be used in
1835    place of this table. */
1836 static const struct pvr2_std_hack std_eeprom_maps[] = {
1837 	{	/* PAL(B/G) */
1838 		.pat = V4L2_STD_B|V4L2_STD_GH,
1839 		.std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1840 	},
1841 	{	/* NTSC(M) */
1842 		.pat = V4L2_STD_MN,
1843 		.std = V4L2_STD_NTSC_M,
1844 	},
1845 	{	/* PAL(I) */
1846 		.pat = V4L2_STD_PAL_I,
1847 		.std = V4L2_STD_PAL_I,
1848 	},
1849 	{	/* SECAM(L/L') */
1850 		.pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1851 		.std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1852 	},
1853 	{	/* PAL(D/D1/K) */
1854 		.pat = V4L2_STD_DK,
1855 		.std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1856 	},
1857 };
1858 
1859 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1860 {
1861 	char buf[40];
1862 	unsigned int bcnt;
1863 	v4l2_std_id std1,std2,std3;
1864 
1865 	std1 = get_default_standard(hdw);
1866 	std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1867 
1868 	bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1869 	pvr2_trace(PVR2_TRACE_STD,
1870 		   "Supported video standard(s) reported available in hardware: %.*s",
1871 		   bcnt,buf);
1872 
1873 	hdw->std_mask_avail = hdw->std_mask_eeprom;
1874 
1875 	std2 = (std1|std3) & ~hdw->std_mask_avail;
1876 	if (std2) {
1877 		bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1878 		pvr2_trace(PVR2_TRACE_STD,
1879 			   "Expanding supported video standards to include: %.*s",
1880 			   bcnt,buf);
1881 		hdw->std_mask_avail |= std2;
1882 	}
1883 
1884 	hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1885 
1886 	if (std1) {
1887 		bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1888 		pvr2_trace(PVR2_TRACE_STD,
1889 			   "Initial video standard forced to %.*s",
1890 			   bcnt,buf);
1891 		hdw->std_mask_cur = std1;
1892 		hdw->std_dirty = !0;
1893 		return;
1894 	}
1895 	if (std3) {
1896 		bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1897 		pvr2_trace(PVR2_TRACE_STD,
1898 			   "Initial video standard (determined by device type): %.*s",
1899 			   bcnt, buf);
1900 		hdw->std_mask_cur = std3;
1901 		hdw->std_dirty = !0;
1902 		return;
1903 	}
1904 
1905 	{
1906 		unsigned int idx;
1907 		for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1908 			if (std_eeprom_maps[idx].msk ?
1909 			    ((std_eeprom_maps[idx].pat ^
1910 			     hdw->std_mask_eeprom) &
1911 			     std_eeprom_maps[idx].msk) :
1912 			    (std_eeprom_maps[idx].pat !=
1913 			     hdw->std_mask_eeprom)) continue;
1914 			bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1915 						  std_eeprom_maps[idx].std);
1916 			pvr2_trace(PVR2_TRACE_STD,
1917 				   "Initial video standard guessed as %.*s",
1918 				   bcnt,buf);
1919 			hdw->std_mask_cur = std_eeprom_maps[idx].std;
1920 			hdw->std_dirty = !0;
1921 			return;
1922 		}
1923 	}
1924 
1925 }
1926 
1927 
1928 static unsigned int pvr2_copy_i2c_addr_list(
1929 	unsigned short *dst, const unsigned char *src,
1930 	unsigned int dst_max)
1931 {
1932 	unsigned int cnt = 0;
1933 	if (!src) return 0;
1934 	while (src[cnt] && (cnt + 1) < dst_max) {
1935 		dst[cnt] = src[cnt];
1936 		cnt++;
1937 	}
1938 	dst[cnt] = I2C_CLIENT_END;
1939 	return cnt;
1940 }
1941 
1942 
1943 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1944 {
1945 	/*
1946 	  Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1947 	  for cx25840 causes that module to correctly set up its video
1948 	  scaling.  This is really a problem in the cx25840 module itself,
1949 	  but we work around it here.  The problem has not been seen in
1950 	  ivtv because there VBI is supported and set up.  We don't do VBI
1951 	  here (at least not yet) and thus we never attempted to even set
1952 	  it up.
1953 	*/
1954 	struct v4l2_format fmt;
1955 	if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1956 		/* We're not using a cx25840 so don't enable the hack */
1957 		return;
1958 	}
1959 
1960 	pvr2_trace(PVR2_TRACE_INIT,
1961 		   "Module ID %u: Executing cx25840 VBI hack",
1962 		   hdw->decoder_client_id);
1963 	memset(&fmt, 0, sizeof(fmt));
1964 	fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1965 	fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1966 	fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1967 	v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1968 			     vbi, s_sliced_fmt, &fmt.fmt.sliced);
1969 }
1970 
1971 
1972 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1973 				const struct pvr2_device_client_desc *cd)
1974 {
1975 	const char *fname;
1976 	unsigned char mid;
1977 	struct v4l2_subdev *sd;
1978 	unsigned int i2ccnt;
1979 	const unsigned char *p;
1980 	/* Arbitrary count - max # i2c addresses we will probe */
1981 	unsigned short i2caddr[25];
1982 
1983 	mid = cd->module_id;
1984 	fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1985 	if (!fname) {
1986 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1987 			   "Module ID %u for device %s has no name?  The driver might have a configuration problem.",
1988 			   mid,
1989 			   hdw->hdw_desc->description);
1990 		return -EINVAL;
1991 	}
1992 	pvr2_trace(PVR2_TRACE_INIT,
1993 		   "Module ID %u (%s) for device %s being loaded...",
1994 		   mid, fname,
1995 		   hdw->hdw_desc->description);
1996 
1997 	i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1998 					 ARRAY_SIZE(i2caddr));
1999 	if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2000 			 module_i2c_addresses[mid] : NULL) != NULL)) {
2001 		/* Second chance: Try default i2c address list */
2002 		i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2003 						 ARRAY_SIZE(i2caddr));
2004 		if (i2ccnt) {
2005 			pvr2_trace(PVR2_TRACE_INIT,
2006 				   "Module ID %u: Using default i2c address list",
2007 				   mid);
2008 		}
2009 	}
2010 
2011 	if (!i2ccnt) {
2012 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2013 			   "Module ID %u (%s) for device %s: No i2c addresses.	The driver might have a configuration problem.",
2014 			   mid, fname, hdw->hdw_desc->description);
2015 		return -EINVAL;
2016 	}
2017 
2018 	if (i2ccnt == 1) {
2019 		pvr2_trace(PVR2_TRACE_INIT,
2020 			   "Module ID %u: Setting up with specified i2c address 0x%x",
2021 			   mid, i2caddr[0]);
2022 		sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2023 					 fname, i2caddr[0], NULL);
2024 	} else {
2025 		pvr2_trace(PVR2_TRACE_INIT,
2026 			   "Module ID %u: Setting up with address probe list",
2027 			   mid);
2028 		sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2029 					 fname, 0, i2caddr);
2030 	}
2031 
2032 	if (!sd) {
2033 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2034 			   "Module ID %u (%s) for device %s failed to load.  Possible missing sub-device kernel module or initialization failure within module.",
2035 			   mid, fname, hdw->hdw_desc->description);
2036 		return -EIO;
2037 	}
2038 
2039 	/* Tag this sub-device instance with the module ID we know about.
2040 	   In other places we'll use that tag to determine if the instance
2041 	   requires special handling. */
2042 	sd->grp_id = mid;
2043 
2044 	pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2045 
2046 
2047 	/* client-specific setup... */
2048 	switch (mid) {
2049 	case PVR2_CLIENT_ID_CX25840:
2050 	case PVR2_CLIENT_ID_SAA7115:
2051 		hdw->decoder_client_id = mid;
2052 		break;
2053 	default: break;
2054 	}
2055 
2056 	return 0;
2057 }
2058 
2059 
2060 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2061 {
2062 	unsigned int idx;
2063 	const struct pvr2_string_table *cm;
2064 	const struct pvr2_device_client_table *ct;
2065 	int okFl = !0;
2066 
2067 	cm = &hdw->hdw_desc->client_modules;
2068 	for (idx = 0; idx < cm->cnt; idx++) {
2069 		request_module(cm->lst[idx]);
2070 	}
2071 
2072 	ct = &hdw->hdw_desc->client_table;
2073 	for (idx = 0; idx < ct->cnt; idx++) {
2074 		if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2075 	}
2076 	if (!okFl) {
2077 		hdw->flag_modulefail = !0;
2078 		pvr2_hdw_render_useless(hdw);
2079 	}
2080 }
2081 
2082 
2083 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2084 {
2085 	int ret;
2086 	unsigned int idx;
2087 	struct pvr2_ctrl *cptr;
2088 	int reloadFl = 0;
2089 	if (hdw->hdw_desc->fx2_firmware.cnt) {
2090 		if (!reloadFl) {
2091 			reloadFl =
2092 				(hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2093 				 == 0);
2094 			if (reloadFl) {
2095 				pvr2_trace(PVR2_TRACE_INIT,
2096 					   "USB endpoint config looks strange; possibly firmware needs to be loaded");
2097 			}
2098 		}
2099 		if (!reloadFl) {
2100 			reloadFl = !pvr2_hdw_check_firmware(hdw);
2101 			if (reloadFl) {
2102 				pvr2_trace(PVR2_TRACE_INIT,
2103 					   "Check for FX2 firmware failed; possibly firmware needs to be loaded");
2104 			}
2105 		}
2106 		if (reloadFl) {
2107 			if (pvr2_upload_firmware1(hdw) != 0) {
2108 				pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2109 					   "Failure uploading firmware1");
2110 			}
2111 			return;
2112 		}
2113 	}
2114 	hdw->fw1_state = FW1_STATE_OK;
2115 
2116 	if (!pvr2_hdw_dev_ok(hdw)) return;
2117 
2118 	hdw->force_dirty = !0;
2119 
2120 	if (!hdw->hdw_desc->flag_no_powerup) {
2121 		pvr2_hdw_cmd_powerup(hdw);
2122 		if (!pvr2_hdw_dev_ok(hdw)) return;
2123 	}
2124 
2125 	/* Take the IR chip out of reset, if appropriate */
2126 	if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2127 		pvr2_issue_simple_cmd(hdw,
2128 				      FX2CMD_HCW_ZILOG_RESET |
2129 				      (1 << 8) |
2130 				      ((0) << 16));
2131 	}
2132 
2133 	/* This step MUST happen after the earlier powerup step */
2134 	pvr2_i2c_core_init(hdw);
2135 	if (!pvr2_hdw_dev_ok(hdw)) return;
2136 
2137 	/* Reset demod only on Hauppauge 160xxx platform */
2138 	if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
2139 	    (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
2140 	     le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
2141 		pr_info("%s(): resetting 160xxx demod\n", __func__);
2142 		/* TODO: not sure this is proper place to reset once only */
2143 		pvr2_issue_simple_cmd(hdw,
2144 				      FX2CMD_HCW_DEMOD_RESET_PIN |
2145 				      (1 << 8) |
2146 				      ((0) << 16));
2147 		usleep_range(10000, 10500);
2148 		pvr2_issue_simple_cmd(hdw,
2149 				      FX2CMD_HCW_DEMOD_RESET_PIN |
2150 				      (1 << 8) |
2151 				      ((1) << 16));
2152 		usleep_range(10000, 10500);
2153 	}
2154 
2155 	pvr2_hdw_load_modules(hdw);
2156 	if (!pvr2_hdw_dev_ok(hdw)) return;
2157 
2158 	v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2159 
2160 	for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2161 		cptr = hdw->controls + idx;
2162 		if (cptr->info->skip_init) continue;
2163 		if (!cptr->info->set_value) continue;
2164 		cptr->info->set_value(cptr,~0,cptr->info->default_value);
2165 	}
2166 
2167 	pvr2_hdw_cx25840_vbi_hack(hdw);
2168 
2169 	/* Set up special default values for the television and radio
2170 	   frequencies here.  It's not really important what these defaults
2171 	   are, but I set them to something usable in the Chicago area just
2172 	   to make driver testing a little easier. */
2173 
2174 	hdw->freqValTelevision = default_tv_freq;
2175 	hdw->freqValRadio = default_radio_freq;
2176 
2177 	// Do not use pvr2_reset_ctl_endpoints() here.  It is not
2178 	// thread-safe against the normal pvr2_send_request() mechanism.
2179 	// (We should make it thread safe).
2180 
2181 	if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2182 		ret = pvr2_hdw_get_eeprom_addr(hdw);
2183 		if (!pvr2_hdw_dev_ok(hdw)) return;
2184 		if (ret < 0) {
2185 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2186 				   "Unable to determine location of eeprom, skipping");
2187 		} else {
2188 			hdw->eeprom_addr = ret;
2189 			pvr2_eeprom_analyze(hdw);
2190 			if (!pvr2_hdw_dev_ok(hdw)) return;
2191 		}
2192 	} else {
2193 		hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2194 		hdw->tuner_updated = !0;
2195 		hdw->std_mask_eeprom = V4L2_STD_ALL;
2196 	}
2197 
2198 	if (hdw->serial_number) {
2199 		idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2200 				"sn-%lu", hdw->serial_number);
2201 	} else if (hdw->unit_number >= 0) {
2202 		idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2203 				"unit-%c",
2204 				hdw->unit_number + 'a');
2205 	} else {
2206 		idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2207 				"unit-??");
2208 	}
2209 	hdw->identifier[idx] = 0;
2210 
2211 	pvr2_hdw_setup_std(hdw);
2212 
2213 	if (!get_default_tuner_type(hdw)) {
2214 		pvr2_trace(PVR2_TRACE_INIT,
2215 			   "pvr2_hdw_setup: Tuner type overridden to %d",
2216 			   hdw->tuner_type);
2217 	}
2218 
2219 
2220 	if (!pvr2_hdw_dev_ok(hdw)) return;
2221 
2222 	if (hdw->hdw_desc->signal_routing_scheme ==
2223 	    PVR2_ROUTING_SCHEME_GOTVIEW) {
2224 		/* Ensure that GPIO 11 is set to output for GOTVIEW
2225 		   hardware. */
2226 		pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2227 	}
2228 
2229 	pvr2_hdw_commit_setup(hdw);
2230 
2231 	hdw->vid_stream = pvr2_stream_create();
2232 	if (!pvr2_hdw_dev_ok(hdw)) return;
2233 	pvr2_trace(PVR2_TRACE_INIT,
2234 		   "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2235 	if (hdw->vid_stream) {
2236 		idx = get_default_error_tolerance(hdw);
2237 		if (idx) {
2238 			pvr2_trace(PVR2_TRACE_INIT,
2239 				   "pvr2_hdw_setup: video stream %p setting tolerance %u",
2240 				   hdw->vid_stream,idx);
2241 		}
2242 		pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2243 				  PVR2_VID_ENDPOINT,idx);
2244 	}
2245 
2246 	if (!pvr2_hdw_dev_ok(hdw)) return;
2247 
2248 	hdw->flag_init_ok = !0;
2249 
2250 	pvr2_hdw_state_sched(hdw);
2251 }
2252 
2253 
2254 /* Set up the structure and attempt to put the device into a usable state.
2255    This can be a time-consuming operation, which is why it is not done
2256    internally as part of the create() step. */
2257 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2258 {
2259 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2260 	do {
2261 		pvr2_hdw_setup_low(hdw);
2262 		pvr2_trace(PVR2_TRACE_INIT,
2263 			   "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2264 			   hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2265 		if (pvr2_hdw_dev_ok(hdw)) {
2266 			if (hdw->flag_init_ok) {
2267 				pvr2_trace(
2268 					PVR2_TRACE_INFO,
2269 					"Device initialization completed successfully.");
2270 				break;
2271 			}
2272 			if (hdw->fw1_state == FW1_STATE_RELOAD) {
2273 				pvr2_trace(
2274 					PVR2_TRACE_INFO,
2275 					"Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
2276 				break;
2277 			}
2278 			pvr2_trace(
2279 				PVR2_TRACE_ERROR_LEGS,
2280 				"Device initialization was not successful.");
2281 			if (hdw->fw1_state == FW1_STATE_MISSING) {
2282 				pvr2_trace(
2283 					PVR2_TRACE_ERROR_LEGS,
2284 					"Giving up since device microcontroller firmware appears to be missing.");
2285 				break;
2286 			}
2287 		}
2288 		if (hdw->flag_modulefail) {
2289 			pvr2_trace(
2290 				PVR2_TRACE_ERROR_LEGS,
2291 				"***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
2292 			pvr2_trace(
2293 				PVR2_TRACE_ERROR_LEGS,
2294 				"You need to resolve the failing condition before this driver can function.  There should be some earlier messages giving more information about the problem.");
2295 			break;
2296 		}
2297 		if (procreload) {
2298 			pvr2_trace(
2299 				PVR2_TRACE_ERROR_LEGS,
2300 				"Attempting pvrusb2 recovery by reloading primary firmware.");
2301 			pvr2_trace(
2302 				PVR2_TRACE_ERROR_LEGS,
2303 				"If this works, device should disconnect and reconnect in a sane state.");
2304 			hdw->fw1_state = FW1_STATE_UNKNOWN;
2305 			pvr2_upload_firmware1(hdw);
2306 		} else {
2307 			pvr2_trace(
2308 				PVR2_TRACE_ERROR_LEGS,
2309 				"***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
2310 			pvr2_trace(
2311 				PVR2_TRACE_ERROR_LEGS,
2312 				"You might need to power cycle the pvrusb2 device in order to recover.");
2313 		}
2314 	} while (0);
2315 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2316 }
2317 
2318 
2319 /* Perform second stage initialization.  Set callback pointer first so that
2320    we can avoid a possible initialization race (if the kernel thread runs
2321    before the callback has been set). */
2322 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2323 			void (*callback_func)(void *),
2324 			void *callback_data)
2325 {
2326 	LOCK_TAKE(hdw->big_lock); do {
2327 		if (hdw->flag_disconnected) {
2328 			/* Handle a race here: If we're already
2329 			   disconnected by this point, then give up.  If we
2330 			   get past this then we'll remain connected for
2331 			   the duration of initialization since the entire
2332 			   initialization sequence is now protected by the
2333 			   big_lock. */
2334 			break;
2335 		}
2336 		hdw->state_data = callback_data;
2337 		hdw->state_func = callback_func;
2338 		pvr2_hdw_setup(hdw);
2339 	} while (0); LOCK_GIVE(hdw->big_lock);
2340 	return hdw->flag_init_ok;
2341 }
2342 
2343 
2344 /* Create, set up, and return a structure for interacting with the
2345    underlying hardware.  */
2346 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2347 				 const struct usb_device_id *devid)
2348 {
2349 	unsigned int idx,cnt1,cnt2,m;
2350 	struct pvr2_hdw *hdw = NULL;
2351 	int valid_std_mask;
2352 	struct pvr2_ctrl *cptr;
2353 	struct usb_device *usb_dev;
2354 	const struct pvr2_device_desc *hdw_desc;
2355 	__u8 ifnum;
2356 	struct v4l2_queryctrl qctrl;
2357 	struct pvr2_ctl_info *ciptr;
2358 
2359 	usb_dev = interface_to_usbdev(intf);
2360 
2361 	hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2362 
2363 	if (hdw_desc == NULL) {
2364 		pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
2365 		pvr2_trace(PVR2_TRACE_INIT,
2366 			   "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver");
2367 		goto fail;
2368 	}
2369 
2370 	hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2371 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2372 		   hdw,hdw_desc->description);
2373 	pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2374 		hdw_desc->description);
2375 	if (hdw_desc->flag_is_experimental) {
2376 		pvr2_trace(PVR2_TRACE_INFO, "**********");
2377 		pvr2_trace(PVR2_TRACE_INFO,
2378 			   "***WARNING*** Support for this device (%s) is experimental.",
2379 							      hdw_desc->description);
2380 		pvr2_trace(PVR2_TRACE_INFO,
2381 			   "Important functionality might not be entirely working.");
2382 		pvr2_trace(PVR2_TRACE_INFO,
2383 			   "Please consider contacting the driver author to help with further stabilization of the driver.");
2384 		pvr2_trace(PVR2_TRACE_INFO, "**********");
2385 	}
2386 	if (!hdw) goto fail;
2387 
2388 	timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
2389 
2390 	timer_setup(&hdw->decoder_stabilization_timer,
2391 		    pvr2_hdw_decoder_stabilization_timeout, 0);
2392 
2393 	timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2394 		    0);
2395 
2396 	timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
2397 
2398 	hdw->master_state = PVR2_STATE_DEAD;
2399 
2400 	init_waitqueue_head(&hdw->state_wait_data);
2401 
2402 	hdw->tuner_signal_stale = !0;
2403 	cx2341x_fill_defaults(&hdw->enc_ctl_state);
2404 
2405 	/* Calculate which inputs are OK */
2406 	m = 0;
2407 	if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2408 	if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2409 		m |= 1 << PVR2_CVAL_INPUT_DTV;
2410 	}
2411 	if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2412 	if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2413 	if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2414 	hdw->input_avail_mask = m;
2415 	hdw->input_allowed_mask = hdw->input_avail_mask;
2416 
2417 	/* If not a hybrid device, pathway_state never changes.  So
2418 	   initialize it here to what it should forever be. */
2419 	if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2420 		hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2421 	} else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2422 		hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2423 	}
2424 
2425 	hdw->control_cnt = CTRLDEF_COUNT;
2426 	hdw->control_cnt += MPEGDEF_COUNT;
2427 	hdw->controls = kcalloc(hdw->control_cnt, sizeof(struct pvr2_ctrl),
2428 				GFP_KERNEL);
2429 	if (!hdw->controls) goto fail;
2430 	hdw->hdw_desc = hdw_desc;
2431 	hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2432 	for (idx = 0; idx < hdw->control_cnt; idx++) {
2433 		cptr = hdw->controls + idx;
2434 		cptr->hdw = hdw;
2435 	}
2436 	for (idx = 0; idx < 32; idx++) {
2437 		hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2438 	}
2439 	for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2440 		cptr = hdw->controls + idx;
2441 		cptr->info = control_defs+idx;
2442 	}
2443 
2444 	/* Ensure that default input choice is a valid one. */
2445 	m = hdw->input_avail_mask;
2446 	if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2447 		if (!((1UL << idx) & m)) continue;
2448 		hdw->input_val = idx;
2449 		break;
2450 	}
2451 
2452 	/* Define and configure additional controls from cx2341x module. */
2453 	hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2454 				      sizeof(*(hdw->mpeg_ctrl_info)),
2455 				      GFP_KERNEL);
2456 	if (!hdw->mpeg_ctrl_info) goto fail;
2457 	for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2458 		cptr = hdw->controls + idx + CTRLDEF_COUNT;
2459 		ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2460 		ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2461 		ciptr->name = mpeg_ids[idx].strid;
2462 		ciptr->v4l_id = mpeg_ids[idx].id;
2463 		ciptr->skip_init = !0;
2464 		ciptr->get_value = ctrl_cx2341x_get;
2465 		ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2466 		ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2467 		if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2468 		qctrl.id = ciptr->v4l_id;
2469 		cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2470 		if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2471 			ciptr->set_value = ctrl_cx2341x_set;
2472 		}
2473 		strscpy(hdw->mpeg_ctrl_info[idx].desc, qctrl.name,
2474 			sizeof(hdw->mpeg_ctrl_info[idx].desc));
2475 		ciptr->default_value = qctrl.default_value;
2476 		switch (qctrl.type) {
2477 		default:
2478 		case V4L2_CTRL_TYPE_INTEGER:
2479 			ciptr->type = pvr2_ctl_int;
2480 			ciptr->def.type_int.min_value = qctrl.minimum;
2481 			ciptr->def.type_int.max_value = qctrl.maximum;
2482 			break;
2483 		case V4L2_CTRL_TYPE_BOOLEAN:
2484 			ciptr->type = pvr2_ctl_bool;
2485 			break;
2486 		case V4L2_CTRL_TYPE_MENU:
2487 			ciptr->type = pvr2_ctl_enum;
2488 			ciptr->def.type_enum.value_names =
2489 				cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2490 								ciptr->v4l_id);
2491 			for (cnt1 = 0;
2492 			     ciptr->def.type_enum.value_names[cnt1] != NULL;
2493 			     cnt1++) { }
2494 			ciptr->def.type_enum.count = cnt1;
2495 			break;
2496 		}
2497 		cptr->info = ciptr;
2498 	}
2499 
2500 	// Initialize control data regarding video standard masks
2501 	valid_std_mask = pvr2_std_get_usable();
2502 	for (idx = 0; idx < 32; idx++) {
2503 		if (!(valid_std_mask & (1UL << idx))) continue;
2504 		cnt1 = pvr2_std_id_to_str(
2505 			hdw->std_mask_names[idx],
2506 			sizeof(hdw->std_mask_names[idx])-1,
2507 			1UL << idx);
2508 		hdw->std_mask_names[idx][cnt1] = 0;
2509 	}
2510 	cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2511 	if (cptr) {
2512 		memcpy(&hdw->std_info_avail,cptr->info,
2513 		       sizeof(hdw->std_info_avail));
2514 		cptr->info = &hdw->std_info_avail;
2515 		hdw->std_info_avail.def.type_bitmask.bit_names =
2516 			hdw->std_mask_ptrs;
2517 		hdw->std_info_avail.def.type_bitmask.valid_bits =
2518 			valid_std_mask;
2519 	}
2520 	cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2521 	if (cptr) {
2522 		memcpy(&hdw->std_info_cur,cptr->info,
2523 		       sizeof(hdw->std_info_cur));
2524 		cptr->info = &hdw->std_info_cur;
2525 		hdw->std_info_cur.def.type_bitmask.bit_names =
2526 			hdw->std_mask_ptrs;
2527 		hdw->std_info_cur.def.type_bitmask.valid_bits =
2528 			valid_std_mask;
2529 	}
2530 	cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2531 	if (cptr) {
2532 		memcpy(&hdw->std_info_detect,cptr->info,
2533 		       sizeof(hdw->std_info_detect));
2534 		cptr->info = &hdw->std_info_detect;
2535 		hdw->std_info_detect.def.type_bitmask.bit_names =
2536 			hdw->std_mask_ptrs;
2537 		hdw->std_info_detect.def.type_bitmask.valid_bits =
2538 			valid_std_mask;
2539 	}
2540 
2541 	hdw->cropcap_stale = !0;
2542 	hdw->eeprom_addr = -1;
2543 	hdw->unit_number = -1;
2544 	hdw->v4l_minor_number_video = -1;
2545 	hdw->v4l_minor_number_vbi = -1;
2546 	hdw->v4l_minor_number_radio = -1;
2547 	hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2548 	if (!hdw->ctl_write_buffer) goto fail;
2549 	hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2550 	if (!hdw->ctl_read_buffer) goto fail;
2551 	hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2552 	if (!hdw->ctl_write_urb) goto fail;
2553 	hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2554 	if (!hdw->ctl_read_urb) goto fail;
2555 
2556 	if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2557 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2558 			   "Error registering with v4l core, giving up");
2559 		goto fail;
2560 	}
2561 	mutex_lock(&pvr2_unit_mtx);
2562 	do {
2563 		for (idx = 0; idx < PVR_NUM; idx++) {
2564 			if (unit_pointers[idx]) continue;
2565 			hdw->unit_number = idx;
2566 			unit_pointers[idx] = hdw;
2567 			break;
2568 		}
2569 	} while (0);
2570 	mutex_unlock(&pvr2_unit_mtx);
2571 
2572 	cnt1 = 0;
2573 	cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2574 	cnt1 += cnt2;
2575 	if (hdw->unit_number >= 0) {
2576 		cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2577 				 ('a' + hdw->unit_number));
2578 		cnt1 += cnt2;
2579 	}
2580 	if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2581 	hdw->name[cnt1] = 0;
2582 
2583 	INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2584 
2585 	pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2586 		   hdw->unit_number,hdw->name);
2587 
2588 	hdw->tuner_type = -1;
2589 	hdw->flag_ok = !0;
2590 
2591 	hdw->usb_intf = intf;
2592 	hdw->usb_dev = usb_dev;
2593 
2594 	usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2595 
2596 	ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2597 	usb_set_interface(hdw->usb_dev,ifnum,0);
2598 
2599 	mutex_init(&hdw->ctl_lock_mutex);
2600 	mutex_init(&hdw->big_lock_mutex);
2601 
2602 	return hdw;
2603  fail:
2604 	if (hdw) {
2605 		del_timer_sync(&hdw->quiescent_timer);
2606 		del_timer_sync(&hdw->decoder_stabilization_timer);
2607 		del_timer_sync(&hdw->encoder_run_timer);
2608 		del_timer_sync(&hdw->encoder_wait_timer);
2609 		flush_work(&hdw->workpoll);
2610 		usb_free_urb(hdw->ctl_read_urb);
2611 		usb_free_urb(hdw->ctl_write_urb);
2612 		kfree(hdw->ctl_read_buffer);
2613 		kfree(hdw->ctl_write_buffer);
2614 		kfree(hdw->controls);
2615 		kfree(hdw->mpeg_ctrl_info);
2616 		kfree(hdw);
2617 	}
2618 	return NULL;
2619 }
2620 
2621 
2622 /* Remove _all_ associations between this driver and the underlying USB
2623    layer. */
2624 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2625 {
2626 	if (hdw->flag_disconnected) return;
2627 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2628 	if (hdw->ctl_read_urb) {
2629 		usb_kill_urb(hdw->ctl_read_urb);
2630 		usb_free_urb(hdw->ctl_read_urb);
2631 		hdw->ctl_read_urb = NULL;
2632 	}
2633 	if (hdw->ctl_write_urb) {
2634 		usb_kill_urb(hdw->ctl_write_urb);
2635 		usb_free_urb(hdw->ctl_write_urb);
2636 		hdw->ctl_write_urb = NULL;
2637 	}
2638 	if (hdw->ctl_read_buffer) {
2639 		kfree(hdw->ctl_read_buffer);
2640 		hdw->ctl_read_buffer = NULL;
2641 	}
2642 	if (hdw->ctl_write_buffer) {
2643 		kfree(hdw->ctl_write_buffer);
2644 		hdw->ctl_write_buffer = NULL;
2645 	}
2646 	hdw->flag_disconnected = !0;
2647 	/* If we don't do this, then there will be a dangling struct device
2648 	   reference to our disappearing device persisting inside the V4L
2649 	   core... */
2650 	v4l2_device_disconnect(&hdw->v4l2_dev);
2651 	hdw->usb_dev = NULL;
2652 	hdw->usb_intf = NULL;
2653 	pvr2_hdw_render_useless(hdw);
2654 }
2655 
2656 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2657 {
2658 	vdev->v4l2_dev = &hdw->v4l2_dev;
2659 }
2660 
2661 /* Destroy hardware interaction structure */
2662 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2663 {
2664 	if (!hdw) return;
2665 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2666 	flush_work(&hdw->workpoll);
2667 	del_timer_sync(&hdw->quiescent_timer);
2668 	del_timer_sync(&hdw->decoder_stabilization_timer);
2669 	del_timer_sync(&hdw->encoder_run_timer);
2670 	del_timer_sync(&hdw->encoder_wait_timer);
2671 	if (hdw->fw_buffer) {
2672 		kfree(hdw->fw_buffer);
2673 		hdw->fw_buffer = NULL;
2674 	}
2675 	if (hdw->vid_stream) {
2676 		pvr2_stream_destroy(hdw->vid_stream);
2677 		hdw->vid_stream = NULL;
2678 	}
2679 	pvr2_i2c_core_done(hdw);
2680 	v4l2_device_unregister(&hdw->v4l2_dev);
2681 	pvr2_hdw_remove_usb_stuff(hdw);
2682 	mutex_lock(&pvr2_unit_mtx);
2683 	do {
2684 		if ((hdw->unit_number >= 0) &&
2685 		    (hdw->unit_number < PVR_NUM) &&
2686 		    (unit_pointers[hdw->unit_number] == hdw)) {
2687 			unit_pointers[hdw->unit_number] = NULL;
2688 		}
2689 	} while (0);
2690 	mutex_unlock(&pvr2_unit_mtx);
2691 	kfree(hdw->controls);
2692 	kfree(hdw->mpeg_ctrl_info);
2693 	kfree(hdw);
2694 }
2695 
2696 
2697 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2698 {
2699 	return (hdw && hdw->flag_ok);
2700 }
2701 
2702 
2703 /* Called when hardware has been unplugged */
2704 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2705 {
2706 	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2707 	LOCK_TAKE(hdw->big_lock);
2708 	LOCK_TAKE(hdw->ctl_lock);
2709 	pvr2_hdw_remove_usb_stuff(hdw);
2710 	LOCK_GIVE(hdw->ctl_lock);
2711 	LOCK_GIVE(hdw->big_lock);
2712 }
2713 
2714 
2715 /* Get the number of defined controls */
2716 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2717 {
2718 	return hdw->control_cnt;
2719 }
2720 
2721 
2722 /* Retrieve a control handle given its index (0..count-1) */
2723 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2724 					     unsigned int idx)
2725 {
2726 	if (idx >= hdw->control_cnt) return NULL;
2727 	return hdw->controls + idx;
2728 }
2729 
2730 
2731 /* Retrieve a control handle given its index (0..count-1) */
2732 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2733 					  unsigned int ctl_id)
2734 {
2735 	struct pvr2_ctrl *cptr;
2736 	unsigned int idx;
2737 	int i;
2738 
2739 	/* This could be made a lot more efficient, but for now... */
2740 	for (idx = 0; idx < hdw->control_cnt; idx++) {
2741 		cptr = hdw->controls + idx;
2742 		i = cptr->info->internal_id;
2743 		if (i && (i == ctl_id)) return cptr;
2744 	}
2745 	return NULL;
2746 }
2747 
2748 
2749 /* Given a V4L ID, retrieve the control structure associated with it. */
2750 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2751 {
2752 	struct pvr2_ctrl *cptr;
2753 	unsigned int idx;
2754 	int i;
2755 
2756 	/* This could be made a lot more efficient, but for now... */
2757 	for (idx = 0; idx < hdw->control_cnt; idx++) {
2758 		cptr = hdw->controls + idx;
2759 		i = cptr->info->v4l_id;
2760 		if (i && (i == ctl_id)) return cptr;
2761 	}
2762 	return NULL;
2763 }
2764 
2765 
2766 /* Given a V4L ID for its immediate predecessor, retrieve the control
2767    structure associated with it. */
2768 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2769 					    unsigned int ctl_id)
2770 {
2771 	struct pvr2_ctrl *cptr,*cp2;
2772 	unsigned int idx;
2773 	int i;
2774 
2775 	/* This could be made a lot more efficient, but for now... */
2776 	cp2 = NULL;
2777 	for (idx = 0; idx < hdw->control_cnt; idx++) {
2778 		cptr = hdw->controls + idx;
2779 		i = cptr->info->v4l_id;
2780 		if (!i) continue;
2781 		if (i <= ctl_id) continue;
2782 		if (cp2 && (cp2->info->v4l_id < i)) continue;
2783 		cp2 = cptr;
2784 	}
2785 	return cp2;
2786 	return NULL;
2787 }
2788 
2789 
2790 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2791 {
2792 	switch (tp) {
2793 	case pvr2_ctl_int: return "integer";
2794 	case pvr2_ctl_enum: return "enum";
2795 	case pvr2_ctl_bool: return "boolean";
2796 	case pvr2_ctl_bitmask: return "bitmask";
2797 	}
2798 	return "";
2799 }
2800 
2801 
2802 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2803 				    const char *name, int val)
2804 {
2805 	struct v4l2_control ctrl;
2806 	struct v4l2_subdev *sd;
2807 
2808 	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2809 	memset(&ctrl, 0, sizeof(ctrl));
2810 	ctrl.id = id;
2811 	ctrl.value = val;
2812 
2813 	v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2814 		v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2815 }
2816 
2817 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2818 	if ((hdw)->lab##_dirty || (hdw)->force_dirty) {		\
2819 		pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2820 	}
2821 
2822 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2823 {
2824 	v4l2_std_id std;
2825 	std = (v4l2_std_id)hdw->std_mask_avail;
2826 	v4l2_device_call_all(&hdw->v4l2_dev, 0,
2827 			     video, querystd, &std);
2828 	return std;
2829 }
2830 
2831 /* Execute whatever commands are required to update the state of all the
2832    sub-devices so that they match our current control values. */
2833 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2834 {
2835 	struct v4l2_subdev *sd;
2836 	unsigned int id;
2837 	pvr2_subdev_update_func fp;
2838 
2839 	pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2840 
2841 	if (hdw->tuner_updated || hdw->force_dirty) {
2842 		struct tuner_setup setup;
2843 		pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2844 			   hdw->tuner_type);
2845 		if (((int)(hdw->tuner_type)) >= 0) {
2846 			memset(&setup, 0, sizeof(setup));
2847 			setup.addr = ADDR_UNSET;
2848 			setup.type = hdw->tuner_type;
2849 			setup.mode_mask = T_RADIO | T_ANALOG_TV;
2850 			v4l2_device_call_all(&hdw->v4l2_dev, 0,
2851 					     tuner, s_type_addr, &setup);
2852 		}
2853 	}
2854 
2855 	if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2856 		pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2857 		if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2858 			v4l2_device_call_all(&hdw->v4l2_dev, 0,
2859 					     tuner, s_radio);
2860 		} else {
2861 			v4l2_std_id vs;
2862 			vs = hdw->std_mask_cur;
2863 			v4l2_device_call_all(&hdw->v4l2_dev, 0,
2864 					     video, s_std, vs);
2865 			pvr2_hdw_cx25840_vbi_hack(hdw);
2866 		}
2867 		hdw->tuner_signal_stale = !0;
2868 		hdw->cropcap_stale = !0;
2869 	}
2870 
2871 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2872 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2873 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2874 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2875 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2876 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2877 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2878 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2879 	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2880 
2881 	if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2882 		struct v4l2_tuner vt;
2883 		memset(&vt, 0, sizeof(vt));
2884 		vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2885 			V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2886 		vt.audmode = hdw->audiomode_val;
2887 		v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2888 	}
2889 
2890 	if (hdw->freqDirty || hdw->force_dirty) {
2891 		unsigned long fv;
2892 		struct v4l2_frequency freq;
2893 		fv = pvr2_hdw_get_cur_freq(hdw);
2894 		pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2895 		if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2896 		memset(&freq, 0, sizeof(freq));
2897 		if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2898 			/* ((fv * 1000) / 62500) */
2899 			freq.frequency = (fv * 2) / 125;
2900 		} else {
2901 			freq.frequency = fv / 62500;
2902 		}
2903 		/* tuner-core currently doesn't seem to care about this, but
2904 		   let's set it anyway for completeness. */
2905 		if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2906 			freq.type = V4L2_TUNER_RADIO;
2907 		} else {
2908 			freq.type = V4L2_TUNER_ANALOG_TV;
2909 		}
2910 		freq.tuner = 0;
2911 		v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2912 				     s_frequency, &freq);
2913 	}
2914 
2915 	if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2916 		struct v4l2_subdev_format format = {
2917 			.which = V4L2_SUBDEV_FORMAT_ACTIVE,
2918 		};
2919 
2920 		format.format.width = hdw->res_hor_val;
2921 		format.format.height = hdw->res_ver_val;
2922 		format.format.code = MEDIA_BUS_FMT_FIXED;
2923 		pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2924 			   format.format.width, format.format.height);
2925 		v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2926 				     NULL, &format);
2927 	}
2928 
2929 	if (hdw->srate_dirty || hdw->force_dirty) {
2930 		u32 val;
2931 		pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2932 			   hdw->srate_val);
2933 		switch (hdw->srate_val) {
2934 		default:
2935 		case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2936 			val = 48000;
2937 			break;
2938 		case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2939 			val = 44100;
2940 			break;
2941 		case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2942 			val = 32000;
2943 			break;
2944 		}
2945 		v4l2_device_call_all(&hdw->v4l2_dev, 0,
2946 				     audio, s_clock_freq, val);
2947 	}
2948 
2949 	/* Unable to set crop parameters; there is apparently no equivalent
2950 	   for VIDIOC_S_CROP */
2951 
2952 	v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2953 		id = sd->grp_id;
2954 		if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2955 		fp = pvr2_module_update_functions[id];
2956 		if (!fp) continue;
2957 		(*fp)(hdw, sd);
2958 	}
2959 
2960 	if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2961 		pvr2_hdw_status_poll(hdw);
2962 	}
2963 }
2964 
2965 
2966 /* Figure out if we need to commit control changes.  If so, mark internal
2967    state flags to indicate this fact and return true.  Otherwise do nothing
2968    else and return false. */
2969 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2970 {
2971 	unsigned int idx;
2972 	struct pvr2_ctrl *cptr;
2973 	int value;
2974 	int commit_flag = hdw->force_dirty;
2975 	char buf[100];
2976 	unsigned int bcnt,ccnt;
2977 
2978 	for (idx = 0; idx < hdw->control_cnt; idx++) {
2979 		cptr = hdw->controls + idx;
2980 		if (!cptr->info->is_dirty) continue;
2981 		if (!cptr->info->is_dirty(cptr)) continue;
2982 		commit_flag = !0;
2983 
2984 		if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2985 		bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2986 				 cptr->info->name);
2987 		value = 0;
2988 		cptr->info->get_value(cptr,&value);
2989 		pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2990 						buf+bcnt,
2991 						sizeof(buf)-bcnt,&ccnt);
2992 		bcnt += ccnt;
2993 		bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2994 				  get_ctrl_typename(cptr->info->type));
2995 		pvr2_trace(PVR2_TRACE_CTL,
2996 			   "/*--TRACE_COMMIT--*/ %.*s",
2997 			   bcnt,buf);
2998 	}
2999 
3000 	if (!commit_flag) {
3001 		/* Nothing has changed */
3002 		return 0;
3003 	}
3004 
3005 	hdw->state_pipeline_config = 0;
3006 	trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3007 	pvr2_hdw_state_sched(hdw);
3008 
3009 	return !0;
3010 }
3011 
3012 
3013 /* Perform all operations needed to commit all control changes.  This must
3014    be performed in synchronization with the pipeline state and is thus
3015    expected to be called as part of the driver's worker thread.  Return
3016    true if commit successful, otherwise return false to indicate that
3017    commit isn't possible at this time. */
3018 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3019 {
3020 	unsigned int idx;
3021 	struct pvr2_ctrl *cptr;
3022 	int disruptive_change;
3023 
3024 	if (hdw->input_dirty && hdw->state_pathway_ok &&
3025 	    (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3026 	      PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3027 	     hdw->pathway_state)) {
3028 		/* Change of mode being asked for... */
3029 		hdw->state_pathway_ok = 0;
3030 		trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3031 	}
3032 	if (!hdw->state_pathway_ok) {
3033 		/* Can't commit anything until pathway is ok. */
3034 		return 0;
3035 	}
3036 
3037 	/* Handle some required side effects when the video standard is
3038 	   changed.... */
3039 	if (hdw->std_dirty) {
3040 		int nvres;
3041 		int gop_size;
3042 		if (hdw->std_mask_cur & V4L2_STD_525_60) {
3043 			nvres = 480;
3044 			gop_size = 15;
3045 		} else {
3046 			nvres = 576;
3047 			gop_size = 12;
3048 		}
3049 		/* Rewrite the vertical resolution to be appropriate to the
3050 		   video standard that has been selected. */
3051 		if (nvres != hdw->res_ver_val) {
3052 			hdw->res_ver_val = nvres;
3053 			hdw->res_ver_dirty = !0;
3054 		}
3055 		/* Rewrite the GOP size to be appropriate to the video
3056 		   standard that has been selected. */
3057 		if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3058 			struct v4l2_ext_controls cs;
3059 			struct v4l2_ext_control c1;
3060 			memset(&cs, 0, sizeof(cs));
3061 			memset(&c1, 0, sizeof(c1));
3062 			cs.controls = &c1;
3063 			cs.count = 1;
3064 			c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3065 			c1.value = gop_size;
3066 			cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3067 					  VIDIOC_S_EXT_CTRLS);
3068 		}
3069 	}
3070 
3071 	/* The broadcast decoder can only scale down, so if
3072 	 * res_*_dirty && crop window < output format ==> enlarge crop.
3073 	 *
3074 	 * The mpeg encoder receives fields of res_hor_val dots and
3075 	 * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3076 	 */
3077 	if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3078 		hdw->cropw_val = hdw->res_hor_val;
3079 		hdw->cropw_dirty = !0;
3080 	} else if (hdw->cropw_dirty) {
3081 		hdw->res_hor_dirty = !0;           /* must rescale */
3082 		hdw->res_hor_val = min(720, hdw->cropw_val);
3083 	}
3084 	if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3085 		hdw->croph_val = hdw->res_ver_val;
3086 		hdw->croph_dirty = !0;
3087 	} else if (hdw->croph_dirty) {
3088 		int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3089 		hdw->res_ver_dirty = !0;
3090 		hdw->res_ver_val = min(nvres, hdw->croph_val);
3091 	}
3092 
3093 	/* If any of the below has changed, then we can't do the update
3094 	   while the pipeline is running.  Pipeline must be paused first
3095 	   and decoder -> encoder connection be made quiescent before we
3096 	   can proceed. */
3097 	disruptive_change =
3098 		(hdw->std_dirty ||
3099 		 hdw->enc_unsafe_stale ||
3100 		 hdw->srate_dirty ||
3101 		 hdw->res_ver_dirty ||
3102 		 hdw->res_hor_dirty ||
3103 		 hdw->cropw_dirty ||
3104 		 hdw->croph_dirty ||
3105 		 hdw->input_dirty ||
3106 		 (hdw->active_stream_type != hdw->desired_stream_type));
3107 	if (disruptive_change && !hdw->state_pipeline_idle) {
3108 		/* Pipeline is not idle; we can't proceed.  Arrange to
3109 		   cause pipeline to stop so that we can try this again
3110 		   later.... */
3111 		hdw->state_pipeline_pause = !0;
3112 		return 0;
3113 	}
3114 
3115 	if (hdw->srate_dirty) {
3116 		/* Write new sample rate into control structure since
3117 		 * the master copy is stale.  We must track srate
3118 		 * separate from the mpeg control structure because
3119 		 * other logic also uses this value. */
3120 		struct v4l2_ext_controls cs;
3121 		struct v4l2_ext_control c1;
3122 		memset(&cs,0,sizeof(cs));
3123 		memset(&c1,0,sizeof(c1));
3124 		cs.controls = &c1;
3125 		cs.count = 1;
3126 		c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3127 		c1.value = hdw->srate_val;
3128 		cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3129 	}
3130 
3131 	if (hdw->active_stream_type != hdw->desired_stream_type) {
3132 		/* Handle any side effects of stream config here */
3133 		hdw->active_stream_type = hdw->desired_stream_type;
3134 	}
3135 
3136 	if (hdw->hdw_desc->signal_routing_scheme ==
3137 	    PVR2_ROUTING_SCHEME_GOTVIEW) {
3138 		u32 b;
3139 		/* Handle GOTVIEW audio switching */
3140 		pvr2_hdw_gpio_get_out(hdw,&b);
3141 		if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3142 			/* Set GPIO 11 */
3143 			pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3144 		} else {
3145 			/* Clear GPIO 11 */
3146 			pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3147 		}
3148 	}
3149 
3150 	/* Check and update state for all sub-devices. */
3151 	pvr2_subdev_update(hdw);
3152 
3153 	hdw->tuner_updated = 0;
3154 	hdw->force_dirty = 0;
3155 	for (idx = 0; idx < hdw->control_cnt; idx++) {
3156 		cptr = hdw->controls + idx;
3157 		if (!cptr->info->clear_dirty) continue;
3158 		cptr->info->clear_dirty(cptr);
3159 	}
3160 
3161 	if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3162 	    hdw->state_encoder_run) {
3163 		/* If encoder isn't running or it can't be touched, then
3164 		   this will get worked out later when we start the
3165 		   encoder. */
3166 		if (pvr2_encoder_adjust(hdw) < 0) return !0;
3167 	}
3168 
3169 	hdw->state_pipeline_config = !0;
3170 	/* Hardware state may have changed in a way to cause the cropping
3171 	   capabilities to have changed.  So mark it stale, which will
3172 	   cause a later re-fetch. */
3173 	trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3174 	return !0;
3175 }
3176 
3177 
3178 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3179 {
3180 	int fl;
3181 	LOCK_TAKE(hdw->big_lock);
3182 	fl = pvr2_hdw_commit_setup(hdw);
3183 	LOCK_GIVE(hdw->big_lock);
3184 	if (!fl) return 0;
3185 	return pvr2_hdw_wait(hdw,0);
3186 }
3187 
3188 
3189 static void pvr2_hdw_worker_poll(struct work_struct *work)
3190 {
3191 	int fl = 0;
3192 	struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3193 	LOCK_TAKE(hdw->big_lock); do {
3194 		fl = pvr2_hdw_state_eval(hdw);
3195 	} while (0); LOCK_GIVE(hdw->big_lock);
3196 	if (fl && hdw->state_func) {
3197 		hdw->state_func(hdw->state_data);
3198 	}
3199 }
3200 
3201 
3202 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3203 {
3204 	return wait_event_interruptible(
3205 		hdw->state_wait_data,
3206 		(hdw->state_stale == 0) &&
3207 		(!state || (hdw->master_state != state)));
3208 }
3209 
3210 
3211 /* Return name for this driver instance */
3212 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3213 {
3214 	return hdw->name;
3215 }
3216 
3217 
3218 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3219 {
3220 	return hdw->hdw_desc->description;
3221 }
3222 
3223 
3224 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3225 {
3226 	return hdw->hdw_desc->shortname;
3227 }
3228 
3229 
3230 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3231 {
3232 	int result;
3233 	LOCK_TAKE(hdw->ctl_lock); do {
3234 		hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3235 		result = pvr2_send_request(hdw,
3236 					   hdw->cmd_buffer,1,
3237 					   hdw->cmd_buffer,1);
3238 		if (result < 0) break;
3239 		result = (hdw->cmd_buffer[0] != 0);
3240 	} while(0); LOCK_GIVE(hdw->ctl_lock);
3241 	return result;
3242 }
3243 
3244 
3245 /* Execute poll of tuner status */
3246 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3247 {
3248 	LOCK_TAKE(hdw->big_lock); do {
3249 		pvr2_hdw_status_poll(hdw);
3250 	} while (0); LOCK_GIVE(hdw->big_lock);
3251 }
3252 
3253 
3254 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3255 {
3256 	if (!hdw->cropcap_stale) {
3257 		return 0;
3258 	}
3259 	pvr2_hdw_status_poll(hdw);
3260 	if (hdw->cropcap_stale) {
3261 		return -EIO;
3262 	}
3263 	return 0;
3264 }
3265 
3266 
3267 /* Return information about cropping capabilities */
3268 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3269 {
3270 	int stat = 0;
3271 	LOCK_TAKE(hdw->big_lock);
3272 	stat = pvr2_hdw_check_cropcap(hdw);
3273 	if (!stat) {
3274 		memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3275 	}
3276 	LOCK_GIVE(hdw->big_lock);
3277 	return stat;
3278 }
3279 
3280 
3281 /* Return information about the tuner */
3282 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3283 {
3284 	LOCK_TAKE(hdw->big_lock); do {
3285 		if (hdw->tuner_signal_stale) {
3286 			pvr2_hdw_status_poll(hdw);
3287 		}
3288 		memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3289 	} while (0); LOCK_GIVE(hdw->big_lock);
3290 	return 0;
3291 }
3292 
3293 
3294 /* Get handle to video output stream */
3295 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3296 {
3297 	return hp->vid_stream;
3298 }
3299 
3300 
3301 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3302 {
3303 	int nr = pvr2_hdw_get_unit_number(hdw);
3304 	LOCK_TAKE(hdw->big_lock);
3305 	do {
3306 		pr_info("pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3307 		v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3308 		pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3309 		cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3310 		pvr2_hdw_state_log_state(hdw);
3311 		pr_info("pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3312 	} while (0);
3313 	LOCK_GIVE(hdw->big_lock);
3314 }
3315 
3316 
3317 /* Grab EEPROM contents, needed for direct method. */
3318 #define EEPROM_SIZE 8192
3319 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3320 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3321 {
3322 	struct i2c_msg msg[2];
3323 	u8 *eeprom;
3324 	u8 iadd[2];
3325 	u8 addr;
3326 	u16 eepromSize;
3327 	unsigned int offs;
3328 	int ret;
3329 	int mode16 = 0;
3330 	unsigned pcnt,tcnt;
3331 	eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
3332 	if (!eeprom) {
3333 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3334 			   "Failed to allocate memory required to read eeprom");
3335 		return NULL;
3336 	}
3337 
3338 	trace_eeprom("Value for eeprom addr from controller was 0x%x",
3339 		     hdw->eeprom_addr);
3340 	addr = hdw->eeprom_addr;
3341 	/* Seems that if the high bit is set, then the *real* eeprom
3342 	   address is shifted right now bit position (noticed this in
3343 	   newer PVR USB2 hardware) */
3344 	if (addr & 0x80) addr >>= 1;
3345 
3346 	/* FX2 documentation states that a 16bit-addressed eeprom is
3347 	   expected if the I2C address is an odd number (yeah, this is
3348 	   strange but it's what they do) */
3349 	mode16 = (addr & 1);
3350 	eepromSize = (mode16 ? EEPROM_SIZE : 256);
3351 	trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
3352 		     eepromSize, addr,
3353 		     mode16 ? 16 : 8);
3354 
3355 	msg[0].addr = addr;
3356 	msg[0].flags = 0;
3357 	msg[0].len = mode16 ? 2 : 1;
3358 	msg[0].buf = iadd;
3359 	msg[1].addr = addr;
3360 	msg[1].flags = I2C_M_RD;
3361 
3362 	/* We have to do the actual eeprom data fetch ourselves, because
3363 	   (1) we're only fetching part of the eeprom, and (2) if we were
3364 	   getting the whole thing our I2C driver can't grab it in one
3365 	   pass - which is what tveeprom is otherwise going to attempt */
3366 	for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3367 		pcnt = 16;
3368 		if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3369 		offs = tcnt + (eepromSize - EEPROM_SIZE);
3370 		if (mode16) {
3371 			iadd[0] = offs >> 8;
3372 			iadd[1] = offs;
3373 		} else {
3374 			iadd[0] = offs;
3375 		}
3376 		msg[1].len = pcnt;
3377 		msg[1].buf = eeprom+tcnt;
3378 		if ((ret = i2c_transfer(&hdw->i2c_adap,
3379 					msg,ARRAY_SIZE(msg))) != 2) {
3380 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3381 				   "eeprom fetch set offs err=%d",ret);
3382 			kfree(eeprom);
3383 			return NULL;
3384 		}
3385 	}
3386 	return eeprom;
3387 }
3388 
3389 
3390 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3391 				int mode,
3392 				int enable_flag)
3393 {
3394 	int ret;
3395 	u16 address;
3396 	unsigned int pipe;
3397 	LOCK_TAKE(hdw->big_lock); do {
3398 		if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3399 
3400 		if (!enable_flag) {
3401 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3402 				   "Cleaning up after CPU firmware fetch");
3403 			kfree(hdw->fw_buffer);
3404 			hdw->fw_buffer = NULL;
3405 			hdw->fw_size = 0;
3406 			if (hdw->fw_cpu_flag) {
3407 				/* Now release the CPU.  It will disconnect
3408 				   and reconnect later. */
3409 				pvr2_hdw_cpureset_assert(hdw,0);
3410 			}
3411 			break;
3412 		}
3413 
3414 		hdw->fw_cpu_flag = (mode != 2);
3415 		if (hdw->fw_cpu_flag) {
3416 			hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3417 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3418 				   "Preparing to suck out CPU firmware (size=%u)",
3419 				   hdw->fw_size);
3420 			hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3421 			if (!hdw->fw_buffer) {
3422 				hdw->fw_size = 0;
3423 				break;
3424 			}
3425 
3426 			/* We have to hold the CPU during firmware upload. */
3427 			pvr2_hdw_cpureset_assert(hdw,1);
3428 
3429 			/* download the firmware from address 0000-1fff in 2048
3430 			   (=0x800) bytes chunk. */
3431 
3432 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3433 				   "Grabbing CPU firmware");
3434 			pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3435 			for(address = 0; address < hdw->fw_size;
3436 			    address += 0x800) {
3437 				ret = usb_control_msg(hdw->usb_dev,pipe,
3438 						      0xa0,0xc0,
3439 						      address,0,
3440 						      hdw->fw_buffer+address,
3441 						      0x800,HZ);
3442 				if (ret < 0) break;
3443 			}
3444 
3445 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3446 				   "Done grabbing CPU firmware");
3447 		} else {
3448 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3449 				   "Sucking down EEPROM contents");
3450 			hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3451 			if (!hdw->fw_buffer) {
3452 				pvr2_trace(PVR2_TRACE_FIRMWARE,
3453 					   "EEPROM content suck failed.");
3454 				break;
3455 			}
3456 			hdw->fw_size = EEPROM_SIZE;
3457 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3458 				   "Done sucking down EEPROM contents");
3459 		}
3460 
3461 	} while (0); LOCK_GIVE(hdw->big_lock);
3462 }
3463 
3464 
3465 /* Return true if we're in a mode for retrieval CPU firmware */
3466 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3467 {
3468 	return hdw->fw_buffer != NULL;
3469 }
3470 
3471 
3472 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3473 		       char *buf,unsigned int cnt)
3474 {
3475 	int ret = -EINVAL;
3476 	LOCK_TAKE(hdw->big_lock); do {
3477 		if (!buf) break;
3478 		if (!cnt) break;
3479 
3480 		if (!hdw->fw_buffer) {
3481 			ret = -EIO;
3482 			break;
3483 		}
3484 
3485 		if (offs >= hdw->fw_size) {
3486 			pvr2_trace(PVR2_TRACE_FIRMWARE,
3487 				   "Read firmware data offs=%d EOF",
3488 				   offs);
3489 			ret = 0;
3490 			break;
3491 		}
3492 
3493 		if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3494 
3495 		memcpy(buf,hdw->fw_buffer+offs,cnt);
3496 
3497 		pvr2_trace(PVR2_TRACE_FIRMWARE,
3498 			   "Read firmware data offs=%d cnt=%d",
3499 			   offs,cnt);
3500 		ret = cnt;
3501 	} while (0); LOCK_GIVE(hdw->big_lock);
3502 
3503 	return ret;
3504 }
3505 
3506 
3507 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3508 				  enum pvr2_v4l_type index)
3509 {
3510 	switch (index) {
3511 	case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3512 	case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3513 	case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3514 	default: return -1;
3515 	}
3516 }
3517 
3518 
3519 /* Store a v4l minor device number */
3520 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3521 				     enum pvr2_v4l_type index,int v)
3522 {
3523 	switch (index) {
3524 	case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3525 	case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3526 	case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3527 	default: break;
3528 	}
3529 }
3530 
3531 
3532 static void pvr2_ctl_write_complete(struct urb *urb)
3533 {
3534 	struct pvr2_hdw *hdw = urb->context;
3535 	hdw->ctl_write_pend_flag = 0;
3536 	if (hdw->ctl_read_pend_flag) return;
3537 	complete(&hdw->ctl_done);
3538 }
3539 
3540 
3541 static void pvr2_ctl_read_complete(struct urb *urb)
3542 {
3543 	struct pvr2_hdw *hdw = urb->context;
3544 	hdw->ctl_read_pend_flag = 0;
3545 	if (hdw->ctl_write_pend_flag) return;
3546 	complete(&hdw->ctl_done);
3547 }
3548 
3549 struct hdw_timer {
3550 	struct timer_list timer;
3551 	struct pvr2_hdw *hdw;
3552 };
3553 
3554 static void pvr2_ctl_timeout(struct timer_list *t)
3555 {
3556 	struct hdw_timer *timer = from_timer(timer, t, timer);
3557 	struct pvr2_hdw *hdw = timer->hdw;
3558 
3559 	if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3560 		hdw->ctl_timeout_flag = !0;
3561 		if (hdw->ctl_write_pend_flag)
3562 			usb_unlink_urb(hdw->ctl_write_urb);
3563 		if (hdw->ctl_read_pend_flag)
3564 			usb_unlink_urb(hdw->ctl_read_urb);
3565 	}
3566 }
3567 
3568 
3569 /* Issue a command and get a response from the device.  This extended
3570    version includes a probe flag (which if set means that device errors
3571    should not be logged or treated as fatal) and a timeout in jiffies.
3572    This can be used to non-lethally probe the health of endpoint 1. */
3573 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3574 				unsigned int timeout,int probe_fl,
3575 				void *write_data,unsigned int write_len,
3576 				void *read_data,unsigned int read_len)
3577 {
3578 	unsigned int idx;
3579 	int status = 0;
3580 	struct hdw_timer timer = {
3581 		.hdw = hdw,
3582 	};
3583 
3584 	if (!hdw->ctl_lock_held) {
3585 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3586 			   "Attempted to execute control transfer without lock!!");
3587 		return -EDEADLK;
3588 	}
3589 	if (!hdw->flag_ok && !probe_fl) {
3590 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3591 			   "Attempted to execute control transfer when device not ok");
3592 		return -EIO;
3593 	}
3594 	if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3595 		if (!probe_fl) {
3596 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3597 				   "Attempted to execute control transfer when USB is disconnected");
3598 		}
3599 		return -ENOTTY;
3600 	}
3601 
3602 	/* Ensure that we have sane parameters */
3603 	if (!write_data) write_len = 0;
3604 	if (!read_data) read_len = 0;
3605 	if (write_len > PVR2_CTL_BUFFSIZE) {
3606 		pvr2_trace(
3607 			PVR2_TRACE_ERROR_LEGS,
3608 			"Attempted to execute %d byte control-write transfer (limit=%d)",
3609 			write_len,PVR2_CTL_BUFFSIZE);
3610 		return -EINVAL;
3611 	}
3612 	if (read_len > PVR2_CTL_BUFFSIZE) {
3613 		pvr2_trace(
3614 			PVR2_TRACE_ERROR_LEGS,
3615 			"Attempted to execute %d byte control-read transfer (limit=%d)",
3616 			write_len,PVR2_CTL_BUFFSIZE);
3617 		return -EINVAL;
3618 	}
3619 	if ((!write_len) && (!read_len)) {
3620 		pvr2_trace(
3621 			PVR2_TRACE_ERROR_LEGS,
3622 			"Attempted to execute null control transfer?");
3623 		return -EINVAL;
3624 	}
3625 
3626 
3627 	hdw->cmd_debug_state = 1;
3628 	if (write_len && write_data)
3629 		hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3630 	else
3631 		hdw->cmd_debug_code = 0;
3632 	hdw->cmd_debug_write_len = write_len;
3633 	hdw->cmd_debug_read_len = read_len;
3634 
3635 	/* Initialize common stuff */
3636 	init_completion(&hdw->ctl_done);
3637 	hdw->ctl_timeout_flag = 0;
3638 	hdw->ctl_write_pend_flag = 0;
3639 	hdw->ctl_read_pend_flag = 0;
3640 	timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0);
3641 	timer.timer.expires = jiffies + timeout;
3642 
3643 	if (write_len && write_data) {
3644 		hdw->cmd_debug_state = 2;
3645 		/* Transfer write data to internal buffer */
3646 		for (idx = 0; idx < write_len; idx++) {
3647 			hdw->ctl_write_buffer[idx] =
3648 				((unsigned char *)write_data)[idx];
3649 		}
3650 		/* Initiate a write request */
3651 		usb_fill_bulk_urb(hdw->ctl_write_urb,
3652 				  hdw->usb_dev,
3653 				  usb_sndbulkpipe(hdw->usb_dev,
3654 						  PVR2_CTL_WRITE_ENDPOINT),
3655 				  hdw->ctl_write_buffer,
3656 				  write_len,
3657 				  pvr2_ctl_write_complete,
3658 				  hdw);
3659 		hdw->ctl_write_urb->actual_length = 0;
3660 		hdw->ctl_write_pend_flag = !0;
3661 		if (usb_urb_ep_type_check(hdw->ctl_write_urb)) {
3662 			pvr2_trace(
3663 				PVR2_TRACE_ERROR_LEGS,
3664 				"Invalid write control endpoint");
3665 			return -EINVAL;
3666 		}
3667 		status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3668 		if (status < 0) {
3669 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3670 				   "Failed to submit write-control URB status=%d",
3671 status);
3672 			hdw->ctl_write_pend_flag = 0;
3673 			goto done;
3674 		}
3675 	}
3676 
3677 	if (read_len) {
3678 		hdw->cmd_debug_state = 3;
3679 		memset(hdw->ctl_read_buffer,0x43,read_len);
3680 		/* Initiate a read request */
3681 		usb_fill_bulk_urb(hdw->ctl_read_urb,
3682 				  hdw->usb_dev,
3683 				  usb_rcvbulkpipe(hdw->usb_dev,
3684 						  PVR2_CTL_READ_ENDPOINT),
3685 				  hdw->ctl_read_buffer,
3686 				  read_len,
3687 				  pvr2_ctl_read_complete,
3688 				  hdw);
3689 		hdw->ctl_read_urb->actual_length = 0;
3690 		hdw->ctl_read_pend_flag = !0;
3691 		if (usb_urb_ep_type_check(hdw->ctl_read_urb)) {
3692 			pvr2_trace(
3693 				PVR2_TRACE_ERROR_LEGS,
3694 				"Invalid read control endpoint");
3695 			return -EINVAL;
3696 		}
3697 		status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3698 		if (status < 0) {
3699 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3700 				   "Failed to submit read-control URB status=%d",
3701 status);
3702 			hdw->ctl_read_pend_flag = 0;
3703 			goto done;
3704 		}
3705 	}
3706 
3707 	/* Start timer */
3708 	add_timer(&timer.timer);
3709 
3710 	/* Now wait for all I/O to complete */
3711 	hdw->cmd_debug_state = 4;
3712 	while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3713 		wait_for_completion(&hdw->ctl_done);
3714 	}
3715 	hdw->cmd_debug_state = 5;
3716 
3717 	/* Stop timer */
3718 	del_timer_sync(&timer.timer);
3719 
3720 	hdw->cmd_debug_state = 6;
3721 	status = 0;
3722 
3723 	if (hdw->ctl_timeout_flag) {
3724 		status = -ETIMEDOUT;
3725 		if (!probe_fl) {
3726 			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3727 				   "Timed out control-write");
3728 		}
3729 		goto done;
3730 	}
3731 
3732 	if (write_len) {
3733 		/* Validate results of write request */
3734 		if ((hdw->ctl_write_urb->status != 0) &&
3735 		    (hdw->ctl_write_urb->status != -ENOENT) &&
3736 		    (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3737 		    (hdw->ctl_write_urb->status != -ECONNRESET)) {
3738 			/* USB subsystem is reporting some kind of failure
3739 			   on the write */
3740 			status = hdw->ctl_write_urb->status;
3741 			if (!probe_fl) {
3742 				pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3743 					   "control-write URB failure, status=%d",
3744 					   status);
3745 			}
3746 			goto done;
3747 		}
3748 		if (hdw->ctl_write_urb->actual_length < write_len) {
3749 			/* Failed to write enough data */
3750 			status = -EIO;
3751 			if (!probe_fl) {
3752 				pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3753 					   "control-write URB short, expected=%d got=%d",
3754 					   write_len,
3755 					   hdw->ctl_write_urb->actual_length);
3756 			}
3757 			goto done;
3758 		}
3759 	}
3760 	if (read_len && read_data) {
3761 		/* Validate results of read request */
3762 		if ((hdw->ctl_read_urb->status != 0) &&
3763 		    (hdw->ctl_read_urb->status != -ENOENT) &&
3764 		    (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3765 		    (hdw->ctl_read_urb->status != -ECONNRESET)) {
3766 			/* USB subsystem is reporting some kind of failure
3767 			   on the read */
3768 			status = hdw->ctl_read_urb->status;
3769 			if (!probe_fl) {
3770 				pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3771 					   "control-read URB failure, status=%d",
3772 					   status);
3773 			}
3774 			goto done;
3775 		}
3776 		if (hdw->ctl_read_urb->actual_length < read_len) {
3777 			/* Failed to read enough data */
3778 			status = -EIO;
3779 			if (!probe_fl) {
3780 				pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3781 					   "control-read URB short, expected=%d got=%d",
3782 					   read_len,
3783 					   hdw->ctl_read_urb->actual_length);
3784 			}
3785 			goto done;
3786 		}
3787 		/* Transfer retrieved data out from internal buffer */
3788 		for (idx = 0; idx < read_len; idx++) {
3789 			((unsigned char *)read_data)[idx] =
3790 				hdw->ctl_read_buffer[idx];
3791 		}
3792 	}
3793 
3794  done:
3795 
3796 	hdw->cmd_debug_state = 0;
3797 	if ((status < 0) && (!probe_fl)) {
3798 		pvr2_hdw_render_useless(hdw);
3799 	}
3800 	destroy_timer_on_stack(&timer.timer);
3801 
3802 	return status;
3803 }
3804 
3805 
3806 int pvr2_send_request(struct pvr2_hdw *hdw,
3807 		      void *write_data,unsigned int write_len,
3808 		      void *read_data,unsigned int read_len)
3809 {
3810 	return pvr2_send_request_ex(hdw,HZ*4,0,
3811 				    write_data,write_len,
3812 				    read_data,read_len);
3813 }
3814 
3815 
3816 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3817 {
3818 	int ret;
3819 	unsigned int cnt = 1;
3820 	unsigned int args = 0;
3821 	LOCK_TAKE(hdw->ctl_lock);
3822 	hdw->cmd_buffer[0] = cmdcode & 0xffu;
3823 	args = (cmdcode >> 8) & 0xffu;
3824 	args = (args > 2) ? 2 : args;
3825 	if (args) {
3826 		cnt += args;
3827 		hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3828 		if (args > 1) {
3829 			hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3830 		}
3831 	}
3832 	if (pvrusb2_debug & PVR2_TRACE_INIT) {
3833 		unsigned int idx;
3834 		unsigned int ccnt,bcnt;
3835 		char tbuf[50];
3836 		cmdcode &= 0xffu;
3837 		bcnt = 0;
3838 		ccnt = scnprintf(tbuf+bcnt,
3839 				 sizeof(tbuf)-bcnt,
3840 				 "Sending FX2 command 0x%x",cmdcode);
3841 		bcnt += ccnt;
3842 		for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3843 			if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3844 				ccnt = scnprintf(tbuf+bcnt,
3845 						 sizeof(tbuf)-bcnt,
3846 						 " \"%s\"",
3847 						 pvr2_fx2cmd_desc[idx].desc);
3848 				bcnt += ccnt;
3849 				break;
3850 			}
3851 		}
3852 		if (args) {
3853 			ccnt = scnprintf(tbuf+bcnt,
3854 					 sizeof(tbuf)-bcnt,
3855 					 " (%u",hdw->cmd_buffer[1]);
3856 			bcnt += ccnt;
3857 			if (args > 1) {
3858 				ccnt = scnprintf(tbuf+bcnt,
3859 						 sizeof(tbuf)-bcnt,
3860 						 ",%u",hdw->cmd_buffer[2]);
3861 				bcnt += ccnt;
3862 			}
3863 			ccnt = scnprintf(tbuf+bcnt,
3864 					 sizeof(tbuf)-bcnt,
3865 					 ")");
3866 			bcnt += ccnt;
3867 		}
3868 		pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3869 	}
3870 	ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3871 	LOCK_GIVE(hdw->ctl_lock);
3872 	return ret;
3873 }
3874 
3875 
3876 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3877 {
3878 	int ret;
3879 
3880 	LOCK_TAKE(hdw->ctl_lock);
3881 
3882 	hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3883 	PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3884 	hdw->cmd_buffer[5] = 0;
3885 	hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3886 	hdw->cmd_buffer[7] = reg & 0xff;
3887 
3888 
3889 	ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3890 
3891 	LOCK_GIVE(hdw->ctl_lock);
3892 
3893 	return ret;
3894 }
3895 
3896 
3897 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3898 {
3899 	int ret = 0;
3900 
3901 	LOCK_TAKE(hdw->ctl_lock);
3902 
3903 	hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3904 	hdw->cmd_buffer[1] = 0;
3905 	hdw->cmd_buffer[2] = 0;
3906 	hdw->cmd_buffer[3] = 0;
3907 	hdw->cmd_buffer[4] = 0;
3908 	hdw->cmd_buffer[5] = 0;
3909 	hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3910 	hdw->cmd_buffer[7] = reg & 0xff;
3911 
3912 	ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3913 	*data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3914 
3915 	LOCK_GIVE(hdw->ctl_lock);
3916 
3917 	return ret;
3918 }
3919 
3920 
3921 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3922 {
3923 	if (!hdw->flag_ok) return;
3924 	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3925 		   "Device being rendered inoperable");
3926 	if (hdw->vid_stream) {
3927 		pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3928 	}
3929 	hdw->flag_ok = 0;
3930 	trace_stbit("flag_ok",hdw->flag_ok);
3931 	pvr2_hdw_state_sched(hdw);
3932 }
3933 
3934 
3935 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3936 {
3937 	int ret;
3938 	pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3939 	ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3940 	if (ret == 0) {
3941 		ret = usb_reset_device(hdw->usb_dev);
3942 		usb_unlock_device(hdw->usb_dev);
3943 	} else {
3944 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3945 			   "Failed to lock USB device ret=%d",ret);
3946 	}
3947 	if (init_pause_msec) {
3948 		pvr2_trace(PVR2_TRACE_INFO,
3949 			   "Waiting %u msec for hardware to settle",
3950 			   init_pause_msec);
3951 		msleep(init_pause_msec);
3952 	}
3953 
3954 }
3955 
3956 
3957 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3958 {
3959 	char *da;
3960 	unsigned int pipe;
3961 	int ret;
3962 
3963 	if (!hdw->usb_dev) return;
3964 
3965 	da = kmalloc(16, GFP_KERNEL);
3966 
3967 	if (da == NULL) {
3968 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3969 			   "Unable to allocate memory to control CPU reset");
3970 		return;
3971 	}
3972 
3973 	pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3974 
3975 	da[0] = val ? 0x01 : 0x00;
3976 
3977 	/* Write the CPUCS register on the 8051.  The lsb of the register
3978 	   is the reset bit; a 1 asserts reset while a 0 clears it. */
3979 	pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3980 	ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3981 	if (ret < 0) {
3982 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3983 			   "cpureset_assert(%d) error=%d",val,ret);
3984 		pvr2_hdw_render_useless(hdw);
3985 	}
3986 
3987 	kfree(da);
3988 }
3989 
3990 
3991 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3992 {
3993 	return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3994 }
3995 
3996 
3997 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3998 {
3999 	return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4000 }
4001 
4002 
4003 
4004 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4005 {
4006 	pvr2_trace(PVR2_TRACE_INIT,
4007 		   "Requesting decoder reset");
4008 	if (hdw->decoder_client_id) {
4009 		v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4010 				     core, reset, 0);
4011 		pvr2_hdw_cx25840_vbi_hack(hdw);
4012 		return 0;
4013 	}
4014 	pvr2_trace(PVR2_TRACE_INIT,
4015 		   "Unable to reset decoder: nothing attached");
4016 	return -ENOTTY;
4017 }
4018 
4019 
4020 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4021 {
4022 	hdw->flag_ok = !0;
4023 
4024 	/* Use this for Hauppauge 160xxx only */
4025 	if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
4026 	    (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
4027 	     le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
4028 		pr_debug("%s(): resetting demod on Hauppauge 160xxx platform skipped\n",
4029 			 __func__);
4030 		/* Can't reset 160xxx or it will trash Demod tristate */
4031 		return pvr2_issue_simple_cmd(hdw,
4032 					     FX2CMD_HCW_MAKO_SLEEP_PIN |
4033 					     (1 << 8) |
4034 					     ((onoff ? 1 : 0) << 16));
4035 	}
4036 
4037 	return pvr2_issue_simple_cmd(hdw,
4038 				     FX2CMD_HCW_DEMOD_RESETIN |
4039 				     (1 << 8) |
4040 				     ((onoff ? 1 : 0) << 16));
4041 }
4042 
4043 
4044 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4045 {
4046 	hdw->flag_ok = !0;
4047 	return pvr2_issue_simple_cmd(hdw,(onoff ?
4048 					  FX2CMD_ONAIR_DTV_POWER_ON :
4049 					  FX2CMD_ONAIR_DTV_POWER_OFF));
4050 }
4051 
4052 
4053 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4054 						int onoff)
4055 {
4056 	return pvr2_issue_simple_cmd(hdw,(onoff ?
4057 					  FX2CMD_ONAIR_DTV_STREAMING_ON :
4058 					  FX2CMD_ONAIR_DTV_STREAMING_OFF));
4059 }
4060 
4061 
4062 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4063 {
4064 	int cmode;
4065 	/* Compare digital/analog desired setting with current setting.  If
4066 	   they don't match, fix it... */
4067 	cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4068 	if (cmode == hdw->pathway_state) {
4069 		/* They match; nothing to do */
4070 		return;
4071 	}
4072 
4073 	switch (hdw->hdw_desc->digital_control_scheme) {
4074 	case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4075 		pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4076 		if (cmode == PVR2_PATHWAY_ANALOG) {
4077 			/* If moving to analog mode, also force the decoder
4078 			   to reset.  If no decoder is attached, then it's
4079 			   ok to ignore this because if/when the decoder
4080 			   attaches, it will reset itself at that time. */
4081 			pvr2_hdw_cmd_decoder_reset(hdw);
4082 		}
4083 		break;
4084 	case PVR2_DIGITAL_SCHEME_ONAIR:
4085 		/* Supposedly we should always have the power on whether in
4086 		   digital or analog mode.  But for now do what appears to
4087 		   work... */
4088 		pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4089 		break;
4090 	default: break;
4091 	}
4092 
4093 	pvr2_hdw_untrip_unlocked(hdw);
4094 	hdw->pathway_state = cmode;
4095 }
4096 
4097 
4098 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4099 {
4100 	/* change some GPIO data
4101 	 *
4102 	 * note: bit d7 of dir appears to control the LED,
4103 	 * so we shut it off here.
4104 	 *
4105 	 */
4106 	if (onoff) {
4107 		pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4108 	} else {
4109 		pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4110 	}
4111 	pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4112 }
4113 
4114 
4115 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4116 
4117 static led_method_func led_methods[] = {
4118 	[PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4119 };
4120 
4121 
4122 /* Toggle LED */
4123 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4124 {
4125 	unsigned int scheme_id;
4126 	led_method_func fp;
4127 
4128 	if ((!onoff) == (!hdw->led_on)) return;
4129 
4130 	hdw->led_on = onoff != 0;
4131 
4132 	scheme_id = hdw->hdw_desc->led_scheme;
4133 	if (scheme_id < ARRAY_SIZE(led_methods)) {
4134 		fp = led_methods[scheme_id];
4135 	} else {
4136 		fp = NULL;
4137 	}
4138 
4139 	if (fp) (*fp)(hdw,onoff);
4140 }
4141 
4142 
4143 /* Stop / start video stream transport */
4144 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4145 {
4146 	int ret;
4147 
4148 	/* If we're in analog mode, then just issue the usual analog
4149 	   command. */
4150 	if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4151 		return pvr2_issue_simple_cmd(hdw,
4152 					     (runFl ?
4153 					      FX2CMD_STREAMING_ON :
4154 					      FX2CMD_STREAMING_OFF));
4155 		/*Note: Not reached */
4156 	}
4157 
4158 	if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4159 		/* Whoops, we don't know what mode we're in... */
4160 		return -EINVAL;
4161 	}
4162 
4163 	/* To get here we have to be in digital mode.  The mechanism here
4164 	   is unfortunately different for different vendors.  So we switch
4165 	   on the device's digital scheme attribute in order to figure out
4166 	   what to do. */
4167 	switch (hdw->hdw_desc->digital_control_scheme) {
4168 	case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4169 		return pvr2_issue_simple_cmd(hdw,
4170 					     (runFl ?
4171 					      FX2CMD_HCW_DTV_STREAMING_ON :
4172 					      FX2CMD_HCW_DTV_STREAMING_OFF));
4173 	case PVR2_DIGITAL_SCHEME_ONAIR:
4174 		ret = pvr2_issue_simple_cmd(hdw,
4175 					    (runFl ?
4176 					     FX2CMD_STREAMING_ON :
4177 					     FX2CMD_STREAMING_OFF));
4178 		if (ret) return ret;
4179 		return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4180 	default:
4181 		return -EINVAL;
4182 	}
4183 }
4184 
4185 
4186 /* Evaluate whether or not state_pathway_ok can change */
4187 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4188 {
4189 	if (hdw->state_pathway_ok) {
4190 		/* Nothing to do if pathway is already ok */
4191 		return 0;
4192 	}
4193 	if (!hdw->state_pipeline_idle) {
4194 		/* Not allowed to change anything if pipeline is not idle */
4195 		return 0;
4196 	}
4197 	pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4198 	hdw->state_pathway_ok = !0;
4199 	trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4200 	return !0;
4201 }
4202 
4203 
4204 /* Evaluate whether or not state_encoder_ok can change */
4205 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4206 {
4207 	if (hdw->state_encoder_ok) return 0;
4208 	if (hdw->flag_tripped) return 0;
4209 	if (hdw->state_encoder_run) return 0;
4210 	if (hdw->state_encoder_config) return 0;
4211 	if (hdw->state_decoder_run) return 0;
4212 	if (hdw->state_usbstream_run) return 0;
4213 	if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4214 		if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4215 	} else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4216 		return 0;
4217 	}
4218 
4219 	if (pvr2_upload_firmware2(hdw) < 0) {
4220 		hdw->flag_tripped = !0;
4221 		trace_stbit("flag_tripped",hdw->flag_tripped);
4222 		return !0;
4223 	}
4224 	hdw->state_encoder_ok = !0;
4225 	trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4226 	return !0;
4227 }
4228 
4229 
4230 /* Evaluate whether or not state_encoder_config can change */
4231 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4232 {
4233 	if (hdw->state_encoder_config) {
4234 		if (hdw->state_encoder_ok) {
4235 			if (hdw->state_pipeline_req &&
4236 			    !hdw->state_pipeline_pause) return 0;
4237 		}
4238 		hdw->state_encoder_config = 0;
4239 		hdw->state_encoder_waitok = 0;
4240 		trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4241 		/* paranoia - solve race if timer just completed */
4242 		del_timer_sync(&hdw->encoder_wait_timer);
4243 	} else {
4244 		if (!hdw->state_pathway_ok ||
4245 		    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4246 		    !hdw->state_encoder_ok ||
4247 		    !hdw->state_pipeline_idle ||
4248 		    hdw->state_pipeline_pause ||
4249 		    !hdw->state_pipeline_req ||
4250 		    !hdw->state_pipeline_config) {
4251 			/* We must reset the enforced wait interval if
4252 			   anything has happened that might have disturbed
4253 			   the encoder.  This should be a rare case. */
4254 			if (timer_pending(&hdw->encoder_wait_timer)) {
4255 				del_timer_sync(&hdw->encoder_wait_timer);
4256 			}
4257 			if (hdw->state_encoder_waitok) {
4258 				/* Must clear the state - therefore we did
4259 				   something to a state bit and must also
4260 				   return true. */
4261 				hdw->state_encoder_waitok = 0;
4262 				trace_stbit("state_encoder_waitok",
4263 					    hdw->state_encoder_waitok);
4264 				return !0;
4265 			}
4266 			return 0;
4267 		}
4268 		if (!hdw->state_encoder_waitok) {
4269 			if (!timer_pending(&hdw->encoder_wait_timer)) {
4270 				/* waitok flag wasn't set and timer isn't
4271 				   running.  Check flag once more to avoid
4272 				   a race then start the timer.  This is
4273 				   the point when we measure out a minimal
4274 				   quiet interval before doing something to
4275 				   the encoder. */
4276 				if (!hdw->state_encoder_waitok) {
4277 					hdw->encoder_wait_timer.expires =
4278 						jiffies + msecs_to_jiffies(
4279 						TIME_MSEC_ENCODER_WAIT);
4280 					add_timer(&hdw->encoder_wait_timer);
4281 				}
4282 			}
4283 			/* We can't continue until we know we have been
4284 			   quiet for the interval measured by this
4285 			   timer. */
4286 			return 0;
4287 		}
4288 		pvr2_encoder_configure(hdw);
4289 		if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4290 	}
4291 	trace_stbit("state_encoder_config",hdw->state_encoder_config);
4292 	return !0;
4293 }
4294 
4295 
4296 /* Return true if the encoder should not be running. */
4297 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4298 {
4299 	if (!hdw->state_encoder_ok) {
4300 		/* Encoder isn't healthy at the moment, so stop it. */
4301 		return !0;
4302 	}
4303 	if (!hdw->state_pathway_ok) {
4304 		/* Mode is not understood at the moment (i.e. it wants to
4305 		   change), so encoder must be stopped. */
4306 		return !0;
4307 	}
4308 
4309 	switch (hdw->pathway_state) {
4310 	case PVR2_PATHWAY_ANALOG:
4311 		if (!hdw->state_decoder_run) {
4312 			/* We're in analog mode and the decoder is not
4313 			   running; thus the encoder should be stopped as
4314 			   well. */
4315 			return !0;
4316 		}
4317 		break;
4318 	case PVR2_PATHWAY_DIGITAL:
4319 		if (hdw->state_encoder_runok) {
4320 			/* This is a funny case.  We're in digital mode so
4321 			   really the encoder should be stopped.  However
4322 			   if it really is running, only kill it after
4323 			   runok has been set.  This gives a chance for the
4324 			   onair quirk to function (encoder must run
4325 			   briefly first, at least once, before onair
4326 			   digital streaming can work). */
4327 			return !0;
4328 		}
4329 		break;
4330 	default:
4331 		/* Unknown mode; so encoder should be stopped. */
4332 		return !0;
4333 	}
4334 
4335 	/* If we get here, we haven't found a reason to stop the
4336 	   encoder. */
4337 	return 0;
4338 }
4339 
4340 
4341 /* Return true if the encoder should be running. */
4342 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4343 {
4344 	if (!hdw->state_encoder_ok) {
4345 		/* Don't run the encoder if it isn't healthy... */
4346 		return 0;
4347 	}
4348 	if (!hdw->state_pathway_ok) {
4349 		/* Don't run the encoder if we don't (yet) know what mode
4350 		   we need to be in... */
4351 		return 0;
4352 	}
4353 
4354 	switch (hdw->pathway_state) {
4355 	case PVR2_PATHWAY_ANALOG:
4356 		if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4357 			/* In analog mode, if the decoder is running, then
4358 			   run the encoder. */
4359 			return !0;
4360 		}
4361 		break;
4362 	case PVR2_PATHWAY_DIGITAL:
4363 		if ((hdw->hdw_desc->digital_control_scheme ==
4364 		     PVR2_DIGITAL_SCHEME_ONAIR) &&
4365 		    !hdw->state_encoder_runok) {
4366 			/* This is a quirk.  OnAir hardware won't stream
4367 			   digital until the encoder has been run at least
4368 			   once, for a minimal period of time (empiricially
4369 			   measured to be 1/4 second).  So if we're on
4370 			   OnAir hardware and the encoder has never been
4371 			   run at all, then start the encoder.  Normal
4372 			   state machine logic in the driver will
4373 			   automatically handle the remaining bits. */
4374 			return !0;
4375 		}
4376 		break;
4377 	default:
4378 		/* For completeness (unknown mode; encoder won't run ever) */
4379 		break;
4380 	}
4381 	/* If we get here, then we haven't found any reason to run the
4382 	   encoder, so don't run it. */
4383 	return 0;
4384 }
4385 
4386 
4387 /* Evaluate whether or not state_encoder_run can change */
4388 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4389 {
4390 	if (hdw->state_encoder_run) {
4391 		if (!state_check_disable_encoder_run(hdw)) return 0;
4392 		if (hdw->state_encoder_ok) {
4393 			del_timer_sync(&hdw->encoder_run_timer);
4394 			if (pvr2_encoder_stop(hdw) < 0) return !0;
4395 		}
4396 		hdw->state_encoder_run = 0;
4397 	} else {
4398 		if (!state_check_enable_encoder_run(hdw)) return 0;
4399 		if (pvr2_encoder_start(hdw) < 0) return !0;
4400 		hdw->state_encoder_run = !0;
4401 		if (!hdw->state_encoder_runok) {
4402 			hdw->encoder_run_timer.expires = jiffies +
4403 				 msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4404 			add_timer(&hdw->encoder_run_timer);
4405 		}
4406 	}
4407 	trace_stbit("state_encoder_run",hdw->state_encoder_run);
4408 	return !0;
4409 }
4410 
4411 
4412 /* Timeout function for quiescent timer. */
4413 static void pvr2_hdw_quiescent_timeout(struct timer_list *t)
4414 {
4415 	struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
4416 	hdw->state_decoder_quiescent = !0;
4417 	trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4418 	hdw->state_stale = !0;
4419 	schedule_work(&hdw->workpoll);
4420 }
4421 
4422 
4423 /* Timeout function for decoder stabilization timer. */
4424 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t)
4425 {
4426 	struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
4427 	hdw->state_decoder_ready = !0;
4428 	trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4429 	hdw->state_stale = !0;
4430 	schedule_work(&hdw->workpoll);
4431 }
4432 
4433 
4434 /* Timeout function for encoder wait timer. */
4435 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t)
4436 {
4437 	struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
4438 	hdw->state_encoder_waitok = !0;
4439 	trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4440 	hdw->state_stale = !0;
4441 	schedule_work(&hdw->workpoll);
4442 }
4443 
4444 
4445 /* Timeout function for encoder run timer. */
4446 static void pvr2_hdw_encoder_run_timeout(struct timer_list *t)
4447 {
4448 	struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
4449 	if (!hdw->state_encoder_runok) {
4450 		hdw->state_encoder_runok = !0;
4451 		trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4452 		hdw->state_stale = !0;
4453 		schedule_work(&hdw->workpoll);
4454 	}
4455 }
4456 
4457 
4458 /* Evaluate whether or not state_decoder_run can change */
4459 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4460 {
4461 	if (hdw->state_decoder_run) {
4462 		if (hdw->state_encoder_ok) {
4463 			if (hdw->state_pipeline_req &&
4464 			    !hdw->state_pipeline_pause &&
4465 			    hdw->state_pathway_ok) return 0;
4466 		}
4467 		if (!hdw->flag_decoder_missed) {
4468 			pvr2_decoder_enable(hdw,0);
4469 		}
4470 		hdw->state_decoder_quiescent = 0;
4471 		hdw->state_decoder_run = 0;
4472 		/* paranoia - solve race if timer(s) just completed */
4473 		del_timer_sync(&hdw->quiescent_timer);
4474 		/* Kill the stabilization timer, in case we're killing the
4475 		   encoder before the previous stabilization interval has
4476 		   been properly timed. */
4477 		del_timer_sync(&hdw->decoder_stabilization_timer);
4478 		hdw->state_decoder_ready = 0;
4479 	} else {
4480 		if (!hdw->state_decoder_quiescent) {
4481 			if (!timer_pending(&hdw->quiescent_timer)) {
4482 				/* We don't do something about the
4483 				   quiescent timer until right here because
4484 				   we also want to catch cases where the
4485 				   decoder was already not running (like
4486 				   after initialization) as opposed to
4487 				   knowing that we had just stopped it.
4488 				   The second flag check is here to cover a
4489 				   race - the timer could have run and set
4490 				   this flag just after the previous check
4491 				   but before we did the pending check. */
4492 				if (!hdw->state_decoder_quiescent) {
4493 					hdw->quiescent_timer.expires =
4494 						jiffies + msecs_to_jiffies(
4495 						TIME_MSEC_DECODER_WAIT);
4496 					add_timer(&hdw->quiescent_timer);
4497 				}
4498 			}
4499 			/* Don't allow decoder to start again until it has
4500 			   been quiesced first.  This little detail should
4501 			   hopefully further stabilize the encoder. */
4502 			return 0;
4503 		}
4504 		if (!hdw->state_pathway_ok ||
4505 		    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4506 		    !hdw->state_pipeline_req ||
4507 		    hdw->state_pipeline_pause ||
4508 		    !hdw->state_pipeline_config ||
4509 		    !hdw->state_encoder_config ||
4510 		    !hdw->state_encoder_ok) return 0;
4511 		del_timer_sync(&hdw->quiescent_timer);
4512 		if (hdw->flag_decoder_missed) return 0;
4513 		if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4514 		hdw->state_decoder_quiescent = 0;
4515 		hdw->state_decoder_ready = 0;
4516 		hdw->state_decoder_run = !0;
4517 		if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4518 			hdw->decoder_stabilization_timer.expires =
4519 				jiffies + msecs_to_jiffies(
4520 				TIME_MSEC_DECODER_STABILIZATION_WAIT);
4521 			add_timer(&hdw->decoder_stabilization_timer);
4522 		} else {
4523 			hdw->state_decoder_ready = !0;
4524 		}
4525 	}
4526 	trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4527 	trace_stbit("state_decoder_run",hdw->state_decoder_run);
4528 	trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4529 	return !0;
4530 }
4531 
4532 
4533 /* Evaluate whether or not state_usbstream_run can change */
4534 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4535 {
4536 	if (hdw->state_usbstream_run) {
4537 		int fl = !0;
4538 		if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4539 			fl = (hdw->state_encoder_ok &&
4540 			      hdw->state_encoder_run);
4541 		} else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4542 			   (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4543 			fl = hdw->state_encoder_ok;
4544 		}
4545 		if (fl &&
4546 		    hdw->state_pipeline_req &&
4547 		    !hdw->state_pipeline_pause &&
4548 		    hdw->state_pathway_ok) {
4549 			return 0;
4550 		}
4551 		pvr2_hdw_cmd_usbstream(hdw,0);
4552 		hdw->state_usbstream_run = 0;
4553 	} else {
4554 		if (!hdw->state_pipeline_req ||
4555 		    hdw->state_pipeline_pause ||
4556 		    !hdw->state_pathway_ok) return 0;
4557 		if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4558 			if (!hdw->state_encoder_ok ||
4559 			    !hdw->state_encoder_run) return 0;
4560 		} else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4561 			   (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4562 			if (!hdw->state_encoder_ok) return 0;
4563 			if (hdw->state_encoder_run) return 0;
4564 			if (hdw->hdw_desc->digital_control_scheme ==
4565 			    PVR2_DIGITAL_SCHEME_ONAIR) {
4566 				/* OnAir digital receivers won't stream
4567 				   unless the analog encoder has run first.
4568 				   Why?  I have no idea.  But don't even
4569 				   try until we know the analog side is
4570 				   known to have run. */
4571 				if (!hdw->state_encoder_runok) return 0;
4572 			}
4573 		}
4574 		if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4575 		hdw->state_usbstream_run = !0;
4576 	}
4577 	trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4578 	return !0;
4579 }
4580 
4581 
4582 /* Attempt to configure pipeline, if needed */
4583 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4584 {
4585 	if (hdw->state_pipeline_config ||
4586 	    hdw->state_pipeline_pause) return 0;
4587 	pvr2_hdw_commit_execute(hdw);
4588 	return !0;
4589 }
4590 
4591 
4592 /* Update pipeline idle and pipeline pause tracking states based on other
4593    inputs.  This must be called whenever the other relevant inputs have
4594    changed. */
4595 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4596 {
4597 	unsigned int st;
4598 	int updatedFl = 0;
4599 	/* Update pipeline state */
4600 	st = !(hdw->state_encoder_run ||
4601 	       hdw->state_decoder_run ||
4602 	       hdw->state_usbstream_run ||
4603 	       (!hdw->state_decoder_quiescent));
4604 	if (!st != !hdw->state_pipeline_idle) {
4605 		hdw->state_pipeline_idle = st;
4606 		updatedFl = !0;
4607 	}
4608 	if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4609 		hdw->state_pipeline_pause = 0;
4610 		updatedFl = !0;
4611 	}
4612 	return updatedFl;
4613 }
4614 
4615 
4616 typedef int (*state_eval_func)(struct pvr2_hdw *);
4617 
4618 /* Set of functions to be run to evaluate various states in the driver. */
4619 static const state_eval_func eval_funcs[] = {
4620 	state_eval_pathway_ok,
4621 	state_eval_pipeline_config,
4622 	state_eval_encoder_ok,
4623 	state_eval_encoder_config,
4624 	state_eval_decoder_run,
4625 	state_eval_encoder_run,
4626 	state_eval_usbstream_run,
4627 };
4628 
4629 
4630 /* Process various states and return true if we did anything interesting. */
4631 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4632 {
4633 	unsigned int i;
4634 	int state_updated = 0;
4635 	int check_flag;
4636 
4637 	if (!hdw->state_stale) return 0;
4638 	if ((hdw->fw1_state != FW1_STATE_OK) ||
4639 	    !hdw->flag_ok) {
4640 		hdw->state_stale = 0;
4641 		return !0;
4642 	}
4643 	/* This loop is the heart of the entire driver.  It keeps trying to
4644 	   evaluate various bits of driver state until nothing changes for
4645 	   one full iteration.  Each "bit of state" tracks some global
4646 	   aspect of the driver, e.g. whether decoder should run, if
4647 	   pipeline is configured, usb streaming is on, etc.  We separately
4648 	   evaluate each of those questions based on other driver state to
4649 	   arrive at the correct running configuration. */
4650 	do {
4651 		check_flag = 0;
4652 		state_update_pipeline_state(hdw);
4653 		/* Iterate over each bit of state */
4654 		for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4655 			if ((*eval_funcs[i])(hdw)) {
4656 				check_flag = !0;
4657 				state_updated = !0;
4658 				state_update_pipeline_state(hdw);
4659 			}
4660 		}
4661 	} while (check_flag && hdw->flag_ok);
4662 	hdw->state_stale = 0;
4663 	trace_stbit("state_stale",hdw->state_stale);
4664 	return state_updated;
4665 }
4666 
4667 
4668 static unsigned int print_input_mask(unsigned int msk,
4669 				     char *buf,unsigned int acnt)
4670 {
4671 	unsigned int idx,ccnt;
4672 	unsigned int tcnt = 0;
4673 	for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4674 		if (!((1UL << idx) & msk)) continue;
4675 		ccnt = scnprintf(buf+tcnt,
4676 				 acnt-tcnt,
4677 				 "%s%s",
4678 				 (tcnt ? ", " : ""),
4679 				 control_values_input[idx]);
4680 		tcnt += ccnt;
4681 	}
4682 	return tcnt;
4683 }
4684 
4685 
4686 static const char *pvr2_pathway_state_name(int id)
4687 {
4688 	switch (id) {
4689 	case PVR2_PATHWAY_ANALOG: return "analog";
4690 	case PVR2_PATHWAY_DIGITAL: return "digital";
4691 	default: return "unknown";
4692 	}
4693 }
4694 
4695 
4696 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4697 					     char *buf,unsigned int acnt)
4698 {
4699 	switch (which) {
4700 	case 0:
4701 		return scnprintf(
4702 			buf,acnt,
4703 			"driver:%s%s%s%s%s <mode=%s>",
4704 			(hdw->flag_ok ? " <ok>" : " <fail>"),
4705 			(hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4706 			(hdw->flag_disconnected ? " <disconnected>" :
4707 			 " <connected>"),
4708 			(hdw->flag_tripped ? " <tripped>" : ""),
4709 			(hdw->flag_decoder_missed ? " <no decoder>" : ""),
4710 			pvr2_pathway_state_name(hdw->pathway_state));
4711 
4712 	case 1:
4713 		return scnprintf(
4714 			buf,acnt,
4715 			"pipeline:%s%s%s%s",
4716 			(hdw->state_pipeline_idle ? " <idle>" : ""),
4717 			(hdw->state_pipeline_config ?
4718 			 " <configok>" : " <stale>"),
4719 			(hdw->state_pipeline_req ? " <req>" : ""),
4720 			(hdw->state_pipeline_pause ? " <pause>" : ""));
4721 	case 2:
4722 		return scnprintf(
4723 			buf,acnt,
4724 			"worker:%s%s%s%s%s%s%s",
4725 			(hdw->state_decoder_run ?
4726 			 (hdw->state_decoder_ready ?
4727 			  "<decode:run>" : " <decode:start>") :
4728 			 (hdw->state_decoder_quiescent ?
4729 			  "" : " <decode:stop>")),
4730 			(hdw->state_decoder_quiescent ?
4731 			 " <decode:quiescent>" : ""),
4732 			(hdw->state_encoder_ok ?
4733 			 "" : " <encode:init>"),
4734 			(hdw->state_encoder_run ?
4735 			 (hdw->state_encoder_runok ?
4736 			  " <encode:run>" :
4737 			  " <encode:firstrun>") :
4738 			 (hdw->state_encoder_runok ?
4739 			  " <encode:stop>" :
4740 			  " <encode:virgin>")),
4741 			(hdw->state_encoder_config ?
4742 			 " <encode:configok>" :
4743 			 (hdw->state_encoder_waitok ?
4744 			  "" : " <encode:waitok>")),
4745 			(hdw->state_usbstream_run ?
4746 			 " <usb:run>" : " <usb:stop>"),
4747 			(hdw->state_pathway_ok ?
4748 			 " <pathway:ok>" : ""));
4749 	case 3:
4750 		return scnprintf(
4751 			buf,acnt,
4752 			"state: %s",
4753 			pvr2_get_state_name(hdw->master_state));
4754 	case 4: {
4755 		unsigned int tcnt = 0;
4756 		unsigned int ccnt;
4757 
4758 		ccnt = scnprintf(buf,
4759 				 acnt,
4760 				 "Hardware supported inputs: ");
4761 		tcnt += ccnt;
4762 		tcnt += print_input_mask(hdw->input_avail_mask,
4763 					 buf+tcnt,
4764 					 acnt-tcnt);
4765 		if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4766 			ccnt = scnprintf(buf+tcnt,
4767 					 acnt-tcnt,
4768 					 "; allowed inputs: ");
4769 			tcnt += ccnt;
4770 			tcnt += print_input_mask(hdw->input_allowed_mask,
4771 						 buf+tcnt,
4772 						 acnt-tcnt);
4773 		}
4774 		return tcnt;
4775 	}
4776 	case 5: {
4777 		struct pvr2_stream_stats stats;
4778 		if (!hdw->vid_stream) break;
4779 		pvr2_stream_get_stats(hdw->vid_stream,
4780 				      &stats,
4781 				      0);
4782 		return scnprintf(
4783 			buf,acnt,
4784 			"Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
4785 			stats.bytes_processed,
4786 			stats.buffers_in_queue,
4787 			stats.buffers_in_idle,
4788 			stats.buffers_in_ready,
4789 			stats.buffers_processed,
4790 			stats.buffers_failed);
4791 	}
4792 	case 6: {
4793 		unsigned int id = hdw->ir_scheme_active;
4794 		return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4795 				 (id >= ARRAY_SIZE(ir_scheme_names) ?
4796 				  "?" : ir_scheme_names[id]));
4797 	}
4798 	default: break;
4799 	}
4800 	return 0;
4801 }
4802 
4803 
4804 /* Generate report containing info about attached sub-devices and attached
4805    i2c clients, including an indication of which attached i2c clients are
4806    actually sub-devices. */
4807 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4808 					    char *buf, unsigned int acnt)
4809 {
4810 	struct v4l2_subdev *sd;
4811 	unsigned int tcnt = 0;
4812 	unsigned int ccnt;
4813 	struct i2c_client *client;
4814 	const char *p;
4815 	unsigned int id;
4816 
4817 	ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4818 	tcnt += ccnt;
4819 	v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4820 		id = sd->grp_id;
4821 		p = NULL;
4822 		if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4823 		if (p) {
4824 			ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4825 			tcnt += ccnt;
4826 		} else {
4827 			ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4828 					 "  (unknown id=%u):", id);
4829 			tcnt += ccnt;
4830 		}
4831 		client = v4l2_get_subdevdata(sd);
4832 		if (client) {
4833 			ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4834 					 " %s @ %02x\n", client->name,
4835 					 client->addr);
4836 			tcnt += ccnt;
4837 		} else {
4838 			ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4839 					 " no i2c client\n");
4840 			tcnt += ccnt;
4841 		}
4842 	}
4843 	return tcnt;
4844 }
4845 
4846 
4847 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4848 				   char *buf,unsigned int acnt)
4849 {
4850 	unsigned int bcnt,ccnt,idx;
4851 	bcnt = 0;
4852 	LOCK_TAKE(hdw->big_lock);
4853 	for (idx = 0; ; idx++) {
4854 		ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4855 		if (!ccnt) break;
4856 		bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4857 		if (!acnt) break;
4858 		buf[0] = '\n'; ccnt = 1;
4859 		bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4860 	}
4861 	ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4862 	bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4863 	LOCK_GIVE(hdw->big_lock);
4864 	return bcnt;
4865 }
4866 
4867 
4868 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4869 {
4870 	char buf[256];
4871 	unsigned int idx, ccnt;
4872 	unsigned int lcnt, ucnt;
4873 
4874 	for (idx = 0; ; idx++) {
4875 		ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4876 		if (!ccnt) break;
4877 		pr_info("%s %.*s\n", hdw->name, ccnt, buf);
4878 	}
4879 	ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4880 	if (ccnt >= sizeof(buf))
4881 		ccnt = sizeof(buf);
4882 
4883 	ucnt = 0;
4884 	while (ucnt < ccnt) {
4885 		lcnt = 0;
4886 		while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4887 			lcnt++;
4888 		}
4889 		pr_info("%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4890 		ucnt += lcnt + 1;
4891 	}
4892 }
4893 
4894 
4895 /* Evaluate and update the driver's current state, taking various actions
4896    as appropriate for the update. */
4897 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4898 {
4899 	unsigned int st;
4900 	int state_updated = 0;
4901 	int callback_flag = 0;
4902 	int analog_mode;
4903 
4904 	pvr2_trace(PVR2_TRACE_STBITS,
4905 		   "Drive state check START");
4906 	if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4907 		pvr2_hdw_state_log_state(hdw);
4908 	}
4909 
4910 	/* Process all state and get back over disposition */
4911 	state_updated = pvr2_hdw_state_update(hdw);
4912 
4913 	analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4914 
4915 	/* Update master state based upon all other states. */
4916 	if (!hdw->flag_ok) {
4917 		st = PVR2_STATE_DEAD;
4918 	} else if (hdw->fw1_state != FW1_STATE_OK) {
4919 		st = PVR2_STATE_COLD;
4920 	} else if ((analog_mode ||
4921 		    hdw->hdw_desc->flag_digital_requires_cx23416) &&
4922 		   !hdw->state_encoder_ok) {
4923 		st = PVR2_STATE_WARM;
4924 	} else if (hdw->flag_tripped ||
4925 		   (analog_mode && hdw->flag_decoder_missed)) {
4926 		st = PVR2_STATE_ERROR;
4927 	} else if (hdw->state_usbstream_run &&
4928 		   (!analog_mode ||
4929 		    (hdw->state_encoder_run && hdw->state_decoder_run))) {
4930 		st = PVR2_STATE_RUN;
4931 	} else {
4932 		st = PVR2_STATE_READY;
4933 	}
4934 	if (hdw->master_state != st) {
4935 		pvr2_trace(PVR2_TRACE_STATE,
4936 			   "Device state change from %s to %s",
4937 			   pvr2_get_state_name(hdw->master_state),
4938 			   pvr2_get_state_name(st));
4939 		pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4940 		hdw->master_state = st;
4941 		state_updated = !0;
4942 		callback_flag = !0;
4943 	}
4944 	if (state_updated) {
4945 		/* Trigger anyone waiting on any state changes here. */
4946 		wake_up(&hdw->state_wait_data);
4947 	}
4948 
4949 	if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4950 		pvr2_hdw_state_log_state(hdw);
4951 	}
4952 	pvr2_trace(PVR2_TRACE_STBITS,
4953 		   "Drive state check DONE callback=%d",callback_flag);
4954 
4955 	return callback_flag;
4956 }
4957 
4958 
4959 /* Cause kernel thread to check / update driver state */
4960 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4961 {
4962 	if (hdw->state_stale) return;
4963 	hdw->state_stale = !0;
4964 	trace_stbit("state_stale",hdw->state_stale);
4965 	schedule_work(&hdw->workpoll);
4966 }
4967 
4968 
4969 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4970 {
4971 	return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4972 }
4973 
4974 
4975 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4976 {
4977 	return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4978 }
4979 
4980 
4981 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4982 {
4983 	return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4984 }
4985 
4986 
4987 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4988 {
4989 	u32 cval,nval;
4990 	int ret;
4991 	if (~msk) {
4992 		ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4993 		if (ret) return ret;
4994 		nval = (cval & ~msk) | (val & msk);
4995 		pvr2_trace(PVR2_TRACE_GPIO,
4996 			   "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
4997 			   msk,val,cval,nval);
4998 	} else {
4999 		nval = val;
5000 		pvr2_trace(PVR2_TRACE_GPIO,
5001 			   "GPIO direction changing to 0x%x",nval);
5002 	}
5003 	return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5004 }
5005 
5006 
5007 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5008 {
5009 	u32 cval,nval;
5010 	int ret;
5011 	if (~msk) {
5012 		ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5013 		if (ret) return ret;
5014 		nval = (cval & ~msk) | (val & msk);
5015 		pvr2_trace(PVR2_TRACE_GPIO,
5016 			   "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5017 			   msk,val,cval,nval);
5018 	} else {
5019 		nval = val;
5020 		pvr2_trace(PVR2_TRACE_GPIO,
5021 			   "GPIO output changing to 0x%x",nval);
5022 	}
5023 	return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5024 }
5025 
5026 
5027 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5028 {
5029 	struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5030 	memset(vtp, 0, sizeof(*vtp));
5031 	vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5032 		V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5033 	hdw->tuner_signal_stale = 0;
5034 	/* Note: There apparently is no replacement for VIDIOC_CROPCAP
5035 	   using v4l2-subdev - therefore we can't support that AT ALL right
5036 	   now.  (Of course, no sub-drivers seem to implement it either.
5037 	   But now it's a a chicken and egg problem...) */
5038 	v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5039 	pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
5040 		   vtp->type,
5041 		   vtp->signal, vtp->rxsubchans, vtp->capability,
5042 		   vtp->rangelow, vtp->rangehigh);
5043 
5044 	/* We have to do this to avoid getting into constant polling if
5045 	   there's nobody to answer a poll of cropcap info. */
5046 	hdw->cropcap_stale = 0;
5047 }
5048 
5049 
5050 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5051 {
5052 	return hdw->input_avail_mask;
5053 }
5054 
5055 
5056 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5057 {
5058 	return hdw->input_allowed_mask;
5059 }
5060 
5061 
5062 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5063 {
5064 	if (hdw->input_val != v) {
5065 		hdw->input_val = v;
5066 		hdw->input_dirty = !0;
5067 	}
5068 
5069 	/* Handle side effects - if we switch to a mode that needs the RF
5070 	   tuner, then select the right frequency choice as well and mark
5071 	   it dirty. */
5072 	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5073 		hdw->freqSelector = 0;
5074 		hdw->freqDirty = !0;
5075 	} else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5076 		   (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5077 		hdw->freqSelector = 1;
5078 		hdw->freqDirty = !0;
5079 	}
5080 	return 0;
5081 }
5082 
5083 
5084 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5085 			       unsigned int change_mask,
5086 			       unsigned int change_val)
5087 {
5088 	int ret = 0;
5089 	unsigned int nv,m,idx;
5090 	LOCK_TAKE(hdw->big_lock);
5091 	do {
5092 		nv = hdw->input_allowed_mask & ~change_mask;
5093 		nv |= (change_val & change_mask);
5094 		nv &= hdw->input_avail_mask;
5095 		if (!nv) {
5096 			/* No legal modes left; return error instead. */
5097 			ret = -EPERM;
5098 			break;
5099 		}
5100 		hdw->input_allowed_mask = nv;
5101 		if ((1UL << hdw->input_val) & hdw->input_allowed_mask) {
5102 			/* Current mode is still in the allowed mask, so
5103 			   we're done. */
5104 			break;
5105 		}
5106 		/* Select and switch to a mode that is still in the allowed
5107 		   mask */
5108 		if (!hdw->input_allowed_mask) {
5109 			/* Nothing legal; give up */
5110 			break;
5111 		}
5112 		m = hdw->input_allowed_mask;
5113 		for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5114 			if (!((1UL << idx) & m)) continue;
5115 			pvr2_hdw_set_input(hdw,idx);
5116 			break;
5117 		}
5118 	} while (0);
5119 	LOCK_GIVE(hdw->big_lock);
5120 	return ret;
5121 }
5122 
5123 
5124 /* Find I2C address of eeprom */
5125 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5126 {
5127 	int result;
5128 	LOCK_TAKE(hdw->ctl_lock); do {
5129 		hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5130 		result = pvr2_send_request(hdw,
5131 					   hdw->cmd_buffer,1,
5132 					   hdw->cmd_buffer,1);
5133 		if (result < 0) break;
5134 		result = hdw->cmd_buffer[0];
5135 	} while(0); LOCK_GIVE(hdw->ctl_lock);
5136 	return result;
5137 }
5138