1 #define EM_GPIO_0 (1 << 0) 2 #define EM_GPIO_1 (1 << 1) 3 #define EM_GPIO_2 (1 << 2) 4 #define EM_GPIO_3 (1 << 3) 5 #define EM_GPIO_4 (1 << 4) 6 #define EM_GPIO_5 (1 << 5) 7 #define EM_GPIO_6 (1 << 6) 8 #define EM_GPIO_7 (1 << 7) 9 10 #define EM_GPO_0 (1 << 0) 11 #define EM_GPO_1 (1 << 1) 12 #define EM_GPO_2 (1 << 2) 13 #define EM_GPO_3 (1 << 3) 14 15 /* em28xx endpoints */ 16 /* 0x82: (always ?) analog */ 17 #define EM28XX_EP_AUDIO 0x83 18 /* 0x84: digital or analog */ 19 20 /* em2800 registers */ 21 #define EM2800_R08_AUDIOSRC 0x08 22 23 /* em28xx registers */ 24 25 #define EM28XX_R00_CHIPCFG 0x00 26 27 /* em28xx Chip Configuration 0x00 */ 28 #define EM2860_CHIPCFG_VENDOR_AUDIO 0x80 29 #define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE 0x40 30 #define EM2820_CHIPCFG_I2S_3_SAMPRATES 0x30 31 #define EM2860_CHIPCFG_I2S_5_SAMPRATES 0x30 32 #define EM2820_CHIPCFG_I2S_1_SAMPRATE 0x20 33 #define EM2860_CHIPCFG_I2S_3_SAMPRATES 0x20 34 #define EM28XX_CHIPCFG_AC97 0x10 35 #define EM28XX_CHIPCFG_AUDIOMASK 0x30 36 37 #define EM28XX_R01_CHIPCFG2 0x01 38 39 /* em28xx Chip Configuration 2 0x01 */ 40 #define EM28XX_CHIPCFG2_TS_PRESENT 0x10 41 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */ 42 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x00 43 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x04 44 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x08 45 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c 46 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */ 47 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x00 48 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x01 49 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x02 50 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x03 51 52 /* GPIO/GPO registers */ 53 #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */ 54 #define EM2820_R08_GPIO_CTRL 0x08 /* em2820-em2873/83 only */ 55 #define EM2820_R09_GPIO_STATE 0x09 /* em2820-em2873/83 only */ 56 57 #define EM28XX_R06_I2C_CLK 0x06 58 59 /* em28xx I2C Clock Register (0x06) */ 60 #define EM28XX_I2C_CLK_ACK_LAST_READ 0x80 61 #define EM28XX_I2C_CLK_WAIT_ENABLE 0x40 62 #define EM28XX_I2C_EEPROM_ON_BOARD 0x08 63 #define EM28XX_I2C_EEPROM_KEY_VALID 0x04 64 #define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */ 65 #define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */ 66 #define EM28XX_I2C_FREQ_25_KHZ 0x02 67 #define EM28XX_I2C_FREQ_400_KHZ 0x01 68 #define EM28XX_I2C_FREQ_100_KHZ 0x00 69 70 #define EM28XX_R0A_CHIPID 0x0a 71 #define EM28XX_R0C_USBSUSP 0x0c 72 #define EM28XX_R0C_USBSUSP_SNAPSHOT 0x20 /* 1=button pressed, needs reset */ 73 74 #define EM28XX_R0E_AUDIOSRC 0x0e 75 #define EM28XX_R0F_XCLK 0x0f 76 77 /* em28xx XCLK Register (0x0f) */ 78 #define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */ 79 #define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */ 80 #define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */ 81 #define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10 82 #define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */ 83 #define EM28XX_XCLK_FREQUENCY_15MHZ 0x01 84 #define EM28XX_XCLK_FREQUENCY_10MHZ 0x02 85 #define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03 86 #define EM28XX_XCLK_FREQUENCY_6MHZ 0x04 87 #define EM28XX_XCLK_FREQUENCY_5MHZ 0x05 88 #define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06 89 #define EM28XX_XCLK_FREQUENCY_12MHZ 0x07 90 #define EM28XX_XCLK_FREQUENCY_20MHZ 0x08 91 #define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09 92 #define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a 93 #define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b 94 95 #define EM28XX_R10_VINMODE 0x10 96 97 #define EM28XX_R11_VINCTRL 0x11 98 99 /* em28xx Video Input Control Register 0x11 */ 100 #define EM28XX_VINCTRL_VBI_SLICED 0x80 101 #define EM28XX_VINCTRL_VBI_RAW 0x40 102 #define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */ 103 #define EM28XX_VINCTRL_CCIR656_ENABLE 0x10 104 #define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */ 105 #define EM28XX_VINCTRL_FID_ON_HREF 0x04 106 #define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02 107 #define EM28XX_VINCTRL_INTERLACED 0x01 108 109 #define EM28XX_R12_VINENABLE 0x12 /* */ 110 111 #define EM28XX_R14_GAMMA 0x14 112 #define EM28XX_R15_RGAIN 0x15 113 #define EM28XX_R16_GGAIN 0x16 114 #define EM28XX_R17_BGAIN 0x17 115 #define EM28XX_R18_ROFFSET 0x18 116 #define EM28XX_R19_GOFFSET 0x19 117 #define EM28XX_R1A_BOFFSET 0x1a 118 119 #define EM28XX_R1B_OFLOW 0x1b 120 #define EM28XX_R1C_HSTART 0x1c 121 #define EM28XX_R1D_VSTART 0x1d 122 #define EM28XX_R1E_CWIDTH 0x1e 123 #define EM28XX_R1F_CHEIGHT 0x1f 124 125 #define EM28XX_R20_YGAIN 0x20 /* contrast [0:4] */ 126 #define CONTRAST_DEFAULT 0x10 127 128 #define EM28XX_R21_YOFFSET 0x21 /* brightness */ /* signed */ 129 #define BRIGHTNESS_DEFAULT 0x00 130 131 #define EM28XX_R22_UVGAIN 0x22 /* saturation [0:4] */ 132 #define SATURATION_DEFAULT 0x10 133 134 #define EM28XX_R23_UOFFSET 0x23 /* blue balance */ /* signed */ 135 #define BLUE_BALANCE_DEFAULT 0x00 136 137 #define EM28XX_R24_VOFFSET 0x24 /* red balance */ /* signed */ 138 #define RED_BALANCE_DEFAULT 0x00 139 140 #define EM28XX_R25_SHARPNESS 0x25 /* sharpness [0:4] */ 141 #define SHARPNESS_DEFAULT 0x00 142 143 #define EM28XX_R26_COMPR 0x26 144 #define EM28XX_R27_OUTFMT 0x27 145 146 /* em28xx Output Format Register (0x27) */ 147 #define EM28XX_OUTFMT_RGB_8_RGRG 0x00 148 #define EM28XX_OUTFMT_RGB_8_GRGR 0x01 149 #define EM28XX_OUTFMT_RGB_8_GBGB 0x02 150 #define EM28XX_OUTFMT_RGB_8_BGBG 0x03 151 #define EM28XX_OUTFMT_RGB_16_656 0x04 152 #define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */ 153 #define EM28XX_OUTFMT_YUV211 0x10 154 #define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14 155 #define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15 156 #define EM28XX_OUTFMT_YUV411 0x18 157 158 #define EM28XX_R28_XMIN 0x28 159 #define EM28XX_R29_XMAX 0x29 160 #define EM28XX_R2A_YMIN 0x2a 161 #define EM28XX_R2B_YMAX 0x2b 162 163 #define EM28XX_R30_HSCALELOW 0x30 164 #define EM28XX_R31_HSCALEHIGH 0x31 165 #define EM28XX_R32_VSCALELOW 0x32 166 #define EM28XX_R33_VSCALEHIGH 0x33 167 #define EM28XX_HVSCALE_MAX 0x3fff /* => 20% */ 168 169 #define EM28XX_R34_VBI_START_H 0x34 170 #define EM28XX_R35_VBI_START_V 0x35 171 /* 172 * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these 173 * registers for a different unknown purpose. 174 * => register 0x34 is set to capture width / 16 175 * => register 0x35 is set to capture height / 16 176 */ 177 178 #define EM28XX_R36_VBI_WIDTH 0x36 179 #define EM28XX_R37_VBI_HEIGHT 0x37 180 181 #define EM28XX_R40_AC97LSB 0x40 182 #define EM28XX_R41_AC97MSB 0x41 183 #define EM28XX_R42_AC97ADDR 0x42 184 #define EM28XX_R43_AC97BUSY 0x43 185 186 #define EM28XX_R45_IR 0x45 187 /* 0x45 bit 7 - parity bit 188 bits 6-0 - count 189 0x46 IR brand 190 0x47 IR data 191 */ 192 193 /* em2874 registers */ 194 #define EM2874_R50_IR_CONFIG 0x50 195 #define EM2874_R51_IR 0x51 196 #define EM2874_R5D_TS1_PKT_SIZE 0x5d 197 #define EM2874_R5E_TS2_PKT_SIZE 0x5e 198 /* 199 * For both TS1 and TS2, In isochronous mode: 200 * 0x01 188 bytes 201 * 0x02 376 bytes 202 * 0x03 564 bytes 203 * 0x04 752 bytes 204 * 0x05 940 bytes 205 * In bulk mode: 206 * 0x01..0xff total packet count in 188-byte 207 */ 208 209 #define EM2874_R5F_TS_ENABLE 0x5f 210 211 /* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */ 212 /* 213 * NOTE: not all ports are bonded out; 214 * Some ports are multiplexed with special function I/O 215 */ 216 #define EM2874_R80_GPIO_P0_CTRL 0x80 217 #define EM2874_R81_GPIO_P1_CTRL 0x81 218 #define EM2874_R82_GPIO_P2_CTRL 0x82 219 #define EM2874_R83_GPIO_P3_CTRL 0x83 220 #define EM2874_R84_GPIO_P0_STATE 0x84 221 #define EM2874_R85_GPIO_P1_STATE 0x85 222 #define EM2874_R86_GPIO_P2_STATE 0x86 223 #define EM2874_R87_GPIO_P3_STATE 0x87 224 225 /* em2874 IR config register (0x50) */ 226 #define EM2874_IR_NEC 0x00 227 #define EM2874_IR_NEC_NO_PARITY 0x01 228 #define EM2874_IR_RC5 0x04 229 #define EM2874_IR_RC6_MODE_0 0x08 230 #define EM2874_IR_RC6_MODE_6A 0x0b 231 232 /* em2874 Transport Stream Enable Register (0x5f) */ 233 #define EM2874_TS1_CAPTURE_ENABLE (1 << 0) 234 #define EM2874_TS1_FILTER_ENABLE (1 << 1) 235 #define EM2874_TS1_NULL_DISCARD (1 << 2) 236 #define EM2874_TS2_CAPTURE_ENABLE (1 << 4) 237 #define EM2874_TS2_FILTER_ENABLE (1 << 5) 238 #define EM2874_TS2_NULL_DISCARD (1 << 6) 239 240 /* register settings */ 241 #define EM2800_AUDIO_SRC_TUNER 0x0d 242 #define EM2800_AUDIO_SRC_LINE 0x0c 243 #define EM28XX_AUDIO_SRC_TUNER 0xc0 244 #define EM28XX_AUDIO_SRC_LINE 0x80 245 246 /* FIXME: Need to be populated with the other chip ID's */ 247 enum em28xx_chip_id { 248 CHIP_ID_EM2800 = 7, 249 CHIP_ID_EM2710 = 17, 250 CHIP_ID_EM2820 = 18, /* Also used by some em2710 */ 251 CHIP_ID_EM2840 = 20, 252 CHIP_ID_EM2750 = 33, 253 CHIP_ID_EM2860 = 34, 254 CHIP_ID_EM2870 = 35, 255 CHIP_ID_EM2883 = 36, 256 CHIP_ID_EM2765 = 54, 257 CHIP_ID_EM2874 = 65, 258 CHIP_ID_EM2884 = 68, 259 CHIP_ID_EM28174 = 113, 260 CHIP_ID_EM28178 = 114, 261 }; 262 263 /* 264 * Registers used by em202 265 */ 266 267 /* EMP202 vendor registers */ 268 #define EM202_EXT_MODEM_CTRL 0x3e 269 #define EM202_GPIO_CONF 0x4c 270 #define EM202_GPIO_POLARITY 0x4e 271 #define EM202_GPIO_STICKY 0x50 272 #define EM202_GPIO_MASK 0x52 273 #define EM202_GPIO_STATUS 0x54 274 #define EM202_SPDIF_OUT_SEL 0x6a 275 #define EM202_ANTIPOP 0x72 276 #define EM202_EAPD_GPIO_ACCESS 0x74 277