1 /*
2  *  mxl111sf-reg.h - driver for the MaxLinear MXL111SF
3  *
4  *  Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
5  *
6  *  This program is free software; you can redistribute it and/or modify
7  *  it under the terms of the GNU General Public License as published by
8  *  the Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *  GNU General Public License for more details.
15  */
16 
17 #ifndef _DVB_USB_MXL111SF_REG_H_
18 #define _DVB_USB_MXL111SF_REG_H_
19 
20 #define CHIP_ID_REG                  0xFC
21 #define TOP_CHIP_REV_ID_REG          0xFA
22 
23 #define V6_SNR_RB_LSB_REG            0x27
24 #define V6_SNR_RB_MSB_REG            0x28
25 
26 #define V6_N_ACCUMULATE_REG          0x11
27 #define V6_RS_AVG_ERRORS_LSB_REG     0x2C
28 #define V6_RS_AVG_ERRORS_MSB_REG     0x2D
29 
30 #define V6_IRQ_STATUS_REG            0x24
31 #define  IRQ_MASK_FEC_LOCK       0x10
32 
33 #define V6_SYNC_LOCK_REG             0x28
34 #define SYNC_LOCK_MASK           0x10
35 
36 #define V6_RS_LOCK_DET_REG           0x28
37 #define  RS_LOCK_DET_MASK        0x08
38 
39 #define V6_INITACQ_NODETECT_REG    0x20
40 #define V6_FORCE_NFFT_CPSIZE_REG   0x20
41 
42 #define V6_CODE_RATE_TPS_REG       0x29
43 #define V6_CODE_RATE_TPS_MASK      0x07
44 
45 
46 #define V6_CP_LOCK_DET_REG        0x28
47 #define V6_CP_LOCK_DET_MASK       0x04
48 
49 #define V6_TPS_HIERACHY_REG        0x29
50 #define V6_TPS_HIERARCHY_INFO_MASK  0x40
51 
52 #define V6_MODORDER_TPS_REG        0x2A
53 #define V6_PARAM_CONSTELLATION_MASK   0x30
54 
55 #define V6_MODE_TPS_REG            0x2A
56 #define V6_PARAM_FFT_MODE_MASK        0x0C
57 
58 
59 #define V6_CP_TPS_REG             0x29
60 #define V6_PARAM_GI_MASK              0x30
61 
62 #define V6_TPS_LOCK_REG           0x2A
63 #define V6_PARAM_TPS_LOCK_MASK        0x40
64 
65 #define V6_FEC_PER_COUNT_REG      0x2E
66 #define V6_FEC_PER_SCALE_REG      0x2B
67 #define V6_FEC_PER_SCALE_MASK        0x03
68 #define V6_FEC_PER_CLR_REG        0x20
69 #define V6_FEC_PER_CLR_MASK          0x01
70 
71 #define V6_PIN_MUX_MODE_REG       0x1B
72 #define V6_ENABLE_PIN_MUX            0x1E
73 
74 #define V6_I2S_NUM_SAMPLES_REG    0x16
75 
76 #define V6_MPEG_IN_CLK_INV_REG    0x17
77 #define V6_MPEG_IN_CTRL_REG       0x18
78 
79 #define V6_INVERTED_CLK_PHASE       0x20
80 #define V6_MPEG_IN_DATA_PARALLEL    0x01
81 #define V6_MPEG_IN_DATA_SERIAL      0x02
82 
83 #define V6_INVERTED_MPEG_SYNC       0x04
84 #define V6_INVERTED_MPEG_VALID      0x08
85 
86 #define TSIF_INPUT_PARALLEL         0
87 #define TSIF_INPUT_SERIAL           1
88 #define TSIF_NORMAL                 0
89 
90 #define V6_MPEG_INOUT_BIT_ORDER_CTRL_REG  0x19
91 #define V6_MPEG_SER_MSB_FIRST                0x80
92 #define MPEG_SER_MSB_FIRST_ENABLED        0x01
93 
94 #define V6_656_I2S_BUFF_STATUS_REG   0x2F
95 #define V6_656_OVERFLOW_MASK_BIT         0x08
96 #define V6_I2S_OVERFLOW_MASK_BIT         0x01
97 
98 #define V6_I2S_STREAM_START_BIT_REG  0x14
99 #define V6_I2S_STREAM_END_BIT_REG    0x15
100 #define I2S_RIGHT_JUSTIFIED     0
101 #define I2S_LEFT_JUSTIFIED      1
102 #define I2S_DATA_FORMAT         2
103 
104 #define V6_TUNER_LOOP_THRU_CONTROL_REG  0x09
105 #define V6_ENABLE_LOOP_THRU               0x01
106 
107 #define TOTAL_NUM_IF_OUTPUT_FREQ       16
108 
109 #define TUNER_NORMAL_IF_SPECTRUM       0x0
110 #define TUNER_INVERT_IF_SPECTRUM       0x10
111 
112 #define V6_TUNER_IF_SEL_REG              0x06
113 #define V6_TUNER_IF_FCW_REG              0x3C
114 #define V6_TUNER_IF_FCW_BYP_REG          0x3D
115 #define V6_RF_LOCK_STATUS_REG            0x23
116 
117 #define NUM_DIG_TV_CHANNEL     1000
118 
119 #define V6_DIG_CLK_FREQ_SEL_REG  0x07
120 #define V6_REF_SYNTH_INT_REG     0x5C
121 #define V6_REF_SYNTH_REMAIN_REG  0x58
122 #define V6_DIG_RFREFSELECT_REG   0x32
123 #define V6_XTAL_CLK_OUT_GAIN_REG   0x31
124 #define V6_TUNER_LOOP_THRU_CTRL_REG      0x09
125 #define V6_DIG_XTAL_ENABLE_REG  0x06
126 #define V6_DIG_XTAL_BIAS_REG  0x66
127 #define V6_XTAL_CAP_REG    0x08
128 
129 #define V6_GPO_CTRL_REG     0x18
130 #define MXL_GPO_0           0x00
131 #define MXL_GPO_1           0x01
132 #define V6_GPO_0_MASK       0x10
133 #define V6_GPO_1_MASK       0x20
134 
135 #define V6_111SF_GPO_CTRL_REG     0x19
136 #define MXL_111SF_GPO_1               0x00
137 #define MXL_111SF_GPO_2               0x01
138 #define MXL_111SF_GPO_3               0x02
139 #define MXL_111SF_GPO_4               0x03
140 #define MXL_111SF_GPO_5               0x04
141 #define MXL_111SF_GPO_6               0x05
142 #define MXL_111SF_GPO_7               0x06
143 
144 #define MXL_111SF_GPO_0_MASK          0x01
145 #define MXL_111SF_GPO_1_MASK          0x02
146 #define MXL_111SF_GPO_2_MASK          0x04
147 #define MXL_111SF_GPO_3_MASK          0x08
148 #define MXL_111SF_GPO_4_MASK          0x10
149 #define MXL_111SF_GPO_5_MASK          0x20
150 #define MXL_111SF_GPO_6_MASK          0x40
151 
152 #define V6_ATSC_CONFIG_REG  0x0A
153 
154 #define MXL_MODE_REG    0x03
155 #define START_TUNE_REG  0x1C
156 
157 #define V6_IDAC_HYSTERESIS_REG    0x0B
158 #define V6_IDAC_SETTINGS_REG      0x0C
159 #define IDAC_MANUAL_CONTROL             1
160 #define IDAC_CURRENT_SINKING_ENABLE     1
161 #define IDAC_MANUAL_CONTROL_BIT_MASK      0x80
162 #define IDAC_CURRENT_SINKING_BIT_MASK     0x40
163 
164 #define V8_SPI_MODE_REG  0xE9
165 
166 #define V6_DIG_RF_PWR_LSB_REG  0x46
167 #define V6_DIG_RF_PWR_MSB_REG  0x47
168 
169 #endif /* _DVB_USB_MXL111SF_REG_H_ */
170