1 /* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #include "cx231xx.h" 26 #include <linux/init.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/kernel.h> 30 #include <linux/bitmap.h> 31 #include <linux/i2c.h> 32 #include <linux/mm.h> 33 #include <linux/mutex.h> 34 #include <media/tuner.h> 35 36 #include <media/v4l2-common.h> 37 #include <media/v4l2-ioctl.h> 38 39 #include "cx231xx-dif.h" 40 41 #define TUNER_MODE_FM_RADIO 0 42 /****************************************************************************** 43 -: BLOCK ARRANGEMENT :- 44 I2S block ----------------------| 45 [I2S audio] | 46 | 47 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 48 [video & audio] | [Audio] 49 | 50 |-> Cx25840 --> Video 51 [Video] 52 53 *******************************************************************************/ 54 /****************************************************************************** 55 * VERVE REGISTER * 56 * * 57 ******************************************************************************/ 58 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 59 { 60 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 61 saddr, 1, data, 1); 62 } 63 64 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 65 { 66 int status; 67 u32 temp = 0; 68 69 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 70 saddr, 1, &temp, 1); 71 *data = (u8) temp; 72 return status; 73 } 74 void initGPIO(struct cx231xx *dev) 75 { 76 u32 _gpio_direction = 0; 77 u32 value = 0; 78 u8 val = 0; 79 80 _gpio_direction = _gpio_direction & 0xFC0003FF; 81 _gpio_direction = _gpio_direction | 0x03FDFC00; 82 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 83 84 verve_read_byte(dev, 0x07, &val); 85 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 86 verve_write_byte(dev, 0x07, 0xF4); 87 verve_read_byte(dev, 0x07, &val); 88 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 89 90 cx231xx_capture_start(dev, 1, Vbi); 91 92 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 93 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 94 95 } 96 void uninitGPIO(struct cx231xx *dev) 97 { 98 u8 value[4] = { 0, 0, 0, 0 }; 99 100 cx231xx_capture_start(dev, 0, Vbi); 101 verve_write_byte(dev, 0x07, 0x14); 102 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 103 0x68, value, 4); 104 } 105 106 /****************************************************************************** 107 * A F E - B L O C K C O N T R O L functions * 108 * [ANALOG FRONT END] * 109 ******************************************************************************/ 110 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 111 { 112 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 113 saddr, 2, data, 1); 114 } 115 116 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 117 { 118 int status; 119 u32 temp = 0; 120 121 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 122 saddr, 2, &temp, 1); 123 *data = (u8) temp; 124 return status; 125 } 126 127 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 128 { 129 int status = 0; 130 u8 temp = 0; 131 u8 afe_power_status = 0; 132 int i = 0; 133 134 /* super block initialize */ 135 temp = (u8) (ref_count & 0xff); 136 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 137 if (status < 0) 138 return status; 139 140 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 141 if (status < 0) 142 return status; 143 144 temp = (u8) ((ref_count & 0x300) >> 8); 145 temp |= 0x40; 146 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 147 if (status < 0) 148 return status; 149 150 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 151 if (status < 0) 152 return status; 153 154 /* enable pll */ 155 while (afe_power_status != 0x18) { 156 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 157 if (status < 0) { 158 dev_dbg(dev->dev, 159 "%s: Init Super Block failed in send cmd\n", 160 __func__); 161 break; 162 } 163 164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 165 afe_power_status &= 0xff; 166 if (status < 0) { 167 dev_dbg(dev->dev, 168 "%s: Init Super Block failed in receive cmd\n", 169 __func__); 170 break; 171 } 172 i++; 173 if (i == 10) { 174 dev_dbg(dev->dev, 175 "%s: Init Super Block force break in loop !!!!\n", 176 __func__); 177 status = -1; 178 break; 179 } 180 } 181 182 if (status < 0) 183 return status; 184 185 /* start tuning filter */ 186 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 187 if (status < 0) 188 return status; 189 190 msleep(5); 191 192 /* exit tuning */ 193 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 194 195 return status; 196 } 197 198 int cx231xx_afe_init_channels(struct cx231xx *dev) 199 { 200 int status = 0; 201 202 /* power up all 3 channels, clear pd_buffer */ 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 205 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 206 207 /* Enable quantizer calibration */ 208 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 209 210 /* channel initialize, force modulator (fb) reset */ 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 213 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 214 215 /* start quantilizer calibration */ 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 218 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 219 msleep(5); 220 221 /* exit modulator (fb) reset */ 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 224 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 225 226 /* enable the pre_clamp in each channel for single-ended input */ 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 229 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 230 231 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 233 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 235 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 236 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 237 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 238 239 /* dynamic element matching off */ 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 242 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 243 244 return status; 245 } 246 247 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 248 { 249 u8 c_value = 0; 250 int status = 0; 251 252 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 253 c_value &= (~(0x50)); 254 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 255 256 return status; 257 } 258 259 /* 260 The Analog Front End in Cx231xx has 3 channels. These 261 channels are used to share between different inputs 262 like tuner, s-video and composite inputs. 263 264 channel 1 ----- pin 1 to pin4(in reg is 1-4) 265 channel 2 ----- pin 5 to pin8(in reg is 5-8) 266 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 267 */ 268 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 269 { 270 u8 ch1_setting = (u8) input_mux; 271 u8 ch2_setting = (u8) (input_mux >> 8); 272 u8 ch3_setting = (u8) (input_mux >> 16); 273 int status = 0; 274 u8 value = 0; 275 276 if (ch1_setting != 0) { 277 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 278 value &= ~INPUT_SEL_MASK; 279 value |= (ch1_setting - 1) << 4; 280 value &= 0xff; 281 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 282 } 283 284 if (ch2_setting != 0) { 285 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 286 value &= ~INPUT_SEL_MASK; 287 value |= (ch2_setting - 1) << 4; 288 value &= 0xff; 289 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 290 } 291 292 /* For ch3_setting, the value to put in the register is 293 7 less than the input number */ 294 if (ch3_setting != 0) { 295 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 296 value &= ~INPUT_SEL_MASK; 297 value |= (ch3_setting - 1) << 4; 298 value &= 0xff; 299 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 300 } 301 302 return status; 303 } 304 305 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 306 { 307 int status = 0; 308 309 /* 310 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 311 * Currently, only baseband works. 312 */ 313 314 switch (mode) { 315 case AFE_MODE_LOW_IF: 316 cx231xx_Setup_AFE_for_LowIF(dev); 317 break; 318 case AFE_MODE_BASEBAND: 319 status = cx231xx_afe_setup_AFE_for_baseband(dev); 320 break; 321 case AFE_MODE_EU_HI_IF: 322 /* SetupAFEforEuHiIF(); */ 323 break; 324 case AFE_MODE_US_HI_IF: 325 /* SetupAFEforUsHiIF(); */ 326 break; 327 case AFE_MODE_JAPAN_HI_IF: 328 /* SetupAFEforJapanHiIF(); */ 329 break; 330 } 331 332 if ((mode != dev->afe_mode) && 333 (dev->video_input == CX231XX_VMUX_TELEVISION)) 334 status = cx231xx_afe_adjust_ref_count(dev, 335 CX231XX_VMUX_TELEVISION); 336 337 dev->afe_mode = mode; 338 339 return status; 340 } 341 342 int cx231xx_afe_update_power_control(struct cx231xx *dev, 343 enum AV_MODE avmode) 344 { 345 u8 afe_power_status = 0; 346 int status = 0; 347 348 switch (dev->model) { 349 case CX231XX_BOARD_CNXT_CARRAERA: 350 case CX231XX_BOARD_CNXT_RDE_250: 351 case CX231XX_BOARD_CNXT_SHELBY: 352 case CX231XX_BOARD_CNXT_RDU_250: 353 case CX231XX_BOARD_CNXT_RDE_253S: 354 case CX231XX_BOARD_CNXT_RDU_253S: 355 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 356 case CX231XX_BOARD_HAUPPAUGE_EXETER: 357 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx: 358 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 359 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 360 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 361 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 362 case CX231XX_BOARD_OTG102: 363 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 364 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 365 FLD_PWRDN_ENABLE_PLL)) { 366 status = afe_write_byte(dev, SUP_BLK_PWRDN, 367 FLD_PWRDN_TUNING_BIAS | 368 FLD_PWRDN_ENABLE_PLL); 369 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 370 &afe_power_status); 371 if (status < 0) 372 break; 373 } 374 375 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 376 0x00); 377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 378 0x00); 379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 380 0x00); 381 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 382 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 383 0x70); 384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 385 0x70); 386 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 387 0x70); 388 389 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 390 &afe_power_status); 391 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 392 FLD_PWRDN_PD_BIAS | 393 FLD_PWRDN_PD_TUNECK; 394 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 395 afe_power_status); 396 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 397 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 398 FLD_PWRDN_ENABLE_PLL)) { 399 status = afe_write_byte(dev, SUP_BLK_PWRDN, 400 FLD_PWRDN_TUNING_BIAS | 401 FLD_PWRDN_ENABLE_PLL); 402 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 403 &afe_power_status); 404 if (status < 0) 405 break; 406 } 407 408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 409 0x00); 410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 411 0x00); 412 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 413 0x00); 414 } else { 415 dev_dbg(dev->dev, "Invalid AV mode input\n"); 416 status = -1; 417 } 418 break; 419 default: 420 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 421 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 422 FLD_PWRDN_ENABLE_PLL)) { 423 status = afe_write_byte(dev, SUP_BLK_PWRDN, 424 FLD_PWRDN_TUNING_BIAS | 425 FLD_PWRDN_ENABLE_PLL); 426 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 427 &afe_power_status); 428 if (status < 0) 429 break; 430 } 431 432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 433 0x40); 434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 435 0x40); 436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 437 0x00); 438 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 439 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 440 0x70); 441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 442 0x70); 443 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 444 0x70); 445 446 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 447 &afe_power_status); 448 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 449 FLD_PWRDN_PD_BIAS | 450 FLD_PWRDN_PD_TUNECK; 451 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 452 afe_power_status); 453 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 454 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 455 FLD_PWRDN_ENABLE_PLL)) { 456 status = afe_write_byte(dev, SUP_BLK_PWRDN, 457 FLD_PWRDN_TUNING_BIAS | 458 FLD_PWRDN_ENABLE_PLL); 459 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 460 &afe_power_status); 461 if (status < 0) 462 break; 463 } 464 465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 466 0x00); 467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 468 0x00); 469 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 470 0x40); 471 } else { 472 dev_dbg(dev->dev, "Invalid AV mode input\n"); 473 status = -1; 474 } 475 } /* switch */ 476 477 return status; 478 } 479 480 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 481 { 482 u8 input_mode = 0; 483 u8 ntf_mode = 0; 484 int status = 0; 485 486 dev->video_input = video_input; 487 488 if (video_input == CX231XX_VMUX_TELEVISION) { 489 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 490 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 491 &ntf_mode); 492 } else { 493 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 494 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 495 &ntf_mode); 496 } 497 498 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 499 500 switch (input_mode) { 501 case SINGLE_ENDED: 502 dev->afe_ref_count = 0x23C; 503 break; 504 case LOW_IF: 505 dev->afe_ref_count = 0x24C; 506 break; 507 case EU_IF: 508 dev->afe_ref_count = 0x258; 509 break; 510 case US_IF: 511 dev->afe_ref_count = 0x260; 512 break; 513 default: 514 break; 515 } 516 517 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 518 519 return status; 520 } 521 522 /****************************************************************************** 523 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 524 ******************************************************************************/ 525 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 526 { 527 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 528 saddr, 2, data, 1); 529 } 530 531 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 532 { 533 int status; 534 u32 temp = 0; 535 536 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 537 saddr, 2, &temp, 1); 538 *data = (u8) temp; 539 return status; 540 } 541 542 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 543 { 544 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 545 saddr, 2, data, 4); 546 } 547 548 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 549 { 550 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 551 saddr, 2, data, 4); 552 } 553 int cx231xx_check_fw(struct cx231xx *dev) 554 { 555 u8 temp = 0; 556 int status = 0; 557 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 558 if (status < 0) 559 return status; 560 else 561 return temp; 562 563 } 564 565 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 566 { 567 int status = 0; 568 569 switch (INPUT(input)->type) { 570 case CX231XX_VMUX_COMPOSITE1: 571 case CX231XX_VMUX_SVIDEO: 572 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 573 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 574 /* External AV */ 575 status = cx231xx_set_power_mode(dev, 576 POLARIS_AVMODE_ENXTERNAL_AV); 577 if (status < 0) { 578 dev_err(dev->dev, 579 "%s: Failed to set Power - errCode [%d]!\n", 580 __func__, status); 581 return status; 582 } 583 } 584 status = cx231xx_set_decoder_video_input(dev, 585 INPUT(input)->type, 586 INPUT(input)->vmux); 587 break; 588 case CX231XX_VMUX_TELEVISION: 589 case CX231XX_VMUX_CABLE: 590 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 591 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 592 /* Tuner */ 593 status = cx231xx_set_power_mode(dev, 594 POLARIS_AVMODE_ANALOGT_TV); 595 if (status < 0) { 596 dev_err(dev->dev, 597 "%s: Failed to set Power - errCode [%d]!\n", 598 __func__, status); 599 return status; 600 } 601 } 602 if (dev->tuner_type == TUNER_NXP_TDA18271) 603 status = cx231xx_set_decoder_video_input(dev, 604 CX231XX_VMUX_TELEVISION, 605 INPUT(input)->vmux); 606 else 607 status = cx231xx_set_decoder_video_input(dev, 608 CX231XX_VMUX_COMPOSITE1, 609 INPUT(input)->vmux); 610 611 break; 612 default: 613 dev_err(dev->dev, "%s: Unknown Input %d !\n", 614 __func__, INPUT(input)->type); 615 break; 616 } 617 618 /* save the selection */ 619 dev->video_input = input; 620 621 return status; 622 } 623 624 int cx231xx_set_decoder_video_input(struct cx231xx *dev, 625 u8 pin_type, u8 input) 626 { 627 int status = 0; 628 u32 value = 0; 629 630 if (pin_type != dev->video_input) { 631 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 632 if (status < 0) { 633 dev_err(dev->dev, 634 "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n", 635 __func__, status); 636 return status; 637 } 638 } 639 640 /* call afe block to set video inputs */ 641 status = cx231xx_afe_set_input_mux(dev, input); 642 if (status < 0) { 643 dev_err(dev->dev, 644 "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n", 645 __func__, status); 646 return status; 647 } 648 649 switch (pin_type) { 650 case CX231XX_VMUX_COMPOSITE1: 651 status = vid_blk_read_word(dev, AFE_CTRL, &value); 652 value |= (0 << 13) | (1 << 4); 653 value &= ~(1 << 5); 654 655 /* set [24:23] [22:15] to 0 */ 656 value &= (~(0x1ff8000)); 657 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 658 value |= 0x1000000; 659 status = vid_blk_write_word(dev, AFE_CTRL, value); 660 661 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 662 value |= (1 << 7); 663 status = vid_blk_write_word(dev, OUT_CTRL1, value); 664 665 /* Set output mode */ 666 status = cx231xx_read_modify_write_i2c_dword(dev, 667 VID_BLK_I2C_ADDRESS, 668 OUT_CTRL1, 669 FLD_OUT_MODE, 670 dev->board.output_mode); 671 672 /* Tell DIF object to go to baseband mode */ 673 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 674 if (status < 0) { 675 dev_err(dev->dev, 676 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 677 __func__, status); 678 return status; 679 } 680 681 /* Read the DFE_CTRL1 register */ 682 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 683 684 /* enable the VBI_GATE_EN */ 685 value |= FLD_VBI_GATE_EN; 686 687 /* Enable the auto-VGA enable */ 688 value |= FLD_VGA_AUTO_EN; 689 690 /* Write it back */ 691 status = vid_blk_write_word(dev, DFE_CTRL1, value); 692 693 /* Disable auto config of registers */ 694 status = cx231xx_read_modify_write_i2c_dword(dev, 695 VID_BLK_I2C_ADDRESS, 696 MODE_CTRL, FLD_ACFG_DIS, 697 cx231xx_set_field(FLD_ACFG_DIS, 1)); 698 699 /* Set CVBS input mode */ 700 status = cx231xx_read_modify_write_i2c_dword(dev, 701 VID_BLK_I2C_ADDRESS, 702 MODE_CTRL, FLD_INPUT_MODE, 703 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 704 break; 705 case CX231XX_VMUX_SVIDEO: 706 /* Disable the use of DIF */ 707 708 status = vid_blk_read_word(dev, AFE_CTRL, &value); 709 710 /* set [24:23] [22:15] to 0 */ 711 value &= (~(0x1ff8000)); 712 /* set FUNC_MODE[24:23] = 2 713 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 714 value |= 0x1000010; 715 status = vid_blk_write_word(dev, AFE_CTRL, value); 716 717 /* Tell DIF object to go to baseband mode */ 718 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 719 if (status < 0) { 720 dev_err(dev->dev, 721 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 722 __func__, status); 723 return status; 724 } 725 726 /* Read the DFE_CTRL1 register */ 727 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 728 729 /* enable the VBI_GATE_EN */ 730 value |= FLD_VBI_GATE_EN; 731 732 /* Enable the auto-VGA enable */ 733 value |= FLD_VGA_AUTO_EN; 734 735 /* Write it back */ 736 status = vid_blk_write_word(dev, DFE_CTRL1, value); 737 738 /* Disable auto config of registers */ 739 status = cx231xx_read_modify_write_i2c_dword(dev, 740 VID_BLK_I2C_ADDRESS, 741 MODE_CTRL, FLD_ACFG_DIS, 742 cx231xx_set_field(FLD_ACFG_DIS, 1)); 743 744 /* Set YC input mode */ 745 status = cx231xx_read_modify_write_i2c_dword(dev, 746 VID_BLK_I2C_ADDRESS, 747 MODE_CTRL, 748 FLD_INPUT_MODE, 749 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 750 751 /* Chroma to ADC2 */ 752 status = vid_blk_read_word(dev, AFE_CTRL, &value); 753 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 754 755 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 756 This sets them to use video 757 rather than audio. Only one of the two will be in use. */ 758 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 759 760 status = vid_blk_write_word(dev, AFE_CTRL, value); 761 762 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 763 break; 764 case CX231XX_VMUX_TELEVISION: 765 case CX231XX_VMUX_CABLE: 766 default: 767 /* TODO: Test if this is also needed for xc2028/xc3028 */ 768 if (dev->board.tuner_type == TUNER_XC5000) { 769 /* Disable the use of DIF */ 770 771 status = vid_blk_read_word(dev, AFE_CTRL, &value); 772 value |= (0 << 13) | (1 << 4); 773 value &= ~(1 << 5); 774 775 /* set [24:23] [22:15] to 0 */ 776 value &= (~(0x1FF8000)); 777 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 778 value |= 0x1000000; 779 status = vid_blk_write_word(dev, AFE_CTRL, value); 780 781 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 782 value |= (1 << 7); 783 status = vid_blk_write_word(dev, OUT_CTRL1, value); 784 785 /* Set output mode */ 786 status = cx231xx_read_modify_write_i2c_dword(dev, 787 VID_BLK_I2C_ADDRESS, 788 OUT_CTRL1, FLD_OUT_MODE, 789 dev->board.output_mode); 790 791 /* Tell DIF object to go to baseband mode */ 792 status = cx231xx_dif_set_standard(dev, 793 DIF_USE_BASEBAND); 794 if (status < 0) { 795 dev_err(dev->dev, 796 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 797 __func__, status); 798 return status; 799 } 800 801 /* Read the DFE_CTRL1 register */ 802 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 803 804 /* enable the VBI_GATE_EN */ 805 value |= FLD_VBI_GATE_EN; 806 807 /* Enable the auto-VGA enable */ 808 value |= FLD_VGA_AUTO_EN; 809 810 /* Write it back */ 811 status = vid_blk_write_word(dev, DFE_CTRL1, value); 812 813 /* Disable auto config of registers */ 814 status = cx231xx_read_modify_write_i2c_dword(dev, 815 VID_BLK_I2C_ADDRESS, 816 MODE_CTRL, FLD_ACFG_DIS, 817 cx231xx_set_field(FLD_ACFG_DIS, 1)); 818 819 /* Set CVBS input mode */ 820 status = cx231xx_read_modify_write_i2c_dword(dev, 821 VID_BLK_I2C_ADDRESS, 822 MODE_CTRL, FLD_INPUT_MODE, 823 cx231xx_set_field(FLD_INPUT_MODE, 824 INPUT_MODE_CVBS_0)); 825 } else { 826 /* Enable the DIF for the tuner */ 827 828 /* Reinitialize the DIF */ 829 status = cx231xx_dif_set_standard(dev, dev->norm); 830 if (status < 0) { 831 dev_err(dev->dev, 832 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 833 __func__, status); 834 return status; 835 } 836 837 /* Make sure bypass is cleared */ 838 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 839 840 /* Clear the bypass bit */ 841 value &= ~FLD_DIF_DIF_BYPASS; 842 843 /* Enable the use of the DIF block */ 844 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 845 846 /* Read the DFE_CTRL1 register */ 847 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 848 849 /* Disable the VBI_GATE_EN */ 850 value &= ~FLD_VBI_GATE_EN; 851 852 /* Enable the auto-VGA enable, AGC, and 853 set the skip count to 2 */ 854 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 855 856 /* Write it back */ 857 status = vid_blk_write_word(dev, DFE_CTRL1, value); 858 859 /* Wait until AGC locks up */ 860 msleep(1); 861 862 /* Disable the auto-VGA enable AGC */ 863 value &= ~(FLD_VGA_AUTO_EN); 864 865 /* Write it back */ 866 status = vid_blk_write_word(dev, DFE_CTRL1, value); 867 868 /* Enable Polaris B0 AGC output */ 869 status = vid_blk_read_word(dev, PIN_CTRL, &value); 870 value |= (FLD_OEF_AGC_RF) | 871 (FLD_OEF_AGC_IFVGA) | 872 (FLD_OEF_AGC_IF); 873 status = vid_blk_write_word(dev, PIN_CTRL, value); 874 875 /* Set output mode */ 876 status = cx231xx_read_modify_write_i2c_dword(dev, 877 VID_BLK_I2C_ADDRESS, 878 OUT_CTRL1, FLD_OUT_MODE, 879 dev->board.output_mode); 880 881 /* Disable auto config of registers */ 882 status = cx231xx_read_modify_write_i2c_dword(dev, 883 VID_BLK_I2C_ADDRESS, 884 MODE_CTRL, FLD_ACFG_DIS, 885 cx231xx_set_field(FLD_ACFG_DIS, 1)); 886 887 /* Set CVBS input mode */ 888 status = cx231xx_read_modify_write_i2c_dword(dev, 889 VID_BLK_I2C_ADDRESS, 890 MODE_CTRL, FLD_INPUT_MODE, 891 cx231xx_set_field(FLD_INPUT_MODE, 892 INPUT_MODE_CVBS_0)); 893 894 /* Set some bits in AFE_CTRL so that channel 2 or 3 895 * is ready to receive audio */ 896 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 897 /* Clear droop comp (bit 19-20) */ 898 /* Set VGA_SEL (for audio control) (bit 7-8) */ 899 status = vid_blk_read_word(dev, AFE_CTRL, &value); 900 901 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 902 value &= (~(FLD_FUNC_MODE)); 903 value |= 0x800000; 904 905 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 906 907 status = vid_blk_write_word(dev, AFE_CTRL, value); 908 909 if (dev->tuner_type == TUNER_NXP_TDA18271) { 910 status = vid_blk_read_word(dev, PIN_CTRL, 911 &value); 912 status = vid_blk_write_word(dev, PIN_CTRL, 913 (value & 0xFFFFFFEF)); 914 } 915 916 break; 917 918 } 919 break; 920 } 921 922 /* Set raw VBI mode */ 923 status = cx231xx_read_modify_write_i2c_dword(dev, 924 VID_BLK_I2C_ADDRESS, 925 OUT_CTRL1, FLD_VBIHACTRAW_EN, 926 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 927 928 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 929 if (value & 0x02) { 930 value |= (1 << 19); 931 status = vid_blk_write_word(dev, OUT_CTRL1, value); 932 } 933 934 return status; 935 } 936 937 void cx231xx_enable656(struct cx231xx *dev) 938 { 939 u8 temp = 0; 940 /*enable TS1 data[0:7] as output to export 656*/ 941 942 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 943 944 /*enable TS1 clock as output to export 656*/ 945 946 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 947 temp = temp|0x04; 948 949 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 950 } 951 EXPORT_SYMBOL_GPL(cx231xx_enable656); 952 953 void cx231xx_disable656(struct cx231xx *dev) 954 { 955 u8 temp = 0; 956 957 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 958 959 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 960 temp = temp&0xFB; 961 962 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 963 } 964 EXPORT_SYMBOL_GPL(cx231xx_disable656); 965 966 /* 967 * Handle any video-mode specific overrides that are different 968 * on a per video standards basis after touching the MODE_CTRL 969 * register which resets many values for autodetect 970 */ 971 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 972 { 973 int status = 0; 974 975 dev_dbg(dev->dev, "%s: 0x%x\n", 976 __func__, (unsigned int)dev->norm); 977 978 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 979 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 980 981 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 982 dev_dbg(dev->dev, "%s: NTSC\n", __func__); 983 984 /* Move the close caption lines out of active video, 985 adjust the active video start point */ 986 status = cx231xx_read_modify_write_i2c_dword(dev, 987 VID_BLK_I2C_ADDRESS, 988 VERT_TIM_CTRL, 989 FLD_VBLANK_CNT, 0x18); 990 status = cx231xx_read_modify_write_i2c_dword(dev, 991 VID_BLK_I2C_ADDRESS, 992 VERT_TIM_CTRL, 993 FLD_VACTIVE_CNT, 994 0x1E7000); 995 status = cx231xx_read_modify_write_i2c_dword(dev, 996 VID_BLK_I2C_ADDRESS, 997 VERT_TIM_CTRL, 998 FLD_V656BLANK_CNT, 999 0x1C000000); 1000 1001 status = cx231xx_read_modify_write_i2c_dword(dev, 1002 VID_BLK_I2C_ADDRESS, 1003 HORIZ_TIM_CTRL, 1004 FLD_HBLANK_CNT, 1005 cx231xx_set_field 1006 (FLD_HBLANK_CNT, 0x79)); 1007 1008 } else if (dev->norm & V4L2_STD_SECAM) { 1009 dev_dbg(dev->dev, "%s: SECAM\n", __func__); 1010 status = cx231xx_read_modify_write_i2c_dword(dev, 1011 VID_BLK_I2C_ADDRESS, 1012 VERT_TIM_CTRL, 1013 FLD_VBLANK_CNT, 0x20); 1014 status = cx231xx_read_modify_write_i2c_dword(dev, 1015 VID_BLK_I2C_ADDRESS, 1016 VERT_TIM_CTRL, 1017 FLD_VACTIVE_CNT, 1018 cx231xx_set_field 1019 (FLD_VACTIVE_CNT, 1020 0x244)); 1021 status = cx231xx_read_modify_write_i2c_dword(dev, 1022 VID_BLK_I2C_ADDRESS, 1023 VERT_TIM_CTRL, 1024 FLD_V656BLANK_CNT, 1025 cx231xx_set_field 1026 (FLD_V656BLANK_CNT, 1027 0x24)); 1028 /* Adjust the active video horizontal start point */ 1029 status = cx231xx_read_modify_write_i2c_dword(dev, 1030 VID_BLK_I2C_ADDRESS, 1031 HORIZ_TIM_CTRL, 1032 FLD_HBLANK_CNT, 1033 cx231xx_set_field 1034 (FLD_HBLANK_CNT, 0x85)); 1035 } else { 1036 dev_dbg(dev->dev, "%s: PAL\n", __func__); 1037 status = cx231xx_read_modify_write_i2c_dword(dev, 1038 VID_BLK_I2C_ADDRESS, 1039 VERT_TIM_CTRL, 1040 FLD_VBLANK_CNT, 0x20); 1041 status = cx231xx_read_modify_write_i2c_dword(dev, 1042 VID_BLK_I2C_ADDRESS, 1043 VERT_TIM_CTRL, 1044 FLD_VACTIVE_CNT, 1045 cx231xx_set_field 1046 (FLD_VACTIVE_CNT, 1047 0x244)); 1048 status = cx231xx_read_modify_write_i2c_dword(dev, 1049 VID_BLK_I2C_ADDRESS, 1050 VERT_TIM_CTRL, 1051 FLD_V656BLANK_CNT, 1052 cx231xx_set_field 1053 (FLD_V656BLANK_CNT, 1054 0x24)); 1055 /* Adjust the active video horizontal start point */ 1056 status = cx231xx_read_modify_write_i2c_dword(dev, 1057 VID_BLK_I2C_ADDRESS, 1058 HORIZ_TIM_CTRL, 1059 FLD_HBLANK_CNT, 1060 cx231xx_set_field 1061 (FLD_HBLANK_CNT, 0x85)); 1062 1063 } 1064 1065 return status; 1066 } 1067 1068 int cx231xx_unmute_audio(struct cx231xx *dev) 1069 { 1070 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1071 } 1072 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1073 1074 static int stopAudioFirmware(struct cx231xx *dev) 1075 { 1076 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1077 } 1078 1079 static int restartAudioFirmware(struct cx231xx *dev) 1080 { 1081 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1082 } 1083 1084 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1085 { 1086 int status = 0; 1087 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1088 1089 switch (INPUT(input)->amux) { 1090 case CX231XX_AMUX_VIDEO: 1091 ainput = AUDIO_INPUT_TUNER_TV; 1092 break; 1093 case CX231XX_AMUX_LINE_IN: 1094 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1095 ainput = AUDIO_INPUT_LINE; 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 status = cx231xx_set_audio_decoder_input(dev, ainput); 1102 1103 return status; 1104 } 1105 1106 int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1107 enum AUDIO_INPUT audio_input) 1108 { 1109 u32 dwval; 1110 int status; 1111 u8 gen_ctrl; 1112 u32 value = 0; 1113 1114 /* Put it in soft reset */ 1115 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1116 gen_ctrl |= 1; 1117 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1118 1119 switch (audio_input) { 1120 case AUDIO_INPUT_LINE: 1121 /* setup AUD_IO control from Merlin paralle output */ 1122 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1123 AUD_CHAN_SRC_PARALLEL); 1124 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1125 1126 /* setup input to Merlin, SRC2 connect to AC97 1127 bypass upsample-by-2, slave mode, sony mode, left justify 1128 adr 091c, dat 01000000 */ 1129 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1130 1131 status = vid_blk_write_word(dev, AC97_CTL, 1132 (dwval | FLD_AC97_UP2X_BYPASS)); 1133 1134 /* select the parallel1 and SRC3 */ 1135 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1136 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1137 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1138 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1139 1140 /* unmute all, AC97 in, independence mode 1141 adr 08d0, data 0x00063073 */ 1142 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1143 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1144 1145 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1146 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1147 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1148 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1149 1150 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1151 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1152 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1153 (dwval | FLD_PATH1_SC_THRESHOLD)); 1154 break; 1155 1156 case AUDIO_INPUT_TUNER_TV: 1157 default: 1158 status = stopAudioFirmware(dev); 1159 /* Setup SRC sources and clocks */ 1160 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1161 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1162 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1163 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1164 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1165 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1166 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1167 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1168 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1169 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1170 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1171 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1172 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1173 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1174 1175 /* Setup the AUD_IO control */ 1176 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1177 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1178 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1179 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1180 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1181 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1182 1183 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1184 1185 /* setAudioStandard(_audio_standard); */ 1186 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1187 1188 status = restartAudioFirmware(dev); 1189 1190 switch (dev->board.tuner_type) { 1191 case TUNER_XC5000: 1192 /* SIF passthrough at 28.6363 MHz sample rate */ 1193 status = cx231xx_read_modify_write_i2c_dword(dev, 1194 VID_BLK_I2C_ADDRESS, 1195 CHIP_CTRL, 1196 FLD_SIF_EN, 1197 cx231xx_set_field(FLD_SIF_EN, 1)); 1198 break; 1199 case TUNER_NXP_TDA18271: 1200 /* Normal mode: SIF passthrough at 14.32 MHz */ 1201 status = cx231xx_read_modify_write_i2c_dword(dev, 1202 VID_BLK_I2C_ADDRESS, 1203 CHIP_CTRL, 1204 FLD_SIF_EN, 1205 cx231xx_set_field(FLD_SIF_EN, 0)); 1206 break; 1207 default: 1208 /* This is just a casual suggestion to people adding 1209 new boards in case they use a tuner type we don't 1210 currently know about */ 1211 dev_info(dev->dev, 1212 "Unknown tuner type configuring SIF"); 1213 break; 1214 } 1215 break; 1216 1217 case AUDIO_INPUT_TUNER_FM: 1218 /* use SIF for FM radio 1219 setupFM(); 1220 setAudioStandard(_audio_standard); 1221 */ 1222 break; 1223 1224 case AUDIO_INPUT_MUTE: 1225 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1226 break; 1227 } 1228 1229 /* Take it out of soft reset */ 1230 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1231 gen_ctrl &= ~1; 1232 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1233 1234 return status; 1235 } 1236 1237 /****************************************************************************** 1238 * C H I P Specific C O N T R O L functions * 1239 ******************************************************************************/ 1240 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1241 { 1242 u32 value; 1243 int status = 0; 1244 1245 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1246 value |= (~dev->board.ctl_pin_status_mask); 1247 status = vid_blk_write_word(dev, PIN_CTRL, value); 1248 1249 return status; 1250 } 1251 1252 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1253 u8 analog_or_digital) 1254 { 1255 int status = 0; 1256 1257 /* first set the direction to output */ 1258 status = cx231xx_set_gpio_direction(dev, 1259 dev->board. 1260 agc_analog_digital_select_gpio, 1); 1261 1262 /* 0 - demod ; 1 - Analog mode */ 1263 status = cx231xx_set_gpio_value(dev, 1264 dev->board.agc_analog_digital_select_gpio, 1265 analog_or_digital); 1266 1267 return status; 1268 } 1269 1270 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1271 { 1272 u8 value[4] = { 0, 0, 0, 0 }; 1273 int status = 0; 1274 bool current_is_port_3; 1275 1276 /* 1277 * Should this code check dev->port_3_switch_enabled first 1278 * to skip unnecessary reading of the register? 1279 * If yes, the flag dev->port_3_switch_enabled must be initialized 1280 * correctly. 1281 */ 1282 1283 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1284 PWR_CTL_EN, value, 4); 1285 if (status < 0) 1286 return status; 1287 1288 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1289 1290 /* Just return, if already using the right port */ 1291 if (current_is_port_3 == is_port_3) 1292 return 0; 1293 1294 if (is_port_3) 1295 value[0] |= I2C_DEMOD_EN; 1296 else 1297 value[0] &= ~I2C_DEMOD_EN; 1298 1299 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1300 PWR_CTL_EN, value, 4); 1301 1302 /* remember status of the switch for usage in is_tuner */ 1303 if (status >= 0) 1304 dev->port_3_switch_enabled = is_port_3; 1305 1306 return status; 1307 1308 } 1309 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1310 1311 void update_HH_register_after_set_DIF(struct cx231xx *dev) 1312 { 1313 /* 1314 u8 status = 0; 1315 u32 value = 0; 1316 1317 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1318 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1319 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1320 1321 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1322 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1323 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1324 */ 1325 } 1326 1327 void cx231xx_dump_HH_reg(struct cx231xx *dev) 1328 { 1329 u32 value = 0; 1330 u16 i = 0; 1331 1332 value = 0x45005390; 1333 vid_blk_write_word(dev, 0x104, value); 1334 1335 for (i = 0x100; i < 0x140; i++) { 1336 vid_blk_read_word(dev, i, &value); 1337 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 1338 i = i+3; 1339 } 1340 1341 for (i = 0x300; i < 0x400; i++) { 1342 vid_blk_read_word(dev, i, &value); 1343 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 1344 i = i+3; 1345 } 1346 1347 for (i = 0x400; i < 0x440; i++) { 1348 vid_blk_read_word(dev, i, &value); 1349 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 1350 i = i+3; 1351 } 1352 1353 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1354 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1355 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1356 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1357 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1358 } 1359 1360 #if 0 1361 static void cx231xx_dump_SC_reg(struct cx231xx *dev) 1362 { 1363 u8 value[4] = { 0, 0, 0, 0 }; 1364 dev_dbg(dev->dev, "%s!\n", __func__); 1365 1366 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1367 value, 4); 1368 dev_dbg(dev->dev, 1369 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1370 value[1], value[2], value[3]); 1371 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1372 value, 4); 1373 dev_dbg(dev->dev, 1374 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1375 value[1], value[2], value[3]); 1376 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1377 value, 4); 1378 dev_dbg(dev->dev, 1379 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1380 value[1], value[2], value[3]); 1381 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1382 value, 4); 1383 dev_dbg(dev->dev, 1384 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1385 value[1], value[2], value[3]); 1386 1387 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1388 value, 4); 1389 dev_dbg(dev->dev, 1390 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1391 value[1], value[2], value[3]); 1392 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1393 value, 4); 1394 dev_dbg(dev->dev, 1395 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1396 value[1], value[2], value[3]); 1397 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1398 value, 4); 1399 dev_dbg(dev->dev, 1400 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1401 value[1], value[2], value[3]); 1402 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1403 value, 4); 1404 dev_dbg(dev->dev, 1405 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1406 value[1], value[2], value[3]); 1407 1408 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1409 value, 4); 1410 dev_dbg(dev->dev, 1411 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1412 value[1], value[2], value[3]); 1413 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1414 value, 4); 1415 dev_dbg(dev->dev, 1416 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1417 value[1], value[2], value[3]); 1418 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1419 value, 4); 1420 dev_dbg(dev->dev, 1421 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1422 value[1], value[2], value[3]); 1423 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1424 value, 4); 1425 dev_dbg(dev->dev, 1426 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1427 value[1], value[2], value[3]); 1428 1429 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1430 value, 4); 1431 dev_dbg(dev->dev, 1432 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1433 value[1], value[2], value[3]); 1434 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1435 value, 4); 1436 dev_dbg(dev->dev, 1437 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1438 value[1], value[2], value[3]); 1439 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1440 value, 4); 1441 dev_dbg(dev->dev, 1442 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1443 value[1], value[2], value[3]); 1444 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1445 value, 4); 1446 dev_dbg(dev->dev, 1447 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1448 value[1], value[2], value[3]); 1449 1450 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1451 value, 4); 1452 dev_dbg(dev->dev, 1453 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1454 value[1], value[2], value[3]); 1455 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1456 value, 4); 1457 dev_dbg(dev->dev, 1458 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1459 value[1], value[2], value[3]); 1460 } 1461 #endif 1462 1463 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1464 1465 { 1466 u8 value = 0; 1467 1468 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1469 value = (value & 0xFE)|0x01; 1470 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1471 1472 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1473 value = (value & 0xFE)|0x00; 1474 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1475 1476 1477 /* 1478 config colibri to lo-if mode 1479 1480 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1481 the diff IF input by half, 1482 1483 for low-if agc defect 1484 */ 1485 1486 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1487 value = (value & 0xFC)|0x00; 1488 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1489 1490 afe_read_byte(dev, ADC_INPUT_CH3, &value); 1491 value = (value & 0xF9)|0x02; 1492 afe_write_byte(dev, ADC_INPUT_CH3, value); 1493 1494 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1495 value = (value & 0xFB)|0x04; 1496 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1497 1498 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1499 value = (value & 0xFC)|0x03; 1500 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1501 1502 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1503 value = (value & 0xFB)|0x04; 1504 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1505 1506 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1507 value = (value & 0xF8)|0x06; 1508 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1509 1510 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1511 value = (value & 0x8F)|0x40; 1512 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1513 1514 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1515 value = (value & 0xDF)|0x20; 1516 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1517 } 1518 1519 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1520 u8 spectral_invert, u32 mode) 1521 { 1522 u32 colibri_carrier_offset = 0; 1523 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1524 u32 standard = 0; 1525 u8 value[4] = { 0, 0, 0, 0 }; 1526 1527 dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n"); 1528 value[0] = (u8) 0x6F; 1529 value[1] = (u8) 0x6F; 1530 value[2] = (u8) 0x6F; 1531 value[3] = (u8) 0x6F; 1532 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1533 PWR_CTL_EN, value, 4); 1534 1535 /*Set colibri for low IF*/ 1536 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1537 1538 /* Set C2HH for low IF operation.*/ 1539 standard = dev->norm; 1540 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1541 func_mode, standard); 1542 1543 /* Get colibri offsets.*/ 1544 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1545 standard); 1546 1547 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n", 1548 colibri_carrier_offset, standard); 1549 1550 /* Set the band Pass filter for DIF*/ 1551 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1552 spectral_invert, mode); 1553 } 1554 1555 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1556 { 1557 u32 colibri_carrier_offset = 0; 1558 1559 if (mode == TUNER_MODE_FM_RADIO) { 1560 colibri_carrier_offset = 1100000; 1561 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1562 colibri_carrier_offset = 4832000; /*4.83MHz */ 1563 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1564 colibri_carrier_offset = 2700000; /*2.70MHz */ 1565 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1566 | V4L2_STD_SECAM)) { 1567 colibri_carrier_offset = 2100000; /*2.10MHz */ 1568 } 1569 1570 return colibri_carrier_offset; 1571 } 1572 1573 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1574 u8 spectral_invert, u32 mode) 1575 { 1576 unsigned long pll_freq_word; 1577 u32 dif_misc_ctrl_value = 0; 1578 u64 pll_freq_u64 = 0; 1579 u32 i = 0; 1580 1581 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1582 if_freq, spectral_invert, mode); 1583 1584 1585 if (mode == TUNER_MODE_FM_RADIO) { 1586 pll_freq_word = 0x905A1CAC; 1587 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1588 1589 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1590 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1591 pll_freq_word = if_freq; 1592 pll_freq_u64 = (u64)pll_freq_word << 28L; 1593 do_div(pll_freq_u64, 50000000); 1594 pll_freq_word = (u32)pll_freq_u64; 1595 /*pll_freq_word = 0x3463497;*/ 1596 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1597 1598 if (spectral_invert) { 1599 if_freq -= 400000; 1600 /* Enable Spectral Invert*/ 1601 vid_blk_read_word(dev, DIF_MISC_CTRL, 1602 &dif_misc_ctrl_value); 1603 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1604 vid_blk_write_word(dev, DIF_MISC_CTRL, 1605 dif_misc_ctrl_value); 1606 } else { 1607 if_freq += 400000; 1608 /* Disable Spectral Invert*/ 1609 vid_blk_read_word(dev, DIF_MISC_CTRL, 1610 &dif_misc_ctrl_value); 1611 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1612 vid_blk_write_word(dev, DIF_MISC_CTRL, 1613 dif_misc_ctrl_value); 1614 } 1615 1616 if_freq = (if_freq / 100000) * 100000; 1617 1618 if (if_freq < 3000000) 1619 if_freq = 3000000; 1620 1621 if (if_freq > 16000000) 1622 if_freq = 16000000; 1623 } 1624 1625 dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array)); 1626 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 1627 if (Dif_set_array[i].if_freq == if_freq) { 1628 vid_blk_write_word(dev, 1629 Dif_set_array[i].register_address, Dif_set_array[i].value); 1630 } 1631 } 1632 } 1633 1634 /****************************************************************************** 1635 * D I F - B L O C K C O N T R O L functions * 1636 ******************************************************************************/ 1637 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1638 u32 function_mode, u32 standard) 1639 { 1640 int status = 0; 1641 1642 1643 if (mode == V4L2_TUNER_RADIO) { 1644 /* C2HH */ 1645 /* lo if big signal */ 1646 status = cx231xx_reg_mask_write(dev, 1647 VID_BLK_I2C_ADDRESS, 32, 1648 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1649 /* FUNC_MODE = DIF */ 1650 status = cx231xx_reg_mask_write(dev, 1651 VID_BLK_I2C_ADDRESS, 32, 1652 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1653 /* IF_MODE */ 1654 status = cx231xx_reg_mask_write(dev, 1655 VID_BLK_I2C_ADDRESS, 32, 1656 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1657 /* no inv */ 1658 status = cx231xx_reg_mask_write(dev, 1659 VID_BLK_I2C_ADDRESS, 32, 1660 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1661 } else if (standard != DIF_USE_BASEBAND) { 1662 if (standard & V4L2_STD_MN) { 1663 /* lo if big signal */ 1664 status = cx231xx_reg_mask_write(dev, 1665 VID_BLK_I2C_ADDRESS, 32, 1666 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1667 /* FUNC_MODE = DIF */ 1668 status = cx231xx_reg_mask_write(dev, 1669 VID_BLK_I2C_ADDRESS, 32, 1670 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1671 function_mode); 1672 /* IF_MODE */ 1673 status = cx231xx_reg_mask_write(dev, 1674 VID_BLK_I2C_ADDRESS, 32, 1675 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1676 /* no inv */ 1677 status = cx231xx_reg_mask_write(dev, 1678 VID_BLK_I2C_ADDRESS, 32, 1679 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1680 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1681 status = cx231xx_reg_mask_write(dev, 1682 VID_BLK_I2C_ADDRESS, 32, 1683 AUD_IO_CTRL, 0, 31, 0x00000003); 1684 } else if ((standard == V4L2_STD_PAL_I) | 1685 (standard & V4L2_STD_PAL_D) | 1686 (standard & V4L2_STD_SECAM)) { 1687 /* C2HH setup */ 1688 /* lo if big signal */ 1689 status = cx231xx_reg_mask_write(dev, 1690 VID_BLK_I2C_ADDRESS, 32, 1691 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1692 /* FUNC_MODE = DIF */ 1693 status = cx231xx_reg_mask_write(dev, 1694 VID_BLK_I2C_ADDRESS, 32, 1695 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1696 function_mode); 1697 /* IF_MODE */ 1698 status = cx231xx_reg_mask_write(dev, 1699 VID_BLK_I2C_ADDRESS, 32, 1700 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1701 /* no inv */ 1702 status = cx231xx_reg_mask_write(dev, 1703 VID_BLK_I2C_ADDRESS, 32, 1704 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1705 } else { 1706 /* default PAL BG */ 1707 /* C2HH setup */ 1708 /* lo if big signal */ 1709 status = cx231xx_reg_mask_write(dev, 1710 VID_BLK_I2C_ADDRESS, 32, 1711 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1712 /* FUNC_MODE = DIF */ 1713 status = cx231xx_reg_mask_write(dev, 1714 VID_BLK_I2C_ADDRESS, 32, 1715 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1716 function_mode); 1717 /* IF_MODE */ 1718 status = cx231xx_reg_mask_write(dev, 1719 VID_BLK_I2C_ADDRESS, 32, 1720 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1721 /* no inv */ 1722 status = cx231xx_reg_mask_write(dev, 1723 VID_BLK_I2C_ADDRESS, 32, 1724 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1725 } 1726 } 1727 1728 return status; 1729 } 1730 1731 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1732 { 1733 int status = 0; 1734 u32 dif_misc_ctrl_value = 0; 1735 u32 func_mode = 0; 1736 1737 dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard); 1738 1739 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1740 if (standard != DIF_USE_BASEBAND) 1741 dev->norm = standard; 1742 1743 switch (dev->model) { 1744 case CX231XX_BOARD_CNXT_CARRAERA: 1745 case CX231XX_BOARD_CNXT_RDE_250: 1746 case CX231XX_BOARD_CNXT_SHELBY: 1747 case CX231XX_BOARD_CNXT_RDU_250: 1748 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1749 case CX231XX_BOARD_HAUPPAUGE_EXETER: 1750 case CX231XX_BOARD_OTG102: 1751 func_mode = 0x03; 1752 break; 1753 case CX231XX_BOARD_CNXT_RDE_253S: 1754 case CX231XX_BOARD_CNXT_RDU_253S: 1755 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 1756 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 1757 func_mode = 0x01; 1758 break; 1759 default: 1760 func_mode = 0x01; 1761 } 1762 1763 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1764 func_mode, standard); 1765 1766 if (standard == DIF_USE_BASEBAND) { /* base band */ 1767 /* There is a different SRC_PHASE_INC value 1768 for baseband vs. DIF */ 1769 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1770 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1771 &dif_misc_ctrl_value); 1772 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1773 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1774 dif_misc_ctrl_value); 1775 } else if (standard & V4L2_STD_PAL_D) { 1776 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1777 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1779 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1780 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1781 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1782 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1783 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1784 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1785 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1787 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1788 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1789 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1790 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1791 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1792 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1793 DIF_AGC_IF_INT_CURRENT, 0, 31, 1794 0x26001700); 1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1796 DIF_AGC_RF_CURRENT, 0, 31, 1797 0x00002660); 1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1799 DIF_VIDEO_AGC_CTRL, 0, 31, 1800 0x72500800); 1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1802 DIF_VID_AUD_OVERRIDE, 0, 31, 1803 0x27000100); 1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1805 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1807 DIF_COMP_FLT_CTRL, 0, 31, 1808 0x00000000); 1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1810 DIF_SRC_PHASE_INC, 0, 31, 1811 0x1befbf06); 1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1813 DIF_SRC_GAIN_CONTROL, 0, 31, 1814 0x000035e8); 1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1816 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1817 /* Save the Spec Inversion value */ 1818 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1819 dif_misc_ctrl_value |= 0x3a023F11; 1820 } else if (standard & V4L2_STD_PAL_I) { 1821 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1822 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1824 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1825 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1826 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1827 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1828 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1829 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1830 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1832 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1833 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1834 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1835 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1836 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1837 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1838 DIF_AGC_IF_INT_CURRENT, 0, 31, 1839 0x26001700); 1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1841 DIF_AGC_RF_CURRENT, 0, 31, 1842 0x00002660); 1843 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1844 DIF_VIDEO_AGC_CTRL, 0, 31, 1845 0x72500800); 1846 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1847 DIF_VID_AUD_OVERRIDE, 0, 31, 1848 0x27000100); 1849 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1850 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1851 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1852 DIF_COMP_FLT_CTRL, 0, 31, 1853 0x00000000); 1854 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1855 DIF_SRC_PHASE_INC, 0, 31, 1856 0x1befbf06); 1857 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1858 DIF_SRC_GAIN_CONTROL, 0, 31, 1859 0x000035e8); 1860 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1861 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1862 /* Save the Spec Inversion value */ 1863 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1864 dif_misc_ctrl_value |= 0x3a033F11; 1865 } else if (standard & V4L2_STD_PAL_M) { 1866 /* improved Low Frequency Phase Noise */ 1867 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1871 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1872 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1873 0x26001700); 1874 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1875 0x00002660); 1876 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1877 0x72500800); 1878 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1879 0x27000100); 1880 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1881 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1882 0x009f50c1); 1883 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1884 0x1befbf06); 1885 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1886 0x000035e8); 1887 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1888 0x00000000); 1889 /* Save the Spec Inversion value */ 1890 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1891 dif_misc_ctrl_value |= 0x3A0A3F10; 1892 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1893 /* improved Low Frequency Phase Noise */ 1894 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1895 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1896 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1897 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1898 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1899 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1900 0x26001700); 1901 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1902 0x00002660); 1903 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1904 0x72500800); 1905 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1906 0x27000100); 1907 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1908 0x012c405d); 1909 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1910 0x009f50c1); 1911 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1912 0x1befbf06); 1913 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1914 0x000035e8); 1915 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1916 0x00000000); 1917 /* Save the Spec Inversion value */ 1918 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1919 dif_misc_ctrl_value = 0x3A093F10; 1920 } else if (standard & 1921 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1922 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1923 1924 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1925 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1926 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1927 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1928 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1929 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1930 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1931 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1933 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1935 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1936 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1937 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1938 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1939 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1940 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1941 DIF_AGC_IF_INT_CURRENT, 0, 31, 1942 0x26001700); 1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1944 DIF_AGC_RF_CURRENT, 0, 31, 1945 0x00002660); 1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1947 DIF_VID_AUD_OVERRIDE, 0, 31, 1948 0x27000100); 1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1950 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1952 DIF_COMP_FLT_CTRL, 0, 31, 1953 0x00000000); 1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1955 DIF_SRC_PHASE_INC, 0, 31, 1956 0x1befbf06); 1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1958 DIF_SRC_GAIN_CONTROL, 0, 31, 1959 0x000035e8); 1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1961 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1963 DIF_VIDEO_AGC_CTRL, 0, 31, 1964 0xf4000000); 1965 1966 /* Save the Spec Inversion value */ 1967 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1968 dif_misc_ctrl_value |= 0x3a023F11; 1969 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1970 /* Is it SECAM_L1? */ 1971 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1972 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1973 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1974 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1975 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1976 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1977 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1978 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1980 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1982 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1983 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1984 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1985 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1986 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1987 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1988 DIF_AGC_IF_INT_CURRENT, 0, 31, 1989 0x26001700); 1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1991 DIF_AGC_RF_CURRENT, 0, 31, 1992 0x00002660); 1993 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1994 DIF_VID_AUD_OVERRIDE, 0, 31, 1995 0x27000100); 1996 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1997 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1998 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1999 DIF_COMP_FLT_CTRL, 0, 31, 2000 0x00000000); 2001 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2002 DIF_SRC_PHASE_INC, 0, 31, 2003 0x1befbf06); 2004 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2005 DIF_SRC_GAIN_CONTROL, 0, 31, 2006 0x000035e8); 2007 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2008 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2009 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2010 DIF_VIDEO_AGC_CTRL, 0, 31, 2011 0xf2560000); 2012 2013 /* Save the Spec Inversion value */ 2014 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2015 dif_misc_ctrl_value |= 0x3a023F11; 2016 2017 } else if (standard & V4L2_STD_NTSC_M) { 2018 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 2019 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 2020 2021 /* For NTSC the centre frequency of video coming out of 2022 sidewinder is around 7.1MHz or 3.6MHz depending on the 2023 spectral inversion. so for a non spectrally inverted channel 2024 the pll freq word is 0x03420c49 2025 */ 2026 2027 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 2028 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 2029 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 2030 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 2031 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 2032 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 2033 0x26001700); 2034 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 2035 0x00002660); 2036 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 2037 0x04000800); 2038 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 2039 0x27000100); 2040 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 2041 2042 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 2043 0x009f50c1); 2044 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 2045 0x1befbf06); 2046 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 2047 0x000035e8); 2048 2049 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 2050 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 2051 0xC2262600); 2052 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 2053 2054 /* Save the Spec Inversion value */ 2055 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2056 dif_misc_ctrl_value |= 0x3a003F10; 2057 } else { 2058 /* default PAL BG */ 2059 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2060 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2062 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 2063 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2064 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 2065 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2066 DIF_PLL_CTRL3, 0, 31, 0x00008800); 2067 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2068 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2070 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 2071 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2072 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 2073 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2074 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 2075 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2076 DIF_AGC_IF_INT_CURRENT, 0, 31, 2077 0x26001700); 2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2079 DIF_AGC_RF_CURRENT, 0, 31, 2080 0x00002660); 2081 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2082 DIF_VIDEO_AGC_CTRL, 0, 31, 2083 0x72500800); 2084 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2085 DIF_VID_AUD_OVERRIDE, 0, 31, 2086 0x27000100); 2087 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2088 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 2089 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2090 DIF_COMP_FLT_CTRL, 0, 31, 2091 0x00A653A8); 2092 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2093 DIF_SRC_PHASE_INC, 0, 31, 2094 0x1befbf06); 2095 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2096 DIF_SRC_GAIN_CONTROL, 0, 31, 2097 0x000035e8); 2098 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2099 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2100 /* Save the Spec Inversion value */ 2101 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2102 dif_misc_ctrl_value |= 0x3a013F11; 2103 } 2104 2105 /* The AGC values should be the same for all standards, 2106 AUD_SRC_SEL[19] should always be disabled */ 2107 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 2108 2109 /* It is still possible to get Set Standard calls even when we 2110 are in FM mode. 2111 This is done to override the value for FM. */ 2112 if (dev->active_mode == V4L2_TUNER_RADIO) 2113 dif_misc_ctrl_value = 0x7a080000; 2114 2115 /* Write the calculated value for misc ontrol register */ 2116 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 2117 2118 return status; 2119 } 2120 2121 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 2122 { 2123 int status = 0; 2124 u32 dwval; 2125 2126 /* Set the RF and IF k_agc values to 3 */ 2127 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2128 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2129 dwval |= 0x33000000; 2130 2131 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2132 2133 return status; 2134 } 2135 2136 int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 2137 { 2138 int status = 0; 2139 u32 dwval; 2140 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n", 2141 __func__, dev->tuner_type); 2142 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2143 * SECAM L/B/D standards */ 2144 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2145 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2146 2147 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2148 V4L2_STD_SECAM_D)) { 2149 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2150 dwval &= ~FLD_DIF_IF_REF; 2151 dwval |= 0x88000300; 2152 } else 2153 dwval |= 0x88000000; 2154 } else { 2155 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2156 dwval &= ~FLD_DIF_IF_REF; 2157 dwval |= 0xCC000300; 2158 } else 2159 dwval |= 0x44000000; 2160 } 2161 2162 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2163 2164 return status == sizeof(dwval) ? 0 : -EIO; 2165 } 2166 2167 /****************************************************************************** 2168 * I 2 S - B L O C K C O N T R O L functions * 2169 ******************************************************************************/ 2170 int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 2171 { 2172 int status = 0; 2173 u32 value; 2174 2175 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2176 CH_PWR_CTRL1, 1, &value, 1); 2177 /* enables clock to delta-sigma and decimation filter */ 2178 value |= 0x80; 2179 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2180 CH_PWR_CTRL1, 1, value, 1); 2181 /* power up all channel */ 2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2183 CH_PWR_CTRL2, 1, 0x00, 1); 2184 2185 return status; 2186 } 2187 2188 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 2189 enum AV_MODE avmode) 2190 { 2191 int status = 0; 2192 u32 value = 0; 2193 2194 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 2195 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2196 CH_PWR_CTRL2, 1, &value, 1); 2197 value |= 0xfe; 2198 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2199 CH_PWR_CTRL2, 1, value, 1); 2200 } else { 2201 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2202 CH_PWR_CTRL2, 1, 0x00, 1); 2203 } 2204 2205 return status; 2206 } 2207 2208 /* set i2s_blk for audio input types */ 2209 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 2210 { 2211 int status = 0; 2212 2213 switch (audio_input) { 2214 case CX231XX_AMUX_LINE_IN: 2215 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2216 CH_PWR_CTRL2, 1, 0x00, 1); 2217 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2218 CH_PWR_CTRL1, 1, 0x80, 1); 2219 break; 2220 case CX231XX_AMUX_VIDEO: 2221 default: 2222 break; 2223 } 2224 2225 dev->ctl_ainput = audio_input; 2226 2227 return status; 2228 } 2229 2230 /****************************************************************************** 2231 * P O W E R C O N T R O L functions * 2232 ******************************************************************************/ 2233 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 2234 { 2235 u8 value[4] = { 0, 0, 0, 0 }; 2236 u32 tmp = 0; 2237 int status = 0; 2238 2239 if (dev->power_mode != mode) 2240 dev->power_mode = mode; 2241 else { 2242 dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n", 2243 __func__, mode); 2244 return 0; 2245 } 2246 2247 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2248 4); 2249 if (status < 0) 2250 return status; 2251 2252 tmp = le32_to_cpu(*((__le32 *) value)); 2253 2254 switch (mode) { 2255 case POLARIS_AVMODE_ENXTERNAL_AV: 2256 2257 tmp &= (~PWR_MODE_MASK); 2258 2259 tmp |= PWR_AV_EN; 2260 value[0] = (u8) tmp; 2261 value[1] = (u8) (tmp >> 8); 2262 value[2] = (u8) (tmp >> 16); 2263 value[3] = (u8) (tmp >> 24); 2264 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2265 PWR_CTL_EN, value, 4); 2266 msleep(PWR_SLEEP_INTERVAL); 2267 2268 tmp |= PWR_ISO_EN; 2269 value[0] = (u8) tmp; 2270 value[1] = (u8) (tmp >> 8); 2271 value[2] = (u8) (tmp >> 16); 2272 value[3] = (u8) (tmp >> 24); 2273 status = 2274 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2275 value, 4); 2276 msleep(PWR_SLEEP_INTERVAL); 2277 2278 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 2279 value[0] = (u8) tmp; 2280 value[1] = (u8) (tmp >> 8); 2281 value[2] = (u8) (tmp >> 16); 2282 value[3] = (u8) (tmp >> 24); 2283 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2284 PWR_CTL_EN, value, 4); 2285 2286 /* reset state of xceive tuner */ 2287 dev->xc_fw_load_done = 0; 2288 break; 2289 2290 case POLARIS_AVMODE_ANALOGT_TV: 2291 2292 tmp |= PWR_DEMOD_EN; 2293 value[0] = (u8) tmp; 2294 value[1] = (u8) (tmp >> 8); 2295 value[2] = (u8) (tmp >> 16); 2296 value[3] = (u8) (tmp >> 24); 2297 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2298 PWR_CTL_EN, value, 4); 2299 msleep(PWR_SLEEP_INTERVAL); 2300 2301 if (!(tmp & PWR_TUNER_EN)) { 2302 tmp |= (PWR_TUNER_EN); 2303 value[0] = (u8) tmp; 2304 value[1] = (u8) (tmp >> 8); 2305 value[2] = (u8) (tmp >> 16); 2306 value[3] = (u8) (tmp >> 24); 2307 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2308 PWR_CTL_EN, value, 4); 2309 msleep(PWR_SLEEP_INTERVAL); 2310 } 2311 2312 if (!(tmp & PWR_AV_EN)) { 2313 tmp |= PWR_AV_EN; 2314 value[0] = (u8) tmp; 2315 value[1] = (u8) (tmp >> 8); 2316 value[2] = (u8) (tmp >> 16); 2317 value[3] = (u8) (tmp >> 24); 2318 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2319 PWR_CTL_EN, value, 4); 2320 msleep(PWR_SLEEP_INTERVAL); 2321 } 2322 if (!(tmp & PWR_ISO_EN)) { 2323 tmp |= PWR_ISO_EN; 2324 value[0] = (u8) tmp; 2325 value[1] = (u8) (tmp >> 8); 2326 value[2] = (u8) (tmp >> 16); 2327 value[3] = (u8) (tmp >> 24); 2328 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2329 PWR_CTL_EN, value, 4); 2330 msleep(PWR_SLEEP_INTERVAL); 2331 } 2332 2333 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 2334 tmp |= POLARIS_AVMODE_ANALOGT_TV; 2335 value[0] = (u8) tmp; 2336 value[1] = (u8) (tmp >> 8); 2337 value[2] = (u8) (tmp >> 16); 2338 value[3] = (u8) (tmp >> 24); 2339 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2340 PWR_CTL_EN, value, 4); 2341 msleep(PWR_SLEEP_INTERVAL); 2342 } 2343 2344 if (dev->board.tuner_type != TUNER_ABSENT) { 2345 /* reset the Tuner */ 2346 if (dev->board.tuner_gpio) 2347 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2348 2349 if (dev->cx231xx_reset_analog_tuner) 2350 dev->cx231xx_reset_analog_tuner(dev); 2351 } 2352 2353 break; 2354 2355 case POLARIS_AVMODE_DIGITAL: 2356 if (!(tmp & PWR_TUNER_EN)) { 2357 tmp |= (PWR_TUNER_EN); 2358 value[0] = (u8) tmp; 2359 value[1] = (u8) (tmp >> 8); 2360 value[2] = (u8) (tmp >> 16); 2361 value[3] = (u8) (tmp >> 24); 2362 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2363 PWR_CTL_EN, value, 4); 2364 msleep(PWR_SLEEP_INTERVAL); 2365 } 2366 if (!(tmp & PWR_AV_EN)) { 2367 tmp |= PWR_AV_EN; 2368 value[0] = (u8) tmp; 2369 value[1] = (u8) (tmp >> 8); 2370 value[2] = (u8) (tmp >> 16); 2371 value[3] = (u8) (tmp >> 24); 2372 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2373 PWR_CTL_EN, value, 4); 2374 msleep(PWR_SLEEP_INTERVAL); 2375 } 2376 if (!(tmp & PWR_ISO_EN)) { 2377 tmp |= PWR_ISO_EN; 2378 value[0] = (u8) tmp; 2379 value[1] = (u8) (tmp >> 8); 2380 value[2] = (u8) (tmp >> 16); 2381 value[3] = (u8) (tmp >> 24); 2382 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2383 PWR_CTL_EN, value, 4); 2384 msleep(PWR_SLEEP_INTERVAL); 2385 } 2386 2387 tmp &= (~PWR_AV_MODE); 2388 tmp |= POLARIS_AVMODE_DIGITAL; 2389 value[0] = (u8) tmp; 2390 value[1] = (u8) (tmp >> 8); 2391 value[2] = (u8) (tmp >> 16); 2392 value[3] = (u8) (tmp >> 24); 2393 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2394 PWR_CTL_EN, value, 4); 2395 msleep(PWR_SLEEP_INTERVAL); 2396 2397 if (!(tmp & PWR_DEMOD_EN)) { 2398 tmp |= PWR_DEMOD_EN; 2399 value[0] = (u8) tmp; 2400 value[1] = (u8) (tmp >> 8); 2401 value[2] = (u8) (tmp >> 16); 2402 value[3] = (u8) (tmp >> 24); 2403 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2404 PWR_CTL_EN, value, 4); 2405 msleep(PWR_SLEEP_INTERVAL); 2406 } 2407 2408 if (dev->board.tuner_type != TUNER_ABSENT) { 2409 /* reset the Tuner */ 2410 if (dev->board.tuner_gpio) 2411 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2412 2413 if (dev->cx231xx_reset_analog_tuner) 2414 dev->cx231xx_reset_analog_tuner(dev); 2415 } 2416 break; 2417 2418 default: 2419 break; 2420 } 2421 2422 msleep(PWR_SLEEP_INTERVAL); 2423 2424 /* For power saving, only enable Pwr_resetout_n 2425 when digital TV is selected. */ 2426 if (mode == POLARIS_AVMODE_DIGITAL) { 2427 tmp |= PWR_RESETOUT_EN; 2428 value[0] = (u8) tmp; 2429 value[1] = (u8) (tmp >> 8); 2430 value[2] = (u8) (tmp >> 16); 2431 value[3] = (u8) (tmp >> 24); 2432 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2433 PWR_CTL_EN, value, 4); 2434 msleep(PWR_SLEEP_INTERVAL); 2435 } 2436 2437 /* update power control for afe */ 2438 status = cx231xx_afe_update_power_control(dev, mode); 2439 2440 /* update power control for i2s_blk */ 2441 status = cx231xx_i2s_blk_update_power_control(dev, mode); 2442 2443 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2444 4); 2445 2446 return status; 2447 } 2448 2449 int cx231xx_power_suspend(struct cx231xx *dev) 2450 { 2451 u8 value[4] = { 0, 0, 0, 0 }; 2452 u32 tmp = 0; 2453 int status = 0; 2454 2455 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 2456 value, 4); 2457 if (status > 0) 2458 return status; 2459 2460 tmp = le32_to_cpu(*((__le32 *) value)); 2461 tmp &= (~PWR_MODE_MASK); 2462 2463 value[0] = (u8) tmp; 2464 value[1] = (u8) (tmp >> 8); 2465 value[2] = (u8) (tmp >> 16); 2466 value[3] = (u8) (tmp >> 24); 2467 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2468 value, 4); 2469 2470 return status; 2471 } 2472 2473 /****************************************************************************** 2474 * S T R E A M C O N T R O L functions * 2475 ******************************************************************************/ 2476 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2477 { 2478 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2479 u32 tmp = 0; 2480 int status = 0; 2481 2482 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 2483 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 2484 value, 4); 2485 if (status < 0) 2486 return status; 2487 2488 tmp = le32_to_cpu(*((__le32 *) value)); 2489 tmp |= ep_mask; 2490 value[0] = (u8) tmp; 2491 value[1] = (u8) (tmp >> 8); 2492 value[2] = (u8) (tmp >> 16); 2493 value[3] = (u8) (tmp >> 24); 2494 2495 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2496 value, 4); 2497 2498 return status; 2499 } 2500 2501 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 2502 { 2503 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2504 u32 tmp = 0; 2505 int status = 0; 2506 2507 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 2508 status = 2509 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2510 if (status < 0) 2511 return status; 2512 2513 tmp = le32_to_cpu(*((__le32 *) value)); 2514 tmp &= (~ep_mask); 2515 value[0] = (u8) tmp; 2516 value[1] = (u8) (tmp >> 8); 2517 value[2] = (u8) (tmp >> 16); 2518 value[3] = (u8) (tmp >> 24); 2519 2520 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2521 value, 4); 2522 2523 return status; 2524 } 2525 2526 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2527 { 2528 int status = 0; 2529 u32 value = 0; 2530 u8 val[4] = { 0, 0, 0, 0 }; 2531 2532 if (dev->udev->speed == USB_SPEED_HIGH) { 2533 switch (media_type) { 2534 case Audio: 2535 dev_dbg(dev->dev, 2536 "%s: Audio enter HANC\n", __func__); 2537 status = 2538 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2539 break; 2540 2541 case Vbi: 2542 dev_dbg(dev->dev, 2543 "%s: set vanc registers\n", __func__); 2544 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2545 break; 2546 2547 case Sliced_cc: 2548 dev_dbg(dev->dev, 2549 "%s: set hanc registers\n", __func__); 2550 status = 2551 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2552 break; 2553 2554 case Raw_Video: 2555 dev_dbg(dev->dev, 2556 "%s: set video registers\n", __func__); 2557 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2558 break; 2559 2560 case TS1_serial_mode: 2561 dev_dbg(dev->dev, 2562 "%s: set ts1 registers", __func__); 2563 2564 if (dev->board.has_417) { 2565 dev_dbg(dev->dev, 2566 "%s: MPEG\n", __func__); 2567 value &= 0xFFFFFFFC; 2568 value |= 0x3; 2569 2570 status = cx231xx_mode_register(dev, 2571 TS_MODE_REG, value); 2572 2573 val[0] = 0x04; 2574 val[1] = 0xA3; 2575 val[2] = 0x3B; 2576 val[3] = 0x00; 2577 status = cx231xx_write_ctrl_reg(dev, 2578 VRT_SET_REGISTER, 2579 TS1_CFG_REG, val, 4); 2580 2581 val[0] = 0x00; 2582 val[1] = 0x08; 2583 val[2] = 0x00; 2584 val[3] = 0x08; 2585 status = cx231xx_write_ctrl_reg(dev, 2586 VRT_SET_REGISTER, 2587 TS1_LENGTH_REG, val, 4); 2588 } else { 2589 dev_dbg(dev->dev, "%s: BDA\n", __func__); 2590 status = cx231xx_mode_register(dev, 2591 TS_MODE_REG, 0x101); 2592 status = cx231xx_mode_register(dev, 2593 TS1_CFG_REG, 0x010); 2594 } 2595 break; 2596 2597 case TS1_parallel_mode: 2598 dev_dbg(dev->dev, 2599 "%s: set ts1 parallel mode registers\n", 2600 __func__); 2601 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2602 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2603 break; 2604 } 2605 } else { 2606 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2607 } 2608 2609 return status; 2610 } 2611 2612 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2613 { 2614 int rc = -1; 2615 u32 ep_mask = -1; 2616 struct pcb_config *pcb_config; 2617 2618 /* get EP for media type */ 2619 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2620 2621 if (pcb_config->config_num) { 2622 switch (media_type) { 2623 case Raw_Video: 2624 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2625 break; 2626 case Audio: 2627 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2628 break; 2629 case Vbi: 2630 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2631 break; 2632 case Sliced_cc: 2633 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2634 break; 2635 case TS1_serial_mode: 2636 case TS1_parallel_mode: 2637 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2638 break; 2639 case TS2: 2640 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2641 break; 2642 } 2643 } 2644 2645 if (start) { 2646 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2647 2648 if (rc < 0) 2649 return rc; 2650 2651 /* enable video capture */ 2652 if (ep_mask > 0) 2653 rc = cx231xx_start_stream(dev, ep_mask); 2654 } else { 2655 /* disable video capture */ 2656 if (ep_mask > 0) 2657 rc = cx231xx_stop_stream(dev, ep_mask); 2658 } 2659 2660 return rc; 2661 } 2662 EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2663 2664 /***************************************************************************** 2665 * G P I O B I T control functions * 2666 ******************************************************************************/ 2667 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val) 2668 { 2669 int status = 0; 2670 2671 gpio_val = (__force u32)cpu_to_le32(gpio_val); 2672 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); 2673 2674 return status; 2675 } 2676 2677 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val) 2678 { 2679 __le32 tmp; 2680 int status = 0; 2681 2682 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); 2683 *gpio_val = le32_to_cpu(tmp); 2684 2685 return status; 2686 } 2687 2688 /* 2689 * cx231xx_set_gpio_direction 2690 * Sets the direction of the GPIO pin to input or output 2691 * 2692 * Parameters : 2693 * pin_number : The GPIO Pin number to program the direction for 2694 * from 0 to 31 2695 * pin_value : The Direction of the GPIO Pin under reference. 2696 * 0 = Input direction 2697 * 1 = Output direction 2698 */ 2699 int cx231xx_set_gpio_direction(struct cx231xx *dev, 2700 int pin_number, int pin_value) 2701 { 2702 int status = 0; 2703 u32 value = 0; 2704 2705 /* Check for valid pin_number - if 32 , bail out */ 2706 if (pin_number >= 32) 2707 return -EINVAL; 2708 2709 /* input */ 2710 if (pin_value == 0) 2711 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2712 else 2713 value = dev->gpio_dir | (1 << pin_number); 2714 2715 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val); 2716 2717 /* cache the value for future */ 2718 dev->gpio_dir = value; 2719 2720 return status; 2721 } 2722 2723 /* 2724 * cx231xx_set_gpio_value 2725 * Sets the value of the GPIO pin to Logic high or low. The Pin under 2726 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2727 * 2728 * Parameters : 2729 * pin_number : The GPIO Pin number to program the direction for 2730 * pin_value : The value of the GPIO Pin under reference. 2731 * 0 = set it to 0 2732 * 1 = set it to 1 2733 */ 2734 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2735 { 2736 int status = 0; 2737 u32 value = 0; 2738 2739 /* Check for valid pin_number - if 0xFF , bail out */ 2740 if (pin_number >= 32) 2741 return -EINVAL; 2742 2743 /* first do a sanity check - if the Pin is not output, make it output */ 2744 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2745 /* It was in input mode */ 2746 value = dev->gpio_dir | (1 << pin_number); 2747 dev->gpio_dir = value; 2748 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2749 dev->gpio_val); 2750 value = 0; 2751 } 2752 2753 if (pin_value == 0) 2754 value = dev->gpio_val & (~(1 << pin_number)); 2755 else 2756 value = dev->gpio_val | (1 << pin_number); 2757 2758 /* store the value */ 2759 dev->gpio_val = value; 2760 2761 /* toggle bit0 of GP_IO */ 2762 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2763 2764 return status; 2765 } 2766 2767 /***************************************************************************** 2768 * G P I O I2C related functions * 2769 ******************************************************************************/ 2770 int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2771 { 2772 int status = 0; 2773 2774 /* set SCL to output 1 ; set SDA to output 1 */ 2775 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2776 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2777 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2778 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2779 2780 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2781 if (status < 0) 2782 return -EINVAL; 2783 2784 /* set SCL to output 1; set SDA to output 0 */ 2785 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2786 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2787 2788 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2789 if (status < 0) 2790 return -EINVAL; 2791 2792 /* set SCL to output 0; set SDA to output 0 */ 2793 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2794 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2795 2796 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2797 if (status < 0) 2798 return -EINVAL; 2799 2800 return status; 2801 } 2802 2803 int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2804 { 2805 int status = 0; 2806 2807 /* set SCL to output 0; set SDA to output 0 */ 2808 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2809 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2810 2811 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2812 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2813 2814 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2815 if (status < 0) 2816 return -EINVAL; 2817 2818 /* set SCL to output 1; set SDA to output 0 */ 2819 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2820 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2821 2822 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2823 if (status < 0) 2824 return -EINVAL; 2825 2826 /* set SCL to input ,release SCL cable control 2827 set SDA to input ,release SDA cable control */ 2828 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2829 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2830 2831 status = 2832 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2833 if (status < 0) 2834 return -EINVAL; 2835 2836 return status; 2837 } 2838 2839 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2840 { 2841 int status = 0; 2842 u8 i; 2843 2844 /* set SCL to output ; set SDA to output */ 2845 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2846 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2847 2848 for (i = 0; i < 8; i++) { 2849 if (((data << i) & 0x80) == 0) { 2850 /* set SCL to output 0; set SDA to output 0 */ 2851 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2852 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2853 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2854 dev->gpio_val); 2855 2856 /* set SCL to output 1; set SDA to output 0 */ 2857 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2858 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2859 dev->gpio_val); 2860 2861 /* set SCL to output 0; set SDA to output 0 */ 2862 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2863 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2864 dev->gpio_val); 2865 } else { 2866 /* set SCL to output 0; set SDA to output 1 */ 2867 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2868 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2869 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2870 dev->gpio_val); 2871 2872 /* set SCL to output 1; set SDA to output 1 */ 2873 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2875 dev->gpio_val); 2876 2877 /* set SCL to output 0; set SDA to output 1 */ 2878 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2879 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2880 dev->gpio_val); 2881 } 2882 } 2883 return status; 2884 } 2885 2886 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 2887 { 2888 u8 value = 0; 2889 int status = 0; 2890 u32 gpio_logic_value = 0; 2891 u8 i; 2892 2893 /* read byte */ 2894 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2895 2896 /* set SCL to output 0; set SDA to input */ 2897 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2898 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2899 dev->gpio_val); 2900 2901 /* set SCL to output 1; set SDA to input */ 2902 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2903 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2904 dev->gpio_val); 2905 2906 /* get SDA data bit */ 2907 gpio_logic_value = dev->gpio_val; 2908 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2909 &dev->gpio_val); 2910 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2911 value |= (1 << (8 - i - 1)); 2912 2913 dev->gpio_val = gpio_logic_value; 2914 } 2915 2916 /* set SCL to output 0,finish the read latest SCL signal. 2917 !!!set SDA to input, never to modify SDA direction at 2918 the same times */ 2919 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2920 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2921 2922 /* store the value */ 2923 *buf = value & 0xff; 2924 2925 return status; 2926 } 2927 2928 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2929 { 2930 int status = 0; 2931 u32 gpio_logic_value = 0; 2932 int nCnt = 10; 2933 int nInit = nCnt; 2934 2935 /* clock stretch; set SCL to input; set SDA to input; 2936 get SCL value till SCL = 1 */ 2937 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2938 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2939 2940 gpio_logic_value = dev->gpio_val; 2941 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2942 2943 do { 2944 msleep(2); 2945 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2946 &dev->gpio_val); 2947 nCnt--; 2948 } while (((dev->gpio_val & 2949 (1 << dev->board.tuner_scl_gpio)) == 0) && 2950 (nCnt > 0)); 2951 2952 if (nCnt == 0) 2953 dev_dbg(dev->dev, 2954 "No ACK after %d msec -GPIO I2C failed!", 2955 nInit * 10); 2956 2957 /* 2958 * readAck 2959 * through clock stretch, slave has given a SCL signal, 2960 * so the SDA data can be directly read. 2961 */ 2962 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val); 2963 2964 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2965 dev->gpio_val = gpio_logic_value; 2966 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2967 status = 0; 2968 } else { 2969 dev->gpio_val = gpio_logic_value; 2970 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2971 } 2972 2973 /* read SDA end, set the SCL to output 0, after this operation, 2974 SDA direction can be changed. */ 2975 dev->gpio_val = gpio_logic_value; 2976 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2977 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2978 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2979 2980 return status; 2981 } 2982 2983 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2984 { 2985 int status = 0; 2986 2987 /* set SDA to ouput */ 2988 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2989 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2990 2991 /* set SCL = 0 (output); set SDA = 0 (output) */ 2992 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2993 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2994 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2995 2996 /* set SCL = 1 (output); set SDA = 0 (output) */ 2997 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2998 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2999 3000 /* set SCL = 0 (output); set SDA = 0 (output) */ 3001 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 3002 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3003 3004 /* set SDA to input,and then the slave will read data from SDA. */ 3005 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 3006 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3007 3008 return status; 3009 } 3010 3011 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 3012 { 3013 int status = 0; 3014 3015 /* set scl to output ; set sda to input */ 3016 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 3017 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 3018 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3019 3020 /* set scl to output 0; set sda to input */ 3021 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 3022 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3023 3024 /* set scl to output 1; set sda to input */ 3025 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 3026 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3027 3028 return status; 3029 } 3030 3031 /***************************************************************************** 3032 * G P I O I2C related functions * 3033 ******************************************************************************/ 3034 /* cx231xx_gpio_i2c_read 3035 * Function to read data from gpio based I2C interface 3036 */ 3037 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3038 { 3039 int status = 0; 3040 int i = 0; 3041 3042 /* get the lock */ 3043 mutex_lock(&dev->gpio_i2c_lock); 3044 3045 /* start */ 3046 status = cx231xx_gpio_i2c_start(dev); 3047 3048 /* write dev_addr */ 3049 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 3050 3051 /* readAck */ 3052 status = cx231xx_gpio_i2c_read_ack(dev); 3053 3054 /* read data */ 3055 for (i = 0; i < len; i++) { 3056 /* read data */ 3057 buf[i] = 0; 3058 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 3059 3060 if ((i + 1) != len) { 3061 /* only do write ack if we more length */ 3062 status = cx231xx_gpio_i2c_write_ack(dev); 3063 } 3064 } 3065 3066 /* write NAK - inform reads are complete */ 3067 status = cx231xx_gpio_i2c_write_nak(dev); 3068 3069 /* write end */ 3070 status = cx231xx_gpio_i2c_end(dev); 3071 3072 /* release the lock */ 3073 mutex_unlock(&dev->gpio_i2c_lock); 3074 3075 return status; 3076 } 3077 3078 /* cx231xx_gpio_i2c_write 3079 * Function to write data to gpio based I2C interface 3080 */ 3081 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3082 { 3083 int i = 0; 3084 3085 /* get the lock */ 3086 mutex_lock(&dev->gpio_i2c_lock); 3087 3088 /* start */ 3089 cx231xx_gpio_i2c_start(dev); 3090 3091 /* write dev_addr */ 3092 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 3093 3094 /* read Ack */ 3095 cx231xx_gpio_i2c_read_ack(dev); 3096 3097 for (i = 0; i < len; i++) { 3098 /* Write data */ 3099 cx231xx_gpio_i2c_write_byte(dev, buf[i]); 3100 3101 /* read Ack */ 3102 cx231xx_gpio_i2c_read_ack(dev); 3103 } 3104 3105 /* write End */ 3106 cx231xx_gpio_i2c_end(dev); 3107 3108 /* release the lock */ 3109 mutex_unlock(&dev->gpio_i2c_lock); 3110 3111 return 0; 3112 } 3113