1 /* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/list.h> 27 #include <linux/module.h> 28 #include <linux/kernel.h> 29 #include <linux/bitmap.h> 30 #include <linux/usb.h> 31 #include <linux/i2c.h> 32 #include <linux/mm.h> 33 #include <linux/mutex.h> 34 #include <media/tuner.h> 35 36 #include <media/v4l2-common.h> 37 #include <media/v4l2-ioctl.h> 38 39 #include "cx231xx.h" 40 #include "cx231xx-dif.h" 41 42 #define TUNER_MODE_FM_RADIO 0 43 /****************************************************************************** 44 -: BLOCK ARRANGEMENT :- 45 I2S block ----------------------| 46 [I2S audio] | 47 | 48 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 49 [video & audio] | [Audio] 50 | 51 |-> Cx25840 --> Video 52 [Video] 53 54 *******************************************************************************/ 55 /****************************************************************************** 56 * VERVE REGISTER * 57 * * 58 ******************************************************************************/ 59 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 60 { 61 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 62 saddr, 1, data, 1); 63 } 64 65 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 66 { 67 int status; 68 u32 temp = 0; 69 70 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 71 saddr, 1, &temp, 1); 72 *data = (u8) temp; 73 return status; 74 } 75 void initGPIO(struct cx231xx *dev) 76 { 77 u32 _gpio_direction = 0; 78 u32 value = 0; 79 u8 val = 0; 80 81 _gpio_direction = _gpio_direction & 0xFC0003FF; 82 _gpio_direction = _gpio_direction | 0x03FDFC00; 83 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 84 85 verve_read_byte(dev, 0x07, &val); 86 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 87 verve_write_byte(dev, 0x07, 0xF4); 88 verve_read_byte(dev, 0x07, &val); 89 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 90 91 cx231xx_capture_start(dev, 1, Vbi); 92 93 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 94 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 95 96 } 97 void uninitGPIO(struct cx231xx *dev) 98 { 99 u8 value[4] = { 0, 0, 0, 0 }; 100 101 cx231xx_capture_start(dev, 0, Vbi); 102 verve_write_byte(dev, 0x07, 0x14); 103 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 104 0x68, value, 4); 105 } 106 107 /****************************************************************************** 108 * A F E - B L O C K C O N T R O L functions * 109 * [ANALOG FRONT END] * 110 ******************************************************************************/ 111 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 112 { 113 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 114 saddr, 2, data, 1); 115 } 116 117 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 118 { 119 int status; 120 u32 temp = 0; 121 122 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 123 saddr, 2, &temp, 1); 124 *data = (u8) temp; 125 return status; 126 } 127 128 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 129 { 130 int status = 0; 131 u8 temp = 0; 132 u8 afe_power_status = 0; 133 int i = 0; 134 135 /* super block initialize */ 136 temp = (u8) (ref_count & 0xff); 137 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 138 if (status < 0) 139 return status; 140 141 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 142 if (status < 0) 143 return status; 144 145 temp = (u8) ((ref_count & 0x300) >> 8); 146 temp |= 0x40; 147 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 148 if (status < 0) 149 return status; 150 151 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 152 if (status < 0) 153 return status; 154 155 /* enable pll */ 156 while (afe_power_status != 0x18) { 157 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 158 if (status < 0) { 159 cx231xx_info( 160 ": Init Super Block failed in send cmd\n"); 161 break; 162 } 163 164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 165 afe_power_status &= 0xff; 166 if (status < 0) { 167 cx231xx_info( 168 ": Init Super Block failed in receive cmd\n"); 169 break; 170 } 171 i++; 172 if (i == 10) { 173 cx231xx_info( 174 ": Init Super Block force break in loop !!!!\n"); 175 status = -1; 176 break; 177 } 178 } 179 180 if (status < 0) 181 return status; 182 183 /* start tuning filter */ 184 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 185 if (status < 0) 186 return status; 187 188 msleep(5); 189 190 /* exit tuning */ 191 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 192 193 return status; 194 } 195 196 int cx231xx_afe_init_channels(struct cx231xx *dev) 197 { 198 int status = 0; 199 200 /* power up all 3 channels, clear pd_buffer */ 201 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 204 205 /* Enable quantizer calibration */ 206 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 207 208 /* channel initialize, force modulator (fb) reset */ 209 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 212 213 /* start quantilizer calibration */ 214 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 217 msleep(5); 218 219 /* exit modulator (fb) reset */ 220 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 223 224 /* enable the pre_clamp in each channel for single-ended input */ 225 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 228 229 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 230 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 231 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 233 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 235 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 236 237 /* dynamic element matching off */ 238 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 241 242 return status; 243 } 244 245 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 246 { 247 u8 c_value = 0; 248 int status = 0; 249 250 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 251 c_value &= (~(0x50)); 252 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 253 254 return status; 255 } 256 257 /* 258 The Analog Front End in Cx231xx has 3 channels. These 259 channels are used to share between different inputs 260 like tuner, s-video and composite inputs. 261 262 channel 1 ----- pin 1 to pin4(in reg is 1-4) 263 channel 2 ----- pin 5 to pin8(in reg is 5-8) 264 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 265 */ 266 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 267 { 268 u8 ch1_setting = (u8) input_mux; 269 u8 ch2_setting = (u8) (input_mux >> 8); 270 u8 ch3_setting = (u8) (input_mux >> 16); 271 int status = 0; 272 u8 value = 0; 273 274 if (ch1_setting != 0) { 275 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 276 value &= ~INPUT_SEL_MASK; 277 value |= (ch1_setting - 1) << 4; 278 value &= 0xff; 279 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 280 } 281 282 if (ch2_setting != 0) { 283 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 284 value &= ~INPUT_SEL_MASK; 285 value |= (ch2_setting - 1) << 4; 286 value &= 0xff; 287 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 288 } 289 290 /* For ch3_setting, the value to put in the register is 291 7 less than the input number */ 292 if (ch3_setting != 0) { 293 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 294 value &= ~INPUT_SEL_MASK; 295 value |= (ch3_setting - 1) << 4; 296 value &= 0xff; 297 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 298 } 299 300 return status; 301 } 302 303 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 304 { 305 int status = 0; 306 307 /* 308 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 309 * Currently, only baseband works. 310 */ 311 312 switch (mode) { 313 case AFE_MODE_LOW_IF: 314 cx231xx_Setup_AFE_for_LowIF(dev); 315 break; 316 case AFE_MODE_BASEBAND: 317 status = cx231xx_afe_setup_AFE_for_baseband(dev); 318 break; 319 case AFE_MODE_EU_HI_IF: 320 /* SetupAFEforEuHiIF(); */ 321 break; 322 case AFE_MODE_US_HI_IF: 323 /* SetupAFEforUsHiIF(); */ 324 break; 325 case AFE_MODE_JAPAN_HI_IF: 326 /* SetupAFEforJapanHiIF(); */ 327 break; 328 } 329 330 if ((mode != dev->afe_mode) && 331 (dev->video_input == CX231XX_VMUX_TELEVISION)) 332 status = cx231xx_afe_adjust_ref_count(dev, 333 CX231XX_VMUX_TELEVISION); 334 335 dev->afe_mode = mode; 336 337 return status; 338 } 339 340 int cx231xx_afe_update_power_control(struct cx231xx *dev, 341 enum AV_MODE avmode) 342 { 343 u8 afe_power_status = 0; 344 int status = 0; 345 346 switch (dev->model) { 347 case CX231XX_BOARD_CNXT_CARRAERA: 348 case CX231XX_BOARD_CNXT_RDE_250: 349 case CX231XX_BOARD_CNXT_SHELBY: 350 case CX231XX_BOARD_CNXT_RDU_250: 351 case CX231XX_BOARD_CNXT_RDE_253S: 352 case CX231XX_BOARD_CNXT_RDU_253S: 353 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 354 case CX231XX_BOARD_HAUPPAUGE_EXETER: 355 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 356 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 357 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 358 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 359 case CX231XX_BOARD_OTG102: 360 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 361 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 362 FLD_PWRDN_ENABLE_PLL)) { 363 status = afe_write_byte(dev, SUP_BLK_PWRDN, 364 FLD_PWRDN_TUNING_BIAS | 365 FLD_PWRDN_ENABLE_PLL); 366 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 367 &afe_power_status); 368 if (status < 0) 369 break; 370 } 371 372 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 373 0x00); 374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 375 0x00); 376 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 377 0x00); 378 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 379 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 380 0x70); 381 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 382 0x70); 383 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 384 0x70); 385 386 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 387 &afe_power_status); 388 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 389 FLD_PWRDN_PD_BIAS | 390 FLD_PWRDN_PD_TUNECK; 391 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 392 afe_power_status); 393 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 394 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 395 FLD_PWRDN_ENABLE_PLL)) { 396 status = afe_write_byte(dev, SUP_BLK_PWRDN, 397 FLD_PWRDN_TUNING_BIAS | 398 FLD_PWRDN_ENABLE_PLL); 399 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 400 &afe_power_status); 401 if (status < 0) 402 break; 403 } 404 405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 406 0x00); 407 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 408 0x00); 409 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 410 0x00); 411 } else { 412 cx231xx_info("Invalid AV mode input\n"); 413 status = -1; 414 } 415 break; 416 default: 417 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 418 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 419 FLD_PWRDN_ENABLE_PLL)) { 420 status = afe_write_byte(dev, SUP_BLK_PWRDN, 421 FLD_PWRDN_TUNING_BIAS | 422 FLD_PWRDN_ENABLE_PLL); 423 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 424 &afe_power_status); 425 if (status < 0) 426 break; 427 } 428 429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 430 0x40); 431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 432 0x40); 433 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 434 0x00); 435 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 436 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 437 0x70); 438 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 439 0x70); 440 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 441 0x70); 442 443 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 444 &afe_power_status); 445 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 446 FLD_PWRDN_PD_BIAS | 447 FLD_PWRDN_PD_TUNECK; 448 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 449 afe_power_status); 450 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 451 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 452 FLD_PWRDN_ENABLE_PLL)) { 453 status = afe_write_byte(dev, SUP_BLK_PWRDN, 454 FLD_PWRDN_TUNING_BIAS | 455 FLD_PWRDN_ENABLE_PLL); 456 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 457 &afe_power_status); 458 if (status < 0) 459 break; 460 } 461 462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 463 0x00); 464 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 465 0x00); 466 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 467 0x40); 468 } else { 469 cx231xx_info("Invalid AV mode input\n"); 470 status = -1; 471 } 472 } /* switch */ 473 474 return status; 475 } 476 477 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 478 { 479 u8 input_mode = 0; 480 u8 ntf_mode = 0; 481 int status = 0; 482 483 dev->video_input = video_input; 484 485 if (video_input == CX231XX_VMUX_TELEVISION) { 486 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 487 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 488 &ntf_mode); 489 } else { 490 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 491 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 492 &ntf_mode); 493 } 494 495 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 496 497 switch (input_mode) { 498 case SINGLE_ENDED: 499 dev->afe_ref_count = 0x23C; 500 break; 501 case LOW_IF: 502 dev->afe_ref_count = 0x24C; 503 break; 504 case EU_IF: 505 dev->afe_ref_count = 0x258; 506 break; 507 case US_IF: 508 dev->afe_ref_count = 0x260; 509 break; 510 default: 511 break; 512 } 513 514 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 515 516 return status; 517 } 518 519 /****************************************************************************** 520 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 521 ******************************************************************************/ 522 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 523 { 524 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 525 saddr, 2, data, 1); 526 } 527 528 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 529 { 530 int status; 531 u32 temp = 0; 532 533 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 534 saddr, 2, &temp, 1); 535 *data = (u8) temp; 536 return status; 537 } 538 539 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 540 { 541 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 542 saddr, 2, data, 4); 543 } 544 545 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 546 { 547 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 548 saddr, 2, data, 4); 549 } 550 int cx231xx_check_fw(struct cx231xx *dev) 551 { 552 u8 temp = 0; 553 int status = 0; 554 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 555 if (status < 0) 556 return status; 557 else 558 return temp; 559 560 } 561 562 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 563 { 564 int status = 0; 565 566 switch (INPUT(input)->type) { 567 case CX231XX_VMUX_COMPOSITE1: 568 case CX231XX_VMUX_SVIDEO: 569 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 570 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 571 /* External AV */ 572 status = cx231xx_set_power_mode(dev, 573 POLARIS_AVMODE_ENXTERNAL_AV); 574 if (status < 0) { 575 cx231xx_errdev("%s: set_power_mode : Failed to" 576 " set Power - errCode [%d]!\n", 577 __func__, status); 578 return status; 579 } 580 } 581 status = cx231xx_set_decoder_video_input(dev, 582 INPUT(input)->type, 583 INPUT(input)->vmux); 584 break; 585 case CX231XX_VMUX_TELEVISION: 586 case CX231XX_VMUX_CABLE: 587 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 588 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 589 /* Tuner */ 590 status = cx231xx_set_power_mode(dev, 591 POLARIS_AVMODE_ANALOGT_TV); 592 if (status < 0) { 593 cx231xx_errdev("%s: set_power_mode:Failed" 594 " to set Power - errCode [%d]!\n", 595 __func__, status); 596 return status; 597 } 598 } 599 if (dev->tuner_type == TUNER_NXP_TDA18271) 600 status = cx231xx_set_decoder_video_input(dev, 601 CX231XX_VMUX_TELEVISION, 602 INPUT(input)->vmux); 603 else 604 status = cx231xx_set_decoder_video_input(dev, 605 CX231XX_VMUX_COMPOSITE1, 606 INPUT(input)->vmux); 607 608 break; 609 default: 610 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 611 __func__, INPUT(input)->type); 612 break; 613 } 614 615 /* save the selection */ 616 dev->video_input = input; 617 618 return status; 619 } 620 621 int cx231xx_set_decoder_video_input(struct cx231xx *dev, 622 u8 pin_type, u8 input) 623 { 624 int status = 0; 625 u32 value = 0; 626 627 if (pin_type != dev->video_input) { 628 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 629 if (status < 0) { 630 cx231xx_errdev("%s: adjust_ref_count :Failed to set" 631 "AFE input mux - errCode [%d]!\n", 632 __func__, status); 633 return status; 634 } 635 } 636 637 /* call afe block to set video inputs */ 638 status = cx231xx_afe_set_input_mux(dev, input); 639 if (status < 0) { 640 cx231xx_errdev("%s: set_input_mux :Failed to set" 641 " AFE input mux - errCode [%d]!\n", 642 __func__, status); 643 return status; 644 } 645 646 switch (pin_type) { 647 case CX231XX_VMUX_COMPOSITE1: 648 status = vid_blk_read_word(dev, AFE_CTRL, &value); 649 value |= (0 << 13) | (1 << 4); 650 value &= ~(1 << 5); 651 652 /* set [24:23] [22:15] to 0 */ 653 value &= (~(0x1ff8000)); 654 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 655 value |= 0x1000000; 656 status = vid_blk_write_word(dev, AFE_CTRL, value); 657 658 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 659 value |= (1 << 7); 660 status = vid_blk_write_word(dev, OUT_CTRL1, value); 661 662 /* Set output mode */ 663 status = cx231xx_read_modify_write_i2c_dword(dev, 664 VID_BLK_I2C_ADDRESS, 665 OUT_CTRL1, 666 FLD_OUT_MODE, 667 dev->board.output_mode); 668 669 /* Tell DIF object to go to baseband mode */ 670 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 671 if (status < 0) { 672 cx231xx_errdev("%s: cx231xx_dif set to By pass" 673 " mode- errCode [%d]!\n", 674 __func__, status); 675 return status; 676 } 677 678 /* Read the DFE_CTRL1 register */ 679 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 680 681 /* enable the VBI_GATE_EN */ 682 value |= FLD_VBI_GATE_EN; 683 684 /* Enable the auto-VGA enable */ 685 value |= FLD_VGA_AUTO_EN; 686 687 /* Write it back */ 688 status = vid_blk_write_word(dev, DFE_CTRL1, value); 689 690 /* Disable auto config of registers */ 691 status = cx231xx_read_modify_write_i2c_dword(dev, 692 VID_BLK_I2C_ADDRESS, 693 MODE_CTRL, FLD_ACFG_DIS, 694 cx231xx_set_field(FLD_ACFG_DIS, 1)); 695 696 /* Set CVBS input mode */ 697 status = cx231xx_read_modify_write_i2c_dword(dev, 698 VID_BLK_I2C_ADDRESS, 699 MODE_CTRL, FLD_INPUT_MODE, 700 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 701 break; 702 case CX231XX_VMUX_SVIDEO: 703 /* Disable the use of DIF */ 704 705 status = vid_blk_read_word(dev, AFE_CTRL, &value); 706 707 /* set [24:23] [22:15] to 0 */ 708 value &= (~(0x1ff8000)); 709 /* set FUNC_MODE[24:23] = 2 710 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 711 value |= 0x1000010; 712 status = vid_blk_write_word(dev, AFE_CTRL, value); 713 714 /* Tell DIF object to go to baseband mode */ 715 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 716 if (status < 0) { 717 cx231xx_errdev("%s: cx231xx_dif set to By pass" 718 " mode- errCode [%d]!\n", 719 __func__, status); 720 return status; 721 } 722 723 /* Read the DFE_CTRL1 register */ 724 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 725 726 /* enable the VBI_GATE_EN */ 727 value |= FLD_VBI_GATE_EN; 728 729 /* Enable the auto-VGA enable */ 730 value |= FLD_VGA_AUTO_EN; 731 732 /* Write it back */ 733 status = vid_blk_write_word(dev, DFE_CTRL1, value); 734 735 /* Disable auto config of registers */ 736 status = cx231xx_read_modify_write_i2c_dword(dev, 737 VID_BLK_I2C_ADDRESS, 738 MODE_CTRL, FLD_ACFG_DIS, 739 cx231xx_set_field(FLD_ACFG_DIS, 1)); 740 741 /* Set YC input mode */ 742 status = cx231xx_read_modify_write_i2c_dword(dev, 743 VID_BLK_I2C_ADDRESS, 744 MODE_CTRL, 745 FLD_INPUT_MODE, 746 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 747 748 /* Chroma to ADC2 */ 749 status = vid_blk_read_word(dev, AFE_CTRL, &value); 750 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 751 752 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 753 This sets them to use video 754 rather than audio. Only one of the two will be in use. */ 755 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 756 757 status = vid_blk_write_word(dev, AFE_CTRL, value); 758 759 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 760 break; 761 case CX231XX_VMUX_TELEVISION: 762 case CX231XX_VMUX_CABLE: 763 default: 764 /* TODO: Test if this is also needed for xc2028/xc3028 */ 765 if (dev->board.tuner_type == TUNER_XC5000) { 766 /* Disable the use of DIF */ 767 768 status = vid_blk_read_word(dev, AFE_CTRL, &value); 769 value |= (0 << 13) | (1 << 4); 770 value &= ~(1 << 5); 771 772 /* set [24:23] [22:15] to 0 */ 773 value &= (~(0x1FF8000)); 774 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 775 value |= 0x1000000; 776 status = vid_blk_write_word(dev, AFE_CTRL, value); 777 778 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 779 value |= (1 << 7); 780 status = vid_blk_write_word(dev, OUT_CTRL1, value); 781 782 /* Set output mode */ 783 status = cx231xx_read_modify_write_i2c_dword(dev, 784 VID_BLK_I2C_ADDRESS, 785 OUT_CTRL1, FLD_OUT_MODE, 786 dev->board.output_mode); 787 788 /* Tell DIF object to go to baseband mode */ 789 status = cx231xx_dif_set_standard(dev, 790 DIF_USE_BASEBAND); 791 if (status < 0) { 792 cx231xx_errdev("%s: cx231xx_dif set to By pass" 793 " mode- errCode [%d]!\n", 794 __func__, status); 795 return status; 796 } 797 798 /* Read the DFE_CTRL1 register */ 799 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 800 801 /* enable the VBI_GATE_EN */ 802 value |= FLD_VBI_GATE_EN; 803 804 /* Enable the auto-VGA enable */ 805 value |= FLD_VGA_AUTO_EN; 806 807 /* Write it back */ 808 status = vid_blk_write_word(dev, DFE_CTRL1, value); 809 810 /* Disable auto config of registers */ 811 status = cx231xx_read_modify_write_i2c_dword(dev, 812 VID_BLK_I2C_ADDRESS, 813 MODE_CTRL, FLD_ACFG_DIS, 814 cx231xx_set_field(FLD_ACFG_DIS, 1)); 815 816 /* Set CVBS input mode */ 817 status = cx231xx_read_modify_write_i2c_dword(dev, 818 VID_BLK_I2C_ADDRESS, 819 MODE_CTRL, FLD_INPUT_MODE, 820 cx231xx_set_field(FLD_INPUT_MODE, 821 INPUT_MODE_CVBS_0)); 822 } else { 823 /* Enable the DIF for the tuner */ 824 825 /* Reinitialize the DIF */ 826 status = cx231xx_dif_set_standard(dev, dev->norm); 827 if (status < 0) { 828 cx231xx_errdev("%s: cx231xx_dif set to By pass" 829 " mode- errCode [%d]!\n", 830 __func__, status); 831 return status; 832 } 833 834 /* Make sure bypass is cleared */ 835 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 836 837 /* Clear the bypass bit */ 838 value &= ~FLD_DIF_DIF_BYPASS; 839 840 /* Enable the use of the DIF block */ 841 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 842 843 /* Read the DFE_CTRL1 register */ 844 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 845 846 /* Disable the VBI_GATE_EN */ 847 value &= ~FLD_VBI_GATE_EN; 848 849 /* Enable the auto-VGA enable, AGC, and 850 set the skip count to 2 */ 851 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 852 853 /* Write it back */ 854 status = vid_blk_write_word(dev, DFE_CTRL1, value); 855 856 /* Wait until AGC locks up */ 857 msleep(1); 858 859 /* Disable the auto-VGA enable AGC */ 860 value &= ~(FLD_VGA_AUTO_EN); 861 862 /* Write it back */ 863 status = vid_blk_write_word(dev, DFE_CTRL1, value); 864 865 /* Enable Polaris B0 AGC output */ 866 status = vid_blk_read_word(dev, PIN_CTRL, &value); 867 value |= (FLD_OEF_AGC_RF) | 868 (FLD_OEF_AGC_IFVGA) | 869 (FLD_OEF_AGC_IF); 870 status = vid_blk_write_word(dev, PIN_CTRL, value); 871 872 /* Set output mode */ 873 status = cx231xx_read_modify_write_i2c_dword(dev, 874 VID_BLK_I2C_ADDRESS, 875 OUT_CTRL1, FLD_OUT_MODE, 876 dev->board.output_mode); 877 878 /* Disable auto config of registers */ 879 status = cx231xx_read_modify_write_i2c_dword(dev, 880 VID_BLK_I2C_ADDRESS, 881 MODE_CTRL, FLD_ACFG_DIS, 882 cx231xx_set_field(FLD_ACFG_DIS, 1)); 883 884 /* Set CVBS input mode */ 885 status = cx231xx_read_modify_write_i2c_dword(dev, 886 VID_BLK_I2C_ADDRESS, 887 MODE_CTRL, FLD_INPUT_MODE, 888 cx231xx_set_field(FLD_INPUT_MODE, 889 INPUT_MODE_CVBS_0)); 890 891 /* Set some bits in AFE_CTRL so that channel 2 or 3 892 * is ready to receive audio */ 893 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 894 /* Clear droop comp (bit 19-20) */ 895 /* Set VGA_SEL (for audio control) (bit 7-8) */ 896 status = vid_blk_read_word(dev, AFE_CTRL, &value); 897 898 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 899 value &= (~(FLD_FUNC_MODE)); 900 value |= 0x800000; 901 902 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 903 904 status = vid_blk_write_word(dev, AFE_CTRL, value); 905 906 if (dev->tuner_type == TUNER_NXP_TDA18271) { 907 status = vid_blk_read_word(dev, PIN_CTRL, 908 &value); 909 status = vid_blk_write_word(dev, PIN_CTRL, 910 (value & 0xFFFFFFEF)); 911 } 912 913 break; 914 915 } 916 break; 917 } 918 919 /* Set raw VBI mode */ 920 status = cx231xx_read_modify_write_i2c_dword(dev, 921 VID_BLK_I2C_ADDRESS, 922 OUT_CTRL1, FLD_VBIHACTRAW_EN, 923 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 924 925 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 926 if (value & 0x02) { 927 value |= (1 << 19); 928 status = vid_blk_write_word(dev, OUT_CTRL1, value); 929 } 930 931 return status; 932 } 933 934 void cx231xx_enable656(struct cx231xx *dev) 935 { 936 u8 temp = 0; 937 /*enable TS1 data[0:7] as output to export 656*/ 938 939 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 940 941 /*enable TS1 clock as output to export 656*/ 942 943 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 944 temp = temp|0x04; 945 946 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 947 } 948 EXPORT_SYMBOL_GPL(cx231xx_enable656); 949 950 void cx231xx_disable656(struct cx231xx *dev) 951 { 952 u8 temp = 0; 953 954 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 955 956 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 957 temp = temp&0xFB; 958 959 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 960 } 961 EXPORT_SYMBOL_GPL(cx231xx_disable656); 962 963 /* 964 * Handle any video-mode specific overrides that are different 965 * on a per video standards basis after touching the MODE_CTRL 966 * register which resets many values for autodetect 967 */ 968 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 969 { 970 int status = 0; 971 972 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", 973 (unsigned int)dev->norm); 974 975 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 976 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 977 978 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 979 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 980 981 /* Move the close caption lines out of active video, 982 adjust the active video start point */ 983 status = cx231xx_read_modify_write_i2c_dword(dev, 984 VID_BLK_I2C_ADDRESS, 985 VERT_TIM_CTRL, 986 FLD_VBLANK_CNT, 0x18); 987 status = cx231xx_read_modify_write_i2c_dword(dev, 988 VID_BLK_I2C_ADDRESS, 989 VERT_TIM_CTRL, 990 FLD_VACTIVE_CNT, 991 0x1E7000); 992 status = cx231xx_read_modify_write_i2c_dword(dev, 993 VID_BLK_I2C_ADDRESS, 994 VERT_TIM_CTRL, 995 FLD_V656BLANK_CNT, 996 0x1C000000); 997 998 status = cx231xx_read_modify_write_i2c_dword(dev, 999 VID_BLK_I2C_ADDRESS, 1000 HORIZ_TIM_CTRL, 1001 FLD_HBLANK_CNT, 1002 cx231xx_set_field 1003 (FLD_HBLANK_CNT, 0x79)); 1004 1005 } else if (dev->norm & V4L2_STD_SECAM) { 1006 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 1007 status = cx231xx_read_modify_write_i2c_dword(dev, 1008 VID_BLK_I2C_ADDRESS, 1009 VERT_TIM_CTRL, 1010 FLD_VBLANK_CNT, 0x20); 1011 status = cx231xx_read_modify_write_i2c_dword(dev, 1012 VID_BLK_I2C_ADDRESS, 1013 VERT_TIM_CTRL, 1014 FLD_VACTIVE_CNT, 1015 cx231xx_set_field 1016 (FLD_VACTIVE_CNT, 1017 0x244)); 1018 status = cx231xx_read_modify_write_i2c_dword(dev, 1019 VID_BLK_I2C_ADDRESS, 1020 VERT_TIM_CTRL, 1021 FLD_V656BLANK_CNT, 1022 cx231xx_set_field 1023 (FLD_V656BLANK_CNT, 1024 0x24)); 1025 /* Adjust the active video horizontal start point */ 1026 status = cx231xx_read_modify_write_i2c_dword(dev, 1027 VID_BLK_I2C_ADDRESS, 1028 HORIZ_TIM_CTRL, 1029 FLD_HBLANK_CNT, 1030 cx231xx_set_field 1031 (FLD_HBLANK_CNT, 0x85)); 1032 } else { 1033 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 1034 status = cx231xx_read_modify_write_i2c_dword(dev, 1035 VID_BLK_I2C_ADDRESS, 1036 VERT_TIM_CTRL, 1037 FLD_VBLANK_CNT, 0x20); 1038 status = cx231xx_read_modify_write_i2c_dword(dev, 1039 VID_BLK_I2C_ADDRESS, 1040 VERT_TIM_CTRL, 1041 FLD_VACTIVE_CNT, 1042 cx231xx_set_field 1043 (FLD_VACTIVE_CNT, 1044 0x244)); 1045 status = cx231xx_read_modify_write_i2c_dword(dev, 1046 VID_BLK_I2C_ADDRESS, 1047 VERT_TIM_CTRL, 1048 FLD_V656BLANK_CNT, 1049 cx231xx_set_field 1050 (FLD_V656BLANK_CNT, 1051 0x24)); 1052 /* Adjust the active video horizontal start point */ 1053 status = cx231xx_read_modify_write_i2c_dword(dev, 1054 VID_BLK_I2C_ADDRESS, 1055 HORIZ_TIM_CTRL, 1056 FLD_HBLANK_CNT, 1057 cx231xx_set_field 1058 (FLD_HBLANK_CNT, 0x85)); 1059 1060 } 1061 1062 return status; 1063 } 1064 1065 int cx231xx_unmute_audio(struct cx231xx *dev) 1066 { 1067 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1068 } 1069 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1070 1071 static int stopAudioFirmware(struct cx231xx *dev) 1072 { 1073 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1074 } 1075 1076 static int restartAudioFirmware(struct cx231xx *dev) 1077 { 1078 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1079 } 1080 1081 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1082 { 1083 int status = 0; 1084 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1085 1086 switch (INPUT(input)->amux) { 1087 case CX231XX_AMUX_VIDEO: 1088 ainput = AUDIO_INPUT_TUNER_TV; 1089 break; 1090 case CX231XX_AMUX_LINE_IN: 1091 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1092 ainput = AUDIO_INPUT_LINE; 1093 break; 1094 default: 1095 break; 1096 } 1097 1098 status = cx231xx_set_audio_decoder_input(dev, ainput); 1099 1100 return status; 1101 } 1102 1103 int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1104 enum AUDIO_INPUT audio_input) 1105 { 1106 u32 dwval; 1107 int status; 1108 u8 gen_ctrl; 1109 u32 value = 0; 1110 1111 /* Put it in soft reset */ 1112 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1113 gen_ctrl |= 1; 1114 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1115 1116 switch (audio_input) { 1117 case AUDIO_INPUT_LINE: 1118 /* setup AUD_IO control from Merlin paralle output */ 1119 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1120 AUD_CHAN_SRC_PARALLEL); 1121 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1122 1123 /* setup input to Merlin, SRC2 connect to AC97 1124 bypass upsample-by-2, slave mode, sony mode, left justify 1125 adr 091c, dat 01000000 */ 1126 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1127 1128 status = vid_blk_write_word(dev, AC97_CTL, 1129 (dwval | FLD_AC97_UP2X_BYPASS)); 1130 1131 /* select the parallel1 and SRC3 */ 1132 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1133 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1134 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1135 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1136 1137 /* unmute all, AC97 in, independence mode 1138 adr 08d0, data 0x00063073 */ 1139 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1140 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1141 1142 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1143 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1144 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1145 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1146 1147 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1148 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1149 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1150 (dwval | FLD_PATH1_SC_THRESHOLD)); 1151 break; 1152 1153 case AUDIO_INPUT_TUNER_TV: 1154 default: 1155 status = stopAudioFirmware(dev); 1156 /* Setup SRC sources and clocks */ 1157 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1158 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1159 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1160 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1161 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1162 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1163 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1164 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1165 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1166 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1167 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1168 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1169 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1170 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1171 1172 /* Setup the AUD_IO control */ 1173 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1174 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1175 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1176 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1177 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1178 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1179 1180 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1181 1182 /* setAudioStandard(_audio_standard); */ 1183 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1184 1185 status = restartAudioFirmware(dev); 1186 1187 switch (dev->board.tuner_type) { 1188 case TUNER_XC5000: 1189 /* SIF passthrough at 28.6363 MHz sample rate */ 1190 status = cx231xx_read_modify_write_i2c_dword(dev, 1191 VID_BLK_I2C_ADDRESS, 1192 CHIP_CTRL, 1193 FLD_SIF_EN, 1194 cx231xx_set_field(FLD_SIF_EN, 1)); 1195 break; 1196 case TUNER_NXP_TDA18271: 1197 /* Normal mode: SIF passthrough at 14.32 MHz */ 1198 status = cx231xx_read_modify_write_i2c_dword(dev, 1199 VID_BLK_I2C_ADDRESS, 1200 CHIP_CTRL, 1201 FLD_SIF_EN, 1202 cx231xx_set_field(FLD_SIF_EN, 0)); 1203 break; 1204 default: 1205 /* This is just a casual suggestion to people adding 1206 new boards in case they use a tuner type we don't 1207 currently know about */ 1208 printk(KERN_INFO "Unknown tuner type configuring SIF"); 1209 break; 1210 } 1211 break; 1212 1213 case AUDIO_INPUT_TUNER_FM: 1214 /* use SIF for FM radio 1215 setupFM(); 1216 setAudioStandard(_audio_standard); 1217 */ 1218 break; 1219 1220 case AUDIO_INPUT_MUTE: 1221 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1222 break; 1223 } 1224 1225 /* Take it out of soft reset */ 1226 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1227 gen_ctrl &= ~1; 1228 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1229 1230 return status; 1231 } 1232 1233 /****************************************************************************** 1234 * C H I P Specific C O N T R O L functions * 1235 ******************************************************************************/ 1236 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1237 { 1238 u32 value; 1239 int status = 0; 1240 1241 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1242 value |= (~dev->board.ctl_pin_status_mask); 1243 status = vid_blk_write_word(dev, PIN_CTRL, value); 1244 1245 return status; 1246 } 1247 1248 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1249 u8 analog_or_digital) 1250 { 1251 int status = 0; 1252 1253 /* first set the direction to output */ 1254 status = cx231xx_set_gpio_direction(dev, 1255 dev->board. 1256 agc_analog_digital_select_gpio, 1); 1257 1258 /* 0 - demod ; 1 - Analog mode */ 1259 status = cx231xx_set_gpio_value(dev, 1260 dev->board.agc_analog_digital_select_gpio, 1261 analog_or_digital); 1262 1263 return status; 1264 } 1265 1266 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1267 { 1268 u8 value[4] = { 0, 0, 0, 0 }; 1269 int status = 0; 1270 bool current_is_port_3; 1271 1272 if (dev->board.dont_use_port_3) 1273 is_port_3 = false; 1274 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1275 PWR_CTL_EN, value, 4); 1276 if (status < 0) 1277 return status; 1278 1279 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1280 1281 /* Just return, if already using the right port */ 1282 if (current_is_port_3 == is_port_3) 1283 return 0; 1284 1285 if (is_port_3) 1286 value[0] |= I2C_DEMOD_EN; 1287 else 1288 value[0] &= ~I2C_DEMOD_EN; 1289 1290 cx231xx_info("Changing the i2c master port to %d\n", 1291 is_port_3 ? 3 : 1); 1292 1293 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1294 PWR_CTL_EN, value, 4); 1295 1296 return status; 1297 1298 } 1299 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1300 1301 void update_HH_register_after_set_DIF(struct cx231xx *dev) 1302 { 1303 /* 1304 u8 status = 0; 1305 u32 value = 0; 1306 1307 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1308 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1309 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1310 1311 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1312 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1313 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1314 */ 1315 } 1316 1317 void cx231xx_dump_HH_reg(struct cx231xx *dev) 1318 { 1319 u32 value = 0; 1320 u16 i = 0; 1321 1322 value = 0x45005390; 1323 vid_blk_write_word(dev, 0x104, value); 1324 1325 for (i = 0x100; i < 0x140; i++) { 1326 vid_blk_read_word(dev, i, &value); 1327 cx231xx_info("reg0x%x=0x%x\n", i, value); 1328 i = i+3; 1329 } 1330 1331 for (i = 0x300; i < 0x400; i++) { 1332 vid_blk_read_word(dev, i, &value); 1333 cx231xx_info("reg0x%x=0x%x\n", i, value); 1334 i = i+3; 1335 } 1336 1337 for (i = 0x400; i < 0x440; i++) { 1338 vid_blk_read_word(dev, i, &value); 1339 cx231xx_info("reg0x%x=0x%x\n", i, value); 1340 i = i+3; 1341 } 1342 1343 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1344 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1345 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1346 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1347 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1348 } 1349 1350 void cx231xx_dump_SC_reg(struct cx231xx *dev) 1351 { 1352 u8 value[4] = { 0, 0, 0, 0 }; 1353 cx231xx_info("cx231xx_dump_SC_reg!\n"); 1354 1355 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1356 value, 4); 1357 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1358 value[1], value[2], value[3]); 1359 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1360 value, 4); 1361 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1362 value[1], value[2], value[3]); 1363 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1364 value, 4); 1365 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1366 value[1], value[2], value[3]); 1367 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1368 value, 4); 1369 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1370 value[1], value[2], value[3]); 1371 1372 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1373 value, 4); 1374 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1375 value[1], value[2], value[3]); 1376 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1377 value, 4); 1378 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1379 value[1], value[2], value[3]); 1380 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1381 value, 4); 1382 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1383 value[1], value[2], value[3]); 1384 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1385 value, 4); 1386 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1387 value[1], value[2], value[3]); 1388 1389 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1390 value, 4); 1391 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1392 value[1], value[2], value[3]); 1393 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1394 value, 4); 1395 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1396 value[1], value[2], value[3]); 1397 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1398 value, 4); 1399 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1400 value[1], value[2], value[3]); 1401 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1402 value, 4); 1403 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1404 value[1], value[2], value[3]); 1405 1406 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1407 value, 4); 1408 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1409 value[1], value[2], value[3]); 1410 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1411 value, 4); 1412 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1413 value[1], value[2], value[3]); 1414 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1415 value, 4); 1416 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1417 value[1], value[2], value[3]); 1418 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1419 value, 4); 1420 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1421 value[1], value[2], value[3]); 1422 1423 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1424 value, 4); 1425 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1426 value[1], value[2], value[3]); 1427 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1428 value, 4); 1429 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1430 value[1], value[2], value[3]); 1431 1432 1433 } 1434 1435 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1436 1437 { 1438 u8 value = 0; 1439 1440 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1441 value = (value & 0xFE)|0x01; 1442 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1443 1444 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1445 value = (value & 0xFE)|0x00; 1446 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1447 1448 1449 /* 1450 config colibri to lo-if mode 1451 1452 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1453 the diff IF input by half, 1454 1455 for low-if agc defect 1456 */ 1457 1458 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1459 value = (value & 0xFC)|0x00; 1460 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1461 1462 afe_read_byte(dev, ADC_INPUT_CH3, &value); 1463 value = (value & 0xF9)|0x02; 1464 afe_write_byte(dev, ADC_INPUT_CH3, value); 1465 1466 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1467 value = (value & 0xFB)|0x04; 1468 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1469 1470 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1471 value = (value & 0xFC)|0x03; 1472 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1473 1474 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1475 value = (value & 0xFB)|0x04; 1476 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1477 1478 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1479 value = (value & 0xF8)|0x06; 1480 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1481 1482 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1483 value = (value & 0x8F)|0x40; 1484 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1485 1486 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1487 value = (value & 0xDF)|0x20; 1488 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1489 } 1490 1491 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1492 u8 spectral_invert, u32 mode) 1493 { 1494 u32 colibri_carrier_offset = 0; 1495 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1496 u32 standard = 0; 1497 u8 value[4] = { 0, 0, 0, 0 }; 1498 1499 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); 1500 value[0] = (u8) 0x6F; 1501 value[1] = (u8) 0x6F; 1502 value[2] = (u8) 0x6F; 1503 value[3] = (u8) 0x6F; 1504 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1505 PWR_CTL_EN, value, 4); 1506 1507 /*Set colibri for low IF*/ 1508 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1509 1510 /* Set C2HH for low IF operation.*/ 1511 standard = dev->norm; 1512 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1513 func_mode, standard); 1514 1515 /* Get colibri offsets.*/ 1516 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1517 standard); 1518 1519 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", 1520 colibri_carrier_offset, standard); 1521 1522 /* Set the band Pass filter for DIF*/ 1523 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1524 spectral_invert, mode); 1525 } 1526 1527 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1528 { 1529 u32 colibri_carrier_offset = 0; 1530 1531 if (mode == TUNER_MODE_FM_RADIO) { 1532 colibri_carrier_offset = 1100000; 1533 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1534 colibri_carrier_offset = 4832000; /*4.83MHz */ 1535 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1536 colibri_carrier_offset = 2700000; /*2.70MHz */ 1537 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1538 | V4L2_STD_SECAM)) { 1539 colibri_carrier_offset = 2100000; /*2.10MHz */ 1540 } 1541 1542 return colibri_carrier_offset; 1543 } 1544 1545 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1546 u8 spectral_invert, u32 mode) 1547 { 1548 unsigned long pll_freq_word; 1549 u32 dif_misc_ctrl_value = 0; 1550 u64 pll_freq_u64 = 0; 1551 u32 i = 0; 1552 1553 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1554 if_freq, spectral_invert, mode); 1555 1556 1557 if (mode == TUNER_MODE_FM_RADIO) { 1558 pll_freq_word = 0x905A1CAC; 1559 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1560 1561 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1562 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1563 pll_freq_word = if_freq; 1564 pll_freq_u64 = (u64)pll_freq_word << 28L; 1565 do_div(pll_freq_u64, 50000000); 1566 pll_freq_word = (u32)pll_freq_u64; 1567 /*pll_freq_word = 0x3463497;*/ 1568 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1569 1570 if (spectral_invert) { 1571 if_freq -= 400000; 1572 /* Enable Spectral Invert*/ 1573 vid_blk_read_word(dev, DIF_MISC_CTRL, 1574 &dif_misc_ctrl_value); 1575 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1576 vid_blk_write_word(dev, DIF_MISC_CTRL, 1577 dif_misc_ctrl_value); 1578 } else { 1579 if_freq += 400000; 1580 /* Disable Spectral Invert*/ 1581 vid_blk_read_word(dev, DIF_MISC_CTRL, 1582 &dif_misc_ctrl_value); 1583 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1584 vid_blk_write_word(dev, DIF_MISC_CTRL, 1585 dif_misc_ctrl_value); 1586 } 1587 1588 if_freq = (if_freq/100000)*100000; 1589 1590 if (if_freq < 3000000) 1591 if_freq = 3000000; 1592 1593 if (if_freq > 16000000) 1594 if_freq = 16000000; 1595 } 1596 1597 cx231xx_info("Enter IF=%zd\n", 1598 ARRAY_SIZE(Dif_set_array)); 1599 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 1600 if (Dif_set_array[i].if_freq == if_freq) { 1601 vid_blk_write_word(dev, 1602 Dif_set_array[i].register_address, Dif_set_array[i].value); 1603 } 1604 } 1605 } 1606 1607 /****************************************************************************** 1608 * D I F - B L O C K C O N T R O L functions * 1609 ******************************************************************************/ 1610 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1611 u32 function_mode, u32 standard) 1612 { 1613 int status = 0; 1614 1615 1616 if (mode == V4L2_TUNER_RADIO) { 1617 /* C2HH */ 1618 /* lo if big signal */ 1619 status = cx231xx_reg_mask_write(dev, 1620 VID_BLK_I2C_ADDRESS, 32, 1621 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1622 /* FUNC_MODE = DIF */ 1623 status = cx231xx_reg_mask_write(dev, 1624 VID_BLK_I2C_ADDRESS, 32, 1625 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1626 /* IF_MODE */ 1627 status = cx231xx_reg_mask_write(dev, 1628 VID_BLK_I2C_ADDRESS, 32, 1629 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1630 /* no inv */ 1631 status = cx231xx_reg_mask_write(dev, 1632 VID_BLK_I2C_ADDRESS, 32, 1633 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1634 } else if (standard != DIF_USE_BASEBAND) { 1635 if (standard & V4L2_STD_MN) { 1636 /* lo if big signal */ 1637 status = cx231xx_reg_mask_write(dev, 1638 VID_BLK_I2C_ADDRESS, 32, 1639 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1640 /* FUNC_MODE = DIF */ 1641 status = cx231xx_reg_mask_write(dev, 1642 VID_BLK_I2C_ADDRESS, 32, 1643 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1644 function_mode); 1645 /* IF_MODE */ 1646 status = cx231xx_reg_mask_write(dev, 1647 VID_BLK_I2C_ADDRESS, 32, 1648 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1649 /* no inv */ 1650 status = cx231xx_reg_mask_write(dev, 1651 VID_BLK_I2C_ADDRESS, 32, 1652 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1653 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1654 status = cx231xx_reg_mask_write(dev, 1655 VID_BLK_I2C_ADDRESS, 32, 1656 AUD_IO_CTRL, 0, 31, 0x00000003); 1657 } else if ((standard == V4L2_STD_PAL_I) | 1658 (standard & V4L2_STD_PAL_D) | 1659 (standard & V4L2_STD_SECAM)) { 1660 /* C2HH setup */ 1661 /* lo if big signal */ 1662 status = cx231xx_reg_mask_write(dev, 1663 VID_BLK_I2C_ADDRESS, 32, 1664 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1665 /* FUNC_MODE = DIF */ 1666 status = cx231xx_reg_mask_write(dev, 1667 VID_BLK_I2C_ADDRESS, 32, 1668 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1669 function_mode); 1670 /* IF_MODE */ 1671 status = cx231xx_reg_mask_write(dev, 1672 VID_BLK_I2C_ADDRESS, 32, 1673 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1674 /* no inv */ 1675 status = cx231xx_reg_mask_write(dev, 1676 VID_BLK_I2C_ADDRESS, 32, 1677 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1678 } else { 1679 /* default PAL BG */ 1680 /* C2HH setup */ 1681 /* lo if big signal */ 1682 status = cx231xx_reg_mask_write(dev, 1683 VID_BLK_I2C_ADDRESS, 32, 1684 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1685 /* FUNC_MODE = DIF */ 1686 status = cx231xx_reg_mask_write(dev, 1687 VID_BLK_I2C_ADDRESS, 32, 1688 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1689 function_mode); 1690 /* IF_MODE */ 1691 status = cx231xx_reg_mask_write(dev, 1692 VID_BLK_I2C_ADDRESS, 32, 1693 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1694 /* no inv */ 1695 status = cx231xx_reg_mask_write(dev, 1696 VID_BLK_I2C_ADDRESS, 32, 1697 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1698 } 1699 } 1700 1701 return status; 1702 } 1703 1704 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1705 { 1706 int status = 0; 1707 u32 dif_misc_ctrl_value = 0; 1708 u32 func_mode = 0; 1709 1710 cx231xx_info("%s: setStandard to %x\n", __func__, standard); 1711 1712 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1713 if (standard != DIF_USE_BASEBAND) 1714 dev->norm = standard; 1715 1716 switch (dev->model) { 1717 case CX231XX_BOARD_CNXT_CARRAERA: 1718 case CX231XX_BOARD_CNXT_RDE_250: 1719 case CX231XX_BOARD_CNXT_SHELBY: 1720 case CX231XX_BOARD_CNXT_RDU_250: 1721 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1722 case CX231XX_BOARD_HAUPPAUGE_EXETER: 1723 case CX231XX_BOARD_OTG102: 1724 func_mode = 0x03; 1725 break; 1726 case CX231XX_BOARD_CNXT_RDE_253S: 1727 case CX231XX_BOARD_CNXT_RDU_253S: 1728 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 1729 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 1730 func_mode = 0x01; 1731 break; 1732 default: 1733 func_mode = 0x01; 1734 } 1735 1736 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1737 func_mode, standard); 1738 1739 if (standard == DIF_USE_BASEBAND) { /* base band */ 1740 /* There is a different SRC_PHASE_INC value 1741 for baseband vs. DIF */ 1742 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1743 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1744 &dif_misc_ctrl_value); 1745 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1746 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1747 dif_misc_ctrl_value); 1748 } else if (standard & V4L2_STD_PAL_D) { 1749 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1750 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1751 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1752 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1753 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1754 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1755 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1756 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1757 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1758 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1759 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1760 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1761 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1762 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1763 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1764 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1765 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1766 DIF_AGC_IF_INT_CURRENT, 0, 31, 1767 0x26001700); 1768 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1769 DIF_AGC_RF_CURRENT, 0, 31, 1770 0x00002660); 1771 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1772 DIF_VIDEO_AGC_CTRL, 0, 31, 1773 0x72500800); 1774 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1775 DIF_VID_AUD_OVERRIDE, 0, 31, 1776 0x27000100); 1777 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1778 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1780 DIF_COMP_FLT_CTRL, 0, 31, 1781 0x00000000); 1782 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1783 DIF_SRC_PHASE_INC, 0, 31, 1784 0x1befbf06); 1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1786 DIF_SRC_GAIN_CONTROL, 0, 31, 1787 0x000035e8); 1788 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1789 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1790 /* Save the Spec Inversion value */ 1791 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1792 dif_misc_ctrl_value |= 0x3a023F11; 1793 } else if (standard & V4L2_STD_PAL_I) { 1794 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1795 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1796 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1797 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1799 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1800 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1801 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1802 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1803 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1805 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1806 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1807 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1808 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1809 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1810 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1811 DIF_AGC_IF_INT_CURRENT, 0, 31, 1812 0x26001700); 1813 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1814 DIF_AGC_RF_CURRENT, 0, 31, 1815 0x00002660); 1816 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1817 DIF_VIDEO_AGC_CTRL, 0, 31, 1818 0x72500800); 1819 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1820 DIF_VID_AUD_OVERRIDE, 0, 31, 1821 0x27000100); 1822 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1823 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1825 DIF_COMP_FLT_CTRL, 0, 31, 1826 0x00000000); 1827 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1828 DIF_SRC_PHASE_INC, 0, 31, 1829 0x1befbf06); 1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1831 DIF_SRC_GAIN_CONTROL, 0, 31, 1832 0x000035e8); 1833 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1834 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1835 /* Save the Spec Inversion value */ 1836 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1837 dif_misc_ctrl_value |= 0x3a033F11; 1838 } else if (standard & V4L2_STD_PAL_M) { 1839 /* improved Low Frequency Phase Noise */ 1840 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1841 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1842 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1843 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1844 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1845 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1846 0x26001700); 1847 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1848 0x00002660); 1849 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1850 0x72500800); 1851 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1852 0x27000100); 1853 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1854 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1855 0x009f50c1); 1856 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1857 0x1befbf06); 1858 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1859 0x000035e8); 1860 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1861 0x00000000); 1862 /* Save the Spec Inversion value */ 1863 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1864 dif_misc_ctrl_value |= 0x3A0A3F10; 1865 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1866 /* improved Low Frequency Phase Noise */ 1867 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1871 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1872 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1873 0x26001700); 1874 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1875 0x00002660); 1876 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1877 0x72500800); 1878 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1879 0x27000100); 1880 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1881 0x012c405d); 1882 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1883 0x009f50c1); 1884 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1885 0x1befbf06); 1886 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1887 0x000035e8); 1888 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1889 0x00000000); 1890 /* Save the Spec Inversion value */ 1891 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1892 dif_misc_ctrl_value = 0x3A093F10; 1893 } else if (standard & 1894 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1895 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1896 1897 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1898 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1899 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1900 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1901 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1902 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1903 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1904 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1905 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1906 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1907 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1908 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1909 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1910 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1911 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1912 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1913 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1914 DIF_AGC_IF_INT_CURRENT, 0, 31, 1915 0x26001700); 1916 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1917 DIF_AGC_RF_CURRENT, 0, 31, 1918 0x00002660); 1919 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1920 DIF_VID_AUD_OVERRIDE, 0, 31, 1921 0x27000100); 1922 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1923 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1924 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1925 DIF_COMP_FLT_CTRL, 0, 31, 1926 0x00000000); 1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1928 DIF_SRC_PHASE_INC, 0, 31, 1929 0x1befbf06); 1930 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1931 DIF_SRC_GAIN_CONTROL, 0, 31, 1932 0x000035e8); 1933 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1934 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1936 DIF_VIDEO_AGC_CTRL, 0, 31, 1937 0xf4000000); 1938 1939 /* Save the Spec Inversion value */ 1940 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1941 dif_misc_ctrl_value |= 0x3a023F11; 1942 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1943 /* Is it SECAM_L1? */ 1944 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1945 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1947 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1948 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1949 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1950 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1951 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1953 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1955 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1956 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1957 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1958 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1959 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1961 DIF_AGC_IF_INT_CURRENT, 0, 31, 1962 0x26001700); 1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1964 DIF_AGC_RF_CURRENT, 0, 31, 1965 0x00002660); 1966 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1967 DIF_VID_AUD_OVERRIDE, 0, 31, 1968 0x27000100); 1969 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1970 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1971 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1972 DIF_COMP_FLT_CTRL, 0, 31, 1973 0x00000000); 1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1975 DIF_SRC_PHASE_INC, 0, 31, 1976 0x1befbf06); 1977 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1978 DIF_SRC_GAIN_CONTROL, 0, 31, 1979 0x000035e8); 1980 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1981 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1983 DIF_VIDEO_AGC_CTRL, 0, 31, 1984 0xf2560000); 1985 1986 /* Save the Spec Inversion value */ 1987 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1988 dif_misc_ctrl_value |= 0x3a023F11; 1989 1990 } else if (standard & V4L2_STD_NTSC_M) { 1991 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 1992 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 1993 1994 /* For NTSC the centre frequency of video coming out of 1995 sidewinder is around 7.1MHz or 3.6MHz depending on the 1996 spectral inversion. so for a non spectrally inverted channel 1997 the pll freq word is 0x03420c49 1998 */ 1999 2000 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 2001 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 2002 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 2003 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 2004 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 2005 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 2006 0x26001700); 2007 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 2008 0x00002660); 2009 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 2010 0x04000800); 2011 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 2012 0x27000100); 2013 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 2014 2015 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 2016 0x009f50c1); 2017 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 2018 0x1befbf06); 2019 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 2020 0x000035e8); 2021 2022 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 2023 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 2024 0xC2262600); 2025 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 2026 2027 /* Save the Spec Inversion value */ 2028 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2029 dif_misc_ctrl_value |= 0x3a003F10; 2030 } else { 2031 /* default PAL BG */ 2032 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2033 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 2034 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2035 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 2036 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2037 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 2038 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2039 DIF_PLL_CTRL3, 0, 31, 0x00008800); 2040 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2041 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 2042 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2043 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 2044 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2045 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 2046 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2047 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 2048 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2049 DIF_AGC_IF_INT_CURRENT, 0, 31, 2050 0x26001700); 2051 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2052 DIF_AGC_RF_CURRENT, 0, 31, 2053 0x00002660); 2054 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2055 DIF_VIDEO_AGC_CTRL, 0, 31, 2056 0x72500800); 2057 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2058 DIF_VID_AUD_OVERRIDE, 0, 31, 2059 0x27000100); 2060 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2061 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2063 DIF_COMP_FLT_CTRL, 0, 31, 2064 0x00A653A8); 2065 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2066 DIF_SRC_PHASE_INC, 0, 31, 2067 0x1befbf06); 2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2069 DIF_SRC_GAIN_CONTROL, 0, 31, 2070 0x000035e8); 2071 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2072 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2073 /* Save the Spec Inversion value */ 2074 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2075 dif_misc_ctrl_value |= 0x3a013F11; 2076 } 2077 2078 /* The AGC values should be the same for all standards, 2079 AUD_SRC_SEL[19] should always be disabled */ 2080 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 2081 2082 /* It is still possible to get Set Standard calls even when we 2083 are in FM mode. 2084 This is done to override the value for FM. */ 2085 if (dev->active_mode == V4L2_TUNER_RADIO) 2086 dif_misc_ctrl_value = 0x7a080000; 2087 2088 /* Write the calculated value for misc ontrol register */ 2089 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 2090 2091 return status; 2092 } 2093 2094 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 2095 { 2096 int status = 0; 2097 u32 dwval; 2098 2099 /* Set the RF and IF k_agc values to 3 */ 2100 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2101 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2102 dwval |= 0x33000000; 2103 2104 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2105 2106 return status; 2107 } 2108 2109 int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 2110 { 2111 int status = 0; 2112 u32 dwval; 2113 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", 2114 dev->tuner_type); 2115 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2116 * SECAM L/B/D standards */ 2117 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2118 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2119 2120 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2121 V4L2_STD_SECAM_D)) { 2122 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2123 dwval &= ~FLD_DIF_IF_REF; 2124 dwval |= 0x88000300; 2125 } else 2126 dwval |= 0x88000000; 2127 } else { 2128 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2129 dwval &= ~FLD_DIF_IF_REF; 2130 dwval |= 0xCC000300; 2131 } else 2132 dwval |= 0x44000000; 2133 } 2134 2135 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2136 2137 return status == sizeof(dwval) ? 0 : -EIO; 2138 } 2139 2140 /****************************************************************************** 2141 * I 2 S - B L O C K C O N T R O L functions * 2142 ******************************************************************************/ 2143 int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 2144 { 2145 int status = 0; 2146 u32 value; 2147 2148 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2149 CH_PWR_CTRL1, 1, &value, 1); 2150 /* enables clock to delta-sigma and decimation filter */ 2151 value |= 0x80; 2152 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2153 CH_PWR_CTRL1, 1, value, 1); 2154 /* power up all channel */ 2155 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2156 CH_PWR_CTRL2, 1, 0x00, 1); 2157 2158 return status; 2159 } 2160 2161 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 2162 enum AV_MODE avmode) 2163 { 2164 int status = 0; 2165 u32 value = 0; 2166 2167 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 2168 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2169 CH_PWR_CTRL2, 1, &value, 1); 2170 value |= 0xfe; 2171 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2172 CH_PWR_CTRL2, 1, value, 1); 2173 } else { 2174 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2175 CH_PWR_CTRL2, 1, 0x00, 1); 2176 } 2177 2178 return status; 2179 } 2180 2181 /* set i2s_blk for audio input types */ 2182 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 2183 { 2184 int status = 0; 2185 2186 switch (audio_input) { 2187 case CX231XX_AMUX_LINE_IN: 2188 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2189 CH_PWR_CTRL2, 1, 0x00, 1); 2190 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2191 CH_PWR_CTRL1, 1, 0x80, 1); 2192 break; 2193 case CX231XX_AMUX_VIDEO: 2194 default: 2195 break; 2196 } 2197 2198 dev->ctl_ainput = audio_input; 2199 2200 return status; 2201 } 2202 2203 /****************************************************************************** 2204 * P O W E R C O N T R O L functions * 2205 ******************************************************************************/ 2206 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 2207 { 2208 u8 value[4] = { 0, 0, 0, 0 }; 2209 u32 tmp = 0; 2210 int status = 0; 2211 2212 if (dev->power_mode != mode) 2213 dev->power_mode = mode; 2214 else { 2215 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", 2216 mode); 2217 return 0; 2218 } 2219 2220 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2221 4); 2222 if (status < 0) 2223 return status; 2224 2225 tmp = le32_to_cpu(*((u32 *) value)); 2226 2227 switch (mode) { 2228 case POLARIS_AVMODE_ENXTERNAL_AV: 2229 2230 tmp &= (~PWR_MODE_MASK); 2231 2232 tmp |= PWR_AV_EN; 2233 value[0] = (u8) tmp; 2234 value[1] = (u8) (tmp >> 8); 2235 value[2] = (u8) (tmp >> 16); 2236 value[3] = (u8) (tmp >> 24); 2237 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2238 PWR_CTL_EN, value, 4); 2239 msleep(PWR_SLEEP_INTERVAL); 2240 2241 tmp |= PWR_ISO_EN; 2242 value[0] = (u8) tmp; 2243 value[1] = (u8) (tmp >> 8); 2244 value[2] = (u8) (tmp >> 16); 2245 value[3] = (u8) (tmp >> 24); 2246 status = 2247 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2248 value, 4); 2249 msleep(PWR_SLEEP_INTERVAL); 2250 2251 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 2252 value[0] = (u8) tmp; 2253 value[1] = (u8) (tmp >> 8); 2254 value[2] = (u8) (tmp >> 16); 2255 value[3] = (u8) (tmp >> 24); 2256 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2257 PWR_CTL_EN, value, 4); 2258 2259 /* reset state of xceive tuner */ 2260 dev->xc_fw_load_done = 0; 2261 break; 2262 2263 case POLARIS_AVMODE_ANALOGT_TV: 2264 2265 tmp |= PWR_DEMOD_EN; 2266 tmp |= (I2C_DEMOD_EN); 2267 value[0] = (u8) tmp; 2268 value[1] = (u8) (tmp >> 8); 2269 value[2] = (u8) (tmp >> 16); 2270 value[3] = (u8) (tmp >> 24); 2271 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2272 PWR_CTL_EN, value, 4); 2273 msleep(PWR_SLEEP_INTERVAL); 2274 2275 if (!(tmp & PWR_TUNER_EN)) { 2276 tmp |= (PWR_TUNER_EN); 2277 value[0] = (u8) tmp; 2278 value[1] = (u8) (tmp >> 8); 2279 value[2] = (u8) (tmp >> 16); 2280 value[3] = (u8) (tmp >> 24); 2281 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2282 PWR_CTL_EN, value, 4); 2283 msleep(PWR_SLEEP_INTERVAL); 2284 } 2285 2286 if (!(tmp & PWR_AV_EN)) { 2287 tmp |= PWR_AV_EN; 2288 value[0] = (u8) tmp; 2289 value[1] = (u8) (tmp >> 8); 2290 value[2] = (u8) (tmp >> 16); 2291 value[3] = (u8) (tmp >> 24); 2292 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2293 PWR_CTL_EN, value, 4); 2294 msleep(PWR_SLEEP_INTERVAL); 2295 } 2296 if (!(tmp & PWR_ISO_EN)) { 2297 tmp |= PWR_ISO_EN; 2298 value[0] = (u8) tmp; 2299 value[1] = (u8) (tmp >> 8); 2300 value[2] = (u8) (tmp >> 16); 2301 value[3] = (u8) (tmp >> 24); 2302 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2303 PWR_CTL_EN, value, 4); 2304 msleep(PWR_SLEEP_INTERVAL); 2305 } 2306 2307 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 2308 tmp |= POLARIS_AVMODE_ANALOGT_TV; 2309 value[0] = (u8) tmp; 2310 value[1] = (u8) (tmp >> 8); 2311 value[2] = (u8) (tmp >> 16); 2312 value[3] = (u8) (tmp >> 24); 2313 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2314 PWR_CTL_EN, value, 4); 2315 msleep(PWR_SLEEP_INTERVAL); 2316 } 2317 2318 if (dev->board.tuner_type != TUNER_ABSENT) { 2319 /* Enable tuner */ 2320 cx231xx_enable_i2c_port_3(dev, true); 2321 2322 /* reset the Tuner */ 2323 if (dev->board.tuner_gpio) 2324 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2325 2326 if (dev->cx231xx_reset_analog_tuner) 2327 dev->cx231xx_reset_analog_tuner(dev); 2328 } 2329 2330 break; 2331 2332 case POLARIS_AVMODE_DIGITAL: 2333 if (!(tmp & PWR_TUNER_EN)) { 2334 tmp |= (PWR_TUNER_EN); 2335 value[0] = (u8) tmp; 2336 value[1] = (u8) (tmp >> 8); 2337 value[2] = (u8) (tmp >> 16); 2338 value[3] = (u8) (tmp >> 24); 2339 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2340 PWR_CTL_EN, value, 4); 2341 msleep(PWR_SLEEP_INTERVAL); 2342 } 2343 if (!(tmp & PWR_AV_EN)) { 2344 tmp |= PWR_AV_EN; 2345 value[0] = (u8) tmp; 2346 value[1] = (u8) (tmp >> 8); 2347 value[2] = (u8) (tmp >> 16); 2348 value[3] = (u8) (tmp >> 24); 2349 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2350 PWR_CTL_EN, value, 4); 2351 msleep(PWR_SLEEP_INTERVAL); 2352 } 2353 if (!(tmp & PWR_ISO_EN)) { 2354 tmp |= PWR_ISO_EN; 2355 value[0] = (u8) tmp; 2356 value[1] = (u8) (tmp >> 8); 2357 value[2] = (u8) (tmp >> 16); 2358 value[3] = (u8) (tmp >> 24); 2359 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2360 PWR_CTL_EN, value, 4); 2361 msleep(PWR_SLEEP_INTERVAL); 2362 } 2363 2364 tmp &= (~PWR_AV_MODE); 2365 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; 2366 value[0] = (u8) tmp; 2367 value[1] = (u8) (tmp >> 8); 2368 value[2] = (u8) (tmp >> 16); 2369 value[3] = (u8) (tmp >> 24); 2370 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2371 PWR_CTL_EN, value, 4); 2372 msleep(PWR_SLEEP_INTERVAL); 2373 2374 if (!(tmp & PWR_DEMOD_EN)) { 2375 tmp |= PWR_DEMOD_EN; 2376 value[0] = (u8) tmp; 2377 value[1] = (u8) (tmp >> 8); 2378 value[2] = (u8) (tmp >> 16); 2379 value[3] = (u8) (tmp >> 24); 2380 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2381 PWR_CTL_EN, value, 4); 2382 msleep(PWR_SLEEP_INTERVAL); 2383 } 2384 2385 if (dev->board.tuner_type != TUNER_ABSENT) { 2386 /* 2387 * Enable tuner 2388 * Hauppauge Exeter seems to need to do something different! 2389 */ 2390 if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) 2391 cx231xx_enable_i2c_port_3(dev, false); 2392 else 2393 cx231xx_enable_i2c_port_3(dev, true); 2394 2395 /* reset the Tuner */ 2396 if (dev->board.tuner_gpio) 2397 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2398 2399 if (dev->cx231xx_reset_analog_tuner) 2400 dev->cx231xx_reset_analog_tuner(dev); 2401 } 2402 break; 2403 2404 default: 2405 break; 2406 } 2407 2408 msleep(PWR_SLEEP_INTERVAL); 2409 2410 /* For power saving, only enable Pwr_resetout_n 2411 when digital TV is selected. */ 2412 if (mode == POLARIS_AVMODE_DIGITAL) { 2413 tmp |= PWR_RESETOUT_EN; 2414 value[0] = (u8) tmp; 2415 value[1] = (u8) (tmp >> 8); 2416 value[2] = (u8) (tmp >> 16); 2417 value[3] = (u8) (tmp >> 24); 2418 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2419 PWR_CTL_EN, value, 4); 2420 msleep(PWR_SLEEP_INTERVAL); 2421 } 2422 2423 /* update power control for afe */ 2424 status = cx231xx_afe_update_power_control(dev, mode); 2425 2426 /* update power control for i2s_blk */ 2427 status = cx231xx_i2s_blk_update_power_control(dev, mode); 2428 2429 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2430 4); 2431 2432 return status; 2433 } 2434 2435 int cx231xx_power_suspend(struct cx231xx *dev) 2436 { 2437 u8 value[4] = { 0, 0, 0, 0 }; 2438 u32 tmp = 0; 2439 int status = 0; 2440 2441 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 2442 value, 4); 2443 if (status > 0) 2444 return status; 2445 2446 tmp = le32_to_cpu(*((u32 *) value)); 2447 tmp &= (~PWR_MODE_MASK); 2448 2449 value[0] = (u8) tmp; 2450 value[1] = (u8) (tmp >> 8); 2451 value[2] = (u8) (tmp >> 16); 2452 value[3] = (u8) (tmp >> 24); 2453 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2454 value, 4); 2455 2456 return status; 2457 } 2458 2459 /****************************************************************************** 2460 * S T R E A M C O N T R O L functions * 2461 ******************************************************************************/ 2462 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2463 { 2464 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2465 u32 tmp = 0; 2466 int status = 0; 2467 2468 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); 2469 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 2470 value, 4); 2471 if (status < 0) 2472 return status; 2473 2474 tmp = le32_to_cpu(*((u32 *) value)); 2475 tmp |= ep_mask; 2476 value[0] = (u8) tmp; 2477 value[1] = (u8) (tmp >> 8); 2478 value[2] = (u8) (tmp >> 16); 2479 value[3] = (u8) (tmp >> 24); 2480 2481 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2482 value, 4); 2483 2484 return status; 2485 } 2486 2487 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 2488 { 2489 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2490 u32 tmp = 0; 2491 int status = 0; 2492 2493 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); 2494 status = 2495 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2496 if (status < 0) 2497 return status; 2498 2499 tmp = le32_to_cpu(*((u32 *) value)); 2500 tmp &= (~ep_mask); 2501 value[0] = (u8) tmp; 2502 value[1] = (u8) (tmp >> 8); 2503 value[2] = (u8) (tmp >> 16); 2504 value[3] = (u8) (tmp >> 24); 2505 2506 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2507 value, 4); 2508 2509 return status; 2510 } 2511 2512 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2513 { 2514 int status = 0; 2515 u32 value = 0; 2516 u8 val[4] = { 0, 0, 0, 0 }; 2517 2518 if (dev->udev->speed == USB_SPEED_HIGH) { 2519 switch (media_type) { 2520 case Audio: 2521 cx231xx_info("%s: Audio enter HANC\n", __func__); 2522 status = 2523 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2524 break; 2525 2526 case Vbi: 2527 cx231xx_info("%s: set vanc registers\n", __func__); 2528 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2529 break; 2530 2531 case Sliced_cc: 2532 cx231xx_info("%s: set hanc registers\n", __func__); 2533 status = 2534 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2535 break; 2536 2537 case Raw_Video: 2538 cx231xx_info("%s: set video registers\n", __func__); 2539 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2540 break; 2541 2542 case TS1_serial_mode: 2543 cx231xx_info("%s: set ts1 registers", __func__); 2544 2545 if (dev->board.has_417) { 2546 cx231xx_info(" MPEG\n"); 2547 value &= 0xFFFFFFFC; 2548 value |= 0x3; 2549 2550 status = cx231xx_mode_register(dev, TS_MODE_REG, value); 2551 2552 val[0] = 0x04; 2553 val[1] = 0xA3; 2554 val[2] = 0x3B; 2555 val[3] = 0x00; 2556 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2557 TS1_CFG_REG, val, 4); 2558 2559 val[0] = 0x00; 2560 val[1] = 0x08; 2561 val[2] = 0x00; 2562 val[3] = 0x08; 2563 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2564 TS1_LENGTH_REG, val, 4); 2565 2566 } else { 2567 cx231xx_info(" BDA\n"); 2568 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2569 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); 2570 } 2571 break; 2572 2573 case TS1_parallel_mode: 2574 cx231xx_info("%s: set ts1 parallel mode registers\n", 2575 __func__); 2576 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2577 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2578 break; 2579 } 2580 } else { 2581 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2582 } 2583 2584 return status; 2585 } 2586 2587 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2588 { 2589 int rc = -1; 2590 u32 ep_mask = -1; 2591 struct pcb_config *pcb_config; 2592 2593 /* get EP for media type */ 2594 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2595 2596 if (pcb_config->config_num) { 2597 switch (media_type) { 2598 case Raw_Video: 2599 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2600 break; 2601 case Audio: 2602 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2603 break; 2604 case Vbi: 2605 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2606 break; 2607 case Sliced_cc: 2608 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2609 break; 2610 case TS1_serial_mode: 2611 case TS1_parallel_mode: 2612 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2613 break; 2614 case TS2: 2615 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2616 break; 2617 } 2618 } 2619 2620 if (start) { 2621 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2622 2623 if (rc < 0) 2624 return rc; 2625 2626 /* enable video capture */ 2627 if (ep_mask > 0) 2628 rc = cx231xx_start_stream(dev, ep_mask); 2629 } else { 2630 /* disable video capture */ 2631 if (ep_mask > 0) 2632 rc = cx231xx_stop_stream(dev, ep_mask); 2633 } 2634 2635 return rc; 2636 } 2637 EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2638 2639 /***************************************************************************** 2640 * G P I O B I T control functions * 2641 ******************************************************************************/ 2642 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val) 2643 { 2644 int status = 0; 2645 2646 gpio_val = cpu_to_le32(gpio_val); 2647 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); 2648 2649 return status; 2650 } 2651 2652 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val) 2653 { 2654 u32 tmp; 2655 int status = 0; 2656 2657 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); 2658 *gpio_val = le32_to_cpu(tmp); 2659 2660 return status; 2661 } 2662 2663 /* 2664 * cx231xx_set_gpio_direction 2665 * Sets the direction of the GPIO pin to input or output 2666 * 2667 * Parameters : 2668 * pin_number : The GPIO Pin number to program the direction for 2669 * from 0 to 31 2670 * pin_value : The Direction of the GPIO Pin under reference. 2671 * 0 = Input direction 2672 * 1 = Output direction 2673 */ 2674 int cx231xx_set_gpio_direction(struct cx231xx *dev, 2675 int pin_number, int pin_value) 2676 { 2677 int status = 0; 2678 u32 value = 0; 2679 2680 /* Check for valid pin_number - if 32 , bail out */ 2681 if (pin_number >= 32) 2682 return -EINVAL; 2683 2684 /* input */ 2685 if (pin_value == 0) 2686 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2687 else 2688 value = dev->gpio_dir | (1 << pin_number); 2689 2690 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val); 2691 2692 /* cache the value for future */ 2693 dev->gpio_dir = value; 2694 2695 return status; 2696 } 2697 2698 /* 2699 * cx231xx_set_gpio_value 2700 * Sets the value of the GPIO pin to Logic high or low. The Pin under 2701 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2702 * 2703 * Parameters : 2704 * pin_number : The GPIO Pin number to program the direction for 2705 * pin_value : The value of the GPIO Pin under reference. 2706 * 0 = set it to 0 2707 * 1 = set it to 1 2708 */ 2709 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2710 { 2711 int status = 0; 2712 u32 value = 0; 2713 2714 /* Check for valid pin_number - if 0xFF , bail out */ 2715 if (pin_number >= 32) 2716 return -EINVAL; 2717 2718 /* first do a sanity check - if the Pin is not output, make it output */ 2719 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2720 /* It was in input mode */ 2721 value = dev->gpio_dir | (1 << pin_number); 2722 dev->gpio_dir = value; 2723 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2724 dev->gpio_val); 2725 value = 0; 2726 } 2727 2728 if (pin_value == 0) 2729 value = dev->gpio_val & (~(1 << pin_number)); 2730 else 2731 value = dev->gpio_val | (1 << pin_number); 2732 2733 /* store the value */ 2734 dev->gpio_val = value; 2735 2736 /* toggle bit0 of GP_IO */ 2737 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2738 2739 return status; 2740 } 2741 2742 /***************************************************************************** 2743 * G P I O I2C related functions * 2744 ******************************************************************************/ 2745 int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2746 { 2747 int status = 0; 2748 2749 /* set SCL to output 1 ; set SDA to output 1 */ 2750 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2751 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2752 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2753 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2754 2755 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2756 if (status < 0) 2757 return -EINVAL; 2758 2759 /* set SCL to output 1; set SDA to output 0 */ 2760 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2761 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2762 2763 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2764 if (status < 0) 2765 return -EINVAL; 2766 2767 /* set SCL to output 0; set SDA to output 0 */ 2768 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2769 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2770 2771 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2772 if (status < 0) 2773 return -EINVAL; 2774 2775 return status; 2776 } 2777 2778 int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2779 { 2780 int status = 0; 2781 2782 /* set SCL to output 0; set SDA to output 0 */ 2783 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2784 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2785 2786 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2787 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2788 2789 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2790 if (status < 0) 2791 return -EINVAL; 2792 2793 /* set SCL to output 1; set SDA to output 0 */ 2794 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2795 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2796 2797 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2798 if (status < 0) 2799 return -EINVAL; 2800 2801 /* set SCL to input ,release SCL cable control 2802 set SDA to input ,release SDA cable control */ 2803 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2804 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2805 2806 status = 2807 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2808 if (status < 0) 2809 return -EINVAL; 2810 2811 return status; 2812 } 2813 2814 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2815 { 2816 int status = 0; 2817 u8 i; 2818 2819 /* set SCL to output ; set SDA to output */ 2820 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2821 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2822 2823 for (i = 0; i < 8; i++) { 2824 if (((data << i) & 0x80) == 0) { 2825 /* set SCL to output 0; set SDA to output 0 */ 2826 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2827 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2828 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2829 dev->gpio_val); 2830 2831 /* set SCL to output 1; set SDA to output 0 */ 2832 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2833 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2834 dev->gpio_val); 2835 2836 /* set SCL to output 0; set SDA to output 0 */ 2837 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2838 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2839 dev->gpio_val); 2840 } else { 2841 /* set SCL to output 0; set SDA to output 1 */ 2842 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2843 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2844 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2845 dev->gpio_val); 2846 2847 /* set SCL to output 1; set SDA to output 1 */ 2848 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2849 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2850 dev->gpio_val); 2851 2852 /* set SCL to output 0; set SDA to output 1 */ 2853 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2854 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2855 dev->gpio_val); 2856 } 2857 } 2858 return status; 2859 } 2860 2861 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 2862 { 2863 u8 value = 0; 2864 int status = 0; 2865 u32 gpio_logic_value = 0; 2866 u8 i; 2867 2868 /* read byte */ 2869 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2870 2871 /* set SCL to output 0; set SDA to input */ 2872 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2873 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2874 dev->gpio_val); 2875 2876 /* set SCL to output 1; set SDA to input */ 2877 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2878 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2879 dev->gpio_val); 2880 2881 /* get SDA data bit */ 2882 gpio_logic_value = dev->gpio_val; 2883 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2884 &dev->gpio_val); 2885 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2886 value |= (1 << (8 - i - 1)); 2887 2888 dev->gpio_val = gpio_logic_value; 2889 } 2890 2891 /* set SCL to output 0,finish the read latest SCL signal. 2892 !!!set SDA to input, never to modify SDA direction at 2893 the same times */ 2894 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2895 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2896 2897 /* store the value */ 2898 *buf = value & 0xff; 2899 2900 return status; 2901 } 2902 2903 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2904 { 2905 int status = 0; 2906 u32 gpio_logic_value = 0; 2907 int nCnt = 10; 2908 int nInit = nCnt; 2909 2910 /* clock stretch; set SCL to input; set SDA to input; 2911 get SCL value till SCL = 1 */ 2912 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2913 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2914 2915 gpio_logic_value = dev->gpio_val; 2916 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2917 2918 do { 2919 msleep(2); 2920 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2921 &dev->gpio_val); 2922 nCnt--; 2923 } while (((dev->gpio_val & 2924 (1 << dev->board.tuner_scl_gpio)) == 0) && 2925 (nCnt > 0)); 2926 2927 if (nCnt == 0) 2928 cx231xx_info("No ACK after %d msec -GPIO I2C failed!", 2929 nInit * 10); 2930 2931 /* 2932 * readAck 2933 * through clock stretch, slave has given a SCL signal, 2934 * so the SDA data can be directly read. 2935 */ 2936 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val); 2937 2938 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2939 dev->gpio_val = gpio_logic_value; 2940 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2941 status = 0; 2942 } else { 2943 dev->gpio_val = gpio_logic_value; 2944 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2945 } 2946 2947 /* read SDA end, set the SCL to output 0, after this operation, 2948 SDA direction can be changed. */ 2949 dev->gpio_val = gpio_logic_value; 2950 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2951 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2952 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2953 2954 return status; 2955 } 2956 2957 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2958 { 2959 int status = 0; 2960 2961 /* set SDA to ouput */ 2962 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2963 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2964 2965 /* set SCL = 0 (output); set SDA = 0 (output) */ 2966 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2967 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2968 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2969 2970 /* set SCL = 1 (output); set SDA = 0 (output) */ 2971 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2972 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2973 2974 /* set SCL = 0 (output); set SDA = 0 (output) */ 2975 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2976 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2977 2978 /* set SDA to input,and then the slave will read data from SDA. */ 2979 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2980 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2981 2982 return status; 2983 } 2984 2985 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 2986 { 2987 int status = 0; 2988 2989 /* set scl to output ; set sda to input */ 2990 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2991 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2992 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2993 2994 /* set scl to output 0; set sda to input */ 2995 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2996 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2997 2998 /* set scl to output 1; set sda to input */ 2999 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 3000 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3001 3002 return status; 3003 } 3004 3005 /***************************************************************************** 3006 * G P I O I2C related functions * 3007 ******************************************************************************/ 3008 /* cx231xx_gpio_i2c_read 3009 * Function to read data from gpio based I2C interface 3010 */ 3011 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3012 { 3013 int status = 0; 3014 int i = 0; 3015 3016 /* get the lock */ 3017 mutex_lock(&dev->gpio_i2c_lock); 3018 3019 /* start */ 3020 status = cx231xx_gpio_i2c_start(dev); 3021 3022 /* write dev_addr */ 3023 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 3024 3025 /* readAck */ 3026 status = cx231xx_gpio_i2c_read_ack(dev); 3027 3028 /* read data */ 3029 for (i = 0; i < len; i++) { 3030 /* read data */ 3031 buf[i] = 0; 3032 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 3033 3034 if ((i + 1) != len) { 3035 /* only do write ack if we more length */ 3036 status = cx231xx_gpio_i2c_write_ack(dev); 3037 } 3038 } 3039 3040 /* write NAK - inform reads are complete */ 3041 status = cx231xx_gpio_i2c_write_nak(dev); 3042 3043 /* write end */ 3044 status = cx231xx_gpio_i2c_end(dev); 3045 3046 /* release the lock */ 3047 mutex_unlock(&dev->gpio_i2c_lock); 3048 3049 return status; 3050 } 3051 3052 /* cx231xx_gpio_i2c_write 3053 * Function to write data to gpio based I2C interface 3054 */ 3055 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3056 { 3057 int i = 0; 3058 3059 /* get the lock */ 3060 mutex_lock(&dev->gpio_i2c_lock); 3061 3062 /* start */ 3063 cx231xx_gpio_i2c_start(dev); 3064 3065 /* write dev_addr */ 3066 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 3067 3068 /* read Ack */ 3069 cx231xx_gpio_i2c_read_ack(dev); 3070 3071 for (i = 0; i < len; i++) { 3072 /* Write data */ 3073 cx231xx_gpio_i2c_write_byte(dev, buf[i]); 3074 3075 /* read Ack */ 3076 cx231xx_gpio_i2c_read_ack(dev); 3077 } 3078 3079 /* write End */ 3080 cx231xx_gpio_i2c_end(dev); 3081 3082 /* release the lock */ 3083 mutex_unlock(&dev->gpio_i2c_lock); 3084 3085 return 0; 3086 } 3087