1 /* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #include "cx231xx.h" 26 #include <linux/init.h> 27 #include <linux/list.h> 28 #include <linux/module.h> 29 #include <linux/kernel.h> 30 #include <linux/bitmap.h> 31 #include <linux/i2c.h> 32 #include <linux/mm.h> 33 #include <linux/mutex.h> 34 #include <media/tuner.h> 35 36 #include <media/v4l2-common.h> 37 #include <media/v4l2-ioctl.h> 38 39 #include "cx231xx-dif.h" 40 41 #define TUNER_MODE_FM_RADIO 0 42 /****************************************************************************** 43 -: BLOCK ARRANGEMENT :- 44 I2S block ----------------------| 45 [I2S audio] | 46 | 47 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 48 [video & audio] | [Audio] 49 | 50 |-> Cx25840 --> Video 51 [Video] 52 53 *******************************************************************************/ 54 /****************************************************************************** 55 * VERVE REGISTER * 56 * * 57 ******************************************************************************/ 58 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 59 { 60 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 61 saddr, 1, data, 1); 62 } 63 64 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 65 { 66 int status; 67 u32 temp = 0; 68 69 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 70 saddr, 1, &temp, 1); 71 *data = (u8) temp; 72 return status; 73 } 74 void initGPIO(struct cx231xx *dev) 75 { 76 u32 _gpio_direction = 0; 77 u32 value = 0; 78 u8 val = 0; 79 80 _gpio_direction = _gpio_direction & 0xFC0003FF; 81 _gpio_direction = _gpio_direction | 0x03FDFC00; 82 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 83 84 verve_read_byte(dev, 0x07, &val); 85 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 86 verve_write_byte(dev, 0x07, 0xF4); 87 verve_read_byte(dev, 0x07, &val); 88 dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 89 90 cx231xx_capture_start(dev, 1, Vbi); 91 92 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 93 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 94 95 } 96 void uninitGPIO(struct cx231xx *dev) 97 { 98 u8 value[4] = { 0, 0, 0, 0 }; 99 100 cx231xx_capture_start(dev, 0, Vbi); 101 verve_write_byte(dev, 0x07, 0x14); 102 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 103 0x68, value, 4); 104 } 105 106 /****************************************************************************** 107 * A F E - B L O C K C O N T R O L functions * 108 * [ANALOG FRONT END] * 109 ******************************************************************************/ 110 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 111 { 112 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 113 saddr, 2, data, 1); 114 } 115 116 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 117 { 118 int status; 119 u32 temp = 0; 120 121 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 122 saddr, 2, &temp, 1); 123 *data = (u8) temp; 124 return status; 125 } 126 127 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 128 { 129 int status = 0; 130 u8 temp = 0; 131 u8 afe_power_status = 0; 132 int i = 0; 133 134 /* super block initialize */ 135 temp = (u8) (ref_count & 0xff); 136 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 137 if (status < 0) 138 return status; 139 140 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 141 if (status < 0) 142 return status; 143 144 temp = (u8) ((ref_count & 0x300) >> 8); 145 temp |= 0x40; 146 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 147 if (status < 0) 148 return status; 149 150 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 151 if (status < 0) 152 return status; 153 154 /* enable pll */ 155 while (afe_power_status != 0x18) { 156 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 157 if (status < 0) { 158 dev_dbg(dev->dev, 159 "%s: Init Super Block failed in send cmd\n", 160 __func__); 161 break; 162 } 163 164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 165 afe_power_status &= 0xff; 166 if (status < 0) { 167 dev_dbg(dev->dev, 168 "%s: Init Super Block failed in receive cmd\n", 169 __func__); 170 break; 171 } 172 i++; 173 if (i == 10) { 174 dev_dbg(dev->dev, 175 "%s: Init Super Block force break in loop !!!!\n", 176 __func__); 177 status = -1; 178 break; 179 } 180 } 181 182 if (status < 0) 183 return status; 184 185 /* start tuning filter */ 186 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 187 if (status < 0) 188 return status; 189 190 msleep(5); 191 192 /* exit tuning */ 193 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 194 195 return status; 196 } 197 198 int cx231xx_afe_init_channels(struct cx231xx *dev) 199 { 200 int status = 0; 201 202 /* power up all 3 channels, clear pd_buffer */ 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 205 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 206 207 /* Enable quantizer calibration */ 208 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 209 210 /* channel initialize, force modulator (fb) reset */ 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 213 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 214 215 /* start quantilizer calibration */ 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 218 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 219 msleep(5); 220 221 /* exit modulator (fb) reset */ 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 224 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 225 226 /* enable the pre_clamp in each channel for single-ended input */ 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 229 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 230 231 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 233 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 235 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 236 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 237 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 238 239 /* dynamic element matching off */ 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 242 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 243 244 return status; 245 } 246 247 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 248 { 249 u8 c_value = 0; 250 int status = 0; 251 252 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 253 c_value &= (~(0x50)); 254 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 255 256 return status; 257 } 258 259 /* 260 The Analog Front End in Cx231xx has 3 channels. These 261 channels are used to share between different inputs 262 like tuner, s-video and composite inputs. 263 264 channel 1 ----- pin 1 to pin4(in reg is 1-4) 265 channel 2 ----- pin 5 to pin8(in reg is 5-8) 266 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 267 */ 268 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 269 { 270 u8 ch1_setting = (u8) input_mux; 271 u8 ch2_setting = (u8) (input_mux >> 8); 272 u8 ch3_setting = (u8) (input_mux >> 16); 273 int status = 0; 274 u8 value = 0; 275 276 if (ch1_setting != 0) { 277 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 278 value &= ~INPUT_SEL_MASK; 279 value |= (ch1_setting - 1) << 4; 280 value &= 0xff; 281 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 282 } 283 284 if (ch2_setting != 0) { 285 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 286 value &= ~INPUT_SEL_MASK; 287 value |= (ch2_setting - 1) << 4; 288 value &= 0xff; 289 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 290 } 291 292 /* For ch3_setting, the value to put in the register is 293 7 less than the input number */ 294 if (ch3_setting != 0) { 295 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 296 value &= ~INPUT_SEL_MASK; 297 value |= (ch3_setting - 1) << 4; 298 value &= 0xff; 299 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 300 } 301 302 return status; 303 } 304 305 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 306 { 307 int status = 0; 308 309 /* 310 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 311 * Currently, only baseband works. 312 */ 313 314 switch (mode) { 315 case AFE_MODE_LOW_IF: 316 cx231xx_Setup_AFE_for_LowIF(dev); 317 break; 318 case AFE_MODE_BASEBAND: 319 status = cx231xx_afe_setup_AFE_for_baseband(dev); 320 break; 321 case AFE_MODE_EU_HI_IF: 322 /* SetupAFEforEuHiIF(); */ 323 break; 324 case AFE_MODE_US_HI_IF: 325 /* SetupAFEforUsHiIF(); */ 326 break; 327 case AFE_MODE_JAPAN_HI_IF: 328 /* SetupAFEforJapanHiIF(); */ 329 break; 330 } 331 332 if ((mode != dev->afe_mode) && 333 (dev->video_input == CX231XX_VMUX_TELEVISION)) 334 status = cx231xx_afe_adjust_ref_count(dev, 335 CX231XX_VMUX_TELEVISION); 336 337 dev->afe_mode = mode; 338 339 return status; 340 } 341 342 int cx231xx_afe_update_power_control(struct cx231xx *dev, 343 enum AV_MODE avmode) 344 { 345 u8 afe_power_status = 0; 346 int status = 0; 347 348 switch (dev->model) { 349 case CX231XX_BOARD_CNXT_CARRAERA: 350 case CX231XX_BOARD_CNXT_RDE_250: 351 case CX231XX_BOARD_CNXT_SHELBY: 352 case CX231XX_BOARD_CNXT_RDU_250: 353 case CX231XX_BOARD_CNXT_RDE_253S: 354 case CX231XX_BOARD_CNXT_RDU_253S: 355 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 356 case CX231XX_BOARD_HAUPPAUGE_EXETER: 357 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx: 358 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 359 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 360 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 361 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 362 case CX231XX_BOARD_OTG102: 363 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 364 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 365 FLD_PWRDN_ENABLE_PLL)) { 366 status = afe_write_byte(dev, SUP_BLK_PWRDN, 367 FLD_PWRDN_TUNING_BIAS | 368 FLD_PWRDN_ENABLE_PLL); 369 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 370 &afe_power_status); 371 if (status < 0) 372 break; 373 } 374 375 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 376 0x00); 377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 378 0x00); 379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 380 0x00); 381 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 382 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 383 0x70); 384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 385 0x70); 386 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 387 0x70); 388 389 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 390 &afe_power_status); 391 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 392 FLD_PWRDN_PD_BIAS | 393 FLD_PWRDN_PD_TUNECK; 394 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 395 afe_power_status); 396 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 397 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 398 FLD_PWRDN_ENABLE_PLL)) { 399 status = afe_write_byte(dev, SUP_BLK_PWRDN, 400 FLD_PWRDN_TUNING_BIAS | 401 FLD_PWRDN_ENABLE_PLL); 402 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 403 &afe_power_status); 404 if (status < 0) 405 break; 406 } 407 408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 409 0x00); 410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 411 0x00); 412 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 413 0x00); 414 } else { 415 dev_dbg(dev->dev, "Invalid AV mode input\n"); 416 status = -1; 417 } 418 break; 419 default: 420 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 421 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 422 FLD_PWRDN_ENABLE_PLL)) { 423 status = afe_write_byte(dev, SUP_BLK_PWRDN, 424 FLD_PWRDN_TUNING_BIAS | 425 FLD_PWRDN_ENABLE_PLL); 426 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 427 &afe_power_status); 428 if (status < 0) 429 break; 430 } 431 432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 433 0x40); 434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 435 0x40); 436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 437 0x00); 438 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 439 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 440 0x70); 441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 442 0x70); 443 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 444 0x70); 445 446 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 447 &afe_power_status); 448 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 449 FLD_PWRDN_PD_BIAS | 450 FLD_PWRDN_PD_TUNECK; 451 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 452 afe_power_status); 453 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 454 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 455 FLD_PWRDN_ENABLE_PLL)) { 456 status = afe_write_byte(dev, SUP_BLK_PWRDN, 457 FLD_PWRDN_TUNING_BIAS | 458 FLD_PWRDN_ENABLE_PLL); 459 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 460 &afe_power_status); 461 if (status < 0) 462 break; 463 } 464 465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 466 0x00); 467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 468 0x00); 469 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 470 0x40); 471 } else { 472 dev_dbg(dev->dev, "Invalid AV mode input\n"); 473 status = -1; 474 } 475 } /* switch */ 476 477 return status; 478 } 479 480 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 481 { 482 u8 input_mode = 0; 483 u8 ntf_mode = 0; 484 int status = 0; 485 486 dev->video_input = video_input; 487 488 if (video_input == CX231XX_VMUX_TELEVISION) { 489 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 490 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 491 &ntf_mode); 492 } else { 493 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 494 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 495 &ntf_mode); 496 } 497 498 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 499 500 switch (input_mode) { 501 case SINGLE_ENDED: 502 dev->afe_ref_count = 0x23C; 503 break; 504 case LOW_IF: 505 dev->afe_ref_count = 0x24C; 506 break; 507 case EU_IF: 508 dev->afe_ref_count = 0x258; 509 break; 510 case US_IF: 511 dev->afe_ref_count = 0x260; 512 break; 513 default: 514 break; 515 } 516 517 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 518 519 return status; 520 } 521 522 /****************************************************************************** 523 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 524 ******************************************************************************/ 525 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 526 { 527 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 528 saddr, 2, data, 1); 529 } 530 531 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 532 { 533 int status; 534 u32 temp = 0; 535 536 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 537 saddr, 2, &temp, 1); 538 *data = (u8) temp; 539 return status; 540 } 541 542 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 543 { 544 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 545 saddr, 2, data, 4); 546 } 547 548 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 549 { 550 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 551 saddr, 2, data, 4); 552 } 553 int cx231xx_check_fw(struct cx231xx *dev) 554 { 555 u8 temp = 0; 556 int status = 0; 557 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 558 if (status < 0) 559 return status; 560 else 561 return temp; 562 563 } 564 565 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 566 { 567 int status = 0; 568 569 switch (INPUT(input)->type) { 570 case CX231XX_VMUX_COMPOSITE1: 571 case CX231XX_VMUX_SVIDEO: 572 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 573 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 574 /* External AV */ 575 status = cx231xx_set_power_mode(dev, 576 POLARIS_AVMODE_ENXTERNAL_AV); 577 if (status < 0) { 578 dev_err(dev->dev, 579 "%s: Failed to set Power - errCode [%d]!\n", 580 __func__, status); 581 return status; 582 } 583 } 584 status = cx231xx_set_decoder_video_input(dev, 585 INPUT(input)->type, 586 INPUT(input)->vmux); 587 break; 588 case CX231XX_VMUX_TELEVISION: 589 case CX231XX_VMUX_CABLE: 590 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 591 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 592 /* Tuner */ 593 status = cx231xx_set_power_mode(dev, 594 POLARIS_AVMODE_ANALOGT_TV); 595 if (status < 0) { 596 dev_err(dev->dev, 597 "%s: Failed to set Power - errCode [%d]!\n", 598 __func__, status); 599 return status; 600 } 601 } 602 if (dev->tuner_type == TUNER_NXP_TDA18271) 603 status = cx231xx_set_decoder_video_input(dev, 604 CX231XX_VMUX_TELEVISION, 605 INPUT(input)->vmux); 606 else 607 status = cx231xx_set_decoder_video_input(dev, 608 CX231XX_VMUX_COMPOSITE1, 609 INPUT(input)->vmux); 610 611 break; 612 default: 613 dev_err(dev->dev, "%s: Unknown Input %d !\n", 614 __func__, INPUT(input)->type); 615 break; 616 } 617 618 /* save the selection */ 619 dev->video_input = input; 620 621 return status; 622 } 623 624 int cx231xx_set_decoder_video_input(struct cx231xx *dev, 625 u8 pin_type, u8 input) 626 { 627 int status = 0; 628 u32 value = 0; 629 630 if (pin_type != dev->video_input) { 631 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 632 if (status < 0) { 633 dev_err(dev->dev, 634 "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n", 635 __func__, status); 636 return status; 637 } 638 } 639 640 /* call afe block to set video inputs */ 641 status = cx231xx_afe_set_input_mux(dev, input); 642 if (status < 0) { 643 dev_err(dev->dev, 644 "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n", 645 __func__, status); 646 return status; 647 } 648 649 switch (pin_type) { 650 case CX231XX_VMUX_COMPOSITE1: 651 status = vid_blk_read_word(dev, AFE_CTRL, &value); 652 value |= (0 << 13) | (1 << 4); 653 value &= ~(1 << 5); 654 655 /* set [24:23] [22:15] to 0 */ 656 value &= (~(0x1ff8000)); 657 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 658 value |= 0x1000000; 659 status = vid_blk_write_word(dev, AFE_CTRL, value); 660 661 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 662 value |= (1 << 7); 663 status = vid_blk_write_word(dev, OUT_CTRL1, value); 664 665 /* Set output mode */ 666 status = cx231xx_read_modify_write_i2c_dword(dev, 667 VID_BLK_I2C_ADDRESS, 668 OUT_CTRL1, 669 FLD_OUT_MODE, 670 dev->board.output_mode); 671 672 /* Tell DIF object to go to baseband mode */ 673 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 674 if (status < 0) { 675 dev_err(dev->dev, 676 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 677 __func__, status); 678 return status; 679 } 680 681 /* Read the DFE_CTRL1 register */ 682 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 683 684 /* enable the VBI_GATE_EN */ 685 value |= FLD_VBI_GATE_EN; 686 687 /* Enable the auto-VGA enable */ 688 value |= FLD_VGA_AUTO_EN; 689 690 /* Write it back */ 691 status = vid_blk_write_word(dev, DFE_CTRL1, value); 692 693 /* Disable auto config of registers */ 694 status = cx231xx_read_modify_write_i2c_dword(dev, 695 VID_BLK_I2C_ADDRESS, 696 MODE_CTRL, FLD_ACFG_DIS, 697 cx231xx_set_field(FLD_ACFG_DIS, 1)); 698 699 /* Set CVBS input mode */ 700 status = cx231xx_read_modify_write_i2c_dword(dev, 701 VID_BLK_I2C_ADDRESS, 702 MODE_CTRL, FLD_INPUT_MODE, 703 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 704 break; 705 case CX231XX_VMUX_SVIDEO: 706 /* Disable the use of DIF */ 707 708 status = vid_blk_read_word(dev, AFE_CTRL, &value); 709 710 /* set [24:23] [22:15] to 0 */ 711 value &= (~(0x1ff8000)); 712 /* set FUNC_MODE[24:23] = 2 713 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 714 value |= 0x1000010; 715 status = vid_blk_write_word(dev, AFE_CTRL, value); 716 717 /* Tell DIF object to go to baseband mode */ 718 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 719 if (status < 0) { 720 dev_err(dev->dev, 721 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 722 __func__, status); 723 return status; 724 } 725 726 /* Read the DFE_CTRL1 register */ 727 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 728 729 /* enable the VBI_GATE_EN */ 730 value |= FLD_VBI_GATE_EN; 731 732 /* Enable the auto-VGA enable */ 733 value |= FLD_VGA_AUTO_EN; 734 735 /* Write it back */ 736 status = vid_blk_write_word(dev, DFE_CTRL1, value); 737 738 /* Disable auto config of registers */ 739 status = cx231xx_read_modify_write_i2c_dword(dev, 740 VID_BLK_I2C_ADDRESS, 741 MODE_CTRL, FLD_ACFG_DIS, 742 cx231xx_set_field(FLD_ACFG_DIS, 1)); 743 744 /* Set YC input mode */ 745 status = cx231xx_read_modify_write_i2c_dword(dev, 746 VID_BLK_I2C_ADDRESS, 747 MODE_CTRL, 748 FLD_INPUT_MODE, 749 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 750 751 /* Chroma to ADC2 */ 752 status = vid_blk_read_word(dev, AFE_CTRL, &value); 753 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 754 755 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 756 This sets them to use video 757 rather than audio. Only one of the two will be in use. */ 758 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 759 760 status = vid_blk_write_word(dev, AFE_CTRL, value); 761 762 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 763 break; 764 case CX231XX_VMUX_TELEVISION: 765 case CX231XX_VMUX_CABLE: 766 default: 767 /* TODO: Test if this is also needed for xc2028/xc3028 */ 768 if (dev->board.tuner_type == TUNER_XC5000) { 769 /* Disable the use of DIF */ 770 771 status = vid_blk_read_word(dev, AFE_CTRL, &value); 772 value |= (0 << 13) | (1 << 4); 773 value &= ~(1 << 5); 774 775 /* set [24:23] [22:15] to 0 */ 776 value &= (~(0x1FF8000)); 777 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 778 value |= 0x1000000; 779 status = vid_blk_write_word(dev, AFE_CTRL, value); 780 781 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 782 value |= (1 << 7); 783 status = vid_blk_write_word(dev, OUT_CTRL1, value); 784 785 /* Set output mode */ 786 status = cx231xx_read_modify_write_i2c_dword(dev, 787 VID_BLK_I2C_ADDRESS, 788 OUT_CTRL1, FLD_OUT_MODE, 789 dev->board.output_mode); 790 791 /* Tell DIF object to go to baseband mode */ 792 status = cx231xx_dif_set_standard(dev, 793 DIF_USE_BASEBAND); 794 if (status < 0) { 795 dev_err(dev->dev, 796 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 797 __func__, status); 798 return status; 799 } 800 801 /* Read the DFE_CTRL1 register */ 802 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 803 804 /* enable the VBI_GATE_EN */ 805 value |= FLD_VBI_GATE_EN; 806 807 /* Enable the auto-VGA enable */ 808 value |= FLD_VGA_AUTO_EN; 809 810 /* Write it back */ 811 status = vid_blk_write_word(dev, DFE_CTRL1, value); 812 813 /* Disable auto config of registers */ 814 status = cx231xx_read_modify_write_i2c_dword(dev, 815 VID_BLK_I2C_ADDRESS, 816 MODE_CTRL, FLD_ACFG_DIS, 817 cx231xx_set_field(FLD_ACFG_DIS, 1)); 818 819 /* Set CVBS input mode */ 820 status = cx231xx_read_modify_write_i2c_dword(dev, 821 VID_BLK_I2C_ADDRESS, 822 MODE_CTRL, FLD_INPUT_MODE, 823 cx231xx_set_field(FLD_INPUT_MODE, 824 INPUT_MODE_CVBS_0)); 825 } else { 826 /* Enable the DIF for the tuner */ 827 828 /* Reinitialize the DIF */ 829 status = cx231xx_dif_set_standard(dev, dev->norm); 830 if (status < 0) { 831 dev_err(dev->dev, 832 "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 833 __func__, status); 834 return status; 835 } 836 837 /* Make sure bypass is cleared */ 838 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 839 840 /* Clear the bypass bit */ 841 value &= ~FLD_DIF_DIF_BYPASS; 842 843 /* Enable the use of the DIF block */ 844 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 845 846 /* Read the DFE_CTRL1 register */ 847 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 848 849 /* Disable the VBI_GATE_EN */ 850 value &= ~FLD_VBI_GATE_EN; 851 852 /* Enable the auto-VGA enable, AGC, and 853 set the skip count to 2 */ 854 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 855 856 /* Write it back */ 857 status = vid_blk_write_word(dev, DFE_CTRL1, value); 858 859 /* Wait until AGC locks up */ 860 msleep(1); 861 862 /* Disable the auto-VGA enable AGC */ 863 value &= ~(FLD_VGA_AUTO_EN); 864 865 /* Write it back */ 866 status = vid_blk_write_word(dev, DFE_CTRL1, value); 867 868 /* Enable Polaris B0 AGC output */ 869 status = vid_blk_read_word(dev, PIN_CTRL, &value); 870 value |= (FLD_OEF_AGC_RF) | 871 (FLD_OEF_AGC_IFVGA) | 872 (FLD_OEF_AGC_IF); 873 status = vid_blk_write_word(dev, PIN_CTRL, value); 874 875 /* Set output mode */ 876 status = cx231xx_read_modify_write_i2c_dword(dev, 877 VID_BLK_I2C_ADDRESS, 878 OUT_CTRL1, FLD_OUT_MODE, 879 dev->board.output_mode); 880 881 /* Disable auto config of registers */ 882 status = cx231xx_read_modify_write_i2c_dword(dev, 883 VID_BLK_I2C_ADDRESS, 884 MODE_CTRL, FLD_ACFG_DIS, 885 cx231xx_set_field(FLD_ACFG_DIS, 1)); 886 887 /* Set CVBS input mode */ 888 status = cx231xx_read_modify_write_i2c_dword(dev, 889 VID_BLK_I2C_ADDRESS, 890 MODE_CTRL, FLD_INPUT_MODE, 891 cx231xx_set_field(FLD_INPUT_MODE, 892 INPUT_MODE_CVBS_0)); 893 894 /* Set some bits in AFE_CTRL so that channel 2 or 3 895 * is ready to receive audio */ 896 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 897 /* Clear droop comp (bit 19-20) */ 898 /* Set VGA_SEL (for audio control) (bit 7-8) */ 899 status = vid_blk_read_word(dev, AFE_CTRL, &value); 900 901 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 902 value &= (~(FLD_FUNC_MODE)); 903 value |= 0x800000; 904 905 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 906 907 status = vid_blk_write_word(dev, AFE_CTRL, value); 908 909 if (dev->tuner_type == TUNER_NXP_TDA18271) { 910 status = vid_blk_read_word(dev, PIN_CTRL, 911 &value); 912 status = vid_blk_write_word(dev, PIN_CTRL, 913 (value & 0xFFFFFFEF)); 914 } 915 916 break; 917 918 } 919 break; 920 } 921 922 /* Set raw VBI mode */ 923 status = cx231xx_read_modify_write_i2c_dword(dev, 924 VID_BLK_I2C_ADDRESS, 925 OUT_CTRL1, FLD_VBIHACTRAW_EN, 926 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 927 928 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 929 if (value & 0x02) { 930 value |= (1 << 19); 931 status = vid_blk_write_word(dev, OUT_CTRL1, value); 932 } 933 934 return status; 935 } 936 937 void cx231xx_enable656(struct cx231xx *dev) 938 { 939 u8 temp = 0; 940 /*enable TS1 data[0:7] as output to export 656*/ 941 942 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 943 944 /*enable TS1 clock as output to export 656*/ 945 946 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 947 temp = temp|0x04; 948 949 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 950 } 951 EXPORT_SYMBOL_GPL(cx231xx_enable656); 952 953 void cx231xx_disable656(struct cx231xx *dev) 954 { 955 u8 temp = 0; 956 957 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 958 959 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 960 temp = temp&0xFB; 961 962 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 963 } 964 EXPORT_SYMBOL_GPL(cx231xx_disable656); 965 966 /* 967 * Handle any video-mode specific overrides that are different 968 * on a per video standards basis after touching the MODE_CTRL 969 * register which resets many values for autodetect 970 */ 971 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 972 { 973 int status = 0; 974 975 dev_dbg(dev->dev, "%s: 0x%x\n", 976 __func__, (unsigned int)dev->norm); 977 978 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 979 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 980 981 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 982 dev_dbg(dev->dev, "%s: NTSC\n", __func__); 983 984 /* Move the close caption lines out of active video, 985 adjust the active video start point */ 986 status = cx231xx_read_modify_write_i2c_dword(dev, 987 VID_BLK_I2C_ADDRESS, 988 VERT_TIM_CTRL, 989 FLD_VBLANK_CNT, 0x18); 990 status = cx231xx_read_modify_write_i2c_dword(dev, 991 VID_BLK_I2C_ADDRESS, 992 VERT_TIM_CTRL, 993 FLD_VACTIVE_CNT, 994 0x1E7000); 995 status = cx231xx_read_modify_write_i2c_dword(dev, 996 VID_BLK_I2C_ADDRESS, 997 VERT_TIM_CTRL, 998 FLD_V656BLANK_CNT, 999 0x1C000000); 1000 1001 status = cx231xx_read_modify_write_i2c_dword(dev, 1002 VID_BLK_I2C_ADDRESS, 1003 HORIZ_TIM_CTRL, 1004 FLD_HBLANK_CNT, 1005 cx231xx_set_field 1006 (FLD_HBLANK_CNT, 0x79)); 1007 1008 } else if (dev->norm & V4L2_STD_SECAM) { 1009 dev_dbg(dev->dev, "%s: SECAM\n", __func__); 1010 status = cx231xx_read_modify_write_i2c_dword(dev, 1011 VID_BLK_I2C_ADDRESS, 1012 VERT_TIM_CTRL, 1013 FLD_VBLANK_CNT, 0x20); 1014 status = cx231xx_read_modify_write_i2c_dword(dev, 1015 VID_BLK_I2C_ADDRESS, 1016 VERT_TIM_CTRL, 1017 FLD_VACTIVE_CNT, 1018 cx231xx_set_field 1019 (FLD_VACTIVE_CNT, 1020 0x244)); 1021 status = cx231xx_read_modify_write_i2c_dword(dev, 1022 VID_BLK_I2C_ADDRESS, 1023 VERT_TIM_CTRL, 1024 FLD_V656BLANK_CNT, 1025 cx231xx_set_field 1026 (FLD_V656BLANK_CNT, 1027 0x24)); 1028 /* Adjust the active video horizontal start point */ 1029 status = cx231xx_read_modify_write_i2c_dword(dev, 1030 VID_BLK_I2C_ADDRESS, 1031 HORIZ_TIM_CTRL, 1032 FLD_HBLANK_CNT, 1033 cx231xx_set_field 1034 (FLD_HBLANK_CNT, 0x85)); 1035 } else { 1036 dev_dbg(dev->dev, "%s: PAL\n", __func__); 1037 status = cx231xx_read_modify_write_i2c_dword(dev, 1038 VID_BLK_I2C_ADDRESS, 1039 VERT_TIM_CTRL, 1040 FLD_VBLANK_CNT, 0x20); 1041 status = cx231xx_read_modify_write_i2c_dword(dev, 1042 VID_BLK_I2C_ADDRESS, 1043 VERT_TIM_CTRL, 1044 FLD_VACTIVE_CNT, 1045 cx231xx_set_field 1046 (FLD_VACTIVE_CNT, 1047 0x244)); 1048 status = cx231xx_read_modify_write_i2c_dword(dev, 1049 VID_BLK_I2C_ADDRESS, 1050 VERT_TIM_CTRL, 1051 FLD_V656BLANK_CNT, 1052 cx231xx_set_field 1053 (FLD_V656BLANK_CNT, 1054 0x24)); 1055 /* Adjust the active video horizontal start point */ 1056 status = cx231xx_read_modify_write_i2c_dword(dev, 1057 VID_BLK_I2C_ADDRESS, 1058 HORIZ_TIM_CTRL, 1059 FLD_HBLANK_CNT, 1060 cx231xx_set_field 1061 (FLD_HBLANK_CNT, 0x85)); 1062 1063 } 1064 1065 return status; 1066 } 1067 1068 int cx231xx_unmute_audio(struct cx231xx *dev) 1069 { 1070 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1071 } 1072 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1073 1074 static int stopAudioFirmware(struct cx231xx *dev) 1075 { 1076 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1077 } 1078 1079 static int restartAudioFirmware(struct cx231xx *dev) 1080 { 1081 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1082 } 1083 1084 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1085 { 1086 int status = 0; 1087 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1088 1089 switch (INPUT(input)->amux) { 1090 case CX231XX_AMUX_VIDEO: 1091 ainput = AUDIO_INPUT_TUNER_TV; 1092 break; 1093 case CX231XX_AMUX_LINE_IN: 1094 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1095 ainput = AUDIO_INPUT_LINE; 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 status = cx231xx_set_audio_decoder_input(dev, ainput); 1102 1103 return status; 1104 } 1105 1106 int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1107 enum AUDIO_INPUT audio_input) 1108 { 1109 u32 dwval; 1110 int status; 1111 u8 gen_ctrl; 1112 u32 value = 0; 1113 1114 /* Put it in soft reset */ 1115 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1116 gen_ctrl |= 1; 1117 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1118 1119 switch (audio_input) { 1120 case AUDIO_INPUT_LINE: 1121 /* setup AUD_IO control from Merlin paralle output */ 1122 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1123 AUD_CHAN_SRC_PARALLEL); 1124 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1125 1126 /* setup input to Merlin, SRC2 connect to AC97 1127 bypass upsample-by-2, slave mode, sony mode, left justify 1128 adr 091c, dat 01000000 */ 1129 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1130 1131 status = vid_blk_write_word(dev, AC97_CTL, 1132 (dwval | FLD_AC97_UP2X_BYPASS)); 1133 1134 /* select the parallel1 and SRC3 */ 1135 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1136 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1137 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1138 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1139 1140 /* unmute all, AC97 in, independence mode 1141 adr 08d0, data 0x00063073 */ 1142 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1143 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1144 1145 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1146 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1147 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1148 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1149 1150 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1151 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1152 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1153 (dwval | FLD_PATH1_SC_THRESHOLD)); 1154 break; 1155 1156 case AUDIO_INPUT_TUNER_TV: 1157 default: 1158 status = stopAudioFirmware(dev); 1159 /* Setup SRC sources and clocks */ 1160 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1161 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1162 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1163 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1164 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1165 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1166 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1167 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1168 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1169 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1170 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1171 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1172 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1173 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1174 1175 /* Setup the AUD_IO control */ 1176 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1177 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1178 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1179 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1180 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1181 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1182 1183 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1184 1185 /* setAudioStandard(_audio_standard); */ 1186 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1187 1188 status = restartAudioFirmware(dev); 1189 1190 switch (dev->board.tuner_type) { 1191 case TUNER_XC5000: 1192 /* SIF passthrough at 28.6363 MHz sample rate */ 1193 status = cx231xx_read_modify_write_i2c_dword(dev, 1194 VID_BLK_I2C_ADDRESS, 1195 CHIP_CTRL, 1196 FLD_SIF_EN, 1197 cx231xx_set_field(FLD_SIF_EN, 1)); 1198 break; 1199 case TUNER_NXP_TDA18271: 1200 /* Normal mode: SIF passthrough at 14.32 MHz */ 1201 status = cx231xx_read_modify_write_i2c_dword(dev, 1202 VID_BLK_I2C_ADDRESS, 1203 CHIP_CTRL, 1204 FLD_SIF_EN, 1205 cx231xx_set_field(FLD_SIF_EN, 0)); 1206 break; 1207 default: 1208 /* This is just a casual suggestion to people adding 1209 new boards in case they use a tuner type we don't 1210 currently know about */ 1211 dev_info(dev->dev, 1212 "Unknown tuner type configuring SIF"); 1213 break; 1214 } 1215 break; 1216 1217 case AUDIO_INPUT_TUNER_FM: 1218 /* use SIF for FM radio 1219 setupFM(); 1220 setAudioStandard(_audio_standard); 1221 */ 1222 break; 1223 1224 case AUDIO_INPUT_MUTE: 1225 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1226 break; 1227 } 1228 1229 /* Take it out of soft reset */ 1230 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1231 gen_ctrl &= ~1; 1232 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1233 1234 return status; 1235 } 1236 1237 /****************************************************************************** 1238 * C H I P Specific C O N T R O L functions * 1239 ******************************************************************************/ 1240 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1241 { 1242 u32 value; 1243 int status = 0; 1244 1245 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1246 value |= (~dev->board.ctl_pin_status_mask); 1247 status = vid_blk_write_word(dev, PIN_CTRL, value); 1248 1249 return status; 1250 } 1251 1252 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1253 u8 analog_or_digital) 1254 { 1255 int status = 0; 1256 1257 /* first set the direction to output */ 1258 status = cx231xx_set_gpio_direction(dev, 1259 dev->board. 1260 agc_analog_digital_select_gpio, 1); 1261 1262 /* 0 - demod ; 1 - Analog mode */ 1263 status = cx231xx_set_gpio_value(dev, 1264 dev->board.agc_analog_digital_select_gpio, 1265 analog_or_digital); 1266 1267 if (status < 0) 1268 return status; 1269 1270 return 0; 1271 } 1272 1273 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1274 { 1275 u8 value[4] = { 0, 0, 0, 0 }; 1276 int status = 0; 1277 bool current_is_port_3; 1278 1279 /* 1280 * Should this code check dev->port_3_switch_enabled first 1281 * to skip unnecessary reading of the register? 1282 * If yes, the flag dev->port_3_switch_enabled must be initialized 1283 * correctly. 1284 */ 1285 1286 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1287 PWR_CTL_EN, value, 4); 1288 if (status < 0) 1289 return status; 1290 1291 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1292 1293 /* Just return, if already using the right port */ 1294 if (current_is_port_3 == is_port_3) 1295 return 0; 1296 1297 if (is_port_3) 1298 value[0] |= I2C_DEMOD_EN; 1299 else 1300 value[0] &= ~I2C_DEMOD_EN; 1301 1302 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1303 PWR_CTL_EN, value, 4); 1304 1305 /* remember status of the switch for usage in is_tuner */ 1306 if (status >= 0) 1307 dev->port_3_switch_enabled = is_port_3; 1308 1309 return status; 1310 1311 } 1312 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1313 1314 void update_HH_register_after_set_DIF(struct cx231xx *dev) 1315 { 1316 /* 1317 u8 status = 0; 1318 u32 value = 0; 1319 1320 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1321 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1322 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1323 1324 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1325 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1326 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1327 */ 1328 } 1329 1330 void cx231xx_dump_HH_reg(struct cx231xx *dev) 1331 { 1332 u32 value = 0; 1333 u16 i = 0; 1334 1335 value = 0x45005390; 1336 vid_blk_write_word(dev, 0x104, value); 1337 1338 for (i = 0x100; i < 0x140; i++) { 1339 vid_blk_read_word(dev, i, &value); 1340 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 1341 i = i+3; 1342 } 1343 1344 for (i = 0x300; i < 0x400; i++) { 1345 vid_blk_read_word(dev, i, &value); 1346 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 1347 i = i+3; 1348 } 1349 1350 for (i = 0x400; i < 0x440; i++) { 1351 vid_blk_read_word(dev, i, &value); 1352 dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 1353 i = i+3; 1354 } 1355 1356 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1357 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1358 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1359 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1360 dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1361 } 1362 1363 #if 0 1364 static void cx231xx_dump_SC_reg(struct cx231xx *dev) 1365 { 1366 u8 value[4] = { 0, 0, 0, 0 }; 1367 dev_dbg(dev->dev, "%s!\n", __func__); 1368 1369 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1370 value, 4); 1371 dev_dbg(dev->dev, 1372 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1373 value[1], value[2], value[3]); 1374 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1375 value, 4); 1376 dev_dbg(dev->dev, 1377 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1378 value[1], value[2], value[3]); 1379 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1380 value, 4); 1381 dev_dbg(dev->dev, 1382 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1383 value[1], value[2], value[3]); 1384 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1385 value, 4); 1386 dev_dbg(dev->dev, 1387 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1388 value[1], value[2], value[3]); 1389 1390 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1391 value, 4); 1392 dev_dbg(dev->dev, 1393 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1394 value[1], value[2], value[3]); 1395 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1396 value, 4); 1397 dev_dbg(dev->dev, 1398 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1399 value[1], value[2], value[3]); 1400 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1401 value, 4); 1402 dev_dbg(dev->dev, 1403 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1404 value[1], value[2], value[3]); 1405 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1406 value, 4); 1407 dev_dbg(dev->dev, 1408 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1409 value[1], value[2], value[3]); 1410 1411 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1412 value, 4); 1413 dev_dbg(dev->dev, 1414 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1415 value[1], value[2], value[3]); 1416 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1417 value, 4); 1418 dev_dbg(dev->dev, 1419 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1420 value[1], value[2], value[3]); 1421 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1422 value, 4); 1423 dev_dbg(dev->dev, 1424 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1425 value[1], value[2], value[3]); 1426 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1427 value, 4); 1428 dev_dbg(dev->dev, 1429 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1430 value[1], value[2], value[3]); 1431 1432 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1433 value, 4); 1434 dev_dbg(dev->dev, 1435 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1436 value[1], value[2], value[3]); 1437 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1438 value, 4); 1439 dev_dbg(dev->dev, 1440 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1441 value[1], value[2], value[3]); 1442 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1443 value, 4); 1444 dev_dbg(dev->dev, 1445 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1446 value[1], value[2], value[3]); 1447 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1448 value, 4); 1449 dev_dbg(dev->dev, 1450 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1451 value[1], value[2], value[3]); 1452 1453 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1454 value, 4); 1455 dev_dbg(dev->dev, 1456 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1457 value[1], value[2], value[3]); 1458 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1459 value, 4); 1460 dev_dbg(dev->dev, 1461 "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1462 value[1], value[2], value[3]); 1463 } 1464 #endif 1465 1466 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1467 1468 { 1469 u8 value = 0; 1470 1471 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1472 value = (value & 0xFE)|0x01; 1473 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1474 1475 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1476 value = (value & 0xFE)|0x00; 1477 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1478 1479 1480 /* 1481 config colibri to lo-if mode 1482 1483 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1484 the diff IF input by half, 1485 1486 for low-if agc defect 1487 */ 1488 1489 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1490 value = (value & 0xFC)|0x00; 1491 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1492 1493 afe_read_byte(dev, ADC_INPUT_CH3, &value); 1494 value = (value & 0xF9)|0x02; 1495 afe_write_byte(dev, ADC_INPUT_CH3, value); 1496 1497 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1498 value = (value & 0xFB)|0x04; 1499 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1500 1501 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1502 value = (value & 0xFC)|0x03; 1503 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1504 1505 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1506 value = (value & 0xFB)|0x04; 1507 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1508 1509 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1510 value = (value & 0xF8)|0x06; 1511 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1512 1513 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1514 value = (value & 0x8F)|0x40; 1515 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1516 1517 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1518 value = (value & 0xDF)|0x20; 1519 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1520 } 1521 1522 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1523 u8 spectral_invert, u32 mode) 1524 { 1525 u32 colibri_carrier_offset = 0; 1526 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1527 u32 standard = 0; 1528 u8 value[4] = { 0, 0, 0, 0 }; 1529 1530 dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n"); 1531 value[0] = (u8) 0x6F; 1532 value[1] = (u8) 0x6F; 1533 value[2] = (u8) 0x6F; 1534 value[3] = (u8) 0x6F; 1535 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1536 PWR_CTL_EN, value, 4); 1537 1538 /*Set colibri for low IF*/ 1539 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1540 1541 /* Set C2HH for low IF operation.*/ 1542 standard = dev->norm; 1543 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1544 func_mode, standard); 1545 1546 /* Get colibri offsets.*/ 1547 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1548 standard); 1549 1550 dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n", 1551 colibri_carrier_offset, standard); 1552 1553 /* Set the band Pass filter for DIF*/ 1554 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1555 spectral_invert, mode); 1556 } 1557 1558 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1559 { 1560 u32 colibri_carrier_offset = 0; 1561 1562 if (mode == TUNER_MODE_FM_RADIO) { 1563 colibri_carrier_offset = 1100000; 1564 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1565 colibri_carrier_offset = 4832000; /*4.83MHz */ 1566 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1567 colibri_carrier_offset = 2700000; /*2.70MHz */ 1568 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1569 | V4L2_STD_SECAM)) { 1570 colibri_carrier_offset = 2100000; /*2.10MHz */ 1571 } 1572 1573 return colibri_carrier_offset; 1574 } 1575 1576 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1577 u8 spectral_invert, u32 mode) 1578 { 1579 unsigned long pll_freq_word; 1580 u32 dif_misc_ctrl_value = 0; 1581 u64 pll_freq_u64 = 0; 1582 u32 i = 0; 1583 1584 dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1585 if_freq, spectral_invert, mode); 1586 1587 1588 if (mode == TUNER_MODE_FM_RADIO) { 1589 pll_freq_word = 0x905A1CAC; 1590 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1591 1592 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1593 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1594 pll_freq_word = if_freq; 1595 pll_freq_u64 = (u64)pll_freq_word << 28L; 1596 do_div(pll_freq_u64, 50000000); 1597 pll_freq_word = (u32)pll_freq_u64; 1598 /*pll_freq_word = 0x3463497;*/ 1599 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1600 1601 if (spectral_invert) { 1602 if_freq -= 400000; 1603 /* Enable Spectral Invert*/ 1604 vid_blk_read_word(dev, DIF_MISC_CTRL, 1605 &dif_misc_ctrl_value); 1606 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1607 vid_blk_write_word(dev, DIF_MISC_CTRL, 1608 dif_misc_ctrl_value); 1609 } else { 1610 if_freq += 400000; 1611 /* Disable Spectral Invert*/ 1612 vid_blk_read_word(dev, DIF_MISC_CTRL, 1613 &dif_misc_ctrl_value); 1614 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1615 vid_blk_write_word(dev, DIF_MISC_CTRL, 1616 dif_misc_ctrl_value); 1617 } 1618 1619 if_freq = (if_freq / 100000) * 100000; 1620 1621 if (if_freq < 3000000) 1622 if_freq = 3000000; 1623 1624 if (if_freq > 16000000) 1625 if_freq = 16000000; 1626 } 1627 1628 dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array)); 1629 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 1630 if (Dif_set_array[i].if_freq == if_freq) { 1631 vid_blk_write_word(dev, 1632 Dif_set_array[i].register_address, Dif_set_array[i].value); 1633 } 1634 } 1635 } 1636 1637 /****************************************************************************** 1638 * D I F - B L O C K C O N T R O L functions * 1639 ******************************************************************************/ 1640 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1641 u32 function_mode, u32 standard) 1642 { 1643 int status = 0; 1644 1645 1646 if (mode == V4L2_TUNER_RADIO) { 1647 /* C2HH */ 1648 /* lo if big signal */ 1649 status = cx231xx_reg_mask_write(dev, 1650 VID_BLK_I2C_ADDRESS, 32, 1651 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1652 /* FUNC_MODE = DIF */ 1653 status = cx231xx_reg_mask_write(dev, 1654 VID_BLK_I2C_ADDRESS, 32, 1655 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1656 /* IF_MODE */ 1657 status = cx231xx_reg_mask_write(dev, 1658 VID_BLK_I2C_ADDRESS, 32, 1659 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1660 /* no inv */ 1661 status = cx231xx_reg_mask_write(dev, 1662 VID_BLK_I2C_ADDRESS, 32, 1663 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1664 } else if (standard != DIF_USE_BASEBAND) { 1665 if (standard & V4L2_STD_MN) { 1666 /* lo if big signal */ 1667 status = cx231xx_reg_mask_write(dev, 1668 VID_BLK_I2C_ADDRESS, 32, 1669 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1670 /* FUNC_MODE = DIF */ 1671 status = cx231xx_reg_mask_write(dev, 1672 VID_BLK_I2C_ADDRESS, 32, 1673 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1674 function_mode); 1675 /* IF_MODE */ 1676 status = cx231xx_reg_mask_write(dev, 1677 VID_BLK_I2C_ADDRESS, 32, 1678 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1679 /* no inv */ 1680 status = cx231xx_reg_mask_write(dev, 1681 VID_BLK_I2C_ADDRESS, 32, 1682 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1683 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1684 status = cx231xx_reg_mask_write(dev, 1685 VID_BLK_I2C_ADDRESS, 32, 1686 AUD_IO_CTRL, 0, 31, 0x00000003); 1687 } else if ((standard == V4L2_STD_PAL_I) | 1688 (standard & V4L2_STD_PAL_D) | 1689 (standard & V4L2_STD_SECAM)) { 1690 /* C2HH setup */ 1691 /* lo if big signal */ 1692 status = cx231xx_reg_mask_write(dev, 1693 VID_BLK_I2C_ADDRESS, 32, 1694 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1695 /* FUNC_MODE = DIF */ 1696 status = cx231xx_reg_mask_write(dev, 1697 VID_BLK_I2C_ADDRESS, 32, 1698 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1699 function_mode); 1700 /* IF_MODE */ 1701 status = cx231xx_reg_mask_write(dev, 1702 VID_BLK_I2C_ADDRESS, 32, 1703 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1704 /* no inv */ 1705 status = cx231xx_reg_mask_write(dev, 1706 VID_BLK_I2C_ADDRESS, 32, 1707 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1708 } else { 1709 /* default PAL BG */ 1710 /* C2HH setup */ 1711 /* lo if big signal */ 1712 status = cx231xx_reg_mask_write(dev, 1713 VID_BLK_I2C_ADDRESS, 32, 1714 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1715 /* FUNC_MODE = DIF */ 1716 status = cx231xx_reg_mask_write(dev, 1717 VID_BLK_I2C_ADDRESS, 32, 1718 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1719 function_mode); 1720 /* IF_MODE */ 1721 status = cx231xx_reg_mask_write(dev, 1722 VID_BLK_I2C_ADDRESS, 32, 1723 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1724 /* no inv */ 1725 status = cx231xx_reg_mask_write(dev, 1726 VID_BLK_I2C_ADDRESS, 32, 1727 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1728 } 1729 } 1730 1731 return status; 1732 } 1733 1734 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1735 { 1736 int status = 0; 1737 u32 dif_misc_ctrl_value = 0; 1738 u32 func_mode = 0; 1739 1740 dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard); 1741 1742 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1743 if (standard != DIF_USE_BASEBAND) 1744 dev->norm = standard; 1745 1746 switch (dev->model) { 1747 case CX231XX_BOARD_CNXT_CARRAERA: 1748 case CX231XX_BOARD_CNXT_RDE_250: 1749 case CX231XX_BOARD_CNXT_SHELBY: 1750 case CX231XX_BOARD_CNXT_RDU_250: 1751 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1752 case CX231XX_BOARD_HAUPPAUGE_EXETER: 1753 case CX231XX_BOARD_OTG102: 1754 func_mode = 0x03; 1755 break; 1756 case CX231XX_BOARD_CNXT_RDE_253S: 1757 case CX231XX_BOARD_CNXT_RDU_253S: 1758 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 1759 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 1760 func_mode = 0x01; 1761 break; 1762 default: 1763 func_mode = 0x01; 1764 } 1765 1766 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1767 func_mode, standard); 1768 1769 if (standard == DIF_USE_BASEBAND) { /* base band */ 1770 /* There is a different SRC_PHASE_INC value 1771 for baseband vs. DIF */ 1772 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1773 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1774 &dif_misc_ctrl_value); 1775 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1776 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1777 dif_misc_ctrl_value); 1778 } else if (standard & V4L2_STD_PAL_D) { 1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1780 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1782 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1784 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1786 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1788 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1790 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1791 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1792 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1794 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1796 DIF_AGC_IF_INT_CURRENT, 0, 31, 1797 0x26001700); 1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1799 DIF_AGC_RF_CURRENT, 0, 31, 1800 0x00002660); 1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1802 DIF_VIDEO_AGC_CTRL, 0, 31, 1803 0x72500800); 1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1805 DIF_VID_AUD_OVERRIDE, 0, 31, 1806 0x27000100); 1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1808 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1810 DIF_COMP_FLT_CTRL, 0, 31, 1811 0x00000000); 1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1813 DIF_SRC_PHASE_INC, 0, 31, 1814 0x1befbf06); 1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1816 DIF_SRC_GAIN_CONTROL, 0, 31, 1817 0x000035e8); 1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1819 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1820 /* Save the Spec Inversion value */ 1821 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1822 dif_misc_ctrl_value |= 0x3a023F11; 1823 } else if (standard & V4L2_STD_PAL_I) { 1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1825 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1827 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1829 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1831 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1833 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1835 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1836 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1837 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1839 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1841 DIF_AGC_IF_INT_CURRENT, 0, 31, 1842 0x26001700); 1843 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1844 DIF_AGC_RF_CURRENT, 0, 31, 1845 0x00002660); 1846 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1847 DIF_VIDEO_AGC_CTRL, 0, 31, 1848 0x72500800); 1849 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1850 DIF_VID_AUD_OVERRIDE, 0, 31, 1851 0x27000100); 1852 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1853 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1854 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1855 DIF_COMP_FLT_CTRL, 0, 31, 1856 0x00000000); 1857 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1858 DIF_SRC_PHASE_INC, 0, 31, 1859 0x1befbf06); 1860 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1861 DIF_SRC_GAIN_CONTROL, 0, 31, 1862 0x000035e8); 1863 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1864 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1865 /* Save the Spec Inversion value */ 1866 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1867 dif_misc_ctrl_value |= 0x3a033F11; 1868 } else if (standard & V4L2_STD_PAL_M) { 1869 /* improved Low Frequency Phase Noise */ 1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1871 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1872 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1873 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1874 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1875 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1876 0x26001700); 1877 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1878 0x00002660); 1879 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1880 0x72500800); 1881 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1882 0x27000100); 1883 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1884 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1885 0x009f50c1); 1886 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1887 0x1befbf06); 1888 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1889 0x000035e8); 1890 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1891 0x00000000); 1892 /* Save the Spec Inversion value */ 1893 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1894 dif_misc_ctrl_value |= 0x3A0A3F10; 1895 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1896 /* improved Low Frequency Phase Noise */ 1897 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1898 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1899 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1900 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1901 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1902 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1903 0x26001700); 1904 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1905 0x00002660); 1906 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1907 0x72500800); 1908 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1909 0x27000100); 1910 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1911 0x012c405d); 1912 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1913 0x009f50c1); 1914 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1915 0x1befbf06); 1916 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1917 0x000035e8); 1918 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1919 0x00000000); 1920 /* Save the Spec Inversion value */ 1921 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1922 dif_misc_ctrl_value = 0x3A093F10; 1923 } else if (standard & 1924 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1925 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1926 1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1928 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1930 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1932 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1933 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1934 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1936 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1937 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1938 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1939 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1940 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1941 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1942 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1944 DIF_AGC_IF_INT_CURRENT, 0, 31, 1945 0x26001700); 1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1947 DIF_AGC_RF_CURRENT, 0, 31, 1948 0x00002660); 1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1950 DIF_VID_AUD_OVERRIDE, 0, 31, 1951 0x27000100); 1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1953 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1955 DIF_COMP_FLT_CTRL, 0, 31, 1956 0x00000000); 1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1958 DIF_SRC_PHASE_INC, 0, 31, 1959 0x1befbf06); 1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1961 DIF_SRC_GAIN_CONTROL, 0, 31, 1962 0x000035e8); 1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1964 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1965 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1966 DIF_VIDEO_AGC_CTRL, 0, 31, 1967 0xf4000000); 1968 1969 /* Save the Spec Inversion value */ 1970 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1971 dif_misc_ctrl_value |= 0x3a023F11; 1972 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1973 /* Is it SECAM_L1? */ 1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1975 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1977 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1979 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1980 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1981 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1983 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1984 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1985 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1986 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1987 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1988 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1989 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1991 DIF_AGC_IF_INT_CURRENT, 0, 31, 1992 0x26001700); 1993 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1994 DIF_AGC_RF_CURRENT, 0, 31, 1995 0x00002660); 1996 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1997 DIF_VID_AUD_OVERRIDE, 0, 31, 1998 0x27000100); 1999 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2000 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 2001 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2002 DIF_COMP_FLT_CTRL, 0, 31, 2003 0x00000000); 2004 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2005 DIF_SRC_PHASE_INC, 0, 31, 2006 0x1befbf06); 2007 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2008 DIF_SRC_GAIN_CONTROL, 0, 31, 2009 0x000035e8); 2010 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2011 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2012 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2013 DIF_VIDEO_AGC_CTRL, 0, 31, 2014 0xf2560000); 2015 2016 /* Save the Spec Inversion value */ 2017 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2018 dif_misc_ctrl_value |= 0x3a023F11; 2019 2020 } else if (standard & V4L2_STD_NTSC_M) { 2021 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 2022 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 2023 2024 /* For NTSC the centre frequency of video coming out of 2025 sidewinder is around 7.1MHz or 3.6MHz depending on the 2026 spectral inversion. so for a non spectrally inverted channel 2027 the pll freq word is 0x03420c49 2028 */ 2029 2030 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 2031 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 2032 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 2033 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 2034 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 2035 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 2036 0x26001700); 2037 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 2038 0x00002660); 2039 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 2040 0x04000800); 2041 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 2042 0x27000100); 2043 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 2044 2045 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 2046 0x009f50c1); 2047 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 2048 0x1befbf06); 2049 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 2050 0x000035e8); 2051 2052 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 2053 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 2054 0xC2262600); 2055 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 2056 2057 /* Save the Spec Inversion value */ 2058 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2059 dif_misc_ctrl_value |= 0x3a003F10; 2060 } else { 2061 /* default PAL BG */ 2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2063 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2065 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2067 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2069 DIF_PLL_CTRL3, 0, 31, 0x00008800); 2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2071 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2073 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 2074 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2075 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2077 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2079 DIF_AGC_IF_INT_CURRENT, 0, 31, 2080 0x26001700); 2081 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2082 DIF_AGC_RF_CURRENT, 0, 31, 2083 0x00002660); 2084 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2085 DIF_VIDEO_AGC_CTRL, 0, 31, 2086 0x72500800); 2087 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2088 DIF_VID_AUD_OVERRIDE, 0, 31, 2089 0x27000100); 2090 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2091 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 2092 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2093 DIF_COMP_FLT_CTRL, 0, 31, 2094 0x00A653A8); 2095 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2096 DIF_SRC_PHASE_INC, 0, 31, 2097 0x1befbf06); 2098 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2099 DIF_SRC_GAIN_CONTROL, 0, 31, 2100 0x000035e8); 2101 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2102 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2103 /* Save the Spec Inversion value */ 2104 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2105 dif_misc_ctrl_value |= 0x3a013F11; 2106 } 2107 2108 /* The AGC values should be the same for all standards, 2109 AUD_SRC_SEL[19] should always be disabled */ 2110 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 2111 2112 /* It is still possible to get Set Standard calls even when we 2113 are in FM mode. 2114 This is done to override the value for FM. */ 2115 if (dev->active_mode == V4L2_TUNER_RADIO) 2116 dif_misc_ctrl_value = 0x7a080000; 2117 2118 /* Write the calculated value for misc ontrol register */ 2119 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 2120 2121 return status; 2122 } 2123 2124 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 2125 { 2126 int status = 0; 2127 u32 dwval; 2128 2129 /* Set the RF and IF k_agc values to 3 */ 2130 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2131 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2132 dwval |= 0x33000000; 2133 2134 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2135 2136 return status; 2137 } 2138 2139 int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 2140 { 2141 int status = 0; 2142 u32 dwval; 2143 dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n", 2144 __func__, dev->tuner_type); 2145 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2146 * SECAM L/B/D standards */ 2147 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2148 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2149 2150 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2151 V4L2_STD_SECAM_D)) { 2152 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2153 dwval &= ~FLD_DIF_IF_REF; 2154 dwval |= 0x88000300; 2155 } else 2156 dwval |= 0x88000000; 2157 } else { 2158 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2159 dwval &= ~FLD_DIF_IF_REF; 2160 dwval |= 0xCC000300; 2161 } else 2162 dwval |= 0x44000000; 2163 } 2164 2165 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2166 2167 return status == sizeof(dwval) ? 0 : -EIO; 2168 } 2169 2170 /****************************************************************************** 2171 * I 2 S - B L O C K C O N T R O L functions * 2172 ******************************************************************************/ 2173 int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 2174 { 2175 int status = 0; 2176 u32 value; 2177 2178 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2179 CH_PWR_CTRL1, 1, &value, 1); 2180 /* enables clock to delta-sigma and decimation filter */ 2181 value |= 0x80; 2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2183 CH_PWR_CTRL1, 1, value, 1); 2184 /* power up all channel */ 2185 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2186 CH_PWR_CTRL2, 1, 0x00, 1); 2187 2188 return status; 2189 } 2190 2191 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 2192 enum AV_MODE avmode) 2193 { 2194 int status = 0; 2195 u32 value = 0; 2196 2197 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 2198 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2199 CH_PWR_CTRL2, 1, &value, 1); 2200 value |= 0xfe; 2201 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2202 CH_PWR_CTRL2, 1, value, 1); 2203 } else { 2204 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2205 CH_PWR_CTRL2, 1, 0x00, 1); 2206 } 2207 2208 return status; 2209 } 2210 2211 /* set i2s_blk for audio input types */ 2212 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 2213 { 2214 int status = 0; 2215 2216 switch (audio_input) { 2217 case CX231XX_AMUX_LINE_IN: 2218 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2219 CH_PWR_CTRL2, 1, 0x00, 1); 2220 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2221 CH_PWR_CTRL1, 1, 0x80, 1); 2222 break; 2223 case CX231XX_AMUX_VIDEO: 2224 default: 2225 break; 2226 } 2227 2228 dev->ctl_ainput = audio_input; 2229 2230 return status; 2231 } 2232 2233 /****************************************************************************** 2234 * P O W E R C O N T R O L functions * 2235 ******************************************************************************/ 2236 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 2237 { 2238 u8 value[4] = { 0, 0, 0, 0 }; 2239 u32 tmp = 0; 2240 int status = 0; 2241 2242 if (dev->power_mode != mode) 2243 dev->power_mode = mode; 2244 else { 2245 dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n", 2246 __func__, mode); 2247 return 0; 2248 } 2249 2250 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2251 4); 2252 if (status < 0) 2253 return status; 2254 2255 tmp = le32_to_cpu(*((__le32 *) value)); 2256 2257 switch (mode) { 2258 case POLARIS_AVMODE_ENXTERNAL_AV: 2259 2260 tmp &= (~PWR_MODE_MASK); 2261 2262 tmp |= PWR_AV_EN; 2263 value[0] = (u8) tmp; 2264 value[1] = (u8) (tmp >> 8); 2265 value[2] = (u8) (tmp >> 16); 2266 value[3] = (u8) (tmp >> 24); 2267 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2268 PWR_CTL_EN, value, 4); 2269 msleep(PWR_SLEEP_INTERVAL); 2270 2271 tmp |= PWR_ISO_EN; 2272 value[0] = (u8) tmp; 2273 value[1] = (u8) (tmp >> 8); 2274 value[2] = (u8) (tmp >> 16); 2275 value[3] = (u8) (tmp >> 24); 2276 status = 2277 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2278 value, 4); 2279 msleep(PWR_SLEEP_INTERVAL); 2280 2281 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 2282 value[0] = (u8) tmp; 2283 value[1] = (u8) (tmp >> 8); 2284 value[2] = (u8) (tmp >> 16); 2285 value[3] = (u8) (tmp >> 24); 2286 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2287 PWR_CTL_EN, value, 4); 2288 2289 /* reset state of xceive tuner */ 2290 dev->xc_fw_load_done = 0; 2291 break; 2292 2293 case POLARIS_AVMODE_ANALOGT_TV: 2294 2295 tmp |= PWR_DEMOD_EN; 2296 value[0] = (u8) tmp; 2297 value[1] = (u8) (tmp >> 8); 2298 value[2] = (u8) (tmp >> 16); 2299 value[3] = (u8) (tmp >> 24); 2300 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2301 PWR_CTL_EN, value, 4); 2302 msleep(PWR_SLEEP_INTERVAL); 2303 2304 if (!(tmp & PWR_TUNER_EN)) { 2305 tmp |= (PWR_TUNER_EN); 2306 value[0] = (u8) tmp; 2307 value[1] = (u8) (tmp >> 8); 2308 value[2] = (u8) (tmp >> 16); 2309 value[3] = (u8) (tmp >> 24); 2310 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2311 PWR_CTL_EN, value, 4); 2312 msleep(PWR_SLEEP_INTERVAL); 2313 } 2314 2315 if (!(tmp & PWR_AV_EN)) { 2316 tmp |= PWR_AV_EN; 2317 value[0] = (u8) tmp; 2318 value[1] = (u8) (tmp >> 8); 2319 value[2] = (u8) (tmp >> 16); 2320 value[3] = (u8) (tmp >> 24); 2321 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2322 PWR_CTL_EN, value, 4); 2323 msleep(PWR_SLEEP_INTERVAL); 2324 } 2325 if (!(tmp & PWR_ISO_EN)) { 2326 tmp |= PWR_ISO_EN; 2327 value[0] = (u8) tmp; 2328 value[1] = (u8) (tmp >> 8); 2329 value[2] = (u8) (tmp >> 16); 2330 value[3] = (u8) (tmp >> 24); 2331 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2332 PWR_CTL_EN, value, 4); 2333 msleep(PWR_SLEEP_INTERVAL); 2334 } 2335 2336 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 2337 tmp |= POLARIS_AVMODE_ANALOGT_TV; 2338 value[0] = (u8) tmp; 2339 value[1] = (u8) (tmp >> 8); 2340 value[2] = (u8) (tmp >> 16); 2341 value[3] = (u8) (tmp >> 24); 2342 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2343 PWR_CTL_EN, value, 4); 2344 msleep(PWR_SLEEP_INTERVAL); 2345 } 2346 2347 if (dev->board.tuner_type != TUNER_ABSENT) { 2348 /* reset the Tuner */ 2349 if (dev->board.tuner_gpio) 2350 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2351 2352 if (dev->cx231xx_reset_analog_tuner) 2353 dev->cx231xx_reset_analog_tuner(dev); 2354 } 2355 2356 break; 2357 2358 case POLARIS_AVMODE_DIGITAL: 2359 if (!(tmp & PWR_TUNER_EN)) { 2360 tmp |= (PWR_TUNER_EN); 2361 value[0] = (u8) tmp; 2362 value[1] = (u8) (tmp >> 8); 2363 value[2] = (u8) (tmp >> 16); 2364 value[3] = (u8) (tmp >> 24); 2365 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2366 PWR_CTL_EN, value, 4); 2367 msleep(PWR_SLEEP_INTERVAL); 2368 } 2369 if (!(tmp & PWR_AV_EN)) { 2370 tmp |= PWR_AV_EN; 2371 value[0] = (u8) tmp; 2372 value[1] = (u8) (tmp >> 8); 2373 value[2] = (u8) (tmp >> 16); 2374 value[3] = (u8) (tmp >> 24); 2375 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2376 PWR_CTL_EN, value, 4); 2377 msleep(PWR_SLEEP_INTERVAL); 2378 } 2379 if (!(tmp & PWR_ISO_EN)) { 2380 tmp |= PWR_ISO_EN; 2381 value[0] = (u8) tmp; 2382 value[1] = (u8) (tmp >> 8); 2383 value[2] = (u8) (tmp >> 16); 2384 value[3] = (u8) (tmp >> 24); 2385 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2386 PWR_CTL_EN, value, 4); 2387 msleep(PWR_SLEEP_INTERVAL); 2388 } 2389 2390 tmp &= (~PWR_AV_MODE); 2391 tmp |= POLARIS_AVMODE_DIGITAL; 2392 value[0] = (u8) tmp; 2393 value[1] = (u8) (tmp >> 8); 2394 value[2] = (u8) (tmp >> 16); 2395 value[3] = (u8) (tmp >> 24); 2396 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2397 PWR_CTL_EN, value, 4); 2398 msleep(PWR_SLEEP_INTERVAL); 2399 2400 if (!(tmp & PWR_DEMOD_EN)) { 2401 tmp |= PWR_DEMOD_EN; 2402 value[0] = (u8) tmp; 2403 value[1] = (u8) (tmp >> 8); 2404 value[2] = (u8) (tmp >> 16); 2405 value[3] = (u8) (tmp >> 24); 2406 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2407 PWR_CTL_EN, value, 4); 2408 msleep(PWR_SLEEP_INTERVAL); 2409 } 2410 2411 if (dev->board.tuner_type != TUNER_ABSENT) { 2412 /* reset the Tuner */ 2413 if (dev->board.tuner_gpio) 2414 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2415 2416 if (dev->cx231xx_reset_analog_tuner) 2417 dev->cx231xx_reset_analog_tuner(dev); 2418 } 2419 break; 2420 2421 default: 2422 break; 2423 } 2424 2425 msleep(PWR_SLEEP_INTERVAL); 2426 2427 /* For power saving, only enable Pwr_resetout_n 2428 when digital TV is selected. */ 2429 if (mode == POLARIS_AVMODE_DIGITAL) { 2430 tmp |= PWR_RESETOUT_EN; 2431 value[0] = (u8) tmp; 2432 value[1] = (u8) (tmp >> 8); 2433 value[2] = (u8) (tmp >> 16); 2434 value[3] = (u8) (tmp >> 24); 2435 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2436 PWR_CTL_EN, value, 4); 2437 msleep(PWR_SLEEP_INTERVAL); 2438 } 2439 2440 /* update power control for afe */ 2441 status = cx231xx_afe_update_power_control(dev, mode); 2442 2443 /* update power control for i2s_blk */ 2444 status = cx231xx_i2s_blk_update_power_control(dev, mode); 2445 2446 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2447 4); 2448 2449 return status; 2450 } 2451 2452 int cx231xx_power_suspend(struct cx231xx *dev) 2453 { 2454 u8 value[4] = { 0, 0, 0, 0 }; 2455 u32 tmp = 0; 2456 int status = 0; 2457 2458 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 2459 value, 4); 2460 if (status > 0) 2461 return status; 2462 2463 tmp = le32_to_cpu(*((__le32 *) value)); 2464 tmp &= (~PWR_MODE_MASK); 2465 2466 value[0] = (u8) tmp; 2467 value[1] = (u8) (tmp >> 8); 2468 value[2] = (u8) (tmp >> 16); 2469 value[3] = (u8) (tmp >> 24); 2470 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2471 value, 4); 2472 2473 return status; 2474 } 2475 2476 /****************************************************************************** 2477 * S T R E A M C O N T R O L functions * 2478 ******************************************************************************/ 2479 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2480 { 2481 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2482 u32 tmp = 0; 2483 int status = 0; 2484 2485 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 2486 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 2487 value, 4); 2488 if (status < 0) 2489 return status; 2490 2491 tmp = le32_to_cpu(*((__le32 *) value)); 2492 tmp |= ep_mask; 2493 value[0] = (u8) tmp; 2494 value[1] = (u8) (tmp >> 8); 2495 value[2] = (u8) (tmp >> 16); 2496 value[3] = (u8) (tmp >> 24); 2497 2498 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2499 value, 4); 2500 2501 return status; 2502 } 2503 2504 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 2505 { 2506 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2507 u32 tmp = 0; 2508 int status = 0; 2509 2510 dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 2511 status = 2512 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2513 if (status < 0) 2514 return status; 2515 2516 tmp = le32_to_cpu(*((__le32 *) value)); 2517 tmp &= (~ep_mask); 2518 value[0] = (u8) tmp; 2519 value[1] = (u8) (tmp >> 8); 2520 value[2] = (u8) (tmp >> 16); 2521 value[3] = (u8) (tmp >> 24); 2522 2523 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2524 value, 4); 2525 2526 return status; 2527 } 2528 2529 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2530 { 2531 int status = 0; 2532 u32 value = 0; 2533 u8 val[4] = { 0, 0, 0, 0 }; 2534 2535 if (dev->udev->speed == USB_SPEED_HIGH) { 2536 switch (media_type) { 2537 case Audio: 2538 dev_dbg(dev->dev, 2539 "%s: Audio enter HANC\n", __func__); 2540 status = 2541 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2542 break; 2543 2544 case Vbi: 2545 dev_dbg(dev->dev, 2546 "%s: set vanc registers\n", __func__); 2547 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2548 break; 2549 2550 case Sliced_cc: 2551 dev_dbg(dev->dev, 2552 "%s: set hanc registers\n", __func__); 2553 status = 2554 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2555 break; 2556 2557 case Raw_Video: 2558 dev_dbg(dev->dev, 2559 "%s: set video registers\n", __func__); 2560 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2561 break; 2562 2563 case TS1_serial_mode: 2564 dev_dbg(dev->dev, 2565 "%s: set ts1 registers", __func__); 2566 2567 if (dev->board.has_417) { 2568 dev_dbg(dev->dev, 2569 "%s: MPEG\n", __func__); 2570 value &= 0xFFFFFFFC; 2571 value |= 0x3; 2572 2573 status = cx231xx_mode_register(dev, 2574 TS_MODE_REG, value); 2575 2576 val[0] = 0x04; 2577 val[1] = 0xA3; 2578 val[2] = 0x3B; 2579 val[3] = 0x00; 2580 status = cx231xx_write_ctrl_reg(dev, 2581 VRT_SET_REGISTER, 2582 TS1_CFG_REG, val, 4); 2583 2584 val[0] = 0x00; 2585 val[1] = 0x08; 2586 val[2] = 0x00; 2587 val[3] = 0x08; 2588 status = cx231xx_write_ctrl_reg(dev, 2589 VRT_SET_REGISTER, 2590 TS1_LENGTH_REG, val, 4); 2591 } else { 2592 dev_dbg(dev->dev, "%s: BDA\n", __func__); 2593 status = cx231xx_mode_register(dev, 2594 TS_MODE_REG, 0x101); 2595 status = cx231xx_mode_register(dev, 2596 TS1_CFG_REG, 0x010); 2597 } 2598 break; 2599 2600 case TS1_parallel_mode: 2601 dev_dbg(dev->dev, 2602 "%s: set ts1 parallel mode registers\n", 2603 __func__); 2604 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2605 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2606 break; 2607 } 2608 } else { 2609 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2610 } 2611 2612 return status; 2613 } 2614 2615 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2616 { 2617 int rc = -1; 2618 u32 ep_mask = -1; 2619 struct pcb_config *pcb_config; 2620 2621 /* get EP for media type */ 2622 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2623 2624 if (pcb_config->config_num) { 2625 switch (media_type) { 2626 case Raw_Video: 2627 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2628 break; 2629 case Audio: 2630 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2631 break; 2632 case Vbi: 2633 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2634 break; 2635 case Sliced_cc: 2636 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2637 break; 2638 case TS1_serial_mode: 2639 case TS1_parallel_mode: 2640 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2641 break; 2642 case TS2: 2643 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2644 break; 2645 } 2646 } 2647 2648 if (start) { 2649 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2650 2651 if (rc < 0) 2652 return rc; 2653 2654 /* enable video capture */ 2655 if (ep_mask > 0) 2656 rc = cx231xx_start_stream(dev, ep_mask); 2657 } else { 2658 /* disable video capture */ 2659 if (ep_mask > 0) 2660 rc = cx231xx_stop_stream(dev, ep_mask); 2661 } 2662 2663 return rc; 2664 } 2665 EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2666 2667 /***************************************************************************** 2668 * G P I O B I T control functions * 2669 ******************************************************************************/ 2670 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val) 2671 { 2672 int status = 0; 2673 2674 gpio_val = (__force u32)cpu_to_le32(gpio_val); 2675 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); 2676 2677 return status; 2678 } 2679 2680 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val) 2681 { 2682 __le32 tmp; 2683 int status = 0; 2684 2685 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); 2686 *gpio_val = le32_to_cpu(tmp); 2687 2688 return status; 2689 } 2690 2691 /* 2692 * cx231xx_set_gpio_direction 2693 * Sets the direction of the GPIO pin to input or output 2694 * 2695 * Parameters : 2696 * pin_number : The GPIO Pin number to program the direction for 2697 * from 0 to 31 2698 * pin_value : The Direction of the GPIO Pin under reference. 2699 * 0 = Input direction 2700 * 1 = Output direction 2701 */ 2702 int cx231xx_set_gpio_direction(struct cx231xx *dev, 2703 int pin_number, int pin_value) 2704 { 2705 int status = 0; 2706 u32 value = 0; 2707 2708 /* Check for valid pin_number - if 32 , bail out */ 2709 if (pin_number >= 32) 2710 return -EINVAL; 2711 2712 /* input */ 2713 if (pin_value == 0) 2714 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2715 else 2716 value = dev->gpio_dir | (1 << pin_number); 2717 2718 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val); 2719 2720 /* cache the value for future */ 2721 dev->gpio_dir = value; 2722 2723 return status; 2724 } 2725 2726 /* 2727 * cx231xx_set_gpio_value 2728 * Sets the value of the GPIO pin to Logic high or low. The Pin under 2729 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2730 * 2731 * Parameters : 2732 * pin_number : The GPIO Pin number to program the direction for 2733 * pin_value : The value of the GPIO Pin under reference. 2734 * 0 = set it to 0 2735 * 1 = set it to 1 2736 */ 2737 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2738 { 2739 int status = 0; 2740 u32 value = 0; 2741 2742 /* Check for valid pin_number - if 0xFF , bail out */ 2743 if (pin_number >= 32) 2744 return -EINVAL; 2745 2746 /* first do a sanity check - if the Pin is not output, make it output */ 2747 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2748 /* It was in input mode */ 2749 value = dev->gpio_dir | (1 << pin_number); 2750 dev->gpio_dir = value; 2751 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2752 dev->gpio_val); 2753 value = 0; 2754 } 2755 2756 if (pin_value == 0) 2757 value = dev->gpio_val & (~(1 << pin_number)); 2758 else 2759 value = dev->gpio_val | (1 << pin_number); 2760 2761 /* store the value */ 2762 dev->gpio_val = value; 2763 2764 /* toggle bit0 of GP_IO */ 2765 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2766 2767 return status; 2768 } 2769 2770 /***************************************************************************** 2771 * G P I O I2C related functions * 2772 ******************************************************************************/ 2773 int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2774 { 2775 int status = 0; 2776 2777 /* set SCL to output 1 ; set SDA to output 1 */ 2778 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2779 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2780 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2781 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2782 2783 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2784 if (status < 0) 2785 return -EINVAL; 2786 2787 /* set SCL to output 1; set SDA to output 0 */ 2788 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2789 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2790 2791 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2792 if (status < 0) 2793 return -EINVAL; 2794 2795 /* set SCL to output 0; set SDA to output 0 */ 2796 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2797 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2798 2799 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2800 if (status < 0) 2801 return -EINVAL; 2802 2803 return status; 2804 } 2805 2806 int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2807 { 2808 int status = 0; 2809 2810 /* set SCL to output 0; set SDA to output 0 */ 2811 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2812 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2813 2814 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2815 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2816 2817 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2818 if (status < 0) 2819 return -EINVAL; 2820 2821 /* set SCL to output 1; set SDA to output 0 */ 2822 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2823 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2824 2825 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2826 if (status < 0) 2827 return -EINVAL; 2828 2829 /* set SCL to input ,release SCL cable control 2830 set SDA to input ,release SDA cable control */ 2831 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2832 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2833 2834 status = 2835 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2836 if (status < 0) 2837 return -EINVAL; 2838 2839 return status; 2840 } 2841 2842 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2843 { 2844 int status = 0; 2845 u8 i; 2846 2847 /* set SCL to output ; set SDA to output */ 2848 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2849 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2850 2851 for (i = 0; i < 8; i++) { 2852 if (((data << i) & 0x80) == 0) { 2853 /* set SCL to output 0; set SDA to output 0 */ 2854 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2855 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2856 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2857 dev->gpio_val); 2858 2859 /* set SCL to output 1; set SDA to output 0 */ 2860 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2861 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2862 dev->gpio_val); 2863 2864 /* set SCL to output 0; set SDA to output 0 */ 2865 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2866 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2867 dev->gpio_val); 2868 } else { 2869 /* set SCL to output 0; set SDA to output 1 */ 2870 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2871 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2872 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2873 dev->gpio_val); 2874 2875 /* set SCL to output 1; set SDA to output 1 */ 2876 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2877 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2878 dev->gpio_val); 2879 2880 /* set SCL to output 0; set SDA to output 1 */ 2881 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2882 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2883 dev->gpio_val); 2884 } 2885 } 2886 return status; 2887 } 2888 2889 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 2890 { 2891 u8 value = 0; 2892 int status = 0; 2893 u32 gpio_logic_value = 0; 2894 u8 i; 2895 2896 /* read byte */ 2897 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2898 2899 /* set SCL to output 0; set SDA to input */ 2900 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2901 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2902 dev->gpio_val); 2903 2904 /* set SCL to output 1; set SDA to input */ 2905 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2906 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2907 dev->gpio_val); 2908 2909 /* get SDA data bit */ 2910 gpio_logic_value = dev->gpio_val; 2911 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2912 &dev->gpio_val); 2913 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2914 value |= (1 << (8 - i - 1)); 2915 2916 dev->gpio_val = gpio_logic_value; 2917 } 2918 2919 /* set SCL to output 0,finish the read latest SCL signal. 2920 !!!set SDA to input, never to modify SDA direction at 2921 the same times */ 2922 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2923 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2924 2925 /* store the value */ 2926 *buf = value & 0xff; 2927 2928 return status; 2929 } 2930 2931 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2932 { 2933 int status = 0; 2934 u32 gpio_logic_value = 0; 2935 int nCnt = 10; 2936 int nInit = nCnt; 2937 2938 /* clock stretch; set SCL to input; set SDA to input; 2939 get SCL value till SCL = 1 */ 2940 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2941 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2942 2943 gpio_logic_value = dev->gpio_val; 2944 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2945 2946 do { 2947 msleep(2); 2948 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2949 &dev->gpio_val); 2950 nCnt--; 2951 } while (((dev->gpio_val & 2952 (1 << dev->board.tuner_scl_gpio)) == 0) && 2953 (nCnt > 0)); 2954 2955 if (nCnt == 0) 2956 dev_dbg(dev->dev, 2957 "No ACK after %d msec -GPIO I2C failed!", 2958 nInit * 10); 2959 2960 /* 2961 * readAck 2962 * through clock stretch, slave has given a SCL signal, 2963 * so the SDA data can be directly read. 2964 */ 2965 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val); 2966 2967 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2968 dev->gpio_val = gpio_logic_value; 2969 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2970 status = 0; 2971 } else { 2972 dev->gpio_val = gpio_logic_value; 2973 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2974 } 2975 2976 /* read SDA end, set the SCL to output 0, after this operation, 2977 SDA direction can be changed. */ 2978 dev->gpio_val = gpio_logic_value; 2979 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2980 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2981 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2982 2983 return status; 2984 } 2985 2986 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2987 { 2988 int status = 0; 2989 2990 /* set SDA to ouput */ 2991 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2992 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2993 2994 /* set SCL = 0 (output); set SDA = 0 (output) */ 2995 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2996 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2998 2999 /* set SCL = 1 (output); set SDA = 0 (output) */ 3000 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 3001 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3002 3003 /* set SCL = 0 (output); set SDA = 0 (output) */ 3004 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 3005 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3006 3007 /* set SDA to input,and then the slave will read data from SDA. */ 3008 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 3009 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3010 3011 return status; 3012 } 3013 3014 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 3015 { 3016 int status = 0; 3017 3018 /* set scl to output ; set sda to input */ 3019 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 3020 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 3021 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3022 3023 /* set scl to output 0; set sda to input */ 3024 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 3025 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3026 3027 /* set scl to output 1; set sda to input */ 3028 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 3029 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3030 3031 return status; 3032 } 3033 3034 /***************************************************************************** 3035 * G P I O I2C related functions * 3036 ******************************************************************************/ 3037 /* cx231xx_gpio_i2c_read 3038 * Function to read data from gpio based I2C interface 3039 */ 3040 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3041 { 3042 int status = 0; 3043 int i = 0; 3044 3045 /* get the lock */ 3046 mutex_lock(&dev->gpio_i2c_lock); 3047 3048 /* start */ 3049 status = cx231xx_gpio_i2c_start(dev); 3050 3051 /* write dev_addr */ 3052 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 3053 3054 /* readAck */ 3055 status = cx231xx_gpio_i2c_read_ack(dev); 3056 3057 /* read data */ 3058 for (i = 0; i < len; i++) { 3059 /* read data */ 3060 buf[i] = 0; 3061 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 3062 3063 if ((i + 1) != len) { 3064 /* only do write ack if we more length */ 3065 status = cx231xx_gpio_i2c_write_ack(dev); 3066 } 3067 } 3068 3069 /* write NAK - inform reads are complete */ 3070 status = cx231xx_gpio_i2c_write_nak(dev); 3071 3072 /* write end */ 3073 status = cx231xx_gpio_i2c_end(dev); 3074 3075 /* release the lock */ 3076 mutex_unlock(&dev->gpio_i2c_lock); 3077 3078 return status; 3079 } 3080 3081 /* cx231xx_gpio_i2c_write 3082 * Function to write data to gpio based I2C interface 3083 */ 3084 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3085 { 3086 int i = 0; 3087 3088 /* get the lock */ 3089 mutex_lock(&dev->gpio_i2c_lock); 3090 3091 /* start */ 3092 cx231xx_gpio_i2c_start(dev); 3093 3094 /* write dev_addr */ 3095 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 3096 3097 /* read Ack */ 3098 cx231xx_gpio_i2c_read_ack(dev); 3099 3100 for (i = 0; i < len; i++) { 3101 /* Write data */ 3102 cx231xx_gpio_i2c_write_byte(dev, buf[i]); 3103 3104 /* read Ack */ 3105 cx231xx_gpio_i2c_read_ack(dev); 3106 } 3107 3108 /* write End */ 3109 cx231xx_gpio_i2c_end(dev); 3110 3111 /* release the lock */ 3112 mutex_unlock(&dev->gpio_i2c_lock); 3113 3114 return 0; 3115 } 3116