174ba9207SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 20c0d06caSMauro Carvalho Chehab /* 30c0d06caSMauro Carvalho Chehab cx231xx_avcore.c - driver for Conexant Cx23100/101/102 40c0d06caSMauro Carvalho Chehab USB video capture devices 50c0d06caSMauro Carvalho Chehab 60c0d06caSMauro Carvalho Chehab Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 70c0d06caSMauro Carvalho Chehab 80c0d06caSMauro Carvalho Chehab This program contains the specific code to control the avdecoder chip and 90c0d06caSMauro Carvalho Chehab other related usb control functions for cx231xx based chipset. 100c0d06caSMauro Carvalho Chehab 110c0d06caSMauro Carvalho Chehab */ 120c0d06caSMauro Carvalho Chehab 13589dadf2SMauro Carvalho Chehab #include "cx231xx.h" 140c0d06caSMauro Carvalho Chehab #include <linux/init.h> 150c0d06caSMauro Carvalho Chehab #include <linux/list.h> 160c0d06caSMauro Carvalho Chehab #include <linux/module.h> 170c0d06caSMauro Carvalho Chehab #include <linux/kernel.h> 180c0d06caSMauro Carvalho Chehab #include <linux/bitmap.h> 190c0d06caSMauro Carvalho Chehab #include <linux/i2c.h> 200c0d06caSMauro Carvalho Chehab #include <linux/mm.h> 210c0d06caSMauro Carvalho Chehab #include <linux/mutex.h> 220c0d06caSMauro Carvalho Chehab #include <media/tuner.h> 230c0d06caSMauro Carvalho Chehab 240c0d06caSMauro Carvalho Chehab #include <media/v4l2-common.h> 250c0d06caSMauro Carvalho Chehab #include <media/v4l2-ioctl.h> 260c0d06caSMauro Carvalho Chehab 270c0d06caSMauro Carvalho Chehab #include "cx231xx-dif.h" 280c0d06caSMauro Carvalho Chehab 290c0d06caSMauro Carvalho Chehab #define TUNER_MODE_FM_RADIO 0 300c0d06caSMauro Carvalho Chehab /****************************************************************************** 310c0d06caSMauro Carvalho Chehab -: BLOCK ARRANGEMENT :- 320c0d06caSMauro Carvalho Chehab I2S block ----------------------| 330c0d06caSMauro Carvalho Chehab [I2S audio] | 340c0d06caSMauro Carvalho Chehab | 350c0d06caSMauro Carvalho Chehab Analog Front End --> Direct IF -|-> Cx25840 --> Audio 360c0d06caSMauro Carvalho Chehab [video & audio] | [Audio] 370c0d06caSMauro Carvalho Chehab | 380c0d06caSMauro Carvalho Chehab |-> Cx25840 --> Video 390c0d06caSMauro Carvalho Chehab [Video] 400c0d06caSMauro Carvalho Chehab 410c0d06caSMauro Carvalho Chehab *******************************************************************************/ 420c0d06caSMauro Carvalho Chehab /****************************************************************************** 430c0d06caSMauro Carvalho Chehab * VERVE REGISTER * 440c0d06caSMauro Carvalho Chehab * * 450c0d06caSMauro Carvalho Chehab ******************************************************************************/ 460c0d06caSMauro Carvalho Chehab static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 470c0d06caSMauro Carvalho Chehab { 480c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 490c0d06caSMauro Carvalho Chehab saddr, 1, data, 1); 500c0d06caSMauro Carvalho Chehab } 510c0d06caSMauro Carvalho Chehab 520c0d06caSMauro Carvalho Chehab static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 530c0d06caSMauro Carvalho Chehab { 540c0d06caSMauro Carvalho Chehab int status; 550c0d06caSMauro Carvalho Chehab u32 temp = 0; 560c0d06caSMauro Carvalho Chehab 570c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 580c0d06caSMauro Carvalho Chehab saddr, 1, &temp, 1); 590c0d06caSMauro Carvalho Chehab *data = (u8) temp; 600c0d06caSMauro Carvalho Chehab return status; 610c0d06caSMauro Carvalho Chehab } 620c0d06caSMauro Carvalho Chehab void initGPIO(struct cx231xx *dev) 630c0d06caSMauro Carvalho Chehab { 640c0d06caSMauro Carvalho Chehab u32 _gpio_direction = 0; 650c0d06caSMauro Carvalho Chehab u32 value = 0; 660c0d06caSMauro Carvalho Chehab u8 val = 0; 670c0d06caSMauro Carvalho Chehab 680c0d06caSMauro Carvalho Chehab _gpio_direction = _gpio_direction & 0xFC0003FF; 690c0d06caSMauro Carvalho Chehab _gpio_direction = _gpio_direction | 0x03FDFC00; 700c0d06caSMauro Carvalho Chehab cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 710c0d06caSMauro Carvalho Chehab 720c0d06caSMauro Carvalho Chehab verve_read_byte(dev, 0x07, &val); 73336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 740c0d06caSMauro Carvalho Chehab verve_write_byte(dev, 0x07, 0xF4); 750c0d06caSMauro Carvalho Chehab verve_read_byte(dev, 0x07, &val); 76336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val); 770c0d06caSMauro Carvalho Chehab 780c0d06caSMauro Carvalho Chehab cx231xx_capture_start(dev, 1, Vbi); 790c0d06caSMauro Carvalho Chehab 800c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 810c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 820c0d06caSMauro Carvalho Chehab 830c0d06caSMauro Carvalho Chehab } 840c0d06caSMauro Carvalho Chehab void uninitGPIO(struct cx231xx *dev) 850c0d06caSMauro Carvalho Chehab { 860c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 870c0d06caSMauro Carvalho Chehab 880c0d06caSMauro Carvalho Chehab cx231xx_capture_start(dev, 0, Vbi); 890c0d06caSMauro Carvalho Chehab verve_write_byte(dev, 0x07, 0x14); 900c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 910c0d06caSMauro Carvalho Chehab 0x68, value, 4); 920c0d06caSMauro Carvalho Chehab } 930c0d06caSMauro Carvalho Chehab 940c0d06caSMauro Carvalho Chehab /****************************************************************************** 950c0d06caSMauro Carvalho Chehab * A F E - B L O C K C O N T R O L functions * 960c0d06caSMauro Carvalho Chehab * [ANALOG FRONT END] * 970c0d06caSMauro Carvalho Chehab ******************************************************************************/ 980c0d06caSMauro Carvalho Chehab static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 990c0d06caSMauro Carvalho Chehab { 1000c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 1010c0d06caSMauro Carvalho Chehab saddr, 2, data, 1); 1020c0d06caSMauro Carvalho Chehab } 1030c0d06caSMauro Carvalho Chehab 1040c0d06caSMauro Carvalho Chehab static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 1050c0d06caSMauro Carvalho Chehab { 1060c0d06caSMauro Carvalho Chehab int status; 1070c0d06caSMauro Carvalho Chehab u32 temp = 0; 1080c0d06caSMauro Carvalho Chehab 1090c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 1100c0d06caSMauro Carvalho Chehab saddr, 2, &temp, 1); 1110c0d06caSMauro Carvalho Chehab *data = (u8) temp; 1120c0d06caSMauro Carvalho Chehab return status; 1130c0d06caSMauro Carvalho Chehab } 1140c0d06caSMauro Carvalho Chehab 1150c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 1160c0d06caSMauro Carvalho Chehab { 1170c0d06caSMauro Carvalho Chehab int status = 0; 1180c0d06caSMauro Carvalho Chehab u8 temp = 0; 1190c0d06caSMauro Carvalho Chehab u8 afe_power_status = 0; 1200c0d06caSMauro Carvalho Chehab int i = 0; 1210c0d06caSMauro Carvalho Chehab 1220c0d06caSMauro Carvalho Chehab /* super block initialize */ 1230c0d06caSMauro Carvalho Chehab temp = (u8) (ref_count & 0xff); 1240c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 1250c0d06caSMauro Carvalho Chehab if (status < 0) 1260c0d06caSMauro Carvalho Chehab return status; 1270c0d06caSMauro Carvalho Chehab 1280c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 1290c0d06caSMauro Carvalho Chehab if (status < 0) 1300c0d06caSMauro Carvalho Chehab return status; 1310c0d06caSMauro Carvalho Chehab 1320c0d06caSMauro Carvalho Chehab temp = (u8) ((ref_count & 0x300) >> 8); 1330c0d06caSMauro Carvalho Chehab temp |= 0x40; 1340c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 1350c0d06caSMauro Carvalho Chehab if (status < 0) 1360c0d06caSMauro Carvalho Chehab return status; 1370c0d06caSMauro Carvalho Chehab 1380c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 1390c0d06caSMauro Carvalho Chehab if (status < 0) 1400c0d06caSMauro Carvalho Chehab return status; 1410c0d06caSMauro Carvalho Chehab 1420c0d06caSMauro Carvalho Chehab /* enable pll */ 1430c0d06caSMauro Carvalho Chehab while (afe_power_status != 0x18) { 1440c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 1450c0d06caSMauro Carvalho Chehab if (status < 0) { 146336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 147b7085c08SMauro Carvalho Chehab "%s: Init Super Block failed in send cmd\n", 148ed0e3729SMauro Carvalho Chehab __func__); 1490c0d06caSMauro Carvalho Chehab break; 1500c0d06caSMauro Carvalho Chehab } 1510c0d06caSMauro Carvalho Chehab 1520c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 1530c0d06caSMauro Carvalho Chehab afe_power_status &= 0xff; 1540c0d06caSMauro Carvalho Chehab if (status < 0) { 155336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 156b7085c08SMauro Carvalho Chehab "%s: Init Super Block failed in receive cmd\n", 157ed0e3729SMauro Carvalho Chehab __func__); 1580c0d06caSMauro Carvalho Chehab break; 1590c0d06caSMauro Carvalho Chehab } 1600c0d06caSMauro Carvalho Chehab i++; 1610c0d06caSMauro Carvalho Chehab if (i == 10) { 162336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 163b7085c08SMauro Carvalho Chehab "%s: Init Super Block force break in loop !!!!\n", 164ed0e3729SMauro Carvalho Chehab __func__); 1650c0d06caSMauro Carvalho Chehab status = -1; 1660c0d06caSMauro Carvalho Chehab break; 1670c0d06caSMauro Carvalho Chehab } 1680c0d06caSMauro Carvalho Chehab } 1690c0d06caSMauro Carvalho Chehab 1700c0d06caSMauro Carvalho Chehab if (status < 0) 1710c0d06caSMauro Carvalho Chehab return status; 1720c0d06caSMauro Carvalho Chehab 1730c0d06caSMauro Carvalho Chehab /* start tuning filter */ 1740c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 1750c0d06caSMauro Carvalho Chehab if (status < 0) 1760c0d06caSMauro Carvalho Chehab return status; 1770c0d06caSMauro Carvalho Chehab 1780c0d06caSMauro Carvalho Chehab msleep(5); 1790c0d06caSMauro Carvalho Chehab 1800c0d06caSMauro Carvalho Chehab /* exit tuning */ 1810c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 1820c0d06caSMauro Carvalho Chehab 1830c0d06caSMauro Carvalho Chehab return status; 1840c0d06caSMauro Carvalho Chehab } 1850c0d06caSMauro Carvalho Chehab 1860c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_channels(struct cx231xx *dev) 1870c0d06caSMauro Carvalho Chehab { 1880c0d06caSMauro Carvalho Chehab int status = 0; 1890c0d06caSMauro Carvalho Chehab 1900c0d06caSMauro Carvalho Chehab /* power up all 3 channels, clear pd_buffer */ 1910c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 1920c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 1930c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 1940c0d06caSMauro Carvalho Chehab 1950c0d06caSMauro Carvalho Chehab /* Enable quantizer calibration */ 1960c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 1970c0d06caSMauro Carvalho Chehab 1980c0d06caSMauro Carvalho Chehab /* channel initialize, force modulator (fb) reset */ 1990c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 2000c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 2010c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 2020c0d06caSMauro Carvalho Chehab 2030c0d06caSMauro Carvalho Chehab /* start quantilizer calibration */ 2040c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 2050c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 2060c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 2070c0d06caSMauro Carvalho Chehab msleep(5); 2080c0d06caSMauro Carvalho Chehab 2090c0d06caSMauro Carvalho Chehab /* exit modulator (fb) reset */ 2100c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 2110c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 2120c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 2130c0d06caSMauro Carvalho Chehab 2140c0d06caSMauro Carvalho Chehab /* enable the pre_clamp in each channel for single-ended input */ 2150c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 2160c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 2170c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 2180c0d06caSMauro Carvalho Chehab 2190c0d06caSMauro Carvalho Chehab /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 2200c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 2210c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 2220c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 2230c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 2240c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 2250c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 2260c0d06caSMauro Carvalho Chehab 2270c0d06caSMauro Carvalho Chehab /* dynamic element matching off */ 2280c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 2290c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 2300c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 2310c0d06caSMauro Carvalho Chehab 2320c0d06caSMauro Carvalho Chehab return status; 2330c0d06caSMauro Carvalho Chehab } 2340c0d06caSMauro Carvalho Chehab 2350c0d06caSMauro Carvalho Chehab int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 2360c0d06caSMauro Carvalho Chehab { 2370c0d06caSMauro Carvalho Chehab u8 c_value = 0; 2380c0d06caSMauro Carvalho Chehab int status = 0; 2390c0d06caSMauro Carvalho Chehab 2400c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 2410c0d06caSMauro Carvalho Chehab c_value &= (~(0x50)); 2420c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 2430c0d06caSMauro Carvalho Chehab 2440c0d06caSMauro Carvalho Chehab return status; 2450c0d06caSMauro Carvalho Chehab } 2460c0d06caSMauro Carvalho Chehab 2470c0d06caSMauro Carvalho Chehab /* 2480c0d06caSMauro Carvalho Chehab The Analog Front End in Cx231xx has 3 channels. These 2490c0d06caSMauro Carvalho Chehab channels are used to share between different inputs 2500c0d06caSMauro Carvalho Chehab like tuner, s-video and composite inputs. 2510c0d06caSMauro Carvalho Chehab 2520c0d06caSMauro Carvalho Chehab channel 1 ----- pin 1 to pin4(in reg is 1-4) 2530c0d06caSMauro Carvalho Chehab channel 2 ----- pin 5 to pin8(in reg is 5-8) 2540c0d06caSMauro Carvalho Chehab channel 3 ----- pin 9 to pin 12(in reg is 9-11) 2550c0d06caSMauro Carvalho Chehab */ 2560c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 2570c0d06caSMauro Carvalho Chehab { 2580c0d06caSMauro Carvalho Chehab u8 ch1_setting = (u8) input_mux; 2590c0d06caSMauro Carvalho Chehab u8 ch2_setting = (u8) (input_mux >> 8); 2600c0d06caSMauro Carvalho Chehab u8 ch3_setting = (u8) (input_mux >> 16); 2610c0d06caSMauro Carvalho Chehab int status = 0; 2620c0d06caSMauro Carvalho Chehab u8 value = 0; 2630c0d06caSMauro Carvalho Chehab 2640c0d06caSMauro Carvalho Chehab if (ch1_setting != 0) { 2650c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 2660c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK; 2670c0d06caSMauro Carvalho Chehab value |= (ch1_setting - 1) << 4; 2680c0d06caSMauro Carvalho Chehab value &= 0xff; 2690c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH1, value); 2700c0d06caSMauro Carvalho Chehab } 2710c0d06caSMauro Carvalho Chehab 2720c0d06caSMauro Carvalho Chehab if (ch2_setting != 0) { 2730c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 2740c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK; 2750c0d06caSMauro Carvalho Chehab value |= (ch2_setting - 1) << 4; 2760c0d06caSMauro Carvalho Chehab value &= 0xff; 2770c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH2, value); 2780c0d06caSMauro Carvalho Chehab } 2790c0d06caSMauro Carvalho Chehab 2800c0d06caSMauro Carvalho Chehab /* For ch3_setting, the value to put in the register is 2810c0d06caSMauro Carvalho Chehab 7 less than the input number */ 2820c0d06caSMauro Carvalho Chehab if (ch3_setting != 0) { 2830c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 2840c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK; 2850c0d06caSMauro Carvalho Chehab value |= (ch3_setting - 1) << 4; 2860c0d06caSMauro Carvalho Chehab value &= 0xff; 2870c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH3, value); 2880c0d06caSMauro Carvalho Chehab } 2890c0d06caSMauro Carvalho Chehab 2900c0d06caSMauro Carvalho Chehab return status; 2910c0d06caSMauro Carvalho Chehab } 2920c0d06caSMauro Carvalho Chehab 2930c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 2940c0d06caSMauro Carvalho Chehab { 2950c0d06caSMauro Carvalho Chehab int status = 0; 2960c0d06caSMauro Carvalho Chehab 2970c0d06caSMauro Carvalho Chehab /* 2980c0d06caSMauro Carvalho Chehab * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 2990c0d06caSMauro Carvalho Chehab * Currently, only baseband works. 3000c0d06caSMauro Carvalho Chehab */ 3010c0d06caSMauro Carvalho Chehab 3020c0d06caSMauro Carvalho Chehab switch (mode) { 3030c0d06caSMauro Carvalho Chehab case AFE_MODE_LOW_IF: 3040c0d06caSMauro Carvalho Chehab cx231xx_Setup_AFE_for_LowIF(dev); 3050c0d06caSMauro Carvalho Chehab break; 3060c0d06caSMauro Carvalho Chehab case AFE_MODE_BASEBAND: 3070c0d06caSMauro Carvalho Chehab status = cx231xx_afe_setup_AFE_for_baseband(dev); 3080c0d06caSMauro Carvalho Chehab break; 3090c0d06caSMauro Carvalho Chehab case AFE_MODE_EU_HI_IF: 3100c0d06caSMauro Carvalho Chehab /* SetupAFEforEuHiIF(); */ 3110c0d06caSMauro Carvalho Chehab break; 3120c0d06caSMauro Carvalho Chehab case AFE_MODE_US_HI_IF: 3130c0d06caSMauro Carvalho Chehab /* SetupAFEforUsHiIF(); */ 3140c0d06caSMauro Carvalho Chehab break; 3150c0d06caSMauro Carvalho Chehab case AFE_MODE_JAPAN_HI_IF: 3160c0d06caSMauro Carvalho Chehab /* SetupAFEforJapanHiIF(); */ 3170c0d06caSMauro Carvalho Chehab break; 3180c0d06caSMauro Carvalho Chehab } 3190c0d06caSMauro Carvalho Chehab 3200c0d06caSMauro Carvalho Chehab if ((mode != dev->afe_mode) && 3210c0d06caSMauro Carvalho Chehab (dev->video_input == CX231XX_VMUX_TELEVISION)) 3220c0d06caSMauro Carvalho Chehab status = cx231xx_afe_adjust_ref_count(dev, 3230c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION); 3240c0d06caSMauro Carvalho Chehab 3250c0d06caSMauro Carvalho Chehab dev->afe_mode = mode; 3260c0d06caSMauro Carvalho Chehab 3270c0d06caSMauro Carvalho Chehab return status; 3280c0d06caSMauro Carvalho Chehab } 3290c0d06caSMauro Carvalho Chehab 3300c0d06caSMauro Carvalho Chehab int cx231xx_afe_update_power_control(struct cx231xx *dev, 3310c0d06caSMauro Carvalho Chehab enum AV_MODE avmode) 3320c0d06caSMauro Carvalho Chehab { 3330c0d06caSMauro Carvalho Chehab u8 afe_power_status = 0; 3340c0d06caSMauro Carvalho Chehab int status = 0; 3350c0d06caSMauro Carvalho Chehab 3360c0d06caSMauro Carvalho Chehab switch (dev->model) { 3370c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_CARRAERA: 3380c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_250: 3390c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_SHELBY: 3400c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_250: 3410c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_253S: 3420c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_253S: 3430c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 3440c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_EXETER: 345dd2e7dd2SMatthias Schwarzott case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx: 3460c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 3470c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 3480c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 3490c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 3503ead1ba3SMatt Gomboc case CX231XX_BOARD_OTG102: 3510c0d06caSMauro Carvalho Chehab if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 3520c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 3530c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 3540c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 3550c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 3560c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 3570c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 3580c0d06caSMauro Carvalho Chehab &afe_power_status); 3590c0d06caSMauro Carvalho Chehab if (status < 0) 3600c0d06caSMauro Carvalho Chehab break; 3610c0d06caSMauro Carvalho Chehab } 3620c0d06caSMauro Carvalho Chehab 3630c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 3640c0d06caSMauro Carvalho Chehab 0x00); 3650c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 3660c0d06caSMauro Carvalho Chehab 0x00); 3670c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 3680c0d06caSMauro Carvalho Chehab 0x00); 3690c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_DIGITAL) { 3700c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 3710c0d06caSMauro Carvalho Chehab 0x70); 3720c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 3730c0d06caSMauro Carvalho Chehab 0x70); 3740c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 3750c0d06caSMauro Carvalho Chehab 0x70); 3760c0d06caSMauro Carvalho Chehab 3770c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 3780c0d06caSMauro Carvalho Chehab &afe_power_status); 3790c0d06caSMauro Carvalho Chehab afe_power_status |= FLD_PWRDN_PD_BANDGAP | 3800c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_BIAS | 3810c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_TUNECK; 3820c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, SUP_BLK_PWRDN, 3830c0d06caSMauro Carvalho Chehab afe_power_status); 3840c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 3850c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 3860c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 3870c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 3880c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 3890c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 3900c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 3910c0d06caSMauro Carvalho Chehab &afe_power_status); 3920c0d06caSMauro Carvalho Chehab if (status < 0) 3930c0d06caSMauro Carvalho Chehab break; 3940c0d06caSMauro Carvalho Chehab } 3950c0d06caSMauro Carvalho Chehab 3960c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 3970c0d06caSMauro Carvalho Chehab 0x00); 3980c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 3990c0d06caSMauro Carvalho Chehab 0x00); 4000c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4010c0d06caSMauro Carvalho Chehab 0x00); 4020c0d06caSMauro Carvalho Chehab } else { 403336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Invalid AV mode input\n"); 4040c0d06caSMauro Carvalho Chehab status = -1; 4050c0d06caSMauro Carvalho Chehab } 4060c0d06caSMauro Carvalho Chehab break; 4070c0d06caSMauro Carvalho Chehab default: 4080c0d06caSMauro Carvalho Chehab if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 4090c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 4100c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 4110c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 4120c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 4130c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 4140c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4150c0d06caSMauro Carvalho Chehab &afe_power_status); 4160c0d06caSMauro Carvalho Chehab if (status < 0) 4170c0d06caSMauro Carvalho Chehab break; 4180c0d06caSMauro Carvalho Chehab } 4190c0d06caSMauro Carvalho Chehab 4200c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4210c0d06caSMauro Carvalho Chehab 0x40); 4220c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4230c0d06caSMauro Carvalho Chehab 0x40); 4240c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4250c0d06caSMauro Carvalho Chehab 0x00); 4260c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_DIGITAL) { 4270c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4280c0d06caSMauro Carvalho Chehab 0x70); 4290c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4300c0d06caSMauro Carvalho Chehab 0x70); 4310c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4320c0d06caSMauro Carvalho Chehab 0x70); 4330c0d06caSMauro Carvalho Chehab 4340c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4350c0d06caSMauro Carvalho Chehab &afe_power_status); 4360c0d06caSMauro Carvalho Chehab afe_power_status |= FLD_PWRDN_PD_BANDGAP | 4370c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_BIAS | 4380c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_TUNECK; 4390c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, SUP_BLK_PWRDN, 4400c0d06caSMauro Carvalho Chehab afe_power_status); 4410c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 4420c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 4430c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 4440c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 4450c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 4460c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 4470c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4480c0d06caSMauro Carvalho Chehab &afe_power_status); 4490c0d06caSMauro Carvalho Chehab if (status < 0) 4500c0d06caSMauro Carvalho Chehab break; 4510c0d06caSMauro Carvalho Chehab } 4520c0d06caSMauro Carvalho Chehab 4530c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4540c0d06caSMauro Carvalho Chehab 0x00); 4550c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4560c0d06caSMauro Carvalho Chehab 0x00); 4570c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4580c0d06caSMauro Carvalho Chehab 0x40); 4590c0d06caSMauro Carvalho Chehab } else { 460336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Invalid AV mode input\n"); 4610c0d06caSMauro Carvalho Chehab status = -1; 4620c0d06caSMauro Carvalho Chehab } 4630c0d06caSMauro Carvalho Chehab } /* switch */ 4640c0d06caSMauro Carvalho Chehab 4650c0d06caSMauro Carvalho Chehab return status; 4660c0d06caSMauro Carvalho Chehab } 4670c0d06caSMauro Carvalho Chehab 4680c0d06caSMauro Carvalho Chehab int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 4690c0d06caSMauro Carvalho Chehab { 4700c0d06caSMauro Carvalho Chehab u8 input_mode = 0; 4710c0d06caSMauro Carvalho Chehab u8 ntf_mode = 0; 4720c0d06caSMauro Carvalho Chehab int status = 0; 4730c0d06caSMauro Carvalho Chehab 4740c0d06caSMauro Carvalho Chehab dev->video_input = video_input; 4750c0d06caSMauro Carvalho Chehab 4760c0d06caSMauro Carvalho Chehab if (video_input == CX231XX_VMUX_TELEVISION) { 4770c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 4780c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 4790c0d06caSMauro Carvalho Chehab &ntf_mode); 4800c0d06caSMauro Carvalho Chehab } else { 4810c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 4820c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 4830c0d06caSMauro Carvalho Chehab &ntf_mode); 4840c0d06caSMauro Carvalho Chehab } 4850c0d06caSMauro Carvalho Chehab 4860c0d06caSMauro Carvalho Chehab input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 4870c0d06caSMauro Carvalho Chehab 4880c0d06caSMauro Carvalho Chehab switch (input_mode) { 4890c0d06caSMauro Carvalho Chehab case SINGLE_ENDED: 4900c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x23C; 4910c0d06caSMauro Carvalho Chehab break; 4920c0d06caSMauro Carvalho Chehab case LOW_IF: 4930c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x24C; 4940c0d06caSMauro Carvalho Chehab break; 4950c0d06caSMauro Carvalho Chehab case EU_IF: 4960c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x258; 4970c0d06caSMauro Carvalho Chehab break; 4980c0d06caSMauro Carvalho Chehab case US_IF: 4990c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x260; 5000c0d06caSMauro Carvalho Chehab break; 5010c0d06caSMauro Carvalho Chehab default: 5020c0d06caSMauro Carvalho Chehab break; 5030c0d06caSMauro Carvalho Chehab } 5040c0d06caSMauro Carvalho Chehab 5050c0d06caSMauro Carvalho Chehab status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 5060c0d06caSMauro Carvalho Chehab 5070c0d06caSMauro Carvalho Chehab return status; 5080c0d06caSMauro Carvalho Chehab } 5090c0d06caSMauro Carvalho Chehab 5100c0d06caSMauro Carvalho Chehab /****************************************************************************** 5110c0d06caSMauro Carvalho Chehab * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 5120c0d06caSMauro Carvalho Chehab ******************************************************************************/ 5130c0d06caSMauro Carvalho Chehab static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 5140c0d06caSMauro Carvalho Chehab { 5150c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5160c0d06caSMauro Carvalho Chehab saddr, 2, data, 1); 5170c0d06caSMauro Carvalho Chehab } 5180c0d06caSMauro Carvalho Chehab 5190c0d06caSMauro Carvalho Chehab static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 5200c0d06caSMauro Carvalho Chehab { 5210c0d06caSMauro Carvalho Chehab int status; 5220c0d06caSMauro Carvalho Chehab u32 temp = 0; 5230c0d06caSMauro Carvalho Chehab 5240c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5250c0d06caSMauro Carvalho Chehab saddr, 2, &temp, 1); 5260c0d06caSMauro Carvalho Chehab *data = (u8) temp; 5270c0d06caSMauro Carvalho Chehab return status; 5280c0d06caSMauro Carvalho Chehab } 5290c0d06caSMauro Carvalho Chehab 5300c0d06caSMauro Carvalho Chehab static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 5310c0d06caSMauro Carvalho Chehab { 5320c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5330c0d06caSMauro Carvalho Chehab saddr, 2, data, 4); 5340c0d06caSMauro Carvalho Chehab } 5350c0d06caSMauro Carvalho Chehab 5360c0d06caSMauro Carvalho Chehab static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 5370c0d06caSMauro Carvalho Chehab { 5380c0d06caSMauro Carvalho Chehab return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5390c0d06caSMauro Carvalho Chehab saddr, 2, data, 4); 5400c0d06caSMauro Carvalho Chehab } 5410c0d06caSMauro Carvalho Chehab int cx231xx_check_fw(struct cx231xx *dev) 5420c0d06caSMauro Carvalho Chehab { 5430c0d06caSMauro Carvalho Chehab u8 temp = 0; 5440c0d06caSMauro Carvalho Chehab int status = 0; 5450c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 5460c0d06caSMauro Carvalho Chehab if (status < 0) 5470c0d06caSMauro Carvalho Chehab return status; 5480c0d06caSMauro Carvalho Chehab else 5490c0d06caSMauro Carvalho Chehab return temp; 5500c0d06caSMauro Carvalho Chehab 5510c0d06caSMauro Carvalho Chehab } 5520c0d06caSMauro Carvalho Chehab 5530c0d06caSMauro Carvalho Chehab int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 5540c0d06caSMauro Carvalho Chehab { 5550c0d06caSMauro Carvalho Chehab int status = 0; 5560c0d06caSMauro Carvalho Chehab 5570c0d06caSMauro Carvalho Chehab switch (INPUT(input)->type) { 5580c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_COMPOSITE1: 5590c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_SVIDEO: 5600c0d06caSMauro Carvalho Chehab if ((dev->current_pcb_config.type == USB_BUS_POWER) && 5610c0d06caSMauro Carvalho Chehab (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 5620c0d06caSMauro Carvalho Chehab /* External AV */ 5630c0d06caSMauro Carvalho Chehab status = cx231xx_set_power_mode(dev, 5640c0d06caSMauro Carvalho Chehab POLARIS_AVMODE_ENXTERNAL_AV); 5650c0d06caSMauro Carvalho Chehab if (status < 0) { 566336fea92SMauro Carvalho Chehab dev_err(dev->dev, 567b7085c08SMauro Carvalho Chehab "%s: Failed to set Power - errCode [%d]!\n", 5680c0d06caSMauro Carvalho Chehab __func__, status); 5690c0d06caSMauro Carvalho Chehab return status; 5700c0d06caSMauro Carvalho Chehab } 5710c0d06caSMauro Carvalho Chehab } 5720c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev, 5730c0d06caSMauro Carvalho Chehab INPUT(input)->type, 5740c0d06caSMauro Carvalho Chehab INPUT(input)->vmux); 5750c0d06caSMauro Carvalho Chehab break; 5760c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_TELEVISION: 5770c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_CABLE: 5780c0d06caSMauro Carvalho Chehab if ((dev->current_pcb_config.type == USB_BUS_POWER) && 5790c0d06caSMauro Carvalho Chehab (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 5800c0d06caSMauro Carvalho Chehab /* Tuner */ 5810c0d06caSMauro Carvalho Chehab status = cx231xx_set_power_mode(dev, 5820c0d06caSMauro Carvalho Chehab POLARIS_AVMODE_ANALOGT_TV); 5830c0d06caSMauro Carvalho Chehab if (status < 0) { 584336fea92SMauro Carvalho Chehab dev_err(dev->dev, 585b7085c08SMauro Carvalho Chehab "%s: Failed to set Power - errCode [%d]!\n", 5860c0d06caSMauro Carvalho Chehab __func__, status); 5870c0d06caSMauro Carvalho Chehab return status; 5880c0d06caSMauro Carvalho Chehab } 5890c0d06caSMauro Carvalho Chehab } 5900c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) 5910c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev, 5920c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION, 5930c0d06caSMauro Carvalho Chehab INPUT(input)->vmux); 5940c0d06caSMauro Carvalho Chehab else 5950c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev, 5960c0d06caSMauro Carvalho Chehab CX231XX_VMUX_COMPOSITE1, 5970c0d06caSMauro Carvalho Chehab INPUT(input)->vmux); 5980c0d06caSMauro Carvalho Chehab 5990c0d06caSMauro Carvalho Chehab break; 6000c0d06caSMauro Carvalho Chehab default: 601336fea92SMauro Carvalho Chehab dev_err(dev->dev, "%s: Unknown Input %d !\n", 6020c0d06caSMauro Carvalho Chehab __func__, INPUT(input)->type); 6030c0d06caSMauro Carvalho Chehab break; 6040c0d06caSMauro Carvalho Chehab } 6050c0d06caSMauro Carvalho Chehab 6060c0d06caSMauro Carvalho Chehab /* save the selection */ 6070c0d06caSMauro Carvalho Chehab dev->video_input = input; 6080c0d06caSMauro Carvalho Chehab 6090c0d06caSMauro Carvalho Chehab return status; 6100c0d06caSMauro Carvalho Chehab } 6110c0d06caSMauro Carvalho Chehab 6120c0d06caSMauro Carvalho Chehab int cx231xx_set_decoder_video_input(struct cx231xx *dev, 6130c0d06caSMauro Carvalho Chehab u8 pin_type, u8 input) 6140c0d06caSMauro Carvalho Chehab { 6150c0d06caSMauro Carvalho Chehab int status = 0; 6160c0d06caSMauro Carvalho Chehab u32 value = 0; 6170c0d06caSMauro Carvalho Chehab 6180c0d06caSMauro Carvalho Chehab if (pin_type != dev->video_input) { 6190c0d06caSMauro Carvalho Chehab status = cx231xx_afe_adjust_ref_count(dev, pin_type); 6200c0d06caSMauro Carvalho Chehab if (status < 0) { 621336fea92SMauro Carvalho Chehab dev_err(dev->dev, 622b7085c08SMauro Carvalho Chehab "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n", 6230c0d06caSMauro Carvalho Chehab __func__, status); 6240c0d06caSMauro Carvalho Chehab return status; 6250c0d06caSMauro Carvalho Chehab } 6260c0d06caSMauro Carvalho Chehab } 6270c0d06caSMauro Carvalho Chehab 6280c0d06caSMauro Carvalho Chehab /* call afe block to set video inputs */ 6290c0d06caSMauro Carvalho Chehab status = cx231xx_afe_set_input_mux(dev, input); 6300c0d06caSMauro Carvalho Chehab if (status < 0) { 631336fea92SMauro Carvalho Chehab dev_err(dev->dev, 632b7085c08SMauro Carvalho Chehab "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n", 6330c0d06caSMauro Carvalho Chehab __func__, status); 6340c0d06caSMauro Carvalho Chehab return status; 6350c0d06caSMauro Carvalho Chehab } 6360c0d06caSMauro Carvalho Chehab 6370c0d06caSMauro Carvalho Chehab switch (pin_type) { 6380c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_COMPOSITE1: 6390c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 6400c0d06caSMauro Carvalho Chehab value |= (0 << 13) | (1 << 4); 6410c0d06caSMauro Carvalho Chehab value &= ~(1 << 5); 6420c0d06caSMauro Carvalho Chehab 6430c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */ 6440c0d06caSMauro Carvalho Chehab value &= (~(0x1ff8000)); 6450c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 6460c0d06caSMauro Carvalho Chehab value |= 0x1000000; 6470c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 6480c0d06caSMauro Carvalho Chehab 6490c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value); 6500c0d06caSMauro Carvalho Chehab value |= (1 << 7); 6510c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value); 6520c0d06caSMauro Carvalho Chehab 6530c0d06caSMauro Carvalho Chehab /* Set output mode */ 6540c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 6550c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 6560c0d06caSMauro Carvalho Chehab OUT_CTRL1, 6570c0d06caSMauro Carvalho Chehab FLD_OUT_MODE, 6580c0d06caSMauro Carvalho Chehab dev->board.output_mode); 6590c0d06caSMauro Carvalho Chehab 6600c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */ 6610c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 6620c0d06caSMauro Carvalho Chehab if (status < 0) { 663336fea92SMauro Carvalho Chehab dev_err(dev->dev, 664b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 6650c0d06caSMauro Carvalho Chehab __func__, status); 6660c0d06caSMauro Carvalho Chehab return status; 6670c0d06caSMauro Carvalho Chehab } 6680c0d06caSMauro Carvalho Chehab 6690c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 6700c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 6710c0d06caSMauro Carvalho Chehab 6720c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */ 6730c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN; 6740c0d06caSMauro Carvalho Chehab 6750c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */ 6760c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN; 6770c0d06caSMauro Carvalho Chehab 6780c0d06caSMauro Carvalho Chehab /* Write it back */ 6790c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 6800c0d06caSMauro Carvalho Chehab 6810c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 6820c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 6830c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 6840c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 6850c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 6860c0d06caSMauro Carvalho Chehab 6870c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */ 6880c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 6890c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 6900c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE, 6910c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 6920c0d06caSMauro Carvalho Chehab break; 6930c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_SVIDEO: 6940c0d06caSMauro Carvalho Chehab /* Disable the use of DIF */ 6950c0d06caSMauro Carvalho Chehab 6960c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 6970c0d06caSMauro Carvalho Chehab 6980c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */ 6990c0d06caSMauro Carvalho Chehab value &= (~(0x1ff8000)); 7000c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 7010c0d06caSMauro Carvalho Chehab IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 7020c0d06caSMauro Carvalho Chehab value |= 0x1000010; 7030c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 7040c0d06caSMauro Carvalho Chehab 7050c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */ 7060c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 7070c0d06caSMauro Carvalho Chehab if (status < 0) { 708336fea92SMauro Carvalho Chehab dev_err(dev->dev, 709b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 7100c0d06caSMauro Carvalho Chehab __func__, status); 7110c0d06caSMauro Carvalho Chehab return status; 7120c0d06caSMauro Carvalho Chehab } 7130c0d06caSMauro Carvalho Chehab 7140c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 7150c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 7160c0d06caSMauro Carvalho Chehab 7170c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */ 7180c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN; 7190c0d06caSMauro Carvalho Chehab 7200c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */ 7210c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN; 7220c0d06caSMauro Carvalho Chehab 7230c0d06caSMauro Carvalho Chehab /* Write it back */ 7240c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 7250c0d06caSMauro Carvalho Chehab 7260c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 7270c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 7280c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 7290c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 7300c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 7310c0d06caSMauro Carvalho Chehab 7320c0d06caSMauro Carvalho Chehab /* Set YC input mode */ 7330c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 7340c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 7350c0d06caSMauro Carvalho Chehab MODE_CTRL, 7360c0d06caSMauro Carvalho Chehab FLD_INPUT_MODE, 7370c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 7380c0d06caSMauro Carvalho Chehab 7390c0d06caSMauro Carvalho Chehab /* Chroma to ADC2 */ 7400c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 7410c0d06caSMauro Carvalho Chehab value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 7420c0d06caSMauro Carvalho Chehab 7430c0d06caSMauro Carvalho Chehab /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 7440c0d06caSMauro Carvalho Chehab This sets them to use video 7450c0d06caSMauro Carvalho Chehab rather than audio. Only one of the two will be in use. */ 7460c0d06caSMauro Carvalho Chehab value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 7470c0d06caSMauro Carvalho Chehab 7480c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 7490c0d06caSMauro Carvalho Chehab 7500c0d06caSMauro Carvalho Chehab status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 7510c0d06caSMauro Carvalho Chehab break; 7520c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_TELEVISION: 7530c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_CABLE: 7540c0d06caSMauro Carvalho Chehab default: 7550c0d06caSMauro Carvalho Chehab /* TODO: Test if this is also needed for xc2028/xc3028 */ 7560c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type == TUNER_XC5000) { 7570c0d06caSMauro Carvalho Chehab /* Disable the use of DIF */ 7580c0d06caSMauro Carvalho Chehab 7590c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 7600c0d06caSMauro Carvalho Chehab value |= (0 << 13) | (1 << 4); 7610c0d06caSMauro Carvalho Chehab value &= ~(1 << 5); 7620c0d06caSMauro Carvalho Chehab 7630c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */ 7640c0d06caSMauro Carvalho Chehab value &= (~(0x1FF8000)); 7650c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 7660c0d06caSMauro Carvalho Chehab value |= 0x1000000; 7670c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 7680c0d06caSMauro Carvalho Chehab 7690c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value); 7700c0d06caSMauro Carvalho Chehab value |= (1 << 7); 7710c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value); 7720c0d06caSMauro Carvalho Chehab 7730c0d06caSMauro Carvalho Chehab /* Set output mode */ 7740c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 7750c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 7760c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_OUT_MODE, 7770c0d06caSMauro Carvalho Chehab dev->board.output_mode); 7780c0d06caSMauro Carvalho Chehab 7790c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */ 7800c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, 7810c0d06caSMauro Carvalho Chehab DIF_USE_BASEBAND); 7820c0d06caSMauro Carvalho Chehab if (status < 0) { 783336fea92SMauro Carvalho Chehab dev_err(dev->dev, 784b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 7850c0d06caSMauro Carvalho Chehab __func__, status); 7860c0d06caSMauro Carvalho Chehab return status; 7870c0d06caSMauro Carvalho Chehab } 7880c0d06caSMauro Carvalho Chehab 7890c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 7900c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 7910c0d06caSMauro Carvalho Chehab 7920c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */ 7930c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN; 7940c0d06caSMauro Carvalho Chehab 7950c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */ 7960c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN; 7970c0d06caSMauro Carvalho Chehab 7980c0d06caSMauro Carvalho Chehab /* Write it back */ 7990c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 8000c0d06caSMauro Carvalho Chehab 8010c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 8020c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8030c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8040c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 8050c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 8060c0d06caSMauro Carvalho Chehab 8070c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */ 8080c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8090c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8100c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE, 8110c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, 8120c0d06caSMauro Carvalho Chehab INPUT_MODE_CVBS_0)); 8130c0d06caSMauro Carvalho Chehab } else { 8140c0d06caSMauro Carvalho Chehab /* Enable the DIF for the tuner */ 8150c0d06caSMauro Carvalho Chehab 8160c0d06caSMauro Carvalho Chehab /* Reinitialize the DIF */ 8170c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, dev->norm); 8180c0d06caSMauro Carvalho Chehab if (status < 0) { 819336fea92SMauro Carvalho Chehab dev_err(dev->dev, 820b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n", 8210c0d06caSMauro Carvalho Chehab __func__, status); 8220c0d06caSMauro Carvalho Chehab return status; 8230c0d06caSMauro Carvalho Chehab } 8240c0d06caSMauro Carvalho Chehab 8250c0d06caSMauro Carvalho Chehab /* Make sure bypass is cleared */ 8260c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 8270c0d06caSMauro Carvalho Chehab 8280c0d06caSMauro Carvalho Chehab /* Clear the bypass bit */ 8290c0d06caSMauro Carvalho Chehab value &= ~FLD_DIF_DIF_BYPASS; 8300c0d06caSMauro Carvalho Chehab 8310c0d06caSMauro Carvalho Chehab /* Enable the use of the DIF block */ 8320c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 8330c0d06caSMauro Carvalho Chehab 8340c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 8350c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 8360c0d06caSMauro Carvalho Chehab 8370c0d06caSMauro Carvalho Chehab /* Disable the VBI_GATE_EN */ 8380c0d06caSMauro Carvalho Chehab value &= ~FLD_VBI_GATE_EN; 8390c0d06caSMauro Carvalho Chehab 8400c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable, AGC, and 8410c0d06caSMauro Carvalho Chehab set the skip count to 2 */ 8420c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 8430c0d06caSMauro Carvalho Chehab 8440c0d06caSMauro Carvalho Chehab /* Write it back */ 8450c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 8460c0d06caSMauro Carvalho Chehab 8470c0d06caSMauro Carvalho Chehab /* Wait until AGC locks up */ 8480c0d06caSMauro Carvalho Chehab msleep(1); 8490c0d06caSMauro Carvalho Chehab 8500c0d06caSMauro Carvalho Chehab /* Disable the auto-VGA enable AGC */ 8510c0d06caSMauro Carvalho Chehab value &= ~(FLD_VGA_AUTO_EN); 8520c0d06caSMauro Carvalho Chehab 8530c0d06caSMauro Carvalho Chehab /* Write it back */ 8540c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 8550c0d06caSMauro Carvalho Chehab 8560c0d06caSMauro Carvalho Chehab /* Enable Polaris B0 AGC output */ 8570c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, &value); 8580c0d06caSMauro Carvalho Chehab value |= (FLD_OEF_AGC_RF) | 8590c0d06caSMauro Carvalho Chehab (FLD_OEF_AGC_IFVGA) | 8600c0d06caSMauro Carvalho Chehab (FLD_OEF_AGC_IF); 8610c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, value); 8620c0d06caSMauro Carvalho Chehab 8630c0d06caSMauro Carvalho Chehab /* Set output mode */ 8640c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8650c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8660c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_OUT_MODE, 8670c0d06caSMauro Carvalho Chehab dev->board.output_mode); 8680c0d06caSMauro Carvalho Chehab 8690c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 8700c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8710c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8720c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 8730c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 8740c0d06caSMauro Carvalho Chehab 8750c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */ 8760c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8770c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8780c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE, 8790c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, 8800c0d06caSMauro Carvalho Chehab INPUT_MODE_CVBS_0)); 8810c0d06caSMauro Carvalho Chehab 8820c0d06caSMauro Carvalho Chehab /* Set some bits in AFE_CTRL so that channel 2 or 3 8830c0d06caSMauro Carvalho Chehab * is ready to receive audio */ 8840c0d06caSMauro Carvalho Chehab /* Clear clamp for channels 2 and 3 (bit 16-17) */ 8850c0d06caSMauro Carvalho Chehab /* Clear droop comp (bit 19-20) */ 8860c0d06caSMauro Carvalho Chehab /* Set VGA_SEL (for audio control) (bit 7-8) */ 8870c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 8880c0d06caSMauro Carvalho Chehab 8890c0d06caSMauro Carvalho Chehab /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 8900c0d06caSMauro Carvalho Chehab value &= (~(FLD_FUNC_MODE)); 8910c0d06caSMauro Carvalho Chehab value |= 0x800000; 8920c0d06caSMauro Carvalho Chehab 8930c0d06caSMauro Carvalho Chehab value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 8940c0d06caSMauro Carvalho Chehab 8950c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 8960c0d06caSMauro Carvalho Chehab 8970c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) { 8980c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, 8990c0d06caSMauro Carvalho Chehab &value); 9000c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, 9010c0d06caSMauro Carvalho Chehab (value & 0xFFFFFFEF)); 9020c0d06caSMauro Carvalho Chehab } 9030c0d06caSMauro Carvalho Chehab 9040c0d06caSMauro Carvalho Chehab break; 9050c0d06caSMauro Carvalho Chehab 9060c0d06caSMauro Carvalho Chehab } 9070c0d06caSMauro Carvalho Chehab break; 9080c0d06caSMauro Carvalho Chehab } 9090c0d06caSMauro Carvalho Chehab 9100c0d06caSMauro Carvalho Chehab /* Set raw VBI mode */ 9110c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9120c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9130c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_VBIHACTRAW_EN, 9140c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 9150c0d06caSMauro Carvalho Chehab 9160c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value); 9170c0d06caSMauro Carvalho Chehab if (value & 0x02) { 9180c0d06caSMauro Carvalho Chehab value |= (1 << 19); 9190c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value); 9200c0d06caSMauro Carvalho Chehab } 9210c0d06caSMauro Carvalho Chehab 9220c0d06caSMauro Carvalho Chehab return status; 9230c0d06caSMauro Carvalho Chehab } 9240c0d06caSMauro Carvalho Chehab 9250c0d06caSMauro Carvalho Chehab void cx231xx_enable656(struct cx231xx *dev) 9260c0d06caSMauro Carvalho Chehab { 9270c0d06caSMauro Carvalho Chehab u8 temp = 0; 9280c0d06caSMauro Carvalho Chehab /*enable TS1 data[0:7] as output to export 656*/ 9290c0d06caSMauro Carvalho Chehab 9300c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 9310c0d06caSMauro Carvalho Chehab 9320c0d06caSMauro Carvalho Chehab /*enable TS1 clock as output to export 656*/ 9330c0d06caSMauro Carvalho Chehab 9340c0d06caSMauro Carvalho Chehab vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 9350c0d06caSMauro Carvalho Chehab temp = temp|0x04; 9360c0d06caSMauro Carvalho Chehab 9370c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 9380c0d06caSMauro Carvalho Chehab } 9390c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_enable656); 9400c0d06caSMauro Carvalho Chehab 9410c0d06caSMauro Carvalho Chehab void cx231xx_disable656(struct cx231xx *dev) 9420c0d06caSMauro Carvalho Chehab { 9430c0d06caSMauro Carvalho Chehab u8 temp = 0; 9440c0d06caSMauro Carvalho Chehab 9450c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 9460c0d06caSMauro Carvalho Chehab 9470c0d06caSMauro Carvalho Chehab vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 9480c0d06caSMauro Carvalho Chehab temp = temp&0xFB; 9490c0d06caSMauro Carvalho Chehab 9500c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 9510c0d06caSMauro Carvalho Chehab } 9520c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_disable656); 9530c0d06caSMauro Carvalho Chehab 9540c0d06caSMauro Carvalho Chehab /* 9550c0d06caSMauro Carvalho Chehab * Handle any video-mode specific overrides that are different 9560c0d06caSMauro Carvalho Chehab * on a per video standards basis after touching the MODE_CTRL 9570c0d06caSMauro Carvalho Chehab * register which resets many values for autodetect 9580c0d06caSMauro Carvalho Chehab */ 9590c0d06caSMauro Carvalho Chehab int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 9600c0d06caSMauro Carvalho Chehab { 9610c0d06caSMauro Carvalho Chehab int status = 0; 9620c0d06caSMauro Carvalho Chehab 963336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: 0x%x\n", 964ed0e3729SMauro Carvalho Chehab __func__, (unsigned int)dev->norm); 9650c0d06caSMauro Carvalho Chehab 9660c0d06caSMauro Carvalho Chehab /* Change the DFE_CTRL3 bp_percent to fix flagging */ 9670c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 9680c0d06caSMauro Carvalho Chehab 9690c0d06caSMauro Carvalho Chehab if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 970336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: NTSC\n", __func__); 9710c0d06caSMauro Carvalho Chehab 9720c0d06caSMauro Carvalho Chehab /* Move the close caption lines out of active video, 9730c0d06caSMauro Carvalho Chehab adjust the active video start point */ 9740c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9750c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9760c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 9770c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x18); 9780c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9790c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9800c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 9810c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT, 9820c0d06caSMauro Carvalho Chehab 0x1E7000); 9830c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9840c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9850c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 9860c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT, 9870c0d06caSMauro Carvalho Chehab 0x1C000000); 9880c0d06caSMauro Carvalho Chehab 9890c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9900c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9910c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL, 9920c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT, 9930c0d06caSMauro Carvalho Chehab cx231xx_set_field 9940c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x79)); 9950c0d06caSMauro Carvalho Chehab 9960c0d06caSMauro Carvalho Chehab } else if (dev->norm & V4L2_STD_SECAM) { 997336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: SECAM\n", __func__); 9980c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9990c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10000c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10010c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x20); 10020c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10030c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10040c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10050c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT, 10060c0d06caSMauro Carvalho Chehab cx231xx_set_field 10070c0d06caSMauro Carvalho Chehab (FLD_VACTIVE_CNT, 10080c0d06caSMauro Carvalho Chehab 0x244)); 10090c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10100c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10110c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10120c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT, 10130c0d06caSMauro Carvalho Chehab cx231xx_set_field 10140c0d06caSMauro Carvalho Chehab (FLD_V656BLANK_CNT, 10150c0d06caSMauro Carvalho Chehab 0x24)); 10160c0d06caSMauro Carvalho Chehab /* Adjust the active video horizontal start point */ 10170c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10180c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10190c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL, 10200c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT, 10210c0d06caSMauro Carvalho Chehab cx231xx_set_field 10220c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x85)); 10230c0d06caSMauro Carvalho Chehab } else { 1024336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: PAL\n", __func__); 10250c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10260c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10270c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10280c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x20); 10290c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10300c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10310c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10320c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT, 10330c0d06caSMauro Carvalho Chehab cx231xx_set_field 10340c0d06caSMauro Carvalho Chehab (FLD_VACTIVE_CNT, 10350c0d06caSMauro Carvalho Chehab 0x244)); 10360c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10370c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10380c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10390c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT, 10400c0d06caSMauro Carvalho Chehab cx231xx_set_field 10410c0d06caSMauro Carvalho Chehab (FLD_V656BLANK_CNT, 10420c0d06caSMauro Carvalho Chehab 0x24)); 10430c0d06caSMauro Carvalho Chehab /* Adjust the active video horizontal start point */ 10440c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10450c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10460c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL, 10470c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT, 10480c0d06caSMauro Carvalho Chehab cx231xx_set_field 10490c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x85)); 10500c0d06caSMauro Carvalho Chehab 10510c0d06caSMauro Carvalho Chehab } 10520c0d06caSMauro Carvalho Chehab 10530c0d06caSMauro Carvalho Chehab return status; 10540c0d06caSMauro Carvalho Chehab } 10550c0d06caSMauro Carvalho Chehab 10560c0d06caSMauro Carvalho Chehab int cx231xx_unmute_audio(struct cx231xx *dev) 10570c0d06caSMauro Carvalho Chehab { 10580c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 10590c0d06caSMauro Carvalho Chehab } 10600c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 10610c0d06caSMauro Carvalho Chehab 1062d4c06133SMauro Carvalho Chehab static int stopAudioFirmware(struct cx231xx *dev) 10630c0d06caSMauro Carvalho Chehab { 10640c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 10650c0d06caSMauro Carvalho Chehab } 10660c0d06caSMauro Carvalho Chehab 1067d4c06133SMauro Carvalho Chehab static int restartAudioFirmware(struct cx231xx *dev) 10680c0d06caSMauro Carvalho Chehab { 10690c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 10700c0d06caSMauro Carvalho Chehab } 10710c0d06caSMauro Carvalho Chehab 10720c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 10730c0d06caSMauro Carvalho Chehab { 10740c0d06caSMauro Carvalho Chehab int status = 0; 10750c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 10760c0d06caSMauro Carvalho Chehab 10770c0d06caSMauro Carvalho Chehab switch (INPUT(input)->amux) { 10780c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_VIDEO: 10790c0d06caSMauro Carvalho Chehab ainput = AUDIO_INPUT_TUNER_TV; 10800c0d06caSMauro Carvalho Chehab break; 10810c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_LINE_IN: 10820c0d06caSMauro Carvalho Chehab status = cx231xx_i2s_blk_set_audio_input(dev, input); 10830c0d06caSMauro Carvalho Chehab ainput = AUDIO_INPUT_LINE; 10840c0d06caSMauro Carvalho Chehab break; 10850c0d06caSMauro Carvalho Chehab default: 10860c0d06caSMauro Carvalho Chehab break; 10870c0d06caSMauro Carvalho Chehab } 10880c0d06caSMauro Carvalho Chehab 10890c0d06caSMauro Carvalho Chehab status = cx231xx_set_audio_decoder_input(dev, ainput); 10900c0d06caSMauro Carvalho Chehab 10910c0d06caSMauro Carvalho Chehab return status; 10920c0d06caSMauro Carvalho Chehab } 10930c0d06caSMauro Carvalho Chehab 10940c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 10950c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT audio_input) 10960c0d06caSMauro Carvalho Chehab { 10970c0d06caSMauro Carvalho Chehab u32 dwval; 10980c0d06caSMauro Carvalho Chehab int status; 10990c0d06caSMauro Carvalho Chehab u8 gen_ctrl; 11000c0d06caSMauro Carvalho Chehab u32 value = 0; 11010c0d06caSMauro Carvalho Chehab 11020c0d06caSMauro Carvalho Chehab /* Put it in soft reset */ 11030c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 11040c0d06caSMauro Carvalho Chehab gen_ctrl |= 1; 11050c0d06caSMauro Carvalho Chehab status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 11060c0d06caSMauro Carvalho Chehab 11070c0d06caSMauro Carvalho Chehab switch (audio_input) { 11080c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_LINE: 11090c0d06caSMauro Carvalho Chehab /* setup AUD_IO control from Merlin paralle output */ 11100c0d06caSMauro Carvalho Chehab value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 11110c0d06caSMauro Carvalho Chehab AUD_CHAN_SRC_PARALLEL); 11120c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 11130c0d06caSMauro Carvalho Chehab 11140c0d06caSMauro Carvalho Chehab /* setup input to Merlin, SRC2 connect to AC97 11150c0d06caSMauro Carvalho Chehab bypass upsample-by-2, slave mode, sony mode, left justify 11160c0d06caSMauro Carvalho Chehab adr 091c, dat 01000000 */ 11170c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AC97_CTL, &dwval); 11180c0d06caSMauro Carvalho Chehab 11190c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AC97_CTL, 11200c0d06caSMauro Carvalho Chehab (dwval | FLD_AC97_UP2X_BYPASS)); 11210c0d06caSMauro Carvalho Chehab 11220c0d06caSMauro Carvalho Chehab /* select the parallel1 and SRC3 */ 11230c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, BAND_OUT_SEL, 11240c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 11250c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 11260c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 11270c0d06caSMauro Carvalho Chehab 11280c0d06caSMauro Carvalho Chehab /* unmute all, AC97 in, independence mode 11290c0d06caSMauro Carvalho Chehab adr 08d0, data 0x00063073 */ 11300c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 11310c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 11320c0d06caSMauro Carvalho Chehab 11330c0d06caSMauro Carvalho Chehab /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 11340c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 11350c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_VOL_CTL, 11360c0d06caSMauro Carvalho Chehab (dwval | FLD_PATH1_AVC_THRESHOLD)); 11370c0d06caSMauro Carvalho Chehab 11380c0d06caSMauro Carvalho Chehab /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 11390c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 11400c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_SC_CTL, 11410c0d06caSMauro Carvalho Chehab (dwval | FLD_PATH1_SC_THRESHOLD)); 11420c0d06caSMauro Carvalho Chehab break; 11430c0d06caSMauro Carvalho Chehab 11440c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_TUNER_TV: 11450c0d06caSMauro Carvalho Chehab default: 11460c0d06caSMauro Carvalho Chehab status = stopAudioFirmware(dev); 11470c0d06caSMauro Carvalho Chehab /* Setup SRC sources and clocks */ 11480c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, BAND_OUT_SEL, 11490c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 11500c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 11510c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 11520c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 11530c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 11540c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 11550c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 11560c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 11570c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 11580c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 11590c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 11600c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 11610c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 11620c0d06caSMauro Carvalho Chehab 11630c0d06caSMauro Carvalho Chehab /* Setup the AUD_IO control */ 11640c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AUD_IO_CTRL, 11650c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 11660c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 11670c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 11680c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 11690c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 11700c0d06caSMauro Carvalho Chehab 11710c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 11720c0d06caSMauro Carvalho Chehab 11730c0d06caSMauro Carvalho Chehab /* setAudioStandard(_audio_standard); */ 11740c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 11750c0d06caSMauro Carvalho Chehab 11760c0d06caSMauro Carvalho Chehab status = restartAudioFirmware(dev); 11770c0d06caSMauro Carvalho Chehab 11780c0d06caSMauro Carvalho Chehab switch (dev->board.tuner_type) { 11790c0d06caSMauro Carvalho Chehab case TUNER_XC5000: 11800c0d06caSMauro Carvalho Chehab /* SIF passthrough at 28.6363 MHz sample rate */ 11810c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 11820c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 11830c0d06caSMauro Carvalho Chehab CHIP_CTRL, 11840c0d06caSMauro Carvalho Chehab FLD_SIF_EN, 11850c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SIF_EN, 1)); 11860c0d06caSMauro Carvalho Chehab break; 11870c0d06caSMauro Carvalho Chehab case TUNER_NXP_TDA18271: 11880c0d06caSMauro Carvalho Chehab /* Normal mode: SIF passthrough at 14.32 MHz */ 11890c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 11900c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 11910c0d06caSMauro Carvalho Chehab CHIP_CTRL, 11920c0d06caSMauro Carvalho Chehab FLD_SIF_EN, 11930c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SIF_EN, 0)); 11940c0d06caSMauro Carvalho Chehab break; 11950c0d06caSMauro Carvalho Chehab default: 11960c0d06caSMauro Carvalho Chehab /* This is just a casual suggestion to people adding 11970c0d06caSMauro Carvalho Chehab new boards in case they use a tuner type we don't 11980c0d06caSMauro Carvalho Chehab currently know about */ 1199336fea92SMauro Carvalho Chehab dev_info(dev->dev, 12003b795d01SMauro Carvalho Chehab "Unknown tuner type configuring SIF"); 12010c0d06caSMauro Carvalho Chehab break; 12020c0d06caSMauro Carvalho Chehab } 12030c0d06caSMauro Carvalho Chehab break; 12040c0d06caSMauro Carvalho Chehab 12050c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_TUNER_FM: 12060c0d06caSMauro Carvalho Chehab /* use SIF for FM radio 12070c0d06caSMauro Carvalho Chehab setupFM(); 12080c0d06caSMauro Carvalho Chehab setAudioStandard(_audio_standard); 12090c0d06caSMauro Carvalho Chehab */ 12100c0d06caSMauro Carvalho Chehab break; 12110c0d06caSMauro Carvalho Chehab 12120c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_MUTE: 12130c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 12140c0d06caSMauro Carvalho Chehab break; 12150c0d06caSMauro Carvalho Chehab } 12160c0d06caSMauro Carvalho Chehab 12170c0d06caSMauro Carvalho Chehab /* Take it out of soft reset */ 12180c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 12190c0d06caSMauro Carvalho Chehab gen_ctrl &= ~1; 12200c0d06caSMauro Carvalho Chehab status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 12210c0d06caSMauro Carvalho Chehab 12220c0d06caSMauro Carvalho Chehab return status; 12230c0d06caSMauro Carvalho Chehab } 12240c0d06caSMauro Carvalho Chehab 12250c0d06caSMauro Carvalho Chehab /****************************************************************************** 12260c0d06caSMauro Carvalho Chehab * C H I P Specific C O N T R O L functions * 12270c0d06caSMauro Carvalho Chehab ******************************************************************************/ 12280c0d06caSMauro Carvalho Chehab int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 12290c0d06caSMauro Carvalho Chehab { 12300c0d06caSMauro Carvalho Chehab u32 value; 12310c0d06caSMauro Carvalho Chehab int status = 0; 12320c0d06caSMauro Carvalho Chehab 12330c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, &value); 12340c0d06caSMauro Carvalho Chehab value |= (~dev->board.ctl_pin_status_mask); 12350c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, value); 12360c0d06caSMauro Carvalho Chehab 12370c0d06caSMauro Carvalho Chehab return status; 12380c0d06caSMauro Carvalho Chehab } 12390c0d06caSMauro Carvalho Chehab 12400c0d06caSMauro Carvalho Chehab int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 12410c0d06caSMauro Carvalho Chehab u8 analog_or_digital) 12420c0d06caSMauro Carvalho Chehab { 12430c0d06caSMauro Carvalho Chehab int status = 0; 12440c0d06caSMauro Carvalho Chehab 12450c0d06caSMauro Carvalho Chehab /* first set the direction to output */ 12460c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_direction(dev, 12470c0d06caSMauro Carvalho Chehab dev->board. 12480c0d06caSMauro Carvalho Chehab agc_analog_digital_select_gpio, 1); 12490c0d06caSMauro Carvalho Chehab 12500c0d06caSMauro Carvalho Chehab /* 0 - demod ; 1 - Analog mode */ 12510c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_value(dev, 12520c0d06caSMauro Carvalho Chehab dev->board.agc_analog_digital_select_gpio, 12530c0d06caSMauro Carvalho Chehab analog_or_digital); 12540c0d06caSMauro Carvalho Chehab 12551871d718SMauro Carvalho Chehab if (status < 0) 12560c0d06caSMauro Carvalho Chehab return status; 12571871d718SMauro Carvalho Chehab 12581871d718SMauro Carvalho Chehab return 0; 12590c0d06caSMauro Carvalho Chehab } 12600c0d06caSMauro Carvalho Chehab 12610c0d06caSMauro Carvalho Chehab int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 12620c0d06caSMauro Carvalho Chehab { 12630c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 12640c0d06caSMauro Carvalho Chehab int status = 0; 12650c0d06caSMauro Carvalho Chehab bool current_is_port_3; 12660c0d06caSMauro Carvalho Chehab 1267a1f26765SMatthias Schwarzott /* 1268a1f26765SMatthias Schwarzott * Should this code check dev->port_3_switch_enabled first 1269a1f26765SMatthias Schwarzott * to skip unnecessary reading of the register? 1270a1f26765SMatthias Schwarzott * If yes, the flag dev->port_3_switch_enabled must be initialized 1271a1f26765SMatthias Schwarzott * correctly. 1272a1f26765SMatthias Schwarzott */ 1273a1f26765SMatthias Schwarzott 12740c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 12750c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 12760c0d06caSMauro Carvalho Chehab if (status < 0) 12770c0d06caSMauro Carvalho Chehab return status; 12780c0d06caSMauro Carvalho Chehab 12790c0d06caSMauro Carvalho Chehab current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 12800c0d06caSMauro Carvalho Chehab 12810c0d06caSMauro Carvalho Chehab /* Just return, if already using the right port */ 12820c0d06caSMauro Carvalho Chehab if (current_is_port_3 == is_port_3) 12830c0d06caSMauro Carvalho Chehab return 0; 12840c0d06caSMauro Carvalho Chehab 12850c0d06caSMauro Carvalho Chehab if (is_port_3) 12860c0d06caSMauro Carvalho Chehab value[0] |= I2C_DEMOD_EN; 12870c0d06caSMauro Carvalho Chehab else 12880c0d06caSMauro Carvalho Chehab value[0] &= ~I2C_DEMOD_EN; 12890c0d06caSMauro Carvalho Chehab 12900c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 12910c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 12920c0d06caSMauro Carvalho Chehab 1293a1f26765SMatthias Schwarzott /* remember status of the switch for usage in is_tuner */ 1294a1f26765SMatthias Schwarzott if (status >= 0) 1295a1f26765SMatthias Schwarzott dev->port_3_switch_enabled = is_port_3; 1296a1f26765SMatthias Schwarzott 12970c0d06caSMauro Carvalho Chehab return status; 12980c0d06caSMauro Carvalho Chehab 12990c0d06caSMauro Carvalho Chehab } 13000c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 13010c0d06caSMauro Carvalho Chehab 13020c0d06caSMauro Carvalho Chehab void update_HH_register_after_set_DIF(struct cx231xx *dev) 13030c0d06caSMauro Carvalho Chehab { 13040c0d06caSMauro Carvalho Chehab /* 13050c0d06caSMauro Carvalho Chehab u8 status = 0; 13060c0d06caSMauro Carvalho Chehab u32 value = 0; 13070c0d06caSMauro Carvalho Chehab 13080c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 13090c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 13100c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 13110c0d06caSMauro Carvalho Chehab 13120c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 13130c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 13140c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 13150c0d06caSMauro Carvalho Chehab */ 13160c0d06caSMauro Carvalho Chehab } 13170c0d06caSMauro Carvalho Chehab 13180c0d06caSMauro Carvalho Chehab void cx231xx_dump_HH_reg(struct cx231xx *dev) 13190c0d06caSMauro Carvalho Chehab { 13200c0d06caSMauro Carvalho Chehab u32 value = 0; 13210c0d06caSMauro Carvalho Chehab u16 i = 0; 13220c0d06caSMauro Carvalho Chehab 13230c0d06caSMauro Carvalho Chehab value = 0x45005390; 13240c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, 0x104, value); 13250c0d06caSMauro Carvalho Chehab 13260c0d06caSMauro Carvalho Chehab for (i = 0x100; i < 0x140; i++) { 13270c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value); 1328336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 13290c0d06caSMauro Carvalho Chehab i = i+3; 13300c0d06caSMauro Carvalho Chehab } 13310c0d06caSMauro Carvalho Chehab 13320c0d06caSMauro Carvalho Chehab for (i = 0x300; i < 0x400; i++) { 13330c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value); 1334336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 13350c0d06caSMauro Carvalho Chehab i = i+3; 13360c0d06caSMauro Carvalho Chehab } 13370c0d06caSMauro Carvalho Chehab 13380c0d06caSMauro Carvalho Chehab for (i = 0x400; i < 0x440; i++) { 13390c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value); 1340336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value); 13410c0d06caSMauro Carvalho Chehab i = i+3; 13420c0d06caSMauro Carvalho Chehab } 13430c0d06caSMauro Carvalho Chehab 13440c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1345336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 13460c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 13470c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1348336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 13490c0d06caSMauro Carvalho Chehab } 13500c0d06caSMauro Carvalho Chehab 1351ed0e3729SMauro Carvalho Chehab #if 0 1352ed0e3729SMauro Carvalho Chehab static void cx231xx_dump_SC_reg(struct cx231xx *dev) 13530c0d06caSMauro Carvalho Chehab { 13540c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 1355336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s!\n", __func__); 13560c0d06caSMauro Carvalho Chehab 13570c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 13580c0d06caSMauro Carvalho Chehab value, 4); 1359336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1360b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 13610c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13620c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 13630c0d06caSMauro Carvalho Chehab value, 4); 1364336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1365b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 13660c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13670c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 13680c0d06caSMauro Carvalho Chehab value, 4); 1369336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1370b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 13710c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13720c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 13730c0d06caSMauro Carvalho Chehab value, 4); 1374336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1375b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 13760c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13770c0d06caSMauro Carvalho Chehab 13780c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 13790c0d06caSMauro Carvalho Chehab value, 4); 1380336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1381b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 13820c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13830c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 13840c0d06caSMauro Carvalho Chehab value, 4); 1385336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1386b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 13870c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13880c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 13890c0d06caSMauro Carvalho Chehab value, 4); 1390336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1391b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 13920c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13930c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 13940c0d06caSMauro Carvalho Chehab value, 4); 1395336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1396b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 13970c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13980c0d06caSMauro Carvalho Chehab 13990c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 14000c0d06caSMauro Carvalho Chehab value, 4); 1401336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1402b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 14030c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14040c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 14050c0d06caSMauro Carvalho Chehab value, 4); 1406336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1407b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 14080c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14090c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 14100c0d06caSMauro Carvalho Chehab value, 4); 1411336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1412b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 14130c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14140c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 14150c0d06caSMauro Carvalho Chehab value, 4); 1416336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1417b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 14180c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14190c0d06caSMauro Carvalho Chehab 14200c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 14210c0d06caSMauro Carvalho Chehab value, 4); 1422336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1423b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 14240c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14250c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 14260c0d06caSMauro Carvalho Chehab value, 4); 1427336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1428b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 14290c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14300c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 14310c0d06caSMauro Carvalho Chehab value, 4); 1432336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1433b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 14340c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14350c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 14360c0d06caSMauro Carvalho Chehab value, 4); 1437336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1438b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 14390c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14400c0d06caSMauro Carvalho Chehab 14410c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 14420c0d06caSMauro Carvalho Chehab value, 4); 1443336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1444b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 14450c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14460c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 14470c0d06caSMauro Carvalho Chehab value, 4); 1448336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 1449b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 14500c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14510c0d06caSMauro Carvalho Chehab } 1452ed0e3729SMauro Carvalho Chehab #endif 14530c0d06caSMauro Carvalho Chehab 14540c0d06caSMauro Carvalho Chehab void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 14550c0d06caSMauro Carvalho Chehab 14560c0d06caSMauro Carvalho Chehab { 14570c0d06caSMauro Carvalho Chehab u8 value = 0; 14580c0d06caSMauro Carvalho Chehab 14590c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_STATUS2_CH3, &value); 14600c0d06caSMauro Carvalho Chehab value = (value & 0xFE)|0x01; 14610c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_STATUS2_CH3, value); 14620c0d06caSMauro Carvalho Chehab 14630c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_STATUS2_CH3, &value); 14640c0d06caSMauro Carvalho Chehab value = (value & 0xFE)|0x00; 14650c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_STATUS2_CH3, value); 14660c0d06caSMauro Carvalho Chehab 14670c0d06caSMauro Carvalho Chehab 14680c0d06caSMauro Carvalho Chehab /* 14690c0d06caSMauro Carvalho Chehab config colibri to lo-if mode 14700c0d06caSMauro Carvalho Chehab 14710c0d06caSMauro Carvalho Chehab FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 14720c0d06caSMauro Carvalho Chehab the diff IF input by half, 14730c0d06caSMauro Carvalho Chehab 14740c0d06caSMauro Carvalho Chehab for low-if agc defect 14750c0d06caSMauro Carvalho Chehab */ 14760c0d06caSMauro Carvalho Chehab 14770c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 14780c0d06caSMauro Carvalho Chehab value = (value & 0xFC)|0x00; 14790c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 14800c0d06caSMauro Carvalho Chehab 14810c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_INPUT_CH3, &value); 14820c0d06caSMauro Carvalho Chehab value = (value & 0xF9)|0x02; 14830c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_INPUT_CH3, value); 14840c0d06caSMauro Carvalho Chehab 14850c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 14860c0d06caSMauro Carvalho Chehab value = (value & 0xFB)|0x04; 14870c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 14880c0d06caSMauro Carvalho Chehab 14890c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 14900c0d06caSMauro Carvalho Chehab value = (value & 0xFC)|0x03; 14910c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 14920c0d06caSMauro Carvalho Chehab 14930c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 14940c0d06caSMauro Carvalho Chehab value = (value & 0xFB)|0x04; 14950c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 14960c0d06caSMauro Carvalho Chehab 14970c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 14980c0d06caSMauro Carvalho Chehab value = (value & 0xF8)|0x06; 14990c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 15000c0d06caSMauro Carvalho Chehab 15010c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 15020c0d06caSMauro Carvalho Chehab value = (value & 0x8F)|0x40; 15030c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 15040c0d06caSMauro Carvalho Chehab 15050c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 15060c0d06caSMauro Carvalho Chehab value = (value & 0xDF)|0x20; 15070c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 15080c0d06caSMauro Carvalho Chehab } 15090c0d06caSMauro Carvalho Chehab 15100c0d06caSMauro Carvalho Chehab void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 15110c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode) 15120c0d06caSMauro Carvalho Chehab { 15130c0d06caSMauro Carvalho Chehab u32 colibri_carrier_offset = 0; 15140c0d06caSMauro Carvalho Chehab u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 15150c0d06caSMauro Carvalho Chehab u32 standard = 0; 15160c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 15170c0d06caSMauro Carvalho Chehab 1518336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n"); 15190c0d06caSMauro Carvalho Chehab value[0] = (u8) 0x6F; 15200c0d06caSMauro Carvalho Chehab value[1] = (u8) 0x6F; 15210c0d06caSMauro Carvalho Chehab value[2] = (u8) 0x6F; 15220c0d06caSMauro Carvalho Chehab value[3] = (u8) 0x6F; 15230c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 15240c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 15250c0d06caSMauro Carvalho Chehab 15260c0d06caSMauro Carvalho Chehab /*Set colibri for low IF*/ 15270c0d06caSMauro Carvalho Chehab cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 15280c0d06caSMauro Carvalho Chehab 15290c0d06caSMauro Carvalho Chehab /* Set C2HH for low IF operation.*/ 15300c0d06caSMauro Carvalho Chehab standard = dev->norm; 15310c0d06caSMauro Carvalho Chehab cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 15320c0d06caSMauro Carvalho Chehab func_mode, standard); 15330c0d06caSMauro Carvalho Chehab 15340c0d06caSMauro Carvalho Chehab /* Get colibri offsets.*/ 15350c0d06caSMauro Carvalho Chehab colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 15360c0d06caSMauro Carvalho Chehab standard); 15370c0d06caSMauro Carvalho Chehab 1538336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n", 15390c0d06caSMauro Carvalho Chehab colibri_carrier_offset, standard); 15400c0d06caSMauro Carvalho Chehab 15410c0d06caSMauro Carvalho Chehab /* Set the band Pass filter for DIF*/ 15420c0d06caSMauro Carvalho Chehab cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 15430c0d06caSMauro Carvalho Chehab spectral_invert, mode); 15440c0d06caSMauro Carvalho Chehab } 15450c0d06caSMauro Carvalho Chehab 15460c0d06caSMauro Carvalho Chehab u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 15470c0d06caSMauro Carvalho Chehab { 15480c0d06caSMauro Carvalho Chehab u32 colibri_carrier_offset = 0; 15490c0d06caSMauro Carvalho Chehab 15500c0d06caSMauro Carvalho Chehab if (mode == TUNER_MODE_FM_RADIO) { 15510c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 1100000; 15520c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 15530c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 4832000; /*4.83MHz */ 15540c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 15550c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 2700000; /*2.70MHz */ 15560c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 15570c0d06caSMauro Carvalho Chehab | V4L2_STD_SECAM)) { 15580c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 2100000; /*2.10MHz */ 15590c0d06caSMauro Carvalho Chehab } 15600c0d06caSMauro Carvalho Chehab 15610c0d06caSMauro Carvalho Chehab return colibri_carrier_offset; 15620c0d06caSMauro Carvalho Chehab } 15630c0d06caSMauro Carvalho Chehab 15640c0d06caSMauro Carvalho Chehab void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 15650c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode) 15660c0d06caSMauro Carvalho Chehab { 15670c0d06caSMauro Carvalho Chehab unsigned long pll_freq_word; 15680c0d06caSMauro Carvalho Chehab u32 dif_misc_ctrl_value = 0; 15690c0d06caSMauro Carvalho Chehab u64 pll_freq_u64 = 0; 15700c0d06caSMauro Carvalho Chehab u32 i = 0; 15710c0d06caSMauro Carvalho Chehab 1572336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 15730c0d06caSMauro Carvalho Chehab if_freq, spectral_invert, mode); 15740c0d06caSMauro Carvalho Chehab 15750c0d06caSMauro Carvalho Chehab 15760c0d06caSMauro Carvalho Chehab if (mode == TUNER_MODE_FM_RADIO) { 15770c0d06caSMauro Carvalho Chehab pll_freq_word = 0x905A1CAC; 15780c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 15790c0d06caSMauro Carvalho Chehab 15800c0d06caSMauro Carvalho Chehab } else /*KSPROPERTY_TUNER_MODE_TV*/{ 15810c0d06caSMauro Carvalho Chehab /* Calculate the PLL frequency word based on the adjusted if_freq*/ 15820c0d06caSMauro Carvalho Chehab pll_freq_word = if_freq; 15830c0d06caSMauro Carvalho Chehab pll_freq_u64 = (u64)pll_freq_word << 28L; 15840c0d06caSMauro Carvalho Chehab do_div(pll_freq_u64, 50000000); 15850c0d06caSMauro Carvalho Chehab pll_freq_word = (u32)pll_freq_u64; 15860c0d06caSMauro Carvalho Chehab /*pll_freq_word = 0x3463497;*/ 15870c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 15880c0d06caSMauro Carvalho Chehab 15890c0d06caSMauro Carvalho Chehab if (spectral_invert) { 15900c0d06caSMauro Carvalho Chehab if_freq -= 400000; 15910c0d06caSMauro Carvalho Chehab /* Enable Spectral Invert*/ 15920c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, DIF_MISC_CTRL, 15930c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value); 15940c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 15950c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 15960c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value); 15970c0d06caSMauro Carvalho Chehab } else { 15980c0d06caSMauro Carvalho Chehab if_freq += 400000; 15990c0d06caSMauro Carvalho Chehab /* Disable Spectral Invert*/ 16000c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, DIF_MISC_CTRL, 16010c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value); 16020c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 16030c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 16040c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value); 16050c0d06caSMauro Carvalho Chehab } 16060c0d06caSMauro Carvalho Chehab 16070c0d06caSMauro Carvalho Chehab if_freq = (if_freq / 100000) * 100000; 16080c0d06caSMauro Carvalho Chehab 16090c0d06caSMauro Carvalho Chehab if (if_freq < 3000000) 16100c0d06caSMauro Carvalho Chehab if_freq = 3000000; 16110c0d06caSMauro Carvalho Chehab 16120c0d06caSMauro Carvalho Chehab if (if_freq > 16000000) 16130c0d06caSMauro Carvalho Chehab if_freq = 16000000; 16140c0d06caSMauro Carvalho Chehab } 16150c0d06caSMauro Carvalho Chehab 1616336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array)); 16170c0d06caSMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 16180c0d06caSMauro Carvalho Chehab if (Dif_set_array[i].if_freq == if_freq) { 16190c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, 16200c0d06caSMauro Carvalho Chehab Dif_set_array[i].register_address, Dif_set_array[i].value); 16210c0d06caSMauro Carvalho Chehab } 16220c0d06caSMauro Carvalho Chehab } 16230c0d06caSMauro Carvalho Chehab } 16240c0d06caSMauro Carvalho Chehab 16250c0d06caSMauro Carvalho Chehab /****************************************************************************** 16260c0d06caSMauro Carvalho Chehab * D I F - B L O C K C O N T R O L functions * 16270c0d06caSMauro Carvalho Chehab ******************************************************************************/ 16280c0d06caSMauro Carvalho Chehab int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 16290c0d06caSMauro Carvalho Chehab u32 function_mode, u32 standard) 16300c0d06caSMauro Carvalho Chehab { 16310c0d06caSMauro Carvalho Chehab int status = 0; 16320c0d06caSMauro Carvalho Chehab 16330c0d06caSMauro Carvalho Chehab 16340c0d06caSMauro Carvalho Chehab if (mode == V4L2_TUNER_RADIO) { 16350c0d06caSMauro Carvalho Chehab /* C2HH */ 16360c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16370c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16380c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16390c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16400c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16410c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16420c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16430c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 16440c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16450c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16460c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16470c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 16480c0d06caSMauro Carvalho Chehab /* no inv */ 16490c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16500c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16510c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16520c0d06caSMauro Carvalho Chehab } else if (standard != DIF_USE_BASEBAND) { 16530c0d06caSMauro Carvalho Chehab if (standard & V4L2_STD_MN) { 16540c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16550c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16560c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16570c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16580c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16590c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16600c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16610c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 16620c0d06caSMauro Carvalho Chehab function_mode); 16630c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16640c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16650c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16660c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 16670c0d06caSMauro Carvalho Chehab /* no inv */ 16680c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16690c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16700c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16710c0d06caSMauro Carvalho Chehab /* 0x124, AUD_CHAN1_SRC = 0x3 */ 16720c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16730c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16740c0d06caSMauro Carvalho Chehab AUD_IO_CTRL, 0, 31, 0x00000003); 16750c0d06caSMauro Carvalho Chehab } else if ((standard == V4L2_STD_PAL_I) | 16760c0d06caSMauro Carvalho Chehab (standard & V4L2_STD_PAL_D) | 16770c0d06caSMauro Carvalho Chehab (standard & V4L2_STD_SECAM)) { 16780c0d06caSMauro Carvalho Chehab /* C2HH setup */ 16790c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16800c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16810c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16820c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16830c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16840c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16850c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16860c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 16870c0d06caSMauro Carvalho Chehab function_mode); 16880c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16890c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16900c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16910c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 16920c0d06caSMauro Carvalho Chehab /* no inv */ 16930c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16940c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16950c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16960c0d06caSMauro Carvalho Chehab } else { 16970c0d06caSMauro Carvalho Chehab /* default PAL BG */ 16980c0d06caSMauro Carvalho Chehab /* C2HH setup */ 16990c0d06caSMauro Carvalho Chehab /* lo if big signal */ 17000c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 17010c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 17020c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 17030c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 17040c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 17050c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 17060c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 17070c0d06caSMauro Carvalho Chehab function_mode); 17080c0d06caSMauro Carvalho Chehab /* IF_MODE */ 17090c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 17100c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 17110c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 17120c0d06caSMauro Carvalho Chehab /* no inv */ 17130c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 17140c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 17150c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 17160c0d06caSMauro Carvalho Chehab } 17170c0d06caSMauro Carvalho Chehab } 17180c0d06caSMauro Carvalho Chehab 17190c0d06caSMauro Carvalho Chehab return status; 17200c0d06caSMauro Carvalho Chehab } 17210c0d06caSMauro Carvalho Chehab 17220c0d06caSMauro Carvalho Chehab int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 17230c0d06caSMauro Carvalho Chehab { 17240c0d06caSMauro Carvalho Chehab int status = 0; 17250c0d06caSMauro Carvalho Chehab u32 dif_misc_ctrl_value = 0; 17260c0d06caSMauro Carvalho Chehab u32 func_mode = 0; 17270c0d06caSMauro Carvalho Chehab 1728336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard); 17290c0d06caSMauro Carvalho Chehab 17300c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 17310c0d06caSMauro Carvalho Chehab if (standard != DIF_USE_BASEBAND) 17320c0d06caSMauro Carvalho Chehab dev->norm = standard; 17330c0d06caSMauro Carvalho Chehab 17340c0d06caSMauro Carvalho Chehab switch (dev->model) { 17350c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_CARRAERA: 17360c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_250: 17370c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_SHELBY: 17380c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_250: 17390c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 17400c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_EXETER: 17413ead1ba3SMatt Gomboc case CX231XX_BOARD_OTG102: 17420c0d06caSMauro Carvalho Chehab func_mode = 0x03; 17430c0d06caSMauro Carvalho Chehab break; 17440c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_253S: 17450c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_253S: 17460c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 17470c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 17480c0d06caSMauro Carvalho Chehab func_mode = 0x01; 17490c0d06caSMauro Carvalho Chehab break; 17500c0d06caSMauro Carvalho Chehab default: 17510c0d06caSMauro Carvalho Chehab func_mode = 0x01; 17520c0d06caSMauro Carvalho Chehab } 17530c0d06caSMauro Carvalho Chehab 17540c0d06caSMauro Carvalho Chehab status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 17550c0d06caSMauro Carvalho Chehab func_mode, standard); 17560c0d06caSMauro Carvalho Chehab 17570c0d06caSMauro Carvalho Chehab if (standard == DIF_USE_BASEBAND) { /* base band */ 17580c0d06caSMauro Carvalho Chehab /* There is a different SRC_PHASE_INC value 17590c0d06caSMauro Carvalho Chehab for baseband vs. DIF */ 17600c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 17610c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, 17620c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value); 17630c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 17640c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, 17650c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value); 17660c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_D) { 17670c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17680c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 17690c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17700c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 17710c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17720c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 17730c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17740c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 17750c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17760c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380); 17770c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17780c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 17790c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17800c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 17810c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17820c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 17830c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17840c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 17850c0d06caSMauro Carvalho Chehab 0x26001700); 17860c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17870c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 17880c0d06caSMauro Carvalho Chehab 0x00002660); 17890c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17900c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 17910c0d06caSMauro Carvalho Chehab 0x72500800); 17920c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17930c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 17940c0d06caSMauro Carvalho Chehab 0x27000100); 17950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17960c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 17970c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17980c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 17990c0d06caSMauro Carvalho Chehab 0x00000000); 18000c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18010c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 18020c0d06caSMauro Carvalho Chehab 0x1befbf06); 18030c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18040c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 18050c0d06caSMauro Carvalho Chehab 0x000035e8); 18060c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18070c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 18080c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 18090c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 18100c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11; 18110c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_I) { 18120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18130c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 18140c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18150c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 18160c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18170c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 18180c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18190c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 18200c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18210c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380); 18220c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18230c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 18240c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18250c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 18260c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18270c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 18280c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18290c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 18300c0d06caSMauro Carvalho Chehab 0x26001700); 18310c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18320c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 18330c0d06caSMauro Carvalho Chehab 0x00002660); 18340c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18350c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 18360c0d06caSMauro Carvalho Chehab 0x72500800); 18370c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18380c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 18390c0d06caSMauro Carvalho Chehab 0x27000100); 18400c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18410c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 18420c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18430c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 18440c0d06caSMauro Carvalho Chehab 0x00000000); 18450c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18460c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 18470c0d06caSMauro Carvalho Chehab 0x1befbf06); 18480c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18490c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 18500c0d06caSMauro Carvalho Chehab 0x000035e8); 18510c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18520c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 18530c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 18540c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 18550c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a033F11; 18560c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_M) { 18570c0d06caSMauro Carvalho Chehab /* improved Low Frequency Phase Noise */ 18580c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 18590c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 18600c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 18610c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 18620c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 18630c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 18640c0d06caSMauro Carvalho Chehab 0x26001700); 18650c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 18660c0d06caSMauro Carvalho Chehab 0x00002660); 18670c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 18680c0d06caSMauro Carvalho Chehab 0x72500800); 18690c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 18700c0d06caSMauro Carvalho Chehab 0x27000100); 18710c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 18720c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 18730c0d06caSMauro Carvalho Chehab 0x009f50c1); 18740c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 18750c0d06caSMauro Carvalho Chehab 0x1befbf06); 18760c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 18770c0d06caSMauro Carvalho Chehab 0x000035e8); 18780c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 18790c0d06caSMauro Carvalho Chehab 0x00000000); 18800c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 18810c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 18820c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3A0A3F10; 18830c0d06caSMauro Carvalho Chehab } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 18840c0d06caSMauro Carvalho Chehab /* improved Low Frequency Phase Noise */ 18850c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 18860c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 18870c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 18880c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 18890c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 18900c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 18910c0d06caSMauro Carvalho Chehab 0x26001700); 18920c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 18930c0d06caSMauro Carvalho Chehab 0x00002660); 18940c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 18950c0d06caSMauro Carvalho Chehab 0x72500800); 18960c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 18970c0d06caSMauro Carvalho Chehab 0x27000100); 18980c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 18990c0d06caSMauro Carvalho Chehab 0x012c405d); 19000c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 19010c0d06caSMauro Carvalho Chehab 0x009f50c1); 19020c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 19030c0d06caSMauro Carvalho Chehab 0x1befbf06); 19040c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 19050c0d06caSMauro Carvalho Chehab 0x000035e8); 19060c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 19070c0d06caSMauro Carvalho Chehab 0x00000000); 19080c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 19090c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 19100c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = 0x3A093F10; 19110c0d06caSMauro Carvalho Chehab } else if (standard & 19120c0d06caSMauro Carvalho Chehab (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 19130c0d06caSMauro Carvalho Chehab V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 19140c0d06caSMauro Carvalho Chehab 19150c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19160c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 19170c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19180c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 19190c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19200c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 19210c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19220c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 19230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19240c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x888C0380); 19250c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19260c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 19270c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19280c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 19290c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19300c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 19310c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19320c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 19330c0d06caSMauro Carvalho Chehab 0x26001700); 19340c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19350c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 19360c0d06caSMauro Carvalho Chehab 0x00002660); 19370c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19380c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 19390c0d06caSMauro Carvalho Chehab 0x27000100); 19400c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19410c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 19420c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19430c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 19440c0d06caSMauro Carvalho Chehab 0x00000000); 19450c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19460c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 19470c0d06caSMauro Carvalho Chehab 0x1befbf06); 19480c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19490c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 19500c0d06caSMauro Carvalho Chehab 0x000035e8); 19510c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19520c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 19530c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19540c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 19550c0d06caSMauro Carvalho Chehab 0xf4000000); 19560c0d06caSMauro Carvalho Chehab 19570c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 19580c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 19590c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11; 19600c0d06caSMauro Carvalho Chehab } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 19610c0d06caSMauro Carvalho Chehab /* Is it SECAM_L1? */ 19620c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19630c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 19640c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19650c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 19660c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19670c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 19680c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19690c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 19700c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19710c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x888C0380); 19720c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19730c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 19740c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19750c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 19760c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19770c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 19780c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19790c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 19800c0d06caSMauro Carvalho Chehab 0x26001700); 19810c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19820c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 19830c0d06caSMauro Carvalho Chehab 0x00002660); 19840c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19850c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 19860c0d06caSMauro Carvalho Chehab 0x27000100); 19870c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19880c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 19890c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19900c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 19910c0d06caSMauro Carvalho Chehab 0x00000000); 19920c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19930c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 19940c0d06caSMauro Carvalho Chehab 0x1befbf06); 19950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19960c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 19970c0d06caSMauro Carvalho Chehab 0x000035e8); 19980c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19990c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 20000c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20010c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 20020c0d06caSMauro Carvalho Chehab 0xf2560000); 20030c0d06caSMauro Carvalho Chehab 20040c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 20050c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 20060c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11; 20070c0d06caSMauro Carvalho Chehab 20080c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_NTSC_M) { 20090c0d06caSMauro Carvalho Chehab /* V4L2_STD_NTSC_M (75 IRE Setup) Or 20100c0d06caSMauro Carvalho Chehab V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 20110c0d06caSMauro Carvalho Chehab 20120c0d06caSMauro Carvalho Chehab /* For NTSC the centre frequency of video coming out of 20130c0d06caSMauro Carvalho Chehab sidewinder is around 7.1MHz or 3.6MHz depending on the 20140c0d06caSMauro Carvalho Chehab spectral inversion. so for a non spectrally inverted channel 20150c0d06caSMauro Carvalho Chehab the pll freq word is 0x03420c49 20160c0d06caSMauro Carvalho Chehab */ 20170c0d06caSMauro Carvalho Chehab 20180c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 20190c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 20200c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 20210c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 20220c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 20230c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 20240c0d06caSMauro Carvalho Chehab 0x26001700); 20250c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 20260c0d06caSMauro Carvalho Chehab 0x00002660); 20270c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 20280c0d06caSMauro Carvalho Chehab 0x04000800); 20290c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 20300c0d06caSMauro Carvalho Chehab 0x27000100); 20310c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 20320c0d06caSMauro Carvalho Chehab 20330c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 20340c0d06caSMauro Carvalho Chehab 0x009f50c1); 20350c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 20360c0d06caSMauro Carvalho Chehab 0x1befbf06); 20370c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 20380c0d06caSMauro Carvalho Chehab 0x000035e8); 20390c0d06caSMauro Carvalho Chehab 20400c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 20410c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 20420c0d06caSMauro Carvalho Chehab 0xC2262600); 20430c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 20440c0d06caSMauro Carvalho Chehab 20450c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 20460c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 20470c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a003F10; 20480c0d06caSMauro Carvalho Chehab } else { 20490c0d06caSMauro Carvalho Chehab /* default PAL BG */ 20500c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20510c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 20520c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20530c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 20540c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20550c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 20560c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20570c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 20580c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20590c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380); 20600c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20610c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 20620c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20630c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 20640c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20650c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 20660c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20670c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 20680c0d06caSMauro Carvalho Chehab 0x26001700); 20690c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20700c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 20710c0d06caSMauro Carvalho Chehab 0x00002660); 20720c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20730c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 20740c0d06caSMauro Carvalho Chehab 0x72500800); 20750c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20760c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 20770c0d06caSMauro Carvalho Chehab 0x27000100); 20780c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20790c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 20800c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20810c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 20820c0d06caSMauro Carvalho Chehab 0x00A653A8); 20830c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20840c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 20850c0d06caSMauro Carvalho Chehab 0x1befbf06); 20860c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20870c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 20880c0d06caSMauro Carvalho Chehab 0x000035e8); 20890c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20900c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 20910c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 20920c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 20930c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a013F11; 20940c0d06caSMauro Carvalho Chehab } 20950c0d06caSMauro Carvalho Chehab 20960c0d06caSMauro Carvalho Chehab /* The AGC values should be the same for all standards, 20970c0d06caSMauro Carvalho Chehab AUD_SRC_SEL[19] should always be disabled */ 20980c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 20990c0d06caSMauro Carvalho Chehab 21000c0d06caSMauro Carvalho Chehab /* It is still possible to get Set Standard calls even when we 21010c0d06caSMauro Carvalho Chehab are in FM mode. 21020c0d06caSMauro Carvalho Chehab This is done to override the value for FM. */ 21030c0d06caSMauro Carvalho Chehab if (dev->active_mode == V4L2_TUNER_RADIO) 21040c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = 0x7a080000; 21050c0d06caSMauro Carvalho Chehab 21060c0d06caSMauro Carvalho Chehab /* Write the calculated value for misc ontrol register */ 21070c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 21080c0d06caSMauro Carvalho Chehab 21090c0d06caSMauro Carvalho Chehab return status; 21100c0d06caSMauro Carvalho Chehab } 21110c0d06caSMauro Carvalho Chehab 21120c0d06caSMauro Carvalho Chehab int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 21130c0d06caSMauro Carvalho Chehab { 21140c0d06caSMauro Carvalho Chehab int status = 0; 21150c0d06caSMauro Carvalho Chehab u32 dwval; 21160c0d06caSMauro Carvalho Chehab 21170c0d06caSMauro Carvalho Chehab /* Set the RF and IF k_agc values to 3 */ 21180c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 21190c0d06caSMauro Carvalho Chehab dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 21200c0d06caSMauro Carvalho Chehab dwval |= 0x33000000; 21210c0d06caSMauro Carvalho Chehab 21220c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 21230c0d06caSMauro Carvalho Chehab 21240c0d06caSMauro Carvalho Chehab return status; 21250c0d06caSMauro Carvalho Chehab } 21260c0d06caSMauro Carvalho Chehab 21270c0d06caSMauro Carvalho Chehab int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 21280c0d06caSMauro Carvalho Chehab { 21290c0d06caSMauro Carvalho Chehab int status = 0; 21300c0d06caSMauro Carvalho Chehab u32 dwval; 2131336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n", 2132ed0e3729SMauro Carvalho Chehab __func__, dev->tuner_type); 21330c0d06caSMauro Carvalho Chehab /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 21340c0d06caSMauro Carvalho Chehab * SECAM L/B/D standards */ 21350c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 21360c0d06caSMauro Carvalho Chehab dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 21370c0d06caSMauro Carvalho Chehab 21380c0d06caSMauro Carvalho Chehab if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 21390c0d06caSMauro Carvalho Chehab V4L2_STD_SECAM_D)) { 21400c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) { 21410c0d06caSMauro Carvalho Chehab dwval &= ~FLD_DIF_IF_REF; 21420c0d06caSMauro Carvalho Chehab dwval |= 0x88000300; 21430c0d06caSMauro Carvalho Chehab } else 21440c0d06caSMauro Carvalho Chehab dwval |= 0x88000000; 21450c0d06caSMauro Carvalho Chehab } else { 21460c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) { 21470c0d06caSMauro Carvalho Chehab dwval &= ~FLD_DIF_IF_REF; 21480c0d06caSMauro Carvalho Chehab dwval |= 0xCC000300; 21490c0d06caSMauro Carvalho Chehab } else 21500c0d06caSMauro Carvalho Chehab dwval |= 0x44000000; 21510c0d06caSMauro Carvalho Chehab } 21520c0d06caSMauro Carvalho Chehab 21530c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 21540c0d06caSMauro Carvalho Chehab 2155b251f957SHans Verkuil return status == sizeof(dwval) ? 0 : -EIO; 21560c0d06caSMauro Carvalho Chehab } 21570c0d06caSMauro Carvalho Chehab 21580c0d06caSMauro Carvalho Chehab /****************************************************************************** 21590c0d06caSMauro Carvalho Chehab * I 2 S - B L O C K C O N T R O L functions * 21600c0d06caSMauro Carvalho Chehab ******************************************************************************/ 21610c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 21620c0d06caSMauro Carvalho Chehab { 21630c0d06caSMauro Carvalho Chehab int status = 0; 21640c0d06caSMauro Carvalho Chehab u32 value; 21650c0d06caSMauro Carvalho Chehab 21660c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21670c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, &value, 1); 21680c0d06caSMauro Carvalho Chehab /* enables clock to delta-sigma and decimation filter */ 21690c0d06caSMauro Carvalho Chehab value |= 0x80; 21700c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21710c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, value, 1); 21720c0d06caSMauro Carvalho Chehab /* power up all channel */ 21730c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21740c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1); 21750c0d06caSMauro Carvalho Chehab 21760c0d06caSMauro Carvalho Chehab return status; 21770c0d06caSMauro Carvalho Chehab } 21780c0d06caSMauro Carvalho Chehab 21790c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 21800c0d06caSMauro Carvalho Chehab enum AV_MODE avmode) 21810c0d06caSMauro Carvalho Chehab { 21820c0d06caSMauro Carvalho Chehab int status = 0; 21830c0d06caSMauro Carvalho Chehab u32 value = 0; 21840c0d06caSMauro Carvalho Chehab 21850c0d06caSMauro Carvalho Chehab if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 21860c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21870c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, &value, 1); 21880c0d06caSMauro Carvalho Chehab value |= 0xfe; 21890c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21900c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, value, 1); 21910c0d06caSMauro Carvalho Chehab } else { 21920c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21930c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1); 21940c0d06caSMauro Carvalho Chehab } 21950c0d06caSMauro Carvalho Chehab 21960c0d06caSMauro Carvalho Chehab return status; 21970c0d06caSMauro Carvalho Chehab } 21980c0d06caSMauro Carvalho Chehab 21990c0d06caSMauro Carvalho Chehab /* set i2s_blk for audio input types */ 22000c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 22010c0d06caSMauro Carvalho Chehab { 22020c0d06caSMauro Carvalho Chehab int status = 0; 22030c0d06caSMauro Carvalho Chehab 22040c0d06caSMauro Carvalho Chehab switch (audio_input) { 22050c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_LINE_IN: 22060c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 22070c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1); 22080c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 22090c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, 0x80, 1); 22100c0d06caSMauro Carvalho Chehab break; 22110c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_VIDEO: 22120c0d06caSMauro Carvalho Chehab default: 22130c0d06caSMauro Carvalho Chehab break; 22140c0d06caSMauro Carvalho Chehab } 22150c0d06caSMauro Carvalho Chehab 22160c0d06caSMauro Carvalho Chehab dev->ctl_ainput = audio_input; 22170c0d06caSMauro Carvalho Chehab 22180c0d06caSMauro Carvalho Chehab return status; 22190c0d06caSMauro Carvalho Chehab } 22200c0d06caSMauro Carvalho Chehab 22210c0d06caSMauro Carvalho Chehab /****************************************************************************** 22220c0d06caSMauro Carvalho Chehab * P O W E R C O N T R O L functions * 22230c0d06caSMauro Carvalho Chehab ******************************************************************************/ 22240c0d06caSMauro Carvalho Chehab int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 22250c0d06caSMauro Carvalho Chehab { 22260c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 22270c0d06caSMauro Carvalho Chehab u32 tmp = 0; 22280c0d06caSMauro Carvalho Chehab int status = 0; 22290c0d06caSMauro Carvalho Chehab 22300c0d06caSMauro Carvalho Chehab if (dev->power_mode != mode) 22310c0d06caSMauro Carvalho Chehab dev->power_mode = mode; 22320c0d06caSMauro Carvalho Chehab else { 2233336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n", 2234ed0e3729SMauro Carvalho Chehab __func__, mode); 22350c0d06caSMauro Carvalho Chehab return 0; 22360c0d06caSMauro Carvalho Chehab } 22370c0d06caSMauro Carvalho Chehab 22380c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 22390c0d06caSMauro Carvalho Chehab 4); 22400c0d06caSMauro Carvalho Chehab if (status < 0) 22410c0d06caSMauro Carvalho Chehab return status; 22420c0d06caSMauro Carvalho Chehab 22433f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value)); 22440c0d06caSMauro Carvalho Chehab 22450c0d06caSMauro Carvalho Chehab switch (mode) { 22460c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_ENXTERNAL_AV: 22470c0d06caSMauro Carvalho Chehab 22480c0d06caSMauro Carvalho Chehab tmp &= (~PWR_MODE_MASK); 22490c0d06caSMauro Carvalho Chehab 22500c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN; 22510c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22520c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22530c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22540c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22550c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22560c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22570c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22580c0d06caSMauro Carvalho Chehab 22590c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN; 22600c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22610c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22620c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22630c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22640c0d06caSMauro Carvalho Chehab status = 22650c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 22660c0d06caSMauro Carvalho Chehab value, 4); 22670c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22680c0d06caSMauro Carvalho Chehab 22690c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 22700c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22710c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22720c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22730c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22740c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22750c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22760c0d06caSMauro Carvalho Chehab 22770c0d06caSMauro Carvalho Chehab /* reset state of xceive tuner */ 22780c0d06caSMauro Carvalho Chehab dev->xc_fw_load_done = 0; 22790c0d06caSMauro Carvalho Chehab break; 22800c0d06caSMauro Carvalho Chehab 22810c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_ANALOGT_TV: 22820c0d06caSMauro Carvalho Chehab 22830c0d06caSMauro Carvalho Chehab tmp |= PWR_DEMOD_EN; 22840c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22850c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22860c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22870c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22880c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22890c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22900c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22910c0d06caSMauro Carvalho Chehab 22920c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_TUNER_EN)) { 22930c0d06caSMauro Carvalho Chehab tmp |= (PWR_TUNER_EN); 22940c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22950c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22960c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22970c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22980c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22990c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23000c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23010c0d06caSMauro Carvalho Chehab } 23020c0d06caSMauro Carvalho Chehab 23030c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_AV_EN)) { 23040c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN; 23050c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23060c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23070c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23080c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23090c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23100c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23110c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23120c0d06caSMauro Carvalho Chehab } 23130c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_ISO_EN)) { 23140c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN; 23150c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23160c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23170c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23180c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23190c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23200c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23210c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23220c0d06caSMauro Carvalho Chehab } 23230c0d06caSMauro Carvalho Chehab 23240c0d06caSMauro Carvalho Chehab if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 23250c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_ANALOGT_TV; 23260c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23270c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23280c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23290c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23300c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23310c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23320c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23330c0d06caSMauro Carvalho Chehab } 23340c0d06caSMauro Carvalho Chehab 23350c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type != TUNER_ABSENT) { 23360c0d06caSMauro Carvalho Chehab /* reset the Tuner */ 23370c0d06caSMauro Carvalho Chehab if (dev->board.tuner_gpio) 23380c0d06caSMauro Carvalho Chehab cx231xx_gpio_set(dev, dev->board.tuner_gpio); 23390c0d06caSMauro Carvalho Chehab 23400c0d06caSMauro Carvalho Chehab if (dev->cx231xx_reset_analog_tuner) 23410c0d06caSMauro Carvalho Chehab dev->cx231xx_reset_analog_tuner(dev); 23420c0d06caSMauro Carvalho Chehab } 23430c0d06caSMauro Carvalho Chehab 23440c0d06caSMauro Carvalho Chehab break; 23450c0d06caSMauro Carvalho Chehab 23460c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_DIGITAL: 23470c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_TUNER_EN)) { 23480c0d06caSMauro Carvalho Chehab tmp |= (PWR_TUNER_EN); 23490c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23500c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23510c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23520c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23530c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23540c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23550c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23560c0d06caSMauro Carvalho Chehab } 23570c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_AV_EN)) { 23580c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN; 23590c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23600c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23610c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23620c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23630c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23640c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23650c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23660c0d06caSMauro Carvalho Chehab } 23670c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_ISO_EN)) { 23680c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN; 23690c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23700c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23710c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23720c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23730c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23740c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23750c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23760c0d06caSMauro Carvalho Chehab } 23770c0d06caSMauro Carvalho Chehab 23780c0d06caSMauro Carvalho Chehab tmp &= (~PWR_AV_MODE); 2379082417d1SMatthias Schwarzott tmp |= POLARIS_AVMODE_DIGITAL; 23800c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23810c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23820c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23830c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23840c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23850c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23860c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23870c0d06caSMauro Carvalho Chehab 23880c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_DEMOD_EN)) { 23890c0d06caSMauro Carvalho Chehab tmp |= PWR_DEMOD_EN; 23900c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23910c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23920c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23930c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23940c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23950c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23960c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23970c0d06caSMauro Carvalho Chehab } 23980c0d06caSMauro Carvalho Chehab 23990c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type != TUNER_ABSENT) { 24000c0d06caSMauro Carvalho Chehab /* reset the Tuner */ 24010c0d06caSMauro Carvalho Chehab if (dev->board.tuner_gpio) 24020c0d06caSMauro Carvalho Chehab cx231xx_gpio_set(dev, dev->board.tuner_gpio); 24030c0d06caSMauro Carvalho Chehab 24040c0d06caSMauro Carvalho Chehab if (dev->cx231xx_reset_analog_tuner) 24050c0d06caSMauro Carvalho Chehab dev->cx231xx_reset_analog_tuner(dev); 24060c0d06caSMauro Carvalho Chehab } 24070c0d06caSMauro Carvalho Chehab break; 24080c0d06caSMauro Carvalho Chehab 24090c0d06caSMauro Carvalho Chehab default: 24100c0d06caSMauro Carvalho Chehab break; 24110c0d06caSMauro Carvalho Chehab } 24120c0d06caSMauro Carvalho Chehab 24130c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 24140c0d06caSMauro Carvalho Chehab 24150c0d06caSMauro Carvalho Chehab /* For power saving, only enable Pwr_resetout_n 24160c0d06caSMauro Carvalho Chehab when digital TV is selected. */ 24170c0d06caSMauro Carvalho Chehab if (mode == POLARIS_AVMODE_DIGITAL) { 24180c0d06caSMauro Carvalho Chehab tmp |= PWR_RESETOUT_EN; 24190c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 24200c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 24210c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 24220c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 24230c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 24240c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 24250c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 24260c0d06caSMauro Carvalho Chehab } 24270c0d06caSMauro Carvalho Chehab 24280c0d06caSMauro Carvalho Chehab /* update power control for afe */ 24290c0d06caSMauro Carvalho Chehab status = cx231xx_afe_update_power_control(dev, mode); 24300c0d06caSMauro Carvalho Chehab 24310c0d06caSMauro Carvalho Chehab /* update power control for i2s_blk */ 24320c0d06caSMauro Carvalho Chehab status = cx231xx_i2s_blk_update_power_control(dev, mode); 24330c0d06caSMauro Carvalho Chehab 24340c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 24350c0d06caSMauro Carvalho Chehab 4); 24360c0d06caSMauro Carvalho Chehab 24370c0d06caSMauro Carvalho Chehab return status; 24380c0d06caSMauro Carvalho Chehab } 24390c0d06caSMauro Carvalho Chehab 24400c0d06caSMauro Carvalho Chehab int cx231xx_power_suspend(struct cx231xx *dev) 24410c0d06caSMauro Carvalho Chehab { 24420c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 24430c0d06caSMauro Carvalho Chehab u32 tmp = 0; 24440c0d06caSMauro Carvalho Chehab int status = 0; 24450c0d06caSMauro Carvalho Chehab 24460c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 24470c0d06caSMauro Carvalho Chehab value, 4); 24480c0d06caSMauro Carvalho Chehab if (status > 0) 24490c0d06caSMauro Carvalho Chehab return status; 24500c0d06caSMauro Carvalho Chehab 24513f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value)); 24520c0d06caSMauro Carvalho Chehab tmp &= (~PWR_MODE_MASK); 24530c0d06caSMauro Carvalho Chehab 24540c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 24550c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 24560c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 24570c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 24580c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 24590c0d06caSMauro Carvalho Chehab value, 4); 24600c0d06caSMauro Carvalho Chehab 24610c0d06caSMauro Carvalho Chehab return status; 24620c0d06caSMauro Carvalho Chehab } 24630c0d06caSMauro Carvalho Chehab 24640c0d06caSMauro Carvalho Chehab /****************************************************************************** 24650c0d06caSMauro Carvalho Chehab * S T R E A M C O N T R O L functions * 24660c0d06caSMauro Carvalho Chehab ******************************************************************************/ 24670c0d06caSMauro Carvalho Chehab int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 24680c0d06caSMauro Carvalho Chehab { 24690c0d06caSMauro Carvalho Chehab u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 24700c0d06caSMauro Carvalho Chehab u32 tmp = 0; 24710c0d06caSMauro Carvalho Chehab int status = 0; 24720c0d06caSMauro Carvalho Chehab 2473336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 24740c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 24750c0d06caSMauro Carvalho Chehab value, 4); 24760c0d06caSMauro Carvalho Chehab if (status < 0) 24770c0d06caSMauro Carvalho Chehab return status; 24780c0d06caSMauro Carvalho Chehab 24793f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value)); 24800c0d06caSMauro Carvalho Chehab tmp |= ep_mask; 24810c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 24820c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 24830c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 24840c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 24850c0d06caSMauro Carvalho Chehab 24860c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 24870c0d06caSMauro Carvalho Chehab value, 4); 24880c0d06caSMauro Carvalho Chehab 24890c0d06caSMauro Carvalho Chehab return status; 24900c0d06caSMauro Carvalho Chehab } 24910c0d06caSMauro Carvalho Chehab 24920c0d06caSMauro Carvalho Chehab int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 24930c0d06caSMauro Carvalho Chehab { 24940c0d06caSMauro Carvalho Chehab u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 24950c0d06caSMauro Carvalho Chehab u32 tmp = 0; 24960c0d06caSMauro Carvalho Chehab int status = 0; 24970c0d06caSMauro Carvalho Chehab 2498336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask); 24990c0d06caSMauro Carvalho Chehab status = 25000c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 25010c0d06caSMauro Carvalho Chehab if (status < 0) 25020c0d06caSMauro Carvalho Chehab return status; 25030c0d06caSMauro Carvalho Chehab 25043f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value)); 25050c0d06caSMauro Carvalho Chehab tmp &= (~ep_mask); 25060c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 25070c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 25080c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 25090c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 25100c0d06caSMauro Carvalho Chehab 25110c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 25120c0d06caSMauro Carvalho Chehab value, 4); 25130c0d06caSMauro Carvalho Chehab 25140c0d06caSMauro Carvalho Chehab return status; 25150c0d06caSMauro Carvalho Chehab } 25160c0d06caSMauro Carvalho Chehab 25170c0d06caSMauro Carvalho Chehab int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 25180c0d06caSMauro Carvalho Chehab { 25190c0d06caSMauro Carvalho Chehab int status = 0; 25200c0d06caSMauro Carvalho Chehab u32 value = 0; 25210c0d06caSMauro Carvalho Chehab u8 val[4] = { 0, 0, 0, 0 }; 25220c0d06caSMauro Carvalho Chehab 25230c0d06caSMauro Carvalho Chehab if (dev->udev->speed == USB_SPEED_HIGH) { 25240c0d06caSMauro Carvalho Chehab switch (media_type) { 25250c0d06caSMauro Carvalho Chehab case Audio: 2526336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2527b7085c08SMauro Carvalho Chehab "%s: Audio enter HANC\n", __func__); 25280c0d06caSMauro Carvalho Chehab status = 25290c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 25300c0d06caSMauro Carvalho Chehab break; 25310c0d06caSMauro Carvalho Chehab 25320c0d06caSMauro Carvalho Chehab case Vbi: 2533336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2534b7085c08SMauro Carvalho Chehab "%s: set vanc registers\n", __func__); 25350c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 25360c0d06caSMauro Carvalho Chehab break; 25370c0d06caSMauro Carvalho Chehab 25380c0d06caSMauro Carvalho Chehab case Sliced_cc: 2539336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2540b7085c08SMauro Carvalho Chehab "%s: set hanc registers\n", __func__); 25410c0d06caSMauro Carvalho Chehab status = 25420c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 25430c0d06caSMauro Carvalho Chehab break; 25440c0d06caSMauro Carvalho Chehab 25450c0d06caSMauro Carvalho Chehab case Raw_Video: 2546336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2547b7085c08SMauro Carvalho Chehab "%s: set video registers\n", __func__); 25480c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 25490c0d06caSMauro Carvalho Chehab break; 25500c0d06caSMauro Carvalho Chehab 25510c0d06caSMauro Carvalho Chehab case TS1_serial_mode: 2552336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2553b7085c08SMauro Carvalho Chehab "%s: set ts1 registers", __func__); 25540c0d06caSMauro Carvalho Chehab 25550c0d06caSMauro Carvalho Chehab if (dev->board.has_417) { 2556336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2557b7085c08SMauro Carvalho Chehab "%s: MPEG\n", __func__); 25580c0d06caSMauro Carvalho Chehab value &= 0xFFFFFFFC; 25590c0d06caSMauro Carvalho Chehab value |= 0x3; 25600c0d06caSMauro Carvalho Chehab 256188538bb5SMauro Carvalho Chehab status = cx231xx_mode_register(dev, 256288538bb5SMauro Carvalho Chehab TS_MODE_REG, value); 25630c0d06caSMauro Carvalho Chehab 25640c0d06caSMauro Carvalho Chehab val[0] = 0x04; 25650c0d06caSMauro Carvalho Chehab val[1] = 0xA3; 25660c0d06caSMauro Carvalho Chehab val[2] = 0x3B; 25670c0d06caSMauro Carvalho Chehab val[3] = 0x00; 256888538bb5SMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, 256988538bb5SMauro Carvalho Chehab VRT_SET_REGISTER, 25700c0d06caSMauro Carvalho Chehab TS1_CFG_REG, val, 4); 25710c0d06caSMauro Carvalho Chehab 25720c0d06caSMauro Carvalho Chehab val[0] = 0x00; 25730c0d06caSMauro Carvalho Chehab val[1] = 0x08; 25740c0d06caSMauro Carvalho Chehab val[2] = 0x00; 25750c0d06caSMauro Carvalho Chehab val[3] = 0x08; 257688538bb5SMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, 257788538bb5SMauro Carvalho Chehab VRT_SET_REGISTER, 25780c0d06caSMauro Carvalho Chehab TS1_LENGTH_REG, val, 4); 25790c0d06caSMauro Carvalho Chehab } else { 2580336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: BDA\n", __func__); 258188538bb5SMauro Carvalho Chehab status = cx231xx_mode_register(dev, 258288538bb5SMauro Carvalho Chehab TS_MODE_REG, 0x101); 258388538bb5SMauro Carvalho Chehab status = cx231xx_mode_register(dev, 258488538bb5SMauro Carvalho Chehab TS1_CFG_REG, 0x010); 25850c0d06caSMauro Carvalho Chehab } 25860c0d06caSMauro Carvalho Chehab break; 25870c0d06caSMauro Carvalho Chehab 25880c0d06caSMauro Carvalho Chehab case TS1_parallel_mode: 2589336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2590b7085c08SMauro Carvalho Chehab "%s: set ts1 parallel mode registers\n", 25910c0d06caSMauro Carvalho Chehab __func__); 25920c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 25930c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 25940c0d06caSMauro Carvalho Chehab break; 25950c0d06caSMauro Carvalho Chehab } 25960c0d06caSMauro Carvalho Chehab } else { 25970c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 25980c0d06caSMauro Carvalho Chehab } 25990c0d06caSMauro Carvalho Chehab 26000c0d06caSMauro Carvalho Chehab return status; 26010c0d06caSMauro Carvalho Chehab } 26020c0d06caSMauro Carvalho Chehab 26030c0d06caSMauro Carvalho Chehab int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 26040c0d06caSMauro Carvalho Chehab { 26050c0d06caSMauro Carvalho Chehab int rc = -1; 26060c0d06caSMauro Carvalho Chehab u32 ep_mask = -1; 26070c0d06caSMauro Carvalho Chehab struct pcb_config *pcb_config; 26080c0d06caSMauro Carvalho Chehab 26090c0d06caSMauro Carvalho Chehab /* get EP for media type */ 26100c0d06caSMauro Carvalho Chehab pcb_config = (struct pcb_config *)&dev->current_pcb_config; 26110c0d06caSMauro Carvalho Chehab 26120c0d06caSMauro Carvalho Chehab if (pcb_config->config_num) { 26130c0d06caSMauro Carvalho Chehab switch (media_type) { 26140c0d06caSMauro Carvalho Chehab case Raw_Video: 26150c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 26160c0d06caSMauro Carvalho Chehab break; 26170c0d06caSMauro Carvalho Chehab case Audio: 26180c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 26190c0d06caSMauro Carvalho Chehab break; 26200c0d06caSMauro Carvalho Chehab case Vbi: 26210c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 26220c0d06caSMauro Carvalho Chehab break; 26230c0d06caSMauro Carvalho Chehab case Sliced_cc: 26240c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 26250c0d06caSMauro Carvalho Chehab break; 26260c0d06caSMauro Carvalho Chehab case TS1_serial_mode: 26270c0d06caSMauro Carvalho Chehab case TS1_parallel_mode: 26280c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 26290c0d06caSMauro Carvalho Chehab break; 26300c0d06caSMauro Carvalho Chehab case TS2: 26310c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 26320c0d06caSMauro Carvalho Chehab break; 26330c0d06caSMauro Carvalho Chehab } 26340c0d06caSMauro Carvalho Chehab } 26350c0d06caSMauro Carvalho Chehab 26360c0d06caSMauro Carvalho Chehab if (start) { 26370c0d06caSMauro Carvalho Chehab rc = cx231xx_initialize_stream_xfer(dev, media_type); 26380c0d06caSMauro Carvalho Chehab 26390c0d06caSMauro Carvalho Chehab if (rc < 0) 26400c0d06caSMauro Carvalho Chehab return rc; 26410c0d06caSMauro Carvalho Chehab 26420c0d06caSMauro Carvalho Chehab /* enable video capture */ 26430c0d06caSMauro Carvalho Chehab if (ep_mask > 0) 26440c0d06caSMauro Carvalho Chehab rc = cx231xx_start_stream(dev, ep_mask); 26450c0d06caSMauro Carvalho Chehab } else { 26460c0d06caSMauro Carvalho Chehab /* disable video capture */ 26470c0d06caSMauro Carvalho Chehab if (ep_mask > 0) 26480c0d06caSMauro Carvalho Chehab rc = cx231xx_stop_stream(dev, ep_mask); 26490c0d06caSMauro Carvalho Chehab } 26500c0d06caSMauro Carvalho Chehab 26510c0d06caSMauro Carvalho Chehab return rc; 26520c0d06caSMauro Carvalho Chehab } 26530c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_capture_start); 26540c0d06caSMauro Carvalho Chehab 26550c0d06caSMauro Carvalho Chehab /***************************************************************************** 26560c0d06caSMauro Carvalho Chehab * G P I O B I T control functions * 26570c0d06caSMauro Carvalho Chehab ******************************************************************************/ 26586b236a37SHans Verkuil static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val) 26590c0d06caSMauro Carvalho Chehab { 26600c0d06caSMauro Carvalho Chehab int status = 0; 26610c0d06caSMauro Carvalho Chehab 26623f9280a8SHans Verkuil gpio_val = (__force u32)cpu_to_le32(gpio_val); 26636b236a37SHans Verkuil status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); 26640c0d06caSMauro Carvalho Chehab 26650c0d06caSMauro Carvalho Chehab return status; 26660c0d06caSMauro Carvalho Chehab } 26670c0d06caSMauro Carvalho Chehab 26686b236a37SHans Verkuil static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val) 26690c0d06caSMauro Carvalho Chehab { 26703f9280a8SHans Verkuil __le32 tmp; 26710c0d06caSMauro Carvalho Chehab int status = 0; 26720c0d06caSMauro Carvalho Chehab 26736b236a37SHans Verkuil status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); 26746b236a37SHans Verkuil *gpio_val = le32_to_cpu(tmp); 26750c0d06caSMauro Carvalho Chehab 26760c0d06caSMauro Carvalho Chehab return status; 26770c0d06caSMauro Carvalho Chehab } 26780c0d06caSMauro Carvalho Chehab 26790c0d06caSMauro Carvalho Chehab /* 26800c0d06caSMauro Carvalho Chehab * cx231xx_set_gpio_direction 26810c0d06caSMauro Carvalho Chehab * Sets the direction of the GPIO pin to input or output 26820c0d06caSMauro Carvalho Chehab * 26830c0d06caSMauro Carvalho Chehab * Parameters : 26840c0d06caSMauro Carvalho Chehab * pin_number : The GPIO Pin number to program the direction for 26850c0d06caSMauro Carvalho Chehab * from 0 to 31 26860c0d06caSMauro Carvalho Chehab * pin_value : The Direction of the GPIO Pin under reference. 26870c0d06caSMauro Carvalho Chehab * 0 = Input direction 26880c0d06caSMauro Carvalho Chehab * 1 = Output direction 26890c0d06caSMauro Carvalho Chehab */ 26900c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_direction(struct cx231xx *dev, 26910c0d06caSMauro Carvalho Chehab int pin_number, int pin_value) 26920c0d06caSMauro Carvalho Chehab { 26930c0d06caSMauro Carvalho Chehab int status = 0; 26940c0d06caSMauro Carvalho Chehab u32 value = 0; 26950c0d06caSMauro Carvalho Chehab 26960c0d06caSMauro Carvalho Chehab /* Check for valid pin_number - if 32 , bail out */ 26970c0d06caSMauro Carvalho Chehab if (pin_number >= 32) 26980c0d06caSMauro Carvalho Chehab return -EINVAL; 26990c0d06caSMauro Carvalho Chehab 27000c0d06caSMauro Carvalho Chehab /* input */ 27010c0d06caSMauro Carvalho Chehab if (pin_value == 0) 27020c0d06caSMauro Carvalho Chehab value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 27030c0d06caSMauro Carvalho Chehab else 27040c0d06caSMauro Carvalho Chehab value = dev->gpio_dir | (1 << pin_number); 27050c0d06caSMauro Carvalho Chehab 27066b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val); 27070c0d06caSMauro Carvalho Chehab 27080c0d06caSMauro Carvalho Chehab /* cache the value for future */ 27090c0d06caSMauro Carvalho Chehab dev->gpio_dir = value; 27100c0d06caSMauro Carvalho Chehab 27110c0d06caSMauro Carvalho Chehab return status; 27120c0d06caSMauro Carvalho Chehab } 27130c0d06caSMauro Carvalho Chehab 27140c0d06caSMauro Carvalho Chehab /* 27150c0d06caSMauro Carvalho Chehab * cx231xx_set_gpio_value 27160c0d06caSMauro Carvalho Chehab * Sets the value of the GPIO pin to Logic high or low. The Pin under 27170c0d06caSMauro Carvalho Chehab * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 27180c0d06caSMauro Carvalho Chehab * 27190c0d06caSMauro Carvalho Chehab * Parameters : 27200c0d06caSMauro Carvalho Chehab * pin_number : The GPIO Pin number to program the direction for 27210c0d06caSMauro Carvalho Chehab * pin_value : The value of the GPIO Pin under reference. 27220c0d06caSMauro Carvalho Chehab * 0 = set it to 0 27230c0d06caSMauro Carvalho Chehab * 1 = set it to 1 27240c0d06caSMauro Carvalho Chehab */ 27250c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 27260c0d06caSMauro Carvalho Chehab { 27270c0d06caSMauro Carvalho Chehab int status = 0; 27280c0d06caSMauro Carvalho Chehab u32 value = 0; 27290c0d06caSMauro Carvalho Chehab 27300c0d06caSMauro Carvalho Chehab /* Check for valid pin_number - if 0xFF , bail out */ 27310c0d06caSMauro Carvalho Chehab if (pin_number >= 32) 27320c0d06caSMauro Carvalho Chehab return -EINVAL; 27330c0d06caSMauro Carvalho Chehab 27340c0d06caSMauro Carvalho Chehab /* first do a sanity check - if the Pin is not output, make it output */ 27350c0d06caSMauro Carvalho Chehab if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 27360c0d06caSMauro Carvalho Chehab /* It was in input mode */ 27370c0d06caSMauro Carvalho Chehab value = dev->gpio_dir | (1 << pin_number); 27380c0d06caSMauro Carvalho Chehab dev->gpio_dir = value; 27390c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 27406b236a37SHans Verkuil dev->gpio_val); 27410c0d06caSMauro Carvalho Chehab value = 0; 27420c0d06caSMauro Carvalho Chehab } 27430c0d06caSMauro Carvalho Chehab 27440c0d06caSMauro Carvalho Chehab if (pin_value == 0) 27450c0d06caSMauro Carvalho Chehab value = dev->gpio_val & (~(1 << pin_number)); 27460c0d06caSMauro Carvalho Chehab else 27470c0d06caSMauro Carvalho Chehab value = dev->gpio_val | (1 << pin_number); 27480c0d06caSMauro Carvalho Chehab 27490c0d06caSMauro Carvalho Chehab /* store the value */ 27500c0d06caSMauro Carvalho Chehab dev->gpio_val = value; 27510c0d06caSMauro Carvalho Chehab 27520c0d06caSMauro Carvalho Chehab /* toggle bit0 of GP_IO */ 27536b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 27540c0d06caSMauro Carvalho Chehab 27550c0d06caSMauro Carvalho Chehab return status; 27560c0d06caSMauro Carvalho Chehab } 27570c0d06caSMauro Carvalho Chehab 27580c0d06caSMauro Carvalho Chehab /***************************************************************************** 27590c0d06caSMauro Carvalho Chehab * G P I O I2C related functions * 27600c0d06caSMauro Carvalho Chehab ******************************************************************************/ 27610c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_start(struct cx231xx *dev) 27620c0d06caSMauro Carvalho Chehab { 27630c0d06caSMauro Carvalho Chehab int status = 0; 27640c0d06caSMauro Carvalho Chehab 27650c0d06caSMauro Carvalho Chehab /* set SCL to output 1 ; set SDA to output 1 */ 27660c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 27670c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 27680c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 27690c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 27700c0d06caSMauro Carvalho Chehab 27716b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 27720c0d06caSMauro Carvalho Chehab if (status < 0) 27730c0d06caSMauro Carvalho Chehab return -EINVAL; 27740c0d06caSMauro Carvalho Chehab 27750c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */ 27760c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 27770c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 27780c0d06caSMauro Carvalho Chehab 27796b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 27800c0d06caSMauro Carvalho Chehab if (status < 0) 27810c0d06caSMauro Carvalho Chehab return -EINVAL; 27820c0d06caSMauro Carvalho Chehab 27830c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 27840c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 27850c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 27860c0d06caSMauro Carvalho Chehab 27876b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 27880c0d06caSMauro Carvalho Chehab if (status < 0) 27890c0d06caSMauro Carvalho Chehab return -EINVAL; 27900c0d06caSMauro Carvalho Chehab 27910c0d06caSMauro Carvalho Chehab return status; 27920c0d06caSMauro Carvalho Chehab } 27930c0d06caSMauro Carvalho Chehab 27940c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_end(struct cx231xx *dev) 27950c0d06caSMauro Carvalho Chehab { 27960c0d06caSMauro Carvalho Chehab int status = 0; 27970c0d06caSMauro Carvalho Chehab 27980c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 27990c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 28000c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 28010c0d06caSMauro Carvalho Chehab 28020c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28030c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 28040c0d06caSMauro Carvalho Chehab 28056b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 28060c0d06caSMauro Carvalho Chehab if (status < 0) 28070c0d06caSMauro Carvalho Chehab return -EINVAL; 28080c0d06caSMauro Carvalho Chehab 28090c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */ 28100c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28110c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 28120c0d06caSMauro Carvalho Chehab 28136b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 28140c0d06caSMauro Carvalho Chehab if (status < 0) 28150c0d06caSMauro Carvalho Chehab return -EINVAL; 28160c0d06caSMauro Carvalho Chehab 28170c0d06caSMauro Carvalho Chehab /* set SCL to input ,release SCL cable control 28180c0d06caSMauro Carvalho Chehab set SDA to input ,release SDA cable control */ 28190c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 28200c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 28210c0d06caSMauro Carvalho Chehab 28220c0d06caSMauro Carvalho Chehab status = 28236b236a37SHans Verkuil cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 28240c0d06caSMauro Carvalho Chehab if (status < 0) 28250c0d06caSMauro Carvalho Chehab return -EINVAL; 28260c0d06caSMauro Carvalho Chehab 28270c0d06caSMauro Carvalho Chehab return status; 28280c0d06caSMauro Carvalho Chehab } 28290c0d06caSMauro Carvalho Chehab 28300c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 28310c0d06caSMauro Carvalho Chehab { 28320c0d06caSMauro Carvalho Chehab int status = 0; 28330c0d06caSMauro Carvalho Chehab u8 i; 28340c0d06caSMauro Carvalho Chehab 28350c0d06caSMauro Carvalho Chehab /* set SCL to output ; set SDA to output */ 28360c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 28370c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 28380c0d06caSMauro Carvalho Chehab 28390c0d06caSMauro Carvalho Chehab for (i = 0; i < 8; i++) { 28400c0d06caSMauro Carvalho Chehab if (((data << i) & 0x80) == 0) { 28410c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 28420c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28430c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 28440c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28456b236a37SHans Verkuil dev->gpio_val); 28460c0d06caSMauro Carvalho Chehab 28470c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */ 28480c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28490c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28506b236a37SHans Verkuil dev->gpio_val); 28510c0d06caSMauro Carvalho Chehab 28520c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 28530c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28540c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28556b236a37SHans Verkuil dev->gpio_val); 28560c0d06caSMauro Carvalho Chehab } else { 28570c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 1 */ 28580c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28590c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 28600c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28616b236a37SHans Verkuil dev->gpio_val); 28620c0d06caSMauro Carvalho Chehab 28630c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 1 */ 28640c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28650c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28666b236a37SHans Verkuil dev->gpio_val); 28670c0d06caSMauro Carvalho Chehab 28680c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 1 */ 28690c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28700c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28716b236a37SHans Verkuil dev->gpio_val); 28720c0d06caSMauro Carvalho Chehab } 28730c0d06caSMauro Carvalho Chehab } 28740c0d06caSMauro Carvalho Chehab return status; 28750c0d06caSMauro Carvalho Chehab } 28760c0d06caSMauro Carvalho Chehab 28770c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 28780c0d06caSMauro Carvalho Chehab { 28790c0d06caSMauro Carvalho Chehab u8 value = 0; 28800c0d06caSMauro Carvalho Chehab int status = 0; 28810c0d06caSMauro Carvalho Chehab u32 gpio_logic_value = 0; 28820c0d06caSMauro Carvalho Chehab u8 i; 28830c0d06caSMauro Carvalho Chehab 28840c0d06caSMauro Carvalho Chehab /* read byte */ 28850c0d06caSMauro Carvalho Chehab for (i = 0; i < 8; i++) { /* send write I2c addr */ 28860c0d06caSMauro Carvalho Chehab 28870c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to input */ 28880c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28890c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28906b236a37SHans Verkuil dev->gpio_val); 28910c0d06caSMauro Carvalho Chehab 28920c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to input */ 28930c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28940c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28956b236a37SHans Verkuil dev->gpio_val); 28960c0d06caSMauro Carvalho Chehab 28970c0d06caSMauro Carvalho Chehab /* get SDA data bit */ 28980c0d06caSMauro Carvalho Chehab gpio_logic_value = dev->gpio_val; 28990c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 29006b236a37SHans Verkuil &dev->gpio_val); 29010c0d06caSMauro Carvalho Chehab if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 29020c0d06caSMauro Carvalho Chehab value |= (1 << (8 - i - 1)); 29030c0d06caSMauro Carvalho Chehab 29040c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29050c0d06caSMauro Carvalho Chehab } 29060c0d06caSMauro Carvalho Chehab 29070c0d06caSMauro Carvalho Chehab /* set SCL to output 0,finish the read latest SCL signal. 29080c0d06caSMauro Carvalho Chehab !!!set SDA to input, never to modify SDA direction at 29090c0d06caSMauro Carvalho Chehab the same times */ 29100c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29116b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29120c0d06caSMauro Carvalho Chehab 29130c0d06caSMauro Carvalho Chehab /* store the value */ 29140c0d06caSMauro Carvalho Chehab *buf = value & 0xff; 29150c0d06caSMauro Carvalho Chehab 29160c0d06caSMauro Carvalho Chehab return status; 29170c0d06caSMauro Carvalho Chehab } 29180c0d06caSMauro Carvalho Chehab 29190c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 29200c0d06caSMauro Carvalho Chehab { 29210c0d06caSMauro Carvalho Chehab int status = 0; 29220c0d06caSMauro Carvalho Chehab u32 gpio_logic_value = 0; 29230c0d06caSMauro Carvalho Chehab int nCnt = 10; 29240c0d06caSMauro Carvalho Chehab int nInit = nCnt; 29250c0d06caSMauro Carvalho Chehab 29260c0d06caSMauro Carvalho Chehab /* clock stretch; set SCL to input; set SDA to input; 29270c0d06caSMauro Carvalho Chehab get SCL value till SCL = 1 */ 29280c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 29290c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 29300c0d06caSMauro Carvalho Chehab 29310c0d06caSMauro Carvalho Chehab gpio_logic_value = dev->gpio_val; 29326b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29330c0d06caSMauro Carvalho Chehab 29340c0d06caSMauro Carvalho Chehab do { 29350c0d06caSMauro Carvalho Chehab msleep(2); 29360c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 29376b236a37SHans Verkuil &dev->gpio_val); 29380c0d06caSMauro Carvalho Chehab nCnt--; 29390c0d06caSMauro Carvalho Chehab } while (((dev->gpio_val & 29400c0d06caSMauro Carvalho Chehab (1 << dev->board.tuner_scl_gpio)) == 0) && 29410c0d06caSMauro Carvalho Chehab (nCnt > 0)); 29420c0d06caSMauro Carvalho Chehab 29430c0d06caSMauro Carvalho Chehab if (nCnt == 0) 2944336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, 2945b7085c08SMauro Carvalho Chehab "No ACK after %d msec -GPIO I2C failed!", 29460c0d06caSMauro Carvalho Chehab nInit * 10); 29470c0d06caSMauro Carvalho Chehab 29480c0d06caSMauro Carvalho Chehab /* 29490c0d06caSMauro Carvalho Chehab * readAck 29500c0d06caSMauro Carvalho Chehab * through clock stretch, slave has given a SCL signal, 29510c0d06caSMauro Carvalho Chehab * so the SDA data can be directly read. 29520c0d06caSMauro Carvalho Chehab */ 29536b236a37SHans Verkuil status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val); 29540c0d06caSMauro Carvalho Chehab 29550c0d06caSMauro Carvalho Chehab if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 29560c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29570c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 29580c0d06caSMauro Carvalho Chehab status = 0; 29590c0d06caSMauro Carvalho Chehab } else { 29600c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29610c0d06caSMauro Carvalho Chehab dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 29620c0d06caSMauro Carvalho Chehab } 29630c0d06caSMauro Carvalho Chehab 29640c0d06caSMauro Carvalho Chehab /* read SDA end, set the SCL to output 0, after this operation, 29650c0d06caSMauro Carvalho Chehab SDA direction can be changed. */ 29660c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29670c0d06caSMauro Carvalho Chehab dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 29680c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29696b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29700c0d06caSMauro Carvalho Chehab 29710c0d06caSMauro Carvalho Chehab return status; 29720c0d06caSMauro Carvalho Chehab } 29730c0d06caSMauro Carvalho Chehab 29740c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 29750c0d06caSMauro Carvalho Chehab { 29760c0d06caSMauro Carvalho Chehab int status = 0; 29770c0d06caSMauro Carvalho Chehab 29783e4d8f48SMauro Carvalho Chehab /* set SDA to output */ 29790c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 29806b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29810c0d06caSMauro Carvalho Chehab 29820c0d06caSMauro Carvalho Chehab /* set SCL = 0 (output); set SDA = 0 (output) */ 29830c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 29840c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29856b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29860c0d06caSMauro Carvalho Chehab 29870c0d06caSMauro Carvalho Chehab /* set SCL = 1 (output); set SDA = 0 (output) */ 29880c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 29896b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29900c0d06caSMauro Carvalho Chehab 29910c0d06caSMauro Carvalho Chehab /* set SCL = 0 (output); set SDA = 0 (output) */ 29920c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29936b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29940c0d06caSMauro Carvalho Chehab 29950c0d06caSMauro Carvalho Chehab /* set SDA to input,and then the slave will read data from SDA. */ 29960c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 29976b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 29980c0d06caSMauro Carvalho Chehab 29990c0d06caSMauro Carvalho Chehab return status; 30000c0d06caSMauro Carvalho Chehab } 30010c0d06caSMauro Carvalho Chehab 30020c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 30030c0d06caSMauro Carvalho Chehab { 30040c0d06caSMauro Carvalho Chehab int status = 0; 30050c0d06caSMauro Carvalho Chehab 30060c0d06caSMauro Carvalho Chehab /* set scl to output ; set sda to input */ 30070c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 30080c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 30096b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 30100c0d06caSMauro Carvalho Chehab 30110c0d06caSMauro Carvalho Chehab /* set scl to output 0; set sda to input */ 30120c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 30136b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 30140c0d06caSMauro Carvalho Chehab 30150c0d06caSMauro Carvalho Chehab /* set scl to output 1; set sda to input */ 30160c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 30176b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 30180c0d06caSMauro Carvalho Chehab 30190c0d06caSMauro Carvalho Chehab return status; 30200c0d06caSMauro Carvalho Chehab } 30210c0d06caSMauro Carvalho Chehab 30220c0d06caSMauro Carvalho Chehab /***************************************************************************** 30230c0d06caSMauro Carvalho Chehab * G P I O I2C related functions * 30240c0d06caSMauro Carvalho Chehab ******************************************************************************/ 30250c0d06caSMauro Carvalho Chehab /* cx231xx_gpio_i2c_read 30260c0d06caSMauro Carvalho Chehab * Function to read data from gpio based I2C interface 30270c0d06caSMauro Carvalho Chehab */ 30280c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 30290c0d06caSMauro Carvalho Chehab { 30300c0d06caSMauro Carvalho Chehab int status = 0; 30310c0d06caSMauro Carvalho Chehab int i = 0; 30320c0d06caSMauro Carvalho Chehab 30330c0d06caSMauro Carvalho Chehab /* get the lock */ 30340c0d06caSMauro Carvalho Chehab mutex_lock(&dev->gpio_i2c_lock); 30350c0d06caSMauro Carvalho Chehab 30360c0d06caSMauro Carvalho Chehab /* start */ 30370c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_start(dev); 30380c0d06caSMauro Carvalho Chehab 30390c0d06caSMauro Carvalho Chehab /* write dev_addr */ 30400c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 30410c0d06caSMauro Carvalho Chehab 30420c0d06caSMauro Carvalho Chehab /* readAck */ 30430c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_read_ack(dev); 30440c0d06caSMauro Carvalho Chehab 30450c0d06caSMauro Carvalho Chehab /* read data */ 30460c0d06caSMauro Carvalho Chehab for (i = 0; i < len; i++) { 30470c0d06caSMauro Carvalho Chehab /* read data */ 30480c0d06caSMauro Carvalho Chehab buf[i] = 0; 30490c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 30500c0d06caSMauro Carvalho Chehab 30510c0d06caSMauro Carvalho Chehab if ((i + 1) != len) { 30520c0d06caSMauro Carvalho Chehab /* only do write ack if we more length */ 30530c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_ack(dev); 30540c0d06caSMauro Carvalho Chehab } 30550c0d06caSMauro Carvalho Chehab } 30560c0d06caSMauro Carvalho Chehab 30570c0d06caSMauro Carvalho Chehab /* write NAK - inform reads are complete */ 30580c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_nak(dev); 30590c0d06caSMauro Carvalho Chehab 30600c0d06caSMauro Carvalho Chehab /* write end */ 30610c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_end(dev); 30620c0d06caSMauro Carvalho Chehab 30630c0d06caSMauro Carvalho Chehab /* release the lock */ 30640c0d06caSMauro Carvalho Chehab mutex_unlock(&dev->gpio_i2c_lock); 30650c0d06caSMauro Carvalho Chehab 30660c0d06caSMauro Carvalho Chehab return status; 30670c0d06caSMauro Carvalho Chehab } 30680c0d06caSMauro Carvalho Chehab 30690c0d06caSMauro Carvalho Chehab /* cx231xx_gpio_i2c_write 30700c0d06caSMauro Carvalho Chehab * Function to write data to gpio based I2C interface 30710c0d06caSMauro Carvalho Chehab */ 30720c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 30730c0d06caSMauro Carvalho Chehab { 30740c0d06caSMauro Carvalho Chehab int i = 0; 30750c0d06caSMauro Carvalho Chehab 30760c0d06caSMauro Carvalho Chehab /* get the lock */ 30770c0d06caSMauro Carvalho Chehab mutex_lock(&dev->gpio_i2c_lock); 30780c0d06caSMauro Carvalho Chehab 30790c0d06caSMauro Carvalho Chehab /* start */ 30800c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_start(dev); 30810c0d06caSMauro Carvalho Chehab 30820c0d06caSMauro Carvalho Chehab /* write dev_addr */ 30830c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 30840c0d06caSMauro Carvalho Chehab 30850c0d06caSMauro Carvalho Chehab /* read Ack */ 30860c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_read_ack(dev); 30870c0d06caSMauro Carvalho Chehab 30880c0d06caSMauro Carvalho Chehab for (i = 0; i < len; i++) { 30890c0d06caSMauro Carvalho Chehab /* Write data */ 30900c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_write_byte(dev, buf[i]); 30910c0d06caSMauro Carvalho Chehab 30920c0d06caSMauro Carvalho Chehab /* read Ack */ 30930c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_read_ack(dev); 30940c0d06caSMauro Carvalho Chehab } 30950c0d06caSMauro Carvalho Chehab 30960c0d06caSMauro Carvalho Chehab /* write End */ 30970c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_end(dev); 30980c0d06caSMauro Carvalho Chehab 30990c0d06caSMauro Carvalho Chehab /* release the lock */ 31000c0d06caSMauro Carvalho Chehab mutex_unlock(&dev->gpio_i2c_lock); 31010c0d06caSMauro Carvalho Chehab 31020c0d06caSMauro Carvalho Chehab return 0; 31030c0d06caSMauro Carvalho Chehab } 3104