10c0d06caSMauro Carvalho Chehab /* 20c0d06caSMauro Carvalho Chehab cx231xx_avcore.c - driver for Conexant Cx23100/101/102 30c0d06caSMauro Carvalho Chehab USB video capture devices 40c0d06caSMauro Carvalho Chehab 50c0d06caSMauro Carvalho Chehab Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 60c0d06caSMauro Carvalho Chehab 70c0d06caSMauro Carvalho Chehab This program contains the specific code to control the avdecoder chip and 80c0d06caSMauro Carvalho Chehab other related usb control functions for cx231xx based chipset. 90c0d06caSMauro Carvalho Chehab 100c0d06caSMauro Carvalho Chehab This program is free software; you can redistribute it and/or modify 110c0d06caSMauro Carvalho Chehab it under the terms of the GNU General Public License as published by 120c0d06caSMauro Carvalho Chehab the Free Software Foundation; either version 2 of the License, or 130c0d06caSMauro Carvalho Chehab (at your option) any later version. 140c0d06caSMauro Carvalho Chehab 150c0d06caSMauro Carvalho Chehab This program is distributed in the hope that it will be useful, 160c0d06caSMauro Carvalho Chehab but WITHOUT ANY WARRANTY; without even the implied warranty of 170c0d06caSMauro Carvalho Chehab MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 180c0d06caSMauro Carvalho Chehab GNU General Public License for more details. 190c0d06caSMauro Carvalho Chehab 200c0d06caSMauro Carvalho Chehab You should have received a copy of the GNU General Public License 210c0d06caSMauro Carvalho Chehab along with this program; if not, write to the Free Software 220c0d06caSMauro Carvalho Chehab Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 230c0d06caSMauro Carvalho Chehab */ 240c0d06caSMauro Carvalho Chehab 250c0d06caSMauro Carvalho Chehab #include <linux/init.h> 260c0d06caSMauro Carvalho Chehab #include <linux/list.h> 270c0d06caSMauro Carvalho Chehab #include <linux/module.h> 280c0d06caSMauro Carvalho Chehab #include <linux/kernel.h> 290c0d06caSMauro Carvalho Chehab #include <linux/bitmap.h> 300c0d06caSMauro Carvalho Chehab #include <linux/usb.h> 310c0d06caSMauro Carvalho Chehab #include <linux/i2c.h> 320c0d06caSMauro Carvalho Chehab #include <linux/mm.h> 330c0d06caSMauro Carvalho Chehab #include <linux/mutex.h> 340c0d06caSMauro Carvalho Chehab #include <media/tuner.h> 350c0d06caSMauro Carvalho Chehab 360c0d06caSMauro Carvalho Chehab #include <media/v4l2-common.h> 370c0d06caSMauro Carvalho Chehab #include <media/v4l2-ioctl.h> 380c0d06caSMauro Carvalho Chehab #include <media/v4l2-chip-ident.h> 390c0d06caSMauro Carvalho Chehab 400c0d06caSMauro Carvalho Chehab #include "cx231xx.h" 410c0d06caSMauro Carvalho Chehab #include "cx231xx-dif.h" 420c0d06caSMauro Carvalho Chehab 430c0d06caSMauro Carvalho Chehab #define TUNER_MODE_FM_RADIO 0 440c0d06caSMauro Carvalho Chehab /****************************************************************************** 450c0d06caSMauro Carvalho Chehab -: BLOCK ARRANGEMENT :- 460c0d06caSMauro Carvalho Chehab I2S block ----------------------| 470c0d06caSMauro Carvalho Chehab [I2S audio] | 480c0d06caSMauro Carvalho Chehab | 490c0d06caSMauro Carvalho Chehab Analog Front End --> Direct IF -|-> Cx25840 --> Audio 500c0d06caSMauro Carvalho Chehab [video & audio] | [Audio] 510c0d06caSMauro Carvalho Chehab | 520c0d06caSMauro Carvalho Chehab |-> Cx25840 --> Video 530c0d06caSMauro Carvalho Chehab [Video] 540c0d06caSMauro Carvalho Chehab 550c0d06caSMauro Carvalho Chehab *******************************************************************************/ 560c0d06caSMauro Carvalho Chehab /****************************************************************************** 570c0d06caSMauro Carvalho Chehab * VERVE REGISTER * 580c0d06caSMauro Carvalho Chehab * * 590c0d06caSMauro Carvalho Chehab ******************************************************************************/ 600c0d06caSMauro Carvalho Chehab static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 610c0d06caSMauro Carvalho Chehab { 620c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 630c0d06caSMauro Carvalho Chehab saddr, 1, data, 1); 640c0d06caSMauro Carvalho Chehab } 650c0d06caSMauro Carvalho Chehab 660c0d06caSMauro Carvalho Chehab static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 670c0d06caSMauro Carvalho Chehab { 680c0d06caSMauro Carvalho Chehab int status; 690c0d06caSMauro Carvalho Chehab u32 temp = 0; 700c0d06caSMauro Carvalho Chehab 710c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 720c0d06caSMauro Carvalho Chehab saddr, 1, &temp, 1); 730c0d06caSMauro Carvalho Chehab *data = (u8) temp; 740c0d06caSMauro Carvalho Chehab return status; 750c0d06caSMauro Carvalho Chehab } 760c0d06caSMauro Carvalho Chehab void initGPIO(struct cx231xx *dev) 770c0d06caSMauro Carvalho Chehab { 780c0d06caSMauro Carvalho Chehab u32 _gpio_direction = 0; 790c0d06caSMauro Carvalho Chehab u32 value = 0; 800c0d06caSMauro Carvalho Chehab u8 val = 0; 810c0d06caSMauro Carvalho Chehab 820c0d06caSMauro Carvalho Chehab _gpio_direction = _gpio_direction & 0xFC0003FF; 830c0d06caSMauro Carvalho Chehab _gpio_direction = _gpio_direction | 0x03FDFC00; 840c0d06caSMauro Carvalho Chehab cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 850c0d06caSMauro Carvalho Chehab 860c0d06caSMauro Carvalho Chehab verve_read_byte(dev, 0x07, &val); 870c0d06caSMauro Carvalho Chehab cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 880c0d06caSMauro Carvalho Chehab verve_write_byte(dev, 0x07, 0xF4); 890c0d06caSMauro Carvalho Chehab verve_read_byte(dev, 0x07, &val); 900c0d06caSMauro Carvalho Chehab cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 910c0d06caSMauro Carvalho Chehab 920c0d06caSMauro Carvalho Chehab cx231xx_capture_start(dev, 1, Vbi); 930c0d06caSMauro Carvalho Chehab 940c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 950c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 960c0d06caSMauro Carvalho Chehab 970c0d06caSMauro Carvalho Chehab } 980c0d06caSMauro Carvalho Chehab void uninitGPIO(struct cx231xx *dev) 990c0d06caSMauro Carvalho Chehab { 1000c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 1010c0d06caSMauro Carvalho Chehab 1020c0d06caSMauro Carvalho Chehab cx231xx_capture_start(dev, 0, Vbi); 1030c0d06caSMauro Carvalho Chehab verve_write_byte(dev, 0x07, 0x14); 1040c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1050c0d06caSMauro Carvalho Chehab 0x68, value, 4); 1060c0d06caSMauro Carvalho Chehab } 1070c0d06caSMauro Carvalho Chehab 1080c0d06caSMauro Carvalho Chehab /****************************************************************************** 1090c0d06caSMauro Carvalho Chehab * A F E - B L O C K C O N T R O L functions * 1100c0d06caSMauro Carvalho Chehab * [ANALOG FRONT END] * 1110c0d06caSMauro Carvalho Chehab ******************************************************************************/ 1120c0d06caSMauro Carvalho Chehab static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 1130c0d06caSMauro Carvalho Chehab { 1140c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 1150c0d06caSMauro Carvalho Chehab saddr, 2, data, 1); 1160c0d06caSMauro Carvalho Chehab } 1170c0d06caSMauro Carvalho Chehab 1180c0d06caSMauro Carvalho Chehab static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 1190c0d06caSMauro Carvalho Chehab { 1200c0d06caSMauro Carvalho Chehab int status; 1210c0d06caSMauro Carvalho Chehab u32 temp = 0; 1220c0d06caSMauro Carvalho Chehab 1230c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 1240c0d06caSMauro Carvalho Chehab saddr, 2, &temp, 1); 1250c0d06caSMauro Carvalho Chehab *data = (u8) temp; 1260c0d06caSMauro Carvalho Chehab return status; 1270c0d06caSMauro Carvalho Chehab } 1280c0d06caSMauro Carvalho Chehab 1290c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 1300c0d06caSMauro Carvalho Chehab { 1310c0d06caSMauro Carvalho Chehab int status = 0; 1320c0d06caSMauro Carvalho Chehab u8 temp = 0; 1330c0d06caSMauro Carvalho Chehab u8 afe_power_status = 0; 1340c0d06caSMauro Carvalho Chehab int i = 0; 1350c0d06caSMauro Carvalho Chehab 1360c0d06caSMauro Carvalho Chehab /* super block initialize */ 1370c0d06caSMauro Carvalho Chehab temp = (u8) (ref_count & 0xff); 1380c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 1390c0d06caSMauro Carvalho Chehab if (status < 0) 1400c0d06caSMauro Carvalho Chehab return status; 1410c0d06caSMauro Carvalho Chehab 1420c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 1430c0d06caSMauro Carvalho Chehab if (status < 0) 1440c0d06caSMauro Carvalho Chehab return status; 1450c0d06caSMauro Carvalho Chehab 1460c0d06caSMauro Carvalho Chehab temp = (u8) ((ref_count & 0x300) >> 8); 1470c0d06caSMauro Carvalho Chehab temp |= 0x40; 1480c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 1490c0d06caSMauro Carvalho Chehab if (status < 0) 1500c0d06caSMauro Carvalho Chehab return status; 1510c0d06caSMauro Carvalho Chehab 1520c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 1530c0d06caSMauro Carvalho Chehab if (status < 0) 1540c0d06caSMauro Carvalho Chehab return status; 1550c0d06caSMauro Carvalho Chehab 1560c0d06caSMauro Carvalho Chehab /* enable pll */ 1570c0d06caSMauro Carvalho Chehab while (afe_power_status != 0x18) { 1580c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 1590c0d06caSMauro Carvalho Chehab if (status < 0) { 1600c0d06caSMauro Carvalho Chehab cx231xx_info( 1610c0d06caSMauro Carvalho Chehab ": Init Super Block failed in send cmd\n"); 1620c0d06caSMauro Carvalho Chehab break; 1630c0d06caSMauro Carvalho Chehab } 1640c0d06caSMauro Carvalho Chehab 1650c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 1660c0d06caSMauro Carvalho Chehab afe_power_status &= 0xff; 1670c0d06caSMauro Carvalho Chehab if (status < 0) { 1680c0d06caSMauro Carvalho Chehab cx231xx_info( 1690c0d06caSMauro Carvalho Chehab ": Init Super Block failed in receive cmd\n"); 1700c0d06caSMauro Carvalho Chehab break; 1710c0d06caSMauro Carvalho Chehab } 1720c0d06caSMauro Carvalho Chehab i++; 1730c0d06caSMauro Carvalho Chehab if (i == 10) { 1740c0d06caSMauro Carvalho Chehab cx231xx_info( 1750c0d06caSMauro Carvalho Chehab ": Init Super Block force break in loop !!!!\n"); 1760c0d06caSMauro Carvalho Chehab status = -1; 1770c0d06caSMauro Carvalho Chehab break; 1780c0d06caSMauro Carvalho Chehab } 1790c0d06caSMauro Carvalho Chehab } 1800c0d06caSMauro Carvalho Chehab 1810c0d06caSMauro Carvalho Chehab if (status < 0) 1820c0d06caSMauro Carvalho Chehab return status; 1830c0d06caSMauro Carvalho Chehab 1840c0d06caSMauro Carvalho Chehab /* start tuning filter */ 1850c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 1860c0d06caSMauro Carvalho Chehab if (status < 0) 1870c0d06caSMauro Carvalho Chehab return status; 1880c0d06caSMauro Carvalho Chehab 1890c0d06caSMauro Carvalho Chehab msleep(5); 1900c0d06caSMauro Carvalho Chehab 1910c0d06caSMauro Carvalho Chehab /* exit tuning */ 1920c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 1930c0d06caSMauro Carvalho Chehab 1940c0d06caSMauro Carvalho Chehab return status; 1950c0d06caSMauro Carvalho Chehab } 1960c0d06caSMauro Carvalho Chehab 1970c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_channels(struct cx231xx *dev) 1980c0d06caSMauro Carvalho Chehab { 1990c0d06caSMauro Carvalho Chehab int status = 0; 2000c0d06caSMauro Carvalho Chehab 2010c0d06caSMauro Carvalho Chehab /* power up all 3 channels, clear pd_buffer */ 2020c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 2030c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 2040c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 2050c0d06caSMauro Carvalho Chehab 2060c0d06caSMauro Carvalho Chehab /* Enable quantizer calibration */ 2070c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 2080c0d06caSMauro Carvalho Chehab 2090c0d06caSMauro Carvalho Chehab /* channel initialize, force modulator (fb) reset */ 2100c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 2110c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 2120c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 2130c0d06caSMauro Carvalho Chehab 2140c0d06caSMauro Carvalho Chehab /* start quantilizer calibration */ 2150c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 2160c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 2170c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 2180c0d06caSMauro Carvalho Chehab msleep(5); 2190c0d06caSMauro Carvalho Chehab 2200c0d06caSMauro Carvalho Chehab /* exit modulator (fb) reset */ 2210c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 2220c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 2230c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 2240c0d06caSMauro Carvalho Chehab 2250c0d06caSMauro Carvalho Chehab /* enable the pre_clamp in each channel for single-ended input */ 2260c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 2270c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 2280c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 2290c0d06caSMauro Carvalho Chehab 2300c0d06caSMauro Carvalho Chehab /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 2310c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 2320c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 2330c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 2340c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 2350c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 2360c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 2370c0d06caSMauro Carvalho Chehab 2380c0d06caSMauro Carvalho Chehab /* dynamic element matching off */ 2390c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 2400c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 2410c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 2420c0d06caSMauro Carvalho Chehab 2430c0d06caSMauro Carvalho Chehab return status; 2440c0d06caSMauro Carvalho Chehab } 2450c0d06caSMauro Carvalho Chehab 2460c0d06caSMauro Carvalho Chehab int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 2470c0d06caSMauro Carvalho Chehab { 2480c0d06caSMauro Carvalho Chehab u8 c_value = 0; 2490c0d06caSMauro Carvalho Chehab int status = 0; 2500c0d06caSMauro Carvalho Chehab 2510c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 2520c0d06caSMauro Carvalho Chehab c_value &= (~(0x50)); 2530c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 2540c0d06caSMauro Carvalho Chehab 2550c0d06caSMauro Carvalho Chehab return status; 2560c0d06caSMauro Carvalho Chehab } 2570c0d06caSMauro Carvalho Chehab 2580c0d06caSMauro Carvalho Chehab /* 2590c0d06caSMauro Carvalho Chehab The Analog Front End in Cx231xx has 3 channels. These 2600c0d06caSMauro Carvalho Chehab channels are used to share between different inputs 2610c0d06caSMauro Carvalho Chehab like tuner, s-video and composite inputs. 2620c0d06caSMauro Carvalho Chehab 2630c0d06caSMauro Carvalho Chehab channel 1 ----- pin 1 to pin4(in reg is 1-4) 2640c0d06caSMauro Carvalho Chehab channel 2 ----- pin 5 to pin8(in reg is 5-8) 2650c0d06caSMauro Carvalho Chehab channel 3 ----- pin 9 to pin 12(in reg is 9-11) 2660c0d06caSMauro Carvalho Chehab */ 2670c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 2680c0d06caSMauro Carvalho Chehab { 2690c0d06caSMauro Carvalho Chehab u8 ch1_setting = (u8) input_mux; 2700c0d06caSMauro Carvalho Chehab u8 ch2_setting = (u8) (input_mux >> 8); 2710c0d06caSMauro Carvalho Chehab u8 ch3_setting = (u8) (input_mux >> 16); 2720c0d06caSMauro Carvalho Chehab int status = 0; 2730c0d06caSMauro Carvalho Chehab u8 value = 0; 2740c0d06caSMauro Carvalho Chehab 2750c0d06caSMauro Carvalho Chehab if (ch1_setting != 0) { 2760c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 2770c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK; 2780c0d06caSMauro Carvalho Chehab value |= (ch1_setting - 1) << 4; 2790c0d06caSMauro Carvalho Chehab value &= 0xff; 2800c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH1, value); 2810c0d06caSMauro Carvalho Chehab } 2820c0d06caSMauro Carvalho Chehab 2830c0d06caSMauro Carvalho Chehab if (ch2_setting != 0) { 2840c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 2850c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK; 2860c0d06caSMauro Carvalho Chehab value |= (ch2_setting - 1) << 4; 2870c0d06caSMauro Carvalho Chehab value &= 0xff; 2880c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH2, value); 2890c0d06caSMauro Carvalho Chehab } 2900c0d06caSMauro Carvalho Chehab 2910c0d06caSMauro Carvalho Chehab /* For ch3_setting, the value to put in the register is 2920c0d06caSMauro Carvalho Chehab 7 less than the input number */ 2930c0d06caSMauro Carvalho Chehab if (ch3_setting != 0) { 2940c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 2950c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK; 2960c0d06caSMauro Carvalho Chehab value |= (ch3_setting - 1) << 4; 2970c0d06caSMauro Carvalho Chehab value &= 0xff; 2980c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH3, value); 2990c0d06caSMauro Carvalho Chehab } 3000c0d06caSMauro Carvalho Chehab 3010c0d06caSMauro Carvalho Chehab return status; 3020c0d06caSMauro Carvalho Chehab } 3030c0d06caSMauro Carvalho Chehab 3040c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 3050c0d06caSMauro Carvalho Chehab { 3060c0d06caSMauro Carvalho Chehab int status = 0; 3070c0d06caSMauro Carvalho Chehab 3080c0d06caSMauro Carvalho Chehab /* 3090c0d06caSMauro Carvalho Chehab * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 3100c0d06caSMauro Carvalho Chehab * Currently, only baseband works. 3110c0d06caSMauro Carvalho Chehab */ 3120c0d06caSMauro Carvalho Chehab 3130c0d06caSMauro Carvalho Chehab switch (mode) { 3140c0d06caSMauro Carvalho Chehab case AFE_MODE_LOW_IF: 3150c0d06caSMauro Carvalho Chehab cx231xx_Setup_AFE_for_LowIF(dev); 3160c0d06caSMauro Carvalho Chehab break; 3170c0d06caSMauro Carvalho Chehab case AFE_MODE_BASEBAND: 3180c0d06caSMauro Carvalho Chehab status = cx231xx_afe_setup_AFE_for_baseband(dev); 3190c0d06caSMauro Carvalho Chehab break; 3200c0d06caSMauro Carvalho Chehab case AFE_MODE_EU_HI_IF: 3210c0d06caSMauro Carvalho Chehab /* SetupAFEforEuHiIF(); */ 3220c0d06caSMauro Carvalho Chehab break; 3230c0d06caSMauro Carvalho Chehab case AFE_MODE_US_HI_IF: 3240c0d06caSMauro Carvalho Chehab /* SetupAFEforUsHiIF(); */ 3250c0d06caSMauro Carvalho Chehab break; 3260c0d06caSMauro Carvalho Chehab case AFE_MODE_JAPAN_HI_IF: 3270c0d06caSMauro Carvalho Chehab /* SetupAFEforJapanHiIF(); */ 3280c0d06caSMauro Carvalho Chehab break; 3290c0d06caSMauro Carvalho Chehab } 3300c0d06caSMauro Carvalho Chehab 3310c0d06caSMauro Carvalho Chehab if ((mode != dev->afe_mode) && 3320c0d06caSMauro Carvalho Chehab (dev->video_input == CX231XX_VMUX_TELEVISION)) 3330c0d06caSMauro Carvalho Chehab status = cx231xx_afe_adjust_ref_count(dev, 3340c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION); 3350c0d06caSMauro Carvalho Chehab 3360c0d06caSMauro Carvalho Chehab dev->afe_mode = mode; 3370c0d06caSMauro Carvalho Chehab 3380c0d06caSMauro Carvalho Chehab return status; 3390c0d06caSMauro Carvalho Chehab } 3400c0d06caSMauro Carvalho Chehab 3410c0d06caSMauro Carvalho Chehab int cx231xx_afe_update_power_control(struct cx231xx *dev, 3420c0d06caSMauro Carvalho Chehab enum AV_MODE avmode) 3430c0d06caSMauro Carvalho Chehab { 3440c0d06caSMauro Carvalho Chehab u8 afe_power_status = 0; 3450c0d06caSMauro Carvalho Chehab int status = 0; 3460c0d06caSMauro Carvalho Chehab 3470c0d06caSMauro Carvalho Chehab switch (dev->model) { 3480c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_CARRAERA: 3490c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_250: 3500c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_SHELBY: 3510c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_250: 3520c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_253S: 3530c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_253S: 3540c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 3550c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_EXETER: 3560c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 3570c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 3580c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 3590c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 3600c0d06caSMauro Carvalho Chehab if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 3610c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 3620c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 3630c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 3640c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 3650c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 3660c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 3670c0d06caSMauro Carvalho Chehab &afe_power_status); 3680c0d06caSMauro Carvalho Chehab if (status < 0) 3690c0d06caSMauro Carvalho Chehab break; 3700c0d06caSMauro Carvalho Chehab } 3710c0d06caSMauro Carvalho Chehab 3720c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 3730c0d06caSMauro Carvalho Chehab 0x00); 3740c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 3750c0d06caSMauro Carvalho Chehab 0x00); 3760c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 3770c0d06caSMauro Carvalho Chehab 0x00); 3780c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_DIGITAL) { 3790c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 3800c0d06caSMauro Carvalho Chehab 0x70); 3810c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 3820c0d06caSMauro Carvalho Chehab 0x70); 3830c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 3840c0d06caSMauro Carvalho Chehab 0x70); 3850c0d06caSMauro Carvalho Chehab 3860c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 3870c0d06caSMauro Carvalho Chehab &afe_power_status); 3880c0d06caSMauro Carvalho Chehab afe_power_status |= FLD_PWRDN_PD_BANDGAP | 3890c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_BIAS | 3900c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_TUNECK; 3910c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, SUP_BLK_PWRDN, 3920c0d06caSMauro Carvalho Chehab afe_power_status); 3930c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 3940c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 3950c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 3960c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 3970c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 3980c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 3990c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4000c0d06caSMauro Carvalho Chehab &afe_power_status); 4010c0d06caSMauro Carvalho Chehab if (status < 0) 4020c0d06caSMauro Carvalho Chehab break; 4030c0d06caSMauro Carvalho Chehab } 4040c0d06caSMauro Carvalho Chehab 4050c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4060c0d06caSMauro Carvalho Chehab 0x00); 4070c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4080c0d06caSMauro Carvalho Chehab 0x00); 4090c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4100c0d06caSMauro Carvalho Chehab 0x00); 4110c0d06caSMauro Carvalho Chehab } else { 4120c0d06caSMauro Carvalho Chehab cx231xx_info("Invalid AV mode input\n"); 4130c0d06caSMauro Carvalho Chehab status = -1; 4140c0d06caSMauro Carvalho Chehab } 4150c0d06caSMauro Carvalho Chehab break; 4160c0d06caSMauro Carvalho Chehab default: 4170c0d06caSMauro Carvalho Chehab if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 4180c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 4190c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 4200c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 4210c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 4220c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 4230c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4240c0d06caSMauro Carvalho Chehab &afe_power_status); 4250c0d06caSMauro Carvalho Chehab if (status < 0) 4260c0d06caSMauro Carvalho Chehab break; 4270c0d06caSMauro Carvalho Chehab } 4280c0d06caSMauro Carvalho Chehab 4290c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4300c0d06caSMauro Carvalho Chehab 0x40); 4310c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4320c0d06caSMauro Carvalho Chehab 0x40); 4330c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4340c0d06caSMauro Carvalho Chehab 0x00); 4350c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_DIGITAL) { 4360c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4370c0d06caSMauro Carvalho Chehab 0x70); 4380c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4390c0d06caSMauro Carvalho Chehab 0x70); 4400c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4410c0d06caSMauro Carvalho Chehab 0x70); 4420c0d06caSMauro Carvalho Chehab 4430c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4440c0d06caSMauro Carvalho Chehab &afe_power_status); 4450c0d06caSMauro Carvalho Chehab afe_power_status |= FLD_PWRDN_PD_BANDGAP | 4460c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_BIAS | 4470c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_TUNECK; 4480c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, SUP_BLK_PWRDN, 4490c0d06caSMauro Carvalho Chehab afe_power_status); 4500c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 4510c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 4520c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) { 4530c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 4540c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS | 4550c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL); 4560c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN, 4570c0d06caSMauro Carvalho Chehab &afe_power_status); 4580c0d06caSMauro Carvalho Chehab if (status < 0) 4590c0d06caSMauro Carvalho Chehab break; 4600c0d06caSMauro Carvalho Chehab } 4610c0d06caSMauro Carvalho Chehab 4620c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 4630c0d06caSMauro Carvalho Chehab 0x00); 4640c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 4650c0d06caSMauro Carvalho Chehab 0x00); 4660c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 4670c0d06caSMauro Carvalho Chehab 0x40); 4680c0d06caSMauro Carvalho Chehab } else { 4690c0d06caSMauro Carvalho Chehab cx231xx_info("Invalid AV mode input\n"); 4700c0d06caSMauro Carvalho Chehab status = -1; 4710c0d06caSMauro Carvalho Chehab } 4720c0d06caSMauro Carvalho Chehab } /* switch */ 4730c0d06caSMauro Carvalho Chehab 4740c0d06caSMauro Carvalho Chehab return status; 4750c0d06caSMauro Carvalho Chehab } 4760c0d06caSMauro Carvalho Chehab 4770c0d06caSMauro Carvalho Chehab int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 4780c0d06caSMauro Carvalho Chehab { 4790c0d06caSMauro Carvalho Chehab u8 input_mode = 0; 4800c0d06caSMauro Carvalho Chehab u8 ntf_mode = 0; 4810c0d06caSMauro Carvalho Chehab int status = 0; 4820c0d06caSMauro Carvalho Chehab 4830c0d06caSMauro Carvalho Chehab dev->video_input = video_input; 4840c0d06caSMauro Carvalho Chehab 4850c0d06caSMauro Carvalho Chehab if (video_input == CX231XX_VMUX_TELEVISION) { 4860c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 4870c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 4880c0d06caSMauro Carvalho Chehab &ntf_mode); 4890c0d06caSMauro Carvalho Chehab } else { 4900c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 4910c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 4920c0d06caSMauro Carvalho Chehab &ntf_mode); 4930c0d06caSMauro Carvalho Chehab } 4940c0d06caSMauro Carvalho Chehab 4950c0d06caSMauro Carvalho Chehab input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 4960c0d06caSMauro Carvalho Chehab 4970c0d06caSMauro Carvalho Chehab switch (input_mode) { 4980c0d06caSMauro Carvalho Chehab case SINGLE_ENDED: 4990c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x23C; 5000c0d06caSMauro Carvalho Chehab break; 5010c0d06caSMauro Carvalho Chehab case LOW_IF: 5020c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x24C; 5030c0d06caSMauro Carvalho Chehab break; 5040c0d06caSMauro Carvalho Chehab case EU_IF: 5050c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x258; 5060c0d06caSMauro Carvalho Chehab break; 5070c0d06caSMauro Carvalho Chehab case US_IF: 5080c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x260; 5090c0d06caSMauro Carvalho Chehab break; 5100c0d06caSMauro Carvalho Chehab default: 5110c0d06caSMauro Carvalho Chehab break; 5120c0d06caSMauro Carvalho Chehab } 5130c0d06caSMauro Carvalho Chehab 5140c0d06caSMauro Carvalho Chehab status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 5150c0d06caSMauro Carvalho Chehab 5160c0d06caSMauro Carvalho Chehab return status; 5170c0d06caSMauro Carvalho Chehab } 5180c0d06caSMauro Carvalho Chehab 5190c0d06caSMauro Carvalho Chehab /****************************************************************************** 5200c0d06caSMauro Carvalho Chehab * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 5210c0d06caSMauro Carvalho Chehab ******************************************************************************/ 5220c0d06caSMauro Carvalho Chehab static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 5230c0d06caSMauro Carvalho Chehab { 5240c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5250c0d06caSMauro Carvalho Chehab saddr, 2, data, 1); 5260c0d06caSMauro Carvalho Chehab } 5270c0d06caSMauro Carvalho Chehab 5280c0d06caSMauro Carvalho Chehab static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 5290c0d06caSMauro Carvalho Chehab { 5300c0d06caSMauro Carvalho Chehab int status; 5310c0d06caSMauro Carvalho Chehab u32 temp = 0; 5320c0d06caSMauro Carvalho Chehab 5330c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5340c0d06caSMauro Carvalho Chehab saddr, 2, &temp, 1); 5350c0d06caSMauro Carvalho Chehab *data = (u8) temp; 5360c0d06caSMauro Carvalho Chehab return status; 5370c0d06caSMauro Carvalho Chehab } 5380c0d06caSMauro Carvalho Chehab 5390c0d06caSMauro Carvalho Chehab static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 5400c0d06caSMauro Carvalho Chehab { 5410c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5420c0d06caSMauro Carvalho Chehab saddr, 2, data, 4); 5430c0d06caSMauro Carvalho Chehab } 5440c0d06caSMauro Carvalho Chehab 5450c0d06caSMauro Carvalho Chehab static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 5460c0d06caSMauro Carvalho Chehab { 5470c0d06caSMauro Carvalho Chehab return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 5480c0d06caSMauro Carvalho Chehab saddr, 2, data, 4); 5490c0d06caSMauro Carvalho Chehab } 5500c0d06caSMauro Carvalho Chehab int cx231xx_check_fw(struct cx231xx *dev) 5510c0d06caSMauro Carvalho Chehab { 5520c0d06caSMauro Carvalho Chehab u8 temp = 0; 5530c0d06caSMauro Carvalho Chehab int status = 0; 5540c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 5550c0d06caSMauro Carvalho Chehab if (status < 0) 5560c0d06caSMauro Carvalho Chehab return status; 5570c0d06caSMauro Carvalho Chehab else 5580c0d06caSMauro Carvalho Chehab return temp; 5590c0d06caSMauro Carvalho Chehab 5600c0d06caSMauro Carvalho Chehab } 5610c0d06caSMauro Carvalho Chehab 5620c0d06caSMauro Carvalho Chehab int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 5630c0d06caSMauro Carvalho Chehab { 5640c0d06caSMauro Carvalho Chehab int status = 0; 5650c0d06caSMauro Carvalho Chehab 5660c0d06caSMauro Carvalho Chehab switch (INPUT(input)->type) { 5670c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_COMPOSITE1: 5680c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_SVIDEO: 5690c0d06caSMauro Carvalho Chehab if ((dev->current_pcb_config.type == USB_BUS_POWER) && 5700c0d06caSMauro Carvalho Chehab (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 5710c0d06caSMauro Carvalho Chehab /* External AV */ 5720c0d06caSMauro Carvalho Chehab status = cx231xx_set_power_mode(dev, 5730c0d06caSMauro Carvalho Chehab POLARIS_AVMODE_ENXTERNAL_AV); 5740c0d06caSMauro Carvalho Chehab if (status < 0) { 5750c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: set_power_mode : Failed to" 5760c0d06caSMauro Carvalho Chehab " set Power - errCode [%d]!\n", 5770c0d06caSMauro Carvalho Chehab __func__, status); 5780c0d06caSMauro Carvalho Chehab return status; 5790c0d06caSMauro Carvalho Chehab } 5800c0d06caSMauro Carvalho Chehab } 5810c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev, 5820c0d06caSMauro Carvalho Chehab INPUT(input)->type, 5830c0d06caSMauro Carvalho Chehab INPUT(input)->vmux); 5840c0d06caSMauro Carvalho Chehab break; 5850c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_TELEVISION: 5860c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_CABLE: 5870c0d06caSMauro Carvalho Chehab if ((dev->current_pcb_config.type == USB_BUS_POWER) && 5880c0d06caSMauro Carvalho Chehab (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 5890c0d06caSMauro Carvalho Chehab /* Tuner */ 5900c0d06caSMauro Carvalho Chehab status = cx231xx_set_power_mode(dev, 5910c0d06caSMauro Carvalho Chehab POLARIS_AVMODE_ANALOGT_TV); 5920c0d06caSMauro Carvalho Chehab if (status < 0) { 5930c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: set_power_mode:Failed" 5940c0d06caSMauro Carvalho Chehab " to set Power - errCode [%d]!\n", 5950c0d06caSMauro Carvalho Chehab __func__, status); 5960c0d06caSMauro Carvalho Chehab return status; 5970c0d06caSMauro Carvalho Chehab } 5980c0d06caSMauro Carvalho Chehab } 5990c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) 6000c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev, 6010c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION, 6020c0d06caSMauro Carvalho Chehab INPUT(input)->vmux); 6030c0d06caSMauro Carvalho Chehab else 6040c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev, 6050c0d06caSMauro Carvalho Chehab CX231XX_VMUX_COMPOSITE1, 6060c0d06caSMauro Carvalho Chehab INPUT(input)->vmux); 6070c0d06caSMauro Carvalho Chehab 6080c0d06caSMauro Carvalho Chehab break; 6090c0d06caSMauro Carvalho Chehab default: 6100c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 6110c0d06caSMauro Carvalho Chehab __func__, INPUT(input)->type); 6120c0d06caSMauro Carvalho Chehab break; 6130c0d06caSMauro Carvalho Chehab } 6140c0d06caSMauro Carvalho Chehab 6150c0d06caSMauro Carvalho Chehab /* save the selection */ 6160c0d06caSMauro Carvalho Chehab dev->video_input = input; 6170c0d06caSMauro Carvalho Chehab 6180c0d06caSMauro Carvalho Chehab return status; 6190c0d06caSMauro Carvalho Chehab } 6200c0d06caSMauro Carvalho Chehab 6210c0d06caSMauro Carvalho Chehab int cx231xx_set_decoder_video_input(struct cx231xx *dev, 6220c0d06caSMauro Carvalho Chehab u8 pin_type, u8 input) 6230c0d06caSMauro Carvalho Chehab { 6240c0d06caSMauro Carvalho Chehab int status = 0; 6250c0d06caSMauro Carvalho Chehab u32 value = 0; 6260c0d06caSMauro Carvalho Chehab 6270c0d06caSMauro Carvalho Chehab if (pin_type != dev->video_input) { 6280c0d06caSMauro Carvalho Chehab status = cx231xx_afe_adjust_ref_count(dev, pin_type); 6290c0d06caSMauro Carvalho Chehab if (status < 0) { 6300c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: adjust_ref_count :Failed to set" 6310c0d06caSMauro Carvalho Chehab "AFE input mux - errCode [%d]!\n", 6320c0d06caSMauro Carvalho Chehab __func__, status); 6330c0d06caSMauro Carvalho Chehab return status; 6340c0d06caSMauro Carvalho Chehab } 6350c0d06caSMauro Carvalho Chehab } 6360c0d06caSMauro Carvalho Chehab 6370c0d06caSMauro Carvalho Chehab /* call afe block to set video inputs */ 6380c0d06caSMauro Carvalho Chehab status = cx231xx_afe_set_input_mux(dev, input); 6390c0d06caSMauro Carvalho Chehab if (status < 0) { 6400c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: set_input_mux :Failed to set" 6410c0d06caSMauro Carvalho Chehab " AFE input mux - errCode [%d]!\n", 6420c0d06caSMauro Carvalho Chehab __func__, status); 6430c0d06caSMauro Carvalho Chehab return status; 6440c0d06caSMauro Carvalho Chehab } 6450c0d06caSMauro Carvalho Chehab 6460c0d06caSMauro Carvalho Chehab switch (pin_type) { 6470c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_COMPOSITE1: 6480c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 6490c0d06caSMauro Carvalho Chehab value |= (0 << 13) | (1 << 4); 6500c0d06caSMauro Carvalho Chehab value &= ~(1 << 5); 6510c0d06caSMauro Carvalho Chehab 6520c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */ 6530c0d06caSMauro Carvalho Chehab value &= (~(0x1ff8000)); 6540c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 6550c0d06caSMauro Carvalho Chehab value |= 0x1000000; 6560c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 6570c0d06caSMauro Carvalho Chehab 6580c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value); 6590c0d06caSMauro Carvalho Chehab value |= (1 << 7); 6600c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value); 6610c0d06caSMauro Carvalho Chehab 6620c0d06caSMauro Carvalho Chehab /* Set output mode */ 6630c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 6640c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 6650c0d06caSMauro Carvalho Chehab OUT_CTRL1, 6660c0d06caSMauro Carvalho Chehab FLD_OUT_MODE, 6670c0d06caSMauro Carvalho Chehab dev->board.output_mode); 6680c0d06caSMauro Carvalho Chehab 6690c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */ 6700c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 6710c0d06caSMauro Carvalho Chehab if (status < 0) { 6720c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: cx231xx_dif set to By pass" 6730c0d06caSMauro Carvalho Chehab " mode- errCode [%d]!\n", 6740c0d06caSMauro Carvalho Chehab __func__, status); 6750c0d06caSMauro Carvalho Chehab return status; 6760c0d06caSMauro Carvalho Chehab } 6770c0d06caSMauro Carvalho Chehab 6780c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 6790c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 6800c0d06caSMauro Carvalho Chehab 6810c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */ 6820c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN; 6830c0d06caSMauro Carvalho Chehab 6840c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */ 6850c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN; 6860c0d06caSMauro Carvalho Chehab 6870c0d06caSMauro Carvalho Chehab /* Write it back */ 6880c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 6890c0d06caSMauro Carvalho Chehab 6900c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 6910c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 6920c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 6930c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 6940c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 6950c0d06caSMauro Carvalho Chehab 6960c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */ 6970c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 6980c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 6990c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE, 7000c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 7010c0d06caSMauro Carvalho Chehab break; 7020c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_SVIDEO: 7030c0d06caSMauro Carvalho Chehab /* Disable the use of DIF */ 7040c0d06caSMauro Carvalho Chehab 7050c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 7060c0d06caSMauro Carvalho Chehab 7070c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */ 7080c0d06caSMauro Carvalho Chehab value &= (~(0x1ff8000)); 7090c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 7100c0d06caSMauro Carvalho Chehab IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 7110c0d06caSMauro Carvalho Chehab value |= 0x1000010; 7120c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 7130c0d06caSMauro Carvalho Chehab 7140c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */ 7150c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 7160c0d06caSMauro Carvalho Chehab if (status < 0) { 7170c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: cx231xx_dif set to By pass" 7180c0d06caSMauro Carvalho Chehab " mode- errCode [%d]!\n", 7190c0d06caSMauro Carvalho Chehab __func__, status); 7200c0d06caSMauro Carvalho Chehab return status; 7210c0d06caSMauro Carvalho Chehab } 7220c0d06caSMauro Carvalho Chehab 7230c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 7240c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 7250c0d06caSMauro Carvalho Chehab 7260c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */ 7270c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN; 7280c0d06caSMauro Carvalho Chehab 7290c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */ 7300c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN; 7310c0d06caSMauro Carvalho Chehab 7320c0d06caSMauro Carvalho Chehab /* Write it back */ 7330c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 7340c0d06caSMauro Carvalho Chehab 7350c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 7360c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 7370c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 7380c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 7390c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 7400c0d06caSMauro Carvalho Chehab 7410c0d06caSMauro Carvalho Chehab /* Set YC input mode */ 7420c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 7430c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 7440c0d06caSMauro Carvalho Chehab MODE_CTRL, 7450c0d06caSMauro Carvalho Chehab FLD_INPUT_MODE, 7460c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 7470c0d06caSMauro Carvalho Chehab 7480c0d06caSMauro Carvalho Chehab /* Chroma to ADC2 */ 7490c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 7500c0d06caSMauro Carvalho Chehab value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 7510c0d06caSMauro Carvalho Chehab 7520c0d06caSMauro Carvalho Chehab /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 7530c0d06caSMauro Carvalho Chehab This sets them to use video 7540c0d06caSMauro Carvalho Chehab rather than audio. Only one of the two will be in use. */ 7550c0d06caSMauro Carvalho Chehab value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 7560c0d06caSMauro Carvalho Chehab 7570c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 7580c0d06caSMauro Carvalho Chehab 7590c0d06caSMauro Carvalho Chehab status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 7600c0d06caSMauro Carvalho Chehab break; 7610c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_TELEVISION: 7620c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_CABLE: 7630c0d06caSMauro Carvalho Chehab default: 7640c0d06caSMauro Carvalho Chehab /* TODO: Test if this is also needed for xc2028/xc3028 */ 7650c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type == TUNER_XC5000) { 7660c0d06caSMauro Carvalho Chehab /* Disable the use of DIF */ 7670c0d06caSMauro Carvalho Chehab 7680c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 7690c0d06caSMauro Carvalho Chehab value |= (0 << 13) | (1 << 4); 7700c0d06caSMauro Carvalho Chehab value &= ~(1 << 5); 7710c0d06caSMauro Carvalho Chehab 7720c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */ 7730c0d06caSMauro Carvalho Chehab value &= (~(0x1FF8000)); 7740c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 7750c0d06caSMauro Carvalho Chehab value |= 0x1000000; 7760c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 7770c0d06caSMauro Carvalho Chehab 7780c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value); 7790c0d06caSMauro Carvalho Chehab value |= (1 << 7); 7800c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value); 7810c0d06caSMauro Carvalho Chehab 7820c0d06caSMauro Carvalho Chehab /* Set output mode */ 7830c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 7840c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 7850c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_OUT_MODE, 7860c0d06caSMauro Carvalho Chehab dev->board.output_mode); 7870c0d06caSMauro Carvalho Chehab 7880c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */ 7890c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, 7900c0d06caSMauro Carvalho Chehab DIF_USE_BASEBAND); 7910c0d06caSMauro Carvalho Chehab if (status < 0) { 7920c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: cx231xx_dif set to By pass" 7930c0d06caSMauro Carvalho Chehab " mode- errCode [%d]!\n", 7940c0d06caSMauro Carvalho Chehab __func__, status); 7950c0d06caSMauro Carvalho Chehab return status; 7960c0d06caSMauro Carvalho Chehab } 7970c0d06caSMauro Carvalho Chehab 7980c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 7990c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 8000c0d06caSMauro Carvalho Chehab 8010c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */ 8020c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN; 8030c0d06caSMauro Carvalho Chehab 8040c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */ 8050c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN; 8060c0d06caSMauro Carvalho Chehab 8070c0d06caSMauro Carvalho Chehab /* Write it back */ 8080c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 8090c0d06caSMauro Carvalho Chehab 8100c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 8110c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8120c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8130c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 8140c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 8150c0d06caSMauro Carvalho Chehab 8160c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */ 8170c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8180c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8190c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE, 8200c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, 8210c0d06caSMauro Carvalho Chehab INPUT_MODE_CVBS_0)); 8220c0d06caSMauro Carvalho Chehab } else { 8230c0d06caSMauro Carvalho Chehab /* Enable the DIF for the tuner */ 8240c0d06caSMauro Carvalho Chehab 8250c0d06caSMauro Carvalho Chehab /* Reinitialize the DIF */ 8260c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, dev->norm); 8270c0d06caSMauro Carvalho Chehab if (status < 0) { 8280c0d06caSMauro Carvalho Chehab cx231xx_errdev("%s: cx231xx_dif set to By pass" 8290c0d06caSMauro Carvalho Chehab " mode- errCode [%d]!\n", 8300c0d06caSMauro Carvalho Chehab __func__, status); 8310c0d06caSMauro Carvalho Chehab return status; 8320c0d06caSMauro Carvalho Chehab } 8330c0d06caSMauro Carvalho Chehab 8340c0d06caSMauro Carvalho Chehab /* Make sure bypass is cleared */ 8350c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 8360c0d06caSMauro Carvalho Chehab 8370c0d06caSMauro Carvalho Chehab /* Clear the bypass bit */ 8380c0d06caSMauro Carvalho Chehab value &= ~FLD_DIF_DIF_BYPASS; 8390c0d06caSMauro Carvalho Chehab 8400c0d06caSMauro Carvalho Chehab /* Enable the use of the DIF block */ 8410c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 8420c0d06caSMauro Carvalho Chehab 8430c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */ 8440c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value); 8450c0d06caSMauro Carvalho Chehab 8460c0d06caSMauro Carvalho Chehab /* Disable the VBI_GATE_EN */ 8470c0d06caSMauro Carvalho Chehab value &= ~FLD_VBI_GATE_EN; 8480c0d06caSMauro Carvalho Chehab 8490c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable, AGC, and 8500c0d06caSMauro Carvalho Chehab set the skip count to 2 */ 8510c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 8520c0d06caSMauro Carvalho Chehab 8530c0d06caSMauro Carvalho Chehab /* Write it back */ 8540c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 8550c0d06caSMauro Carvalho Chehab 8560c0d06caSMauro Carvalho Chehab /* Wait until AGC locks up */ 8570c0d06caSMauro Carvalho Chehab msleep(1); 8580c0d06caSMauro Carvalho Chehab 8590c0d06caSMauro Carvalho Chehab /* Disable the auto-VGA enable AGC */ 8600c0d06caSMauro Carvalho Chehab value &= ~(FLD_VGA_AUTO_EN); 8610c0d06caSMauro Carvalho Chehab 8620c0d06caSMauro Carvalho Chehab /* Write it back */ 8630c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value); 8640c0d06caSMauro Carvalho Chehab 8650c0d06caSMauro Carvalho Chehab /* Enable Polaris B0 AGC output */ 8660c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, &value); 8670c0d06caSMauro Carvalho Chehab value |= (FLD_OEF_AGC_RF) | 8680c0d06caSMauro Carvalho Chehab (FLD_OEF_AGC_IFVGA) | 8690c0d06caSMauro Carvalho Chehab (FLD_OEF_AGC_IF); 8700c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, value); 8710c0d06caSMauro Carvalho Chehab 8720c0d06caSMauro Carvalho Chehab /* Set output mode */ 8730c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8740c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8750c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_OUT_MODE, 8760c0d06caSMauro Carvalho Chehab dev->board.output_mode); 8770c0d06caSMauro Carvalho Chehab 8780c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */ 8790c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8800c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8810c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS, 8820c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1)); 8830c0d06caSMauro Carvalho Chehab 8840c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */ 8850c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 8860c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 8870c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE, 8880c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, 8890c0d06caSMauro Carvalho Chehab INPUT_MODE_CVBS_0)); 8900c0d06caSMauro Carvalho Chehab 8910c0d06caSMauro Carvalho Chehab /* Set some bits in AFE_CTRL so that channel 2 or 3 8920c0d06caSMauro Carvalho Chehab * is ready to receive audio */ 8930c0d06caSMauro Carvalho Chehab /* Clear clamp for channels 2 and 3 (bit 16-17) */ 8940c0d06caSMauro Carvalho Chehab /* Clear droop comp (bit 19-20) */ 8950c0d06caSMauro Carvalho Chehab /* Set VGA_SEL (for audio control) (bit 7-8) */ 8960c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value); 8970c0d06caSMauro Carvalho Chehab 8980c0d06caSMauro Carvalho Chehab /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 8990c0d06caSMauro Carvalho Chehab value &= (~(FLD_FUNC_MODE)); 9000c0d06caSMauro Carvalho Chehab value |= 0x800000; 9010c0d06caSMauro Carvalho Chehab 9020c0d06caSMauro Carvalho Chehab value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 9030c0d06caSMauro Carvalho Chehab 9040c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value); 9050c0d06caSMauro Carvalho Chehab 9060c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) { 9070c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, 9080c0d06caSMauro Carvalho Chehab &value); 9090c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, 9100c0d06caSMauro Carvalho Chehab (value & 0xFFFFFFEF)); 9110c0d06caSMauro Carvalho Chehab } 9120c0d06caSMauro Carvalho Chehab 9130c0d06caSMauro Carvalho Chehab break; 9140c0d06caSMauro Carvalho Chehab 9150c0d06caSMauro Carvalho Chehab } 9160c0d06caSMauro Carvalho Chehab break; 9170c0d06caSMauro Carvalho Chehab } 9180c0d06caSMauro Carvalho Chehab 9190c0d06caSMauro Carvalho Chehab /* Set raw VBI mode */ 9200c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9210c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9220c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_VBIHACTRAW_EN, 9230c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 9240c0d06caSMauro Carvalho Chehab 9250c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value); 9260c0d06caSMauro Carvalho Chehab if (value & 0x02) { 9270c0d06caSMauro Carvalho Chehab value |= (1 << 19); 9280c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value); 9290c0d06caSMauro Carvalho Chehab } 9300c0d06caSMauro Carvalho Chehab 9310c0d06caSMauro Carvalho Chehab return status; 9320c0d06caSMauro Carvalho Chehab } 9330c0d06caSMauro Carvalho Chehab 9340c0d06caSMauro Carvalho Chehab void cx231xx_enable656(struct cx231xx *dev) 9350c0d06caSMauro Carvalho Chehab { 9360c0d06caSMauro Carvalho Chehab u8 temp = 0; 9370c0d06caSMauro Carvalho Chehab /*enable TS1 data[0:7] as output to export 656*/ 9380c0d06caSMauro Carvalho Chehab 9390c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 9400c0d06caSMauro Carvalho Chehab 9410c0d06caSMauro Carvalho Chehab /*enable TS1 clock as output to export 656*/ 9420c0d06caSMauro Carvalho Chehab 9430c0d06caSMauro Carvalho Chehab vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 9440c0d06caSMauro Carvalho Chehab temp = temp|0x04; 9450c0d06caSMauro Carvalho Chehab 9460c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 9470c0d06caSMauro Carvalho Chehab } 9480c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_enable656); 9490c0d06caSMauro Carvalho Chehab 9500c0d06caSMauro Carvalho Chehab void cx231xx_disable656(struct cx231xx *dev) 9510c0d06caSMauro Carvalho Chehab { 9520c0d06caSMauro Carvalho Chehab u8 temp = 0; 9530c0d06caSMauro Carvalho Chehab 9540c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 9550c0d06caSMauro Carvalho Chehab 9560c0d06caSMauro Carvalho Chehab vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 9570c0d06caSMauro Carvalho Chehab temp = temp&0xFB; 9580c0d06caSMauro Carvalho Chehab 9590c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 9600c0d06caSMauro Carvalho Chehab } 9610c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_disable656); 9620c0d06caSMauro Carvalho Chehab 9630c0d06caSMauro Carvalho Chehab /* 9640c0d06caSMauro Carvalho Chehab * Handle any video-mode specific overrides that are different 9650c0d06caSMauro Carvalho Chehab * on a per video standards basis after touching the MODE_CTRL 9660c0d06caSMauro Carvalho Chehab * register which resets many values for autodetect 9670c0d06caSMauro Carvalho Chehab */ 9680c0d06caSMauro Carvalho Chehab int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 9690c0d06caSMauro Carvalho Chehab { 9700c0d06caSMauro Carvalho Chehab int status = 0; 9710c0d06caSMauro Carvalho Chehab 9720c0d06caSMauro Carvalho Chehab cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", 9730c0d06caSMauro Carvalho Chehab (unsigned int)dev->norm); 9740c0d06caSMauro Carvalho Chehab 9750c0d06caSMauro Carvalho Chehab /* Change the DFE_CTRL3 bp_percent to fix flagging */ 9760c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 9770c0d06caSMauro Carvalho Chehab 9780c0d06caSMauro Carvalho Chehab if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 9790c0d06caSMauro Carvalho Chehab cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 9800c0d06caSMauro Carvalho Chehab 9810c0d06caSMauro Carvalho Chehab /* Move the close caption lines out of active video, 9820c0d06caSMauro Carvalho Chehab adjust the active video start point */ 9830c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9840c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9850c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 9860c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x18); 9870c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9880c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9890c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 9900c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT, 9910c0d06caSMauro Carvalho Chehab 0x1E7000); 9920c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9930c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 9940c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 9950c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT, 9960c0d06caSMauro Carvalho Chehab 0x1C000000); 9970c0d06caSMauro Carvalho Chehab 9980c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 9990c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10000c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL, 10010c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT, 10020c0d06caSMauro Carvalho Chehab cx231xx_set_field 10030c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x79)); 10040c0d06caSMauro Carvalho Chehab 10050c0d06caSMauro Carvalho Chehab } else if (dev->norm & V4L2_STD_SECAM) { 10060c0d06caSMauro Carvalho Chehab cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 10070c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10080c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10090c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10100c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x20); 10110c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10120c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10130c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10140c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT, 10150c0d06caSMauro Carvalho Chehab cx231xx_set_field 10160c0d06caSMauro Carvalho Chehab (FLD_VACTIVE_CNT, 10170c0d06caSMauro Carvalho Chehab 0x244)); 10180c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10190c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10200c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10210c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT, 10220c0d06caSMauro Carvalho Chehab cx231xx_set_field 10230c0d06caSMauro Carvalho Chehab (FLD_V656BLANK_CNT, 10240c0d06caSMauro Carvalho Chehab 0x24)); 10250c0d06caSMauro Carvalho Chehab /* Adjust the active video horizontal start point */ 10260c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10270c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10280c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL, 10290c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT, 10300c0d06caSMauro Carvalho Chehab cx231xx_set_field 10310c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x85)); 10320c0d06caSMauro Carvalho Chehab } else { 10330c0d06caSMauro Carvalho Chehab cx231xx_info("do_mode_ctrl_overrides PAL\n"); 10340c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10350c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10360c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10370c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x20); 10380c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10390c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10400c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10410c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT, 10420c0d06caSMauro Carvalho Chehab cx231xx_set_field 10430c0d06caSMauro Carvalho Chehab (FLD_VACTIVE_CNT, 10440c0d06caSMauro Carvalho Chehab 0x244)); 10450c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10460c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10470c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL, 10480c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT, 10490c0d06caSMauro Carvalho Chehab cx231xx_set_field 10500c0d06caSMauro Carvalho Chehab (FLD_V656BLANK_CNT, 10510c0d06caSMauro Carvalho Chehab 0x24)); 10520c0d06caSMauro Carvalho Chehab /* Adjust the active video horizontal start point */ 10530c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 10540c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 10550c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL, 10560c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT, 10570c0d06caSMauro Carvalho Chehab cx231xx_set_field 10580c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x85)); 10590c0d06caSMauro Carvalho Chehab 10600c0d06caSMauro Carvalho Chehab } 10610c0d06caSMauro Carvalho Chehab 10620c0d06caSMauro Carvalho Chehab return status; 10630c0d06caSMauro Carvalho Chehab } 10640c0d06caSMauro Carvalho Chehab 10650c0d06caSMauro Carvalho Chehab int cx231xx_unmute_audio(struct cx231xx *dev) 10660c0d06caSMauro Carvalho Chehab { 10670c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 10680c0d06caSMauro Carvalho Chehab } 10690c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 10700c0d06caSMauro Carvalho Chehab 10710c0d06caSMauro Carvalho Chehab int stopAudioFirmware(struct cx231xx *dev) 10720c0d06caSMauro Carvalho Chehab { 10730c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 10740c0d06caSMauro Carvalho Chehab } 10750c0d06caSMauro Carvalho Chehab 10760c0d06caSMauro Carvalho Chehab int restartAudioFirmware(struct cx231xx *dev) 10770c0d06caSMauro Carvalho Chehab { 10780c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 10790c0d06caSMauro Carvalho Chehab } 10800c0d06caSMauro Carvalho Chehab 10810c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 10820c0d06caSMauro Carvalho Chehab { 10830c0d06caSMauro Carvalho Chehab int status = 0; 10840c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 10850c0d06caSMauro Carvalho Chehab 10860c0d06caSMauro Carvalho Chehab switch (INPUT(input)->amux) { 10870c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_VIDEO: 10880c0d06caSMauro Carvalho Chehab ainput = AUDIO_INPUT_TUNER_TV; 10890c0d06caSMauro Carvalho Chehab break; 10900c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_LINE_IN: 10910c0d06caSMauro Carvalho Chehab status = cx231xx_i2s_blk_set_audio_input(dev, input); 10920c0d06caSMauro Carvalho Chehab ainput = AUDIO_INPUT_LINE; 10930c0d06caSMauro Carvalho Chehab break; 10940c0d06caSMauro Carvalho Chehab default: 10950c0d06caSMauro Carvalho Chehab break; 10960c0d06caSMauro Carvalho Chehab } 10970c0d06caSMauro Carvalho Chehab 10980c0d06caSMauro Carvalho Chehab status = cx231xx_set_audio_decoder_input(dev, ainput); 10990c0d06caSMauro Carvalho Chehab 11000c0d06caSMauro Carvalho Chehab return status; 11010c0d06caSMauro Carvalho Chehab } 11020c0d06caSMauro Carvalho Chehab 11030c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 11040c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT audio_input) 11050c0d06caSMauro Carvalho Chehab { 11060c0d06caSMauro Carvalho Chehab u32 dwval; 11070c0d06caSMauro Carvalho Chehab int status; 11080c0d06caSMauro Carvalho Chehab u8 gen_ctrl; 11090c0d06caSMauro Carvalho Chehab u32 value = 0; 11100c0d06caSMauro Carvalho Chehab 11110c0d06caSMauro Carvalho Chehab /* Put it in soft reset */ 11120c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 11130c0d06caSMauro Carvalho Chehab gen_ctrl |= 1; 11140c0d06caSMauro Carvalho Chehab status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 11150c0d06caSMauro Carvalho Chehab 11160c0d06caSMauro Carvalho Chehab switch (audio_input) { 11170c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_LINE: 11180c0d06caSMauro Carvalho Chehab /* setup AUD_IO control from Merlin paralle output */ 11190c0d06caSMauro Carvalho Chehab value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 11200c0d06caSMauro Carvalho Chehab AUD_CHAN_SRC_PARALLEL); 11210c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 11220c0d06caSMauro Carvalho Chehab 11230c0d06caSMauro Carvalho Chehab /* setup input to Merlin, SRC2 connect to AC97 11240c0d06caSMauro Carvalho Chehab bypass upsample-by-2, slave mode, sony mode, left justify 11250c0d06caSMauro Carvalho Chehab adr 091c, dat 01000000 */ 11260c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AC97_CTL, &dwval); 11270c0d06caSMauro Carvalho Chehab 11280c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AC97_CTL, 11290c0d06caSMauro Carvalho Chehab (dwval | FLD_AC97_UP2X_BYPASS)); 11300c0d06caSMauro Carvalho Chehab 11310c0d06caSMauro Carvalho Chehab /* select the parallel1 and SRC3 */ 11320c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, BAND_OUT_SEL, 11330c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 11340c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 11350c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 11360c0d06caSMauro Carvalho Chehab 11370c0d06caSMauro Carvalho Chehab /* unmute all, AC97 in, independence mode 11380c0d06caSMauro Carvalho Chehab adr 08d0, data 0x00063073 */ 11390c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 11400c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 11410c0d06caSMauro Carvalho Chehab 11420c0d06caSMauro Carvalho Chehab /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 11430c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 11440c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_VOL_CTL, 11450c0d06caSMauro Carvalho Chehab (dwval | FLD_PATH1_AVC_THRESHOLD)); 11460c0d06caSMauro Carvalho Chehab 11470c0d06caSMauro Carvalho Chehab /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 11480c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 11490c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_SC_CTL, 11500c0d06caSMauro Carvalho Chehab (dwval | FLD_PATH1_SC_THRESHOLD)); 11510c0d06caSMauro Carvalho Chehab break; 11520c0d06caSMauro Carvalho Chehab 11530c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_TUNER_TV: 11540c0d06caSMauro Carvalho Chehab default: 11550c0d06caSMauro Carvalho Chehab status = stopAudioFirmware(dev); 11560c0d06caSMauro Carvalho Chehab /* Setup SRC sources and clocks */ 11570c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, BAND_OUT_SEL, 11580c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 11590c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 11600c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 11610c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 11620c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 11630c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 11640c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 11650c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 11660c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 11670c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 11680c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 11690c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 11700c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 11710c0d06caSMauro Carvalho Chehab 11720c0d06caSMauro Carvalho Chehab /* Setup the AUD_IO control */ 11730c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AUD_IO_CTRL, 11740c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 11750c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 11760c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 11770c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 11780c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 11790c0d06caSMauro Carvalho Chehab 11800c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 11810c0d06caSMauro Carvalho Chehab 11820c0d06caSMauro Carvalho Chehab /* setAudioStandard(_audio_standard); */ 11830c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 11840c0d06caSMauro Carvalho Chehab 11850c0d06caSMauro Carvalho Chehab status = restartAudioFirmware(dev); 11860c0d06caSMauro Carvalho Chehab 11870c0d06caSMauro Carvalho Chehab switch (dev->board.tuner_type) { 11880c0d06caSMauro Carvalho Chehab case TUNER_XC5000: 11890c0d06caSMauro Carvalho Chehab /* SIF passthrough at 28.6363 MHz sample rate */ 11900c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 11910c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 11920c0d06caSMauro Carvalho Chehab CHIP_CTRL, 11930c0d06caSMauro Carvalho Chehab FLD_SIF_EN, 11940c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SIF_EN, 1)); 11950c0d06caSMauro Carvalho Chehab break; 11960c0d06caSMauro Carvalho Chehab case TUNER_NXP_TDA18271: 11970c0d06caSMauro Carvalho Chehab /* Normal mode: SIF passthrough at 14.32 MHz */ 11980c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev, 11990c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 12000c0d06caSMauro Carvalho Chehab CHIP_CTRL, 12010c0d06caSMauro Carvalho Chehab FLD_SIF_EN, 12020c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SIF_EN, 0)); 12030c0d06caSMauro Carvalho Chehab break; 12040c0d06caSMauro Carvalho Chehab default: 12050c0d06caSMauro Carvalho Chehab /* This is just a casual suggestion to people adding 12060c0d06caSMauro Carvalho Chehab new boards in case they use a tuner type we don't 12070c0d06caSMauro Carvalho Chehab currently know about */ 12080c0d06caSMauro Carvalho Chehab printk(KERN_INFO "Unknown tuner type configuring SIF"); 12090c0d06caSMauro Carvalho Chehab break; 12100c0d06caSMauro Carvalho Chehab } 12110c0d06caSMauro Carvalho Chehab break; 12120c0d06caSMauro Carvalho Chehab 12130c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_TUNER_FM: 12140c0d06caSMauro Carvalho Chehab /* use SIF for FM radio 12150c0d06caSMauro Carvalho Chehab setupFM(); 12160c0d06caSMauro Carvalho Chehab setAudioStandard(_audio_standard); 12170c0d06caSMauro Carvalho Chehab */ 12180c0d06caSMauro Carvalho Chehab break; 12190c0d06caSMauro Carvalho Chehab 12200c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_MUTE: 12210c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 12220c0d06caSMauro Carvalho Chehab break; 12230c0d06caSMauro Carvalho Chehab } 12240c0d06caSMauro Carvalho Chehab 12250c0d06caSMauro Carvalho Chehab /* Take it out of soft reset */ 12260c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 12270c0d06caSMauro Carvalho Chehab gen_ctrl &= ~1; 12280c0d06caSMauro Carvalho Chehab status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 12290c0d06caSMauro Carvalho Chehab 12300c0d06caSMauro Carvalho Chehab return status; 12310c0d06caSMauro Carvalho Chehab } 12320c0d06caSMauro Carvalho Chehab 12330c0d06caSMauro Carvalho Chehab /****************************************************************************** 12340c0d06caSMauro Carvalho Chehab * C H I P Specific C O N T R O L functions * 12350c0d06caSMauro Carvalho Chehab ******************************************************************************/ 12360c0d06caSMauro Carvalho Chehab int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 12370c0d06caSMauro Carvalho Chehab { 12380c0d06caSMauro Carvalho Chehab u32 value; 12390c0d06caSMauro Carvalho Chehab int status = 0; 12400c0d06caSMauro Carvalho Chehab 12410c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, &value); 12420c0d06caSMauro Carvalho Chehab value |= (~dev->board.ctl_pin_status_mask); 12430c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, value); 12440c0d06caSMauro Carvalho Chehab 12450c0d06caSMauro Carvalho Chehab return status; 12460c0d06caSMauro Carvalho Chehab } 12470c0d06caSMauro Carvalho Chehab 12480c0d06caSMauro Carvalho Chehab int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 12490c0d06caSMauro Carvalho Chehab u8 analog_or_digital) 12500c0d06caSMauro Carvalho Chehab { 12510c0d06caSMauro Carvalho Chehab int status = 0; 12520c0d06caSMauro Carvalho Chehab 12530c0d06caSMauro Carvalho Chehab /* first set the direction to output */ 12540c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_direction(dev, 12550c0d06caSMauro Carvalho Chehab dev->board. 12560c0d06caSMauro Carvalho Chehab agc_analog_digital_select_gpio, 1); 12570c0d06caSMauro Carvalho Chehab 12580c0d06caSMauro Carvalho Chehab /* 0 - demod ; 1 - Analog mode */ 12590c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_value(dev, 12600c0d06caSMauro Carvalho Chehab dev->board.agc_analog_digital_select_gpio, 12610c0d06caSMauro Carvalho Chehab analog_or_digital); 12620c0d06caSMauro Carvalho Chehab 12630c0d06caSMauro Carvalho Chehab return status; 12640c0d06caSMauro Carvalho Chehab } 12650c0d06caSMauro Carvalho Chehab 12660c0d06caSMauro Carvalho Chehab int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 12670c0d06caSMauro Carvalho Chehab { 12680c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 12690c0d06caSMauro Carvalho Chehab int status = 0; 12700c0d06caSMauro Carvalho Chehab bool current_is_port_3; 12710c0d06caSMauro Carvalho Chehab 12720c0d06caSMauro Carvalho Chehab if (dev->board.dont_use_port_3) 12730c0d06caSMauro Carvalho Chehab is_port_3 = false; 12740c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 12750c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 12760c0d06caSMauro Carvalho Chehab if (status < 0) 12770c0d06caSMauro Carvalho Chehab return status; 12780c0d06caSMauro Carvalho Chehab 12790c0d06caSMauro Carvalho Chehab current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 12800c0d06caSMauro Carvalho Chehab 12810c0d06caSMauro Carvalho Chehab /* Just return, if already using the right port */ 12820c0d06caSMauro Carvalho Chehab if (current_is_port_3 == is_port_3) 12830c0d06caSMauro Carvalho Chehab return 0; 12840c0d06caSMauro Carvalho Chehab 12850c0d06caSMauro Carvalho Chehab if (is_port_3) 12860c0d06caSMauro Carvalho Chehab value[0] |= I2C_DEMOD_EN; 12870c0d06caSMauro Carvalho Chehab else 12880c0d06caSMauro Carvalho Chehab value[0] &= ~I2C_DEMOD_EN; 12890c0d06caSMauro Carvalho Chehab 12900c0d06caSMauro Carvalho Chehab cx231xx_info("Changing the i2c master port to %d\n", 12910c0d06caSMauro Carvalho Chehab is_port_3 ? 3 : 1); 12920c0d06caSMauro Carvalho Chehab 12930c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 12940c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 12950c0d06caSMauro Carvalho Chehab 12960c0d06caSMauro Carvalho Chehab return status; 12970c0d06caSMauro Carvalho Chehab 12980c0d06caSMauro Carvalho Chehab } 12990c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 13000c0d06caSMauro Carvalho Chehab 13010c0d06caSMauro Carvalho Chehab void update_HH_register_after_set_DIF(struct cx231xx *dev) 13020c0d06caSMauro Carvalho Chehab { 13030c0d06caSMauro Carvalho Chehab /* 13040c0d06caSMauro Carvalho Chehab u8 status = 0; 13050c0d06caSMauro Carvalho Chehab u32 value = 0; 13060c0d06caSMauro Carvalho Chehab 13070c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 13080c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 13090c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 13100c0d06caSMauro Carvalho Chehab 13110c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 13120c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 13130c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 13140c0d06caSMauro Carvalho Chehab */ 13150c0d06caSMauro Carvalho Chehab } 13160c0d06caSMauro Carvalho Chehab 13170c0d06caSMauro Carvalho Chehab void cx231xx_dump_HH_reg(struct cx231xx *dev) 13180c0d06caSMauro Carvalho Chehab { 13190c0d06caSMauro Carvalho Chehab u32 value = 0; 13200c0d06caSMauro Carvalho Chehab u16 i = 0; 13210c0d06caSMauro Carvalho Chehab 13220c0d06caSMauro Carvalho Chehab value = 0x45005390; 13230c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, 0x104, value); 13240c0d06caSMauro Carvalho Chehab 13250c0d06caSMauro Carvalho Chehab for (i = 0x100; i < 0x140; i++) { 13260c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value); 13270c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x\n", i, value); 13280c0d06caSMauro Carvalho Chehab i = i+3; 13290c0d06caSMauro Carvalho Chehab } 13300c0d06caSMauro Carvalho Chehab 13310c0d06caSMauro Carvalho Chehab for (i = 0x300; i < 0x400; i++) { 13320c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value); 13330c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x\n", i, value); 13340c0d06caSMauro Carvalho Chehab i = i+3; 13350c0d06caSMauro Carvalho Chehab } 13360c0d06caSMauro Carvalho Chehab 13370c0d06caSMauro Carvalho Chehab for (i = 0x400; i < 0x440; i++) { 13380c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value); 13390c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x\n", i, value); 13400c0d06caSMauro Carvalho Chehab i = i+3; 13410c0d06caSMauro Carvalho Chehab } 13420c0d06caSMauro Carvalho Chehab 13430c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 13440c0d06caSMauro Carvalho Chehab cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 13450c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 13460c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 13470c0d06caSMauro Carvalho Chehab cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 13480c0d06caSMauro Carvalho Chehab } 13490c0d06caSMauro Carvalho Chehab 13500c0d06caSMauro Carvalho Chehab void cx231xx_dump_SC_reg(struct cx231xx *dev) 13510c0d06caSMauro Carvalho Chehab { 13520c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 13530c0d06caSMauro Carvalho Chehab cx231xx_info("cx231xx_dump_SC_reg!\n"); 13540c0d06caSMauro Carvalho Chehab 13550c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 13560c0d06caSMauro Carvalho Chehab value, 4); 13570c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 13580c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13590c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 13600c0d06caSMauro Carvalho Chehab value, 4); 13610c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 13620c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13630c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 13640c0d06caSMauro Carvalho Chehab value, 4); 13650c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 13660c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13670c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 13680c0d06caSMauro Carvalho Chehab value, 4); 13690c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 13700c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13710c0d06caSMauro Carvalho Chehab 13720c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 13730c0d06caSMauro Carvalho Chehab value, 4); 13740c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 13750c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13760c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 13770c0d06caSMauro Carvalho Chehab value, 4); 13780c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 13790c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13800c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 13810c0d06caSMauro Carvalho Chehab value, 4); 13820c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 13830c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13840c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 13850c0d06caSMauro Carvalho Chehab value, 4); 13860c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 13870c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13880c0d06caSMauro Carvalho Chehab 13890c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 13900c0d06caSMauro Carvalho Chehab value, 4); 13910c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 13920c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13930c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 13940c0d06caSMauro Carvalho Chehab value, 4); 13950c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 13960c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 13970c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 13980c0d06caSMauro Carvalho Chehab value, 4); 13990c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 14000c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14010c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 14020c0d06caSMauro Carvalho Chehab value, 4); 14030c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 14040c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14050c0d06caSMauro Carvalho Chehab 14060c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 14070c0d06caSMauro Carvalho Chehab value, 4); 14080c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 14090c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14100c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 14110c0d06caSMauro Carvalho Chehab value, 4); 14120c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 14130c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14140c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 14150c0d06caSMauro Carvalho Chehab value, 4); 14160c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 14170c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14180c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 14190c0d06caSMauro Carvalho Chehab value, 4); 14200c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 14210c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14220c0d06caSMauro Carvalho Chehab 14230c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 14240c0d06caSMauro Carvalho Chehab value, 4); 14250c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 14260c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14270c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 14280c0d06caSMauro Carvalho Chehab value, 4); 14290c0d06caSMauro Carvalho Chehab cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 14300c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]); 14310c0d06caSMauro Carvalho Chehab 14320c0d06caSMauro Carvalho Chehab 14330c0d06caSMauro Carvalho Chehab } 14340c0d06caSMauro Carvalho Chehab 14350c0d06caSMauro Carvalho Chehab void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 14360c0d06caSMauro Carvalho Chehab 14370c0d06caSMauro Carvalho Chehab { 14380c0d06caSMauro Carvalho Chehab u8 value = 0; 14390c0d06caSMauro Carvalho Chehab 14400c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_STATUS2_CH3, &value); 14410c0d06caSMauro Carvalho Chehab value = (value & 0xFE)|0x01; 14420c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_STATUS2_CH3, value); 14430c0d06caSMauro Carvalho Chehab 14440c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_STATUS2_CH3, &value); 14450c0d06caSMauro Carvalho Chehab value = (value & 0xFE)|0x00; 14460c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_STATUS2_CH3, value); 14470c0d06caSMauro Carvalho Chehab 14480c0d06caSMauro Carvalho Chehab 14490c0d06caSMauro Carvalho Chehab /* 14500c0d06caSMauro Carvalho Chehab config colibri to lo-if mode 14510c0d06caSMauro Carvalho Chehab 14520c0d06caSMauro Carvalho Chehab FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 14530c0d06caSMauro Carvalho Chehab the diff IF input by half, 14540c0d06caSMauro Carvalho Chehab 14550c0d06caSMauro Carvalho Chehab for low-if agc defect 14560c0d06caSMauro Carvalho Chehab */ 14570c0d06caSMauro Carvalho Chehab 14580c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 14590c0d06caSMauro Carvalho Chehab value = (value & 0xFC)|0x00; 14600c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 14610c0d06caSMauro Carvalho Chehab 14620c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_INPUT_CH3, &value); 14630c0d06caSMauro Carvalho Chehab value = (value & 0xF9)|0x02; 14640c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_INPUT_CH3, value); 14650c0d06caSMauro Carvalho Chehab 14660c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 14670c0d06caSMauro Carvalho Chehab value = (value & 0xFB)|0x04; 14680c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 14690c0d06caSMauro Carvalho Chehab 14700c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 14710c0d06caSMauro Carvalho Chehab value = (value & 0xFC)|0x03; 14720c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 14730c0d06caSMauro Carvalho Chehab 14740c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 14750c0d06caSMauro Carvalho Chehab value = (value & 0xFB)|0x04; 14760c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 14770c0d06caSMauro Carvalho Chehab 14780c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 14790c0d06caSMauro Carvalho Chehab value = (value & 0xF8)|0x06; 14800c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 14810c0d06caSMauro Carvalho Chehab 14820c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 14830c0d06caSMauro Carvalho Chehab value = (value & 0x8F)|0x40; 14840c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 14850c0d06caSMauro Carvalho Chehab 14860c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 14870c0d06caSMauro Carvalho Chehab value = (value & 0xDF)|0x20; 14880c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 14890c0d06caSMauro Carvalho Chehab } 14900c0d06caSMauro Carvalho Chehab 14910c0d06caSMauro Carvalho Chehab void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 14920c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode) 14930c0d06caSMauro Carvalho Chehab { 14940c0d06caSMauro Carvalho Chehab u32 colibri_carrier_offset = 0; 14950c0d06caSMauro Carvalho Chehab u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 14960c0d06caSMauro Carvalho Chehab u32 standard = 0; 14970c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 14980c0d06caSMauro Carvalho Chehab 14990c0d06caSMauro Carvalho Chehab cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); 15000c0d06caSMauro Carvalho Chehab value[0] = (u8) 0x6F; 15010c0d06caSMauro Carvalho Chehab value[1] = (u8) 0x6F; 15020c0d06caSMauro Carvalho Chehab value[2] = (u8) 0x6F; 15030c0d06caSMauro Carvalho Chehab value[3] = (u8) 0x6F; 15040c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 15050c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 15060c0d06caSMauro Carvalho Chehab 15070c0d06caSMauro Carvalho Chehab /*Set colibri for low IF*/ 15080c0d06caSMauro Carvalho Chehab cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 15090c0d06caSMauro Carvalho Chehab 15100c0d06caSMauro Carvalho Chehab /* Set C2HH for low IF operation.*/ 15110c0d06caSMauro Carvalho Chehab standard = dev->norm; 15120c0d06caSMauro Carvalho Chehab cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 15130c0d06caSMauro Carvalho Chehab func_mode, standard); 15140c0d06caSMauro Carvalho Chehab 15150c0d06caSMauro Carvalho Chehab /* Get colibri offsets.*/ 15160c0d06caSMauro Carvalho Chehab colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 15170c0d06caSMauro Carvalho Chehab standard); 15180c0d06caSMauro Carvalho Chehab 15190c0d06caSMauro Carvalho Chehab cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", 15200c0d06caSMauro Carvalho Chehab colibri_carrier_offset, standard); 15210c0d06caSMauro Carvalho Chehab 15220c0d06caSMauro Carvalho Chehab /* Set the band Pass filter for DIF*/ 15230c0d06caSMauro Carvalho Chehab cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 15240c0d06caSMauro Carvalho Chehab spectral_invert, mode); 15250c0d06caSMauro Carvalho Chehab } 15260c0d06caSMauro Carvalho Chehab 15270c0d06caSMauro Carvalho Chehab u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 15280c0d06caSMauro Carvalho Chehab { 15290c0d06caSMauro Carvalho Chehab u32 colibri_carrier_offset = 0; 15300c0d06caSMauro Carvalho Chehab 15310c0d06caSMauro Carvalho Chehab if (mode == TUNER_MODE_FM_RADIO) { 15320c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 1100000; 15330c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 15340c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 4832000; /*4.83MHz */ 15350c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 15360c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 2700000; /*2.70MHz */ 15370c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 15380c0d06caSMauro Carvalho Chehab | V4L2_STD_SECAM)) { 15390c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 2100000; /*2.10MHz */ 15400c0d06caSMauro Carvalho Chehab } 15410c0d06caSMauro Carvalho Chehab 15420c0d06caSMauro Carvalho Chehab return colibri_carrier_offset; 15430c0d06caSMauro Carvalho Chehab } 15440c0d06caSMauro Carvalho Chehab 15450c0d06caSMauro Carvalho Chehab void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 15460c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode) 15470c0d06caSMauro Carvalho Chehab { 15480c0d06caSMauro Carvalho Chehab unsigned long pll_freq_word; 15490c0d06caSMauro Carvalho Chehab u32 dif_misc_ctrl_value = 0; 15500c0d06caSMauro Carvalho Chehab u64 pll_freq_u64 = 0; 15510c0d06caSMauro Carvalho Chehab u32 i = 0; 15520c0d06caSMauro Carvalho Chehab 15530c0d06caSMauro Carvalho Chehab cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 15540c0d06caSMauro Carvalho Chehab if_freq, spectral_invert, mode); 15550c0d06caSMauro Carvalho Chehab 15560c0d06caSMauro Carvalho Chehab 15570c0d06caSMauro Carvalho Chehab if (mode == TUNER_MODE_FM_RADIO) { 15580c0d06caSMauro Carvalho Chehab pll_freq_word = 0x905A1CAC; 15590c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 15600c0d06caSMauro Carvalho Chehab 15610c0d06caSMauro Carvalho Chehab } else /*KSPROPERTY_TUNER_MODE_TV*/{ 15620c0d06caSMauro Carvalho Chehab /* Calculate the PLL frequency word based on the adjusted if_freq*/ 15630c0d06caSMauro Carvalho Chehab pll_freq_word = if_freq; 15640c0d06caSMauro Carvalho Chehab pll_freq_u64 = (u64)pll_freq_word << 28L; 15650c0d06caSMauro Carvalho Chehab do_div(pll_freq_u64, 50000000); 15660c0d06caSMauro Carvalho Chehab pll_freq_word = (u32)pll_freq_u64; 15670c0d06caSMauro Carvalho Chehab /*pll_freq_word = 0x3463497;*/ 15680c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 15690c0d06caSMauro Carvalho Chehab 15700c0d06caSMauro Carvalho Chehab if (spectral_invert) { 15710c0d06caSMauro Carvalho Chehab if_freq -= 400000; 15720c0d06caSMauro Carvalho Chehab /* Enable Spectral Invert*/ 15730c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, DIF_MISC_CTRL, 15740c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value); 15750c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 15760c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 15770c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value); 15780c0d06caSMauro Carvalho Chehab } else { 15790c0d06caSMauro Carvalho Chehab if_freq += 400000; 15800c0d06caSMauro Carvalho Chehab /* Disable Spectral Invert*/ 15810c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, DIF_MISC_CTRL, 15820c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value); 15830c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 15840c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 15850c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value); 15860c0d06caSMauro Carvalho Chehab } 15870c0d06caSMauro Carvalho Chehab 15880c0d06caSMauro Carvalho Chehab if_freq = (if_freq/100000)*100000; 15890c0d06caSMauro Carvalho Chehab 15900c0d06caSMauro Carvalho Chehab if (if_freq < 3000000) 15910c0d06caSMauro Carvalho Chehab if_freq = 3000000; 15920c0d06caSMauro Carvalho Chehab 15930c0d06caSMauro Carvalho Chehab if (if_freq > 16000000) 15940c0d06caSMauro Carvalho Chehab if_freq = 16000000; 15950c0d06caSMauro Carvalho Chehab } 15960c0d06caSMauro Carvalho Chehab 15970c0d06caSMauro Carvalho Chehab cx231xx_info("Enter IF=%zd\n", 15980c0d06caSMauro Carvalho Chehab ARRAY_SIZE(Dif_set_array)); 15990c0d06caSMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 16000c0d06caSMauro Carvalho Chehab if (Dif_set_array[i].if_freq == if_freq) { 16010c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, 16020c0d06caSMauro Carvalho Chehab Dif_set_array[i].register_address, Dif_set_array[i].value); 16030c0d06caSMauro Carvalho Chehab } 16040c0d06caSMauro Carvalho Chehab } 16050c0d06caSMauro Carvalho Chehab } 16060c0d06caSMauro Carvalho Chehab 16070c0d06caSMauro Carvalho Chehab /****************************************************************************** 16080c0d06caSMauro Carvalho Chehab * D I F - B L O C K C O N T R O L functions * 16090c0d06caSMauro Carvalho Chehab ******************************************************************************/ 16100c0d06caSMauro Carvalho Chehab int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 16110c0d06caSMauro Carvalho Chehab u32 function_mode, u32 standard) 16120c0d06caSMauro Carvalho Chehab { 16130c0d06caSMauro Carvalho Chehab int status = 0; 16140c0d06caSMauro Carvalho Chehab 16150c0d06caSMauro Carvalho Chehab 16160c0d06caSMauro Carvalho Chehab if (mode == V4L2_TUNER_RADIO) { 16170c0d06caSMauro Carvalho Chehab /* C2HH */ 16180c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16190c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16200c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16210c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16220c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16240c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16250c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 16260c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16270c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16280c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16290c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 16300c0d06caSMauro Carvalho Chehab /* no inv */ 16310c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16320c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16330c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16340c0d06caSMauro Carvalho Chehab } else if (standard != DIF_USE_BASEBAND) { 16350c0d06caSMauro Carvalho Chehab if (standard & V4L2_STD_MN) { 16360c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16370c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16380c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16390c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16400c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16410c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16420c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16430c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 16440c0d06caSMauro Carvalho Chehab function_mode); 16450c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16460c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16470c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16480c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 16490c0d06caSMauro Carvalho Chehab /* no inv */ 16500c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16510c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16520c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16530c0d06caSMauro Carvalho Chehab /* 0x124, AUD_CHAN1_SRC = 0x3 */ 16540c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16550c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16560c0d06caSMauro Carvalho Chehab AUD_IO_CTRL, 0, 31, 0x00000003); 16570c0d06caSMauro Carvalho Chehab } else if ((standard == V4L2_STD_PAL_I) | 16580c0d06caSMauro Carvalho Chehab (standard & V4L2_STD_PAL_D) | 16590c0d06caSMauro Carvalho Chehab (standard & V4L2_STD_SECAM)) { 16600c0d06caSMauro Carvalho Chehab /* C2HH setup */ 16610c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16620c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16630c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16640c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16650c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16660c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16670c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16680c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 16690c0d06caSMauro Carvalho Chehab function_mode); 16700c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16710c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16720c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16730c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 16740c0d06caSMauro Carvalho Chehab /* no inv */ 16750c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16760c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16770c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16780c0d06caSMauro Carvalho Chehab } else { 16790c0d06caSMauro Carvalho Chehab /* default PAL BG */ 16800c0d06caSMauro Carvalho Chehab /* C2HH setup */ 16810c0d06caSMauro Carvalho Chehab /* lo if big signal */ 16820c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16830c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16840c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 16850c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */ 16860c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16870c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16880c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 16890c0d06caSMauro Carvalho Chehab function_mode); 16900c0d06caSMauro Carvalho Chehab /* IF_MODE */ 16910c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16920c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16930c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 16940c0d06caSMauro Carvalho Chehab /* no inv */ 16950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, 16960c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32, 16970c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 16980c0d06caSMauro Carvalho Chehab } 16990c0d06caSMauro Carvalho Chehab } 17000c0d06caSMauro Carvalho Chehab 17010c0d06caSMauro Carvalho Chehab return status; 17020c0d06caSMauro Carvalho Chehab } 17030c0d06caSMauro Carvalho Chehab 17040c0d06caSMauro Carvalho Chehab int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 17050c0d06caSMauro Carvalho Chehab { 17060c0d06caSMauro Carvalho Chehab int status = 0; 17070c0d06caSMauro Carvalho Chehab u32 dif_misc_ctrl_value = 0; 17080c0d06caSMauro Carvalho Chehab u32 func_mode = 0; 17090c0d06caSMauro Carvalho Chehab 17100c0d06caSMauro Carvalho Chehab cx231xx_info("%s: setStandard to %x\n", __func__, standard); 17110c0d06caSMauro Carvalho Chehab 17120c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 17130c0d06caSMauro Carvalho Chehab if (standard != DIF_USE_BASEBAND) 17140c0d06caSMauro Carvalho Chehab dev->norm = standard; 17150c0d06caSMauro Carvalho Chehab 17160c0d06caSMauro Carvalho Chehab switch (dev->model) { 17170c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_CARRAERA: 17180c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_250: 17190c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_SHELBY: 17200c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_250: 17210c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 17220c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_EXETER: 17230c0d06caSMauro Carvalho Chehab func_mode = 0x03; 17240c0d06caSMauro Carvalho Chehab break; 17250c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_253S: 17260c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_253S: 17270c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 17280c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 17290c0d06caSMauro Carvalho Chehab func_mode = 0x01; 17300c0d06caSMauro Carvalho Chehab break; 17310c0d06caSMauro Carvalho Chehab default: 17320c0d06caSMauro Carvalho Chehab func_mode = 0x01; 17330c0d06caSMauro Carvalho Chehab } 17340c0d06caSMauro Carvalho Chehab 17350c0d06caSMauro Carvalho Chehab status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 17360c0d06caSMauro Carvalho Chehab func_mode, standard); 17370c0d06caSMauro Carvalho Chehab 17380c0d06caSMauro Carvalho Chehab if (standard == DIF_USE_BASEBAND) { /* base band */ 17390c0d06caSMauro Carvalho Chehab /* There is a different SRC_PHASE_INC value 17400c0d06caSMauro Carvalho Chehab for baseband vs. DIF */ 17410c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 17420c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, 17430c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value); 17440c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 17450c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, 17460c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value); 17470c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_D) { 17480c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17490c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 17500c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17510c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 17520c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17530c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 17540c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17550c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 17560c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17570c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380); 17580c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17590c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 17600c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17610c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 17620c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17630c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 17640c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17650c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 17660c0d06caSMauro Carvalho Chehab 0x26001700); 17670c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17680c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 17690c0d06caSMauro Carvalho Chehab 0x00002660); 17700c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17710c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 17720c0d06caSMauro Carvalho Chehab 0x72500800); 17730c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17740c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 17750c0d06caSMauro Carvalho Chehab 0x27000100); 17760c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17770c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 17780c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17790c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 17800c0d06caSMauro Carvalho Chehab 0x00000000); 17810c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17820c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 17830c0d06caSMauro Carvalho Chehab 0x1befbf06); 17840c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17850c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 17860c0d06caSMauro Carvalho Chehab 0x000035e8); 17870c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17880c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 17890c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 17900c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 17910c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11; 17920c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_I) { 17930c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17940c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 17950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17960c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 17970c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 17980c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 17990c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18000c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 18010c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18020c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380); 18030c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18040c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 18050c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18060c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 18070c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18080c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 18090c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18100c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 18110c0d06caSMauro Carvalho Chehab 0x26001700); 18120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18130c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 18140c0d06caSMauro Carvalho Chehab 0x00002660); 18150c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18160c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 18170c0d06caSMauro Carvalho Chehab 0x72500800); 18180c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18190c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 18200c0d06caSMauro Carvalho Chehab 0x27000100); 18210c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18220c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 18230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18240c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 18250c0d06caSMauro Carvalho Chehab 0x00000000); 18260c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18270c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 18280c0d06caSMauro Carvalho Chehab 0x1befbf06); 18290c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18300c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 18310c0d06caSMauro Carvalho Chehab 0x000035e8); 18320c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18330c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 18340c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 18350c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 18360c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a033F11; 18370c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_M) { 18380c0d06caSMauro Carvalho Chehab /* improved Low Frequency Phase Noise */ 18390c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 18400c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 18410c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 18420c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 18430c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 18440c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 18450c0d06caSMauro Carvalho Chehab 0x26001700); 18460c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 18470c0d06caSMauro Carvalho Chehab 0x00002660); 18480c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 18490c0d06caSMauro Carvalho Chehab 0x72500800); 18500c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 18510c0d06caSMauro Carvalho Chehab 0x27000100); 18520c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 18530c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 18540c0d06caSMauro Carvalho Chehab 0x009f50c1); 18550c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 18560c0d06caSMauro Carvalho Chehab 0x1befbf06); 18570c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 18580c0d06caSMauro Carvalho Chehab 0x000035e8); 18590c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 18600c0d06caSMauro Carvalho Chehab 0x00000000); 18610c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 18620c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 18630c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3A0A3F10; 18640c0d06caSMauro Carvalho Chehab } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 18650c0d06caSMauro Carvalho Chehab /* improved Low Frequency Phase Noise */ 18660c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 18670c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 18680c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 18690c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 18700c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 18710c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 18720c0d06caSMauro Carvalho Chehab 0x26001700); 18730c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 18740c0d06caSMauro Carvalho Chehab 0x00002660); 18750c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 18760c0d06caSMauro Carvalho Chehab 0x72500800); 18770c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 18780c0d06caSMauro Carvalho Chehab 0x27000100); 18790c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 18800c0d06caSMauro Carvalho Chehab 0x012c405d); 18810c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 18820c0d06caSMauro Carvalho Chehab 0x009f50c1); 18830c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 18840c0d06caSMauro Carvalho Chehab 0x1befbf06); 18850c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 18860c0d06caSMauro Carvalho Chehab 0x000035e8); 18870c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 18880c0d06caSMauro Carvalho Chehab 0x00000000); 18890c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 18900c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 18910c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = 0x3A093F10; 18920c0d06caSMauro Carvalho Chehab } else if (standard & 18930c0d06caSMauro Carvalho Chehab (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 18940c0d06caSMauro Carvalho Chehab V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 18950c0d06caSMauro Carvalho Chehab 18960c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18970c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 18980c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 18990c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 19000c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19010c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 19020c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19030c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 19040c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19050c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x888C0380); 19060c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19070c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 19080c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19090c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 19100c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19110c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 19120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19130c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 19140c0d06caSMauro Carvalho Chehab 0x26001700); 19150c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19160c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 19170c0d06caSMauro Carvalho Chehab 0x00002660); 19180c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19190c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 19200c0d06caSMauro Carvalho Chehab 0x27000100); 19210c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19220c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 19230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19240c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 19250c0d06caSMauro Carvalho Chehab 0x00000000); 19260c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19270c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 19280c0d06caSMauro Carvalho Chehab 0x1befbf06); 19290c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19300c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 19310c0d06caSMauro Carvalho Chehab 0x000035e8); 19320c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19330c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 19340c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19350c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 19360c0d06caSMauro Carvalho Chehab 0xf4000000); 19370c0d06caSMauro Carvalho Chehab 19380c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 19390c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 19400c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11; 19410c0d06caSMauro Carvalho Chehab } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 19420c0d06caSMauro Carvalho Chehab /* Is it SECAM_L1? */ 19430c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19440c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 19450c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19460c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 19470c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19480c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 19490c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19500c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 19510c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19520c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x888C0380); 19530c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19540c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 19550c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19560c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 19570c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19580c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 19590c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19600c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 19610c0d06caSMauro Carvalho Chehab 0x26001700); 19620c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19630c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 19640c0d06caSMauro Carvalho Chehab 0x00002660); 19650c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19660c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 19670c0d06caSMauro Carvalho Chehab 0x27000100); 19680c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19690c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 19700c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19710c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 19720c0d06caSMauro Carvalho Chehab 0x00000000); 19730c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19740c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 19750c0d06caSMauro Carvalho Chehab 0x1befbf06); 19760c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19770c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 19780c0d06caSMauro Carvalho Chehab 0x000035e8); 19790c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19800c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 19810c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 19820c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 19830c0d06caSMauro Carvalho Chehab 0xf2560000); 19840c0d06caSMauro Carvalho Chehab 19850c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 19860c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 19870c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11; 19880c0d06caSMauro Carvalho Chehab 19890c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_NTSC_M) { 19900c0d06caSMauro Carvalho Chehab /* V4L2_STD_NTSC_M (75 IRE Setup) Or 19910c0d06caSMauro Carvalho Chehab V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 19920c0d06caSMauro Carvalho Chehab 19930c0d06caSMauro Carvalho Chehab /* For NTSC the centre frequency of video coming out of 19940c0d06caSMauro Carvalho Chehab sidewinder is around 7.1MHz or 3.6MHz depending on the 19950c0d06caSMauro Carvalho Chehab spectral inversion. so for a non spectrally inverted channel 19960c0d06caSMauro Carvalho Chehab the pll freq word is 0x03420c49 19970c0d06caSMauro Carvalho Chehab */ 19980c0d06caSMauro Carvalho Chehab 19990c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 20000c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 20010c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 20020c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 20030c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 20040c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 20050c0d06caSMauro Carvalho Chehab 0x26001700); 20060c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 20070c0d06caSMauro Carvalho Chehab 0x00002660); 20080c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 20090c0d06caSMauro Carvalho Chehab 0x04000800); 20100c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 20110c0d06caSMauro Carvalho Chehab 0x27000100); 20120c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 20130c0d06caSMauro Carvalho Chehab 20140c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 20150c0d06caSMauro Carvalho Chehab 0x009f50c1); 20160c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 20170c0d06caSMauro Carvalho Chehab 0x1befbf06); 20180c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 20190c0d06caSMauro Carvalho Chehab 0x000035e8); 20200c0d06caSMauro Carvalho Chehab 20210c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 20220c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 20230c0d06caSMauro Carvalho Chehab 0xC2262600); 20240c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 20250c0d06caSMauro Carvalho Chehab 20260c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 20270c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 20280c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a003F10; 20290c0d06caSMauro Carvalho Chehab } else { 20300c0d06caSMauro Carvalho Chehab /* default PAL BG */ 20310c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20320c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 20330c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20340c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 20350c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20360c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 20370c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20380c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800); 20390c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20400c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380); 20410c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20420c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 20430c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20440c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 20450c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20460c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 20470c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20480c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31, 20490c0d06caSMauro Carvalho Chehab 0x26001700); 20500c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20510c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31, 20520c0d06caSMauro Carvalho Chehab 0x00002660); 20530c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20540c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31, 20550c0d06caSMauro Carvalho Chehab 0x72500800); 20560c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20570c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31, 20580c0d06caSMauro Carvalho Chehab 0x27000100); 20590c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20600c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 20610c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20620c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31, 20630c0d06caSMauro Carvalho Chehab 0x00A653A8); 20640c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20650c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31, 20660c0d06caSMauro Carvalho Chehab 0x1befbf06); 20670c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20680c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31, 20690c0d06caSMauro Carvalho Chehab 0x000035e8); 20700c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 20710c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000); 20720c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */ 20730c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 20740c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a013F11; 20750c0d06caSMauro Carvalho Chehab } 20760c0d06caSMauro Carvalho Chehab 20770c0d06caSMauro Carvalho Chehab /* The AGC values should be the same for all standards, 20780c0d06caSMauro Carvalho Chehab AUD_SRC_SEL[19] should always be disabled */ 20790c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 20800c0d06caSMauro Carvalho Chehab 20810c0d06caSMauro Carvalho Chehab /* It is still possible to get Set Standard calls even when we 20820c0d06caSMauro Carvalho Chehab are in FM mode. 20830c0d06caSMauro Carvalho Chehab This is done to override the value for FM. */ 20840c0d06caSMauro Carvalho Chehab if (dev->active_mode == V4L2_TUNER_RADIO) 20850c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = 0x7a080000; 20860c0d06caSMauro Carvalho Chehab 20870c0d06caSMauro Carvalho Chehab /* Write the calculated value for misc ontrol register */ 20880c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 20890c0d06caSMauro Carvalho Chehab 20900c0d06caSMauro Carvalho Chehab return status; 20910c0d06caSMauro Carvalho Chehab } 20920c0d06caSMauro Carvalho Chehab 20930c0d06caSMauro Carvalho Chehab int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 20940c0d06caSMauro Carvalho Chehab { 20950c0d06caSMauro Carvalho Chehab int status = 0; 20960c0d06caSMauro Carvalho Chehab u32 dwval; 20970c0d06caSMauro Carvalho Chehab 20980c0d06caSMauro Carvalho Chehab /* Set the RF and IF k_agc values to 3 */ 20990c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 21000c0d06caSMauro Carvalho Chehab dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 21010c0d06caSMauro Carvalho Chehab dwval |= 0x33000000; 21020c0d06caSMauro Carvalho Chehab 21030c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 21040c0d06caSMauro Carvalho Chehab 21050c0d06caSMauro Carvalho Chehab return status; 21060c0d06caSMauro Carvalho Chehab } 21070c0d06caSMauro Carvalho Chehab 21080c0d06caSMauro Carvalho Chehab int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 21090c0d06caSMauro Carvalho Chehab { 21100c0d06caSMauro Carvalho Chehab int status = 0; 21110c0d06caSMauro Carvalho Chehab u32 dwval; 21120c0d06caSMauro Carvalho Chehab cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", 21130c0d06caSMauro Carvalho Chehab dev->tuner_type); 21140c0d06caSMauro Carvalho Chehab /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 21150c0d06caSMauro Carvalho Chehab * SECAM L/B/D standards */ 21160c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 21170c0d06caSMauro Carvalho Chehab dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 21180c0d06caSMauro Carvalho Chehab 21190c0d06caSMauro Carvalho Chehab if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 21200c0d06caSMauro Carvalho Chehab V4L2_STD_SECAM_D)) { 21210c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) { 21220c0d06caSMauro Carvalho Chehab dwval &= ~FLD_DIF_IF_REF; 21230c0d06caSMauro Carvalho Chehab dwval |= 0x88000300; 21240c0d06caSMauro Carvalho Chehab } else 21250c0d06caSMauro Carvalho Chehab dwval |= 0x88000000; 21260c0d06caSMauro Carvalho Chehab } else { 21270c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) { 21280c0d06caSMauro Carvalho Chehab dwval &= ~FLD_DIF_IF_REF; 21290c0d06caSMauro Carvalho Chehab dwval |= 0xCC000300; 21300c0d06caSMauro Carvalho Chehab } else 21310c0d06caSMauro Carvalho Chehab dwval |= 0x44000000; 21320c0d06caSMauro Carvalho Chehab } 21330c0d06caSMauro Carvalho Chehab 21340c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 21350c0d06caSMauro Carvalho Chehab 21360c0d06caSMauro Carvalho Chehab return status; 21370c0d06caSMauro Carvalho Chehab } 21380c0d06caSMauro Carvalho Chehab 21390c0d06caSMauro Carvalho Chehab /****************************************************************************** 21400c0d06caSMauro Carvalho Chehab * I 2 S - B L O C K C O N T R O L functions * 21410c0d06caSMauro Carvalho Chehab ******************************************************************************/ 21420c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 21430c0d06caSMauro Carvalho Chehab { 21440c0d06caSMauro Carvalho Chehab int status = 0; 21450c0d06caSMauro Carvalho Chehab u32 value; 21460c0d06caSMauro Carvalho Chehab 21470c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21480c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, &value, 1); 21490c0d06caSMauro Carvalho Chehab /* enables clock to delta-sigma and decimation filter */ 21500c0d06caSMauro Carvalho Chehab value |= 0x80; 21510c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21520c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, value, 1); 21530c0d06caSMauro Carvalho Chehab /* power up all channel */ 21540c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21550c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1); 21560c0d06caSMauro Carvalho Chehab 21570c0d06caSMauro Carvalho Chehab return status; 21580c0d06caSMauro Carvalho Chehab } 21590c0d06caSMauro Carvalho Chehab 21600c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 21610c0d06caSMauro Carvalho Chehab enum AV_MODE avmode) 21620c0d06caSMauro Carvalho Chehab { 21630c0d06caSMauro Carvalho Chehab int status = 0; 21640c0d06caSMauro Carvalho Chehab u32 value = 0; 21650c0d06caSMauro Carvalho Chehab 21660c0d06caSMauro Carvalho Chehab if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 21670c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21680c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, &value, 1); 21690c0d06caSMauro Carvalho Chehab value |= 0xfe; 21700c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21710c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, value, 1); 21720c0d06caSMauro Carvalho Chehab } else { 21730c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21740c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1); 21750c0d06caSMauro Carvalho Chehab } 21760c0d06caSMauro Carvalho Chehab 21770c0d06caSMauro Carvalho Chehab return status; 21780c0d06caSMauro Carvalho Chehab } 21790c0d06caSMauro Carvalho Chehab 21800c0d06caSMauro Carvalho Chehab /* set i2s_blk for audio input types */ 21810c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 21820c0d06caSMauro Carvalho Chehab { 21830c0d06caSMauro Carvalho Chehab int status = 0; 21840c0d06caSMauro Carvalho Chehab 21850c0d06caSMauro Carvalho Chehab switch (audio_input) { 21860c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_LINE_IN: 21870c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21880c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1); 21890c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 21900c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, 0x80, 1); 21910c0d06caSMauro Carvalho Chehab break; 21920c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_VIDEO: 21930c0d06caSMauro Carvalho Chehab default: 21940c0d06caSMauro Carvalho Chehab break; 21950c0d06caSMauro Carvalho Chehab } 21960c0d06caSMauro Carvalho Chehab 21970c0d06caSMauro Carvalho Chehab dev->ctl_ainput = audio_input; 21980c0d06caSMauro Carvalho Chehab 21990c0d06caSMauro Carvalho Chehab return status; 22000c0d06caSMauro Carvalho Chehab } 22010c0d06caSMauro Carvalho Chehab 22020c0d06caSMauro Carvalho Chehab /****************************************************************************** 22030c0d06caSMauro Carvalho Chehab * P O W E R C O N T R O L functions * 22040c0d06caSMauro Carvalho Chehab ******************************************************************************/ 22050c0d06caSMauro Carvalho Chehab int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 22060c0d06caSMauro Carvalho Chehab { 22070c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 22080c0d06caSMauro Carvalho Chehab u32 tmp = 0; 22090c0d06caSMauro Carvalho Chehab int status = 0; 22100c0d06caSMauro Carvalho Chehab 22110c0d06caSMauro Carvalho Chehab if (dev->power_mode != mode) 22120c0d06caSMauro Carvalho Chehab dev->power_mode = mode; 22130c0d06caSMauro Carvalho Chehab else { 22140c0d06caSMauro Carvalho Chehab cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", 22150c0d06caSMauro Carvalho Chehab mode); 22160c0d06caSMauro Carvalho Chehab return 0; 22170c0d06caSMauro Carvalho Chehab } 22180c0d06caSMauro Carvalho Chehab 22190c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 22200c0d06caSMauro Carvalho Chehab 4); 22210c0d06caSMauro Carvalho Chehab if (status < 0) 22220c0d06caSMauro Carvalho Chehab return status; 22230c0d06caSMauro Carvalho Chehab 22240c0d06caSMauro Carvalho Chehab tmp = *((u32 *) value); 22250c0d06caSMauro Carvalho Chehab 22260c0d06caSMauro Carvalho Chehab switch (mode) { 22270c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_ENXTERNAL_AV: 22280c0d06caSMauro Carvalho Chehab 22290c0d06caSMauro Carvalho Chehab tmp &= (~PWR_MODE_MASK); 22300c0d06caSMauro Carvalho Chehab 22310c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN; 22320c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22330c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22340c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22350c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22360c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22370c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22380c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22390c0d06caSMauro Carvalho Chehab 22400c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN; 22410c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22420c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22430c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22440c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22450c0d06caSMauro Carvalho Chehab status = 22460c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 22470c0d06caSMauro Carvalho Chehab value, 4); 22480c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22490c0d06caSMauro Carvalho Chehab 22500c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 22510c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22520c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22530c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22540c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22550c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22560c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22570c0d06caSMauro Carvalho Chehab 22580c0d06caSMauro Carvalho Chehab /* reset state of xceive tuner */ 22590c0d06caSMauro Carvalho Chehab dev->xc_fw_load_done = 0; 22600c0d06caSMauro Carvalho Chehab break; 22610c0d06caSMauro Carvalho Chehab 22620c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_ANALOGT_TV: 22630c0d06caSMauro Carvalho Chehab 22640c0d06caSMauro Carvalho Chehab tmp |= PWR_DEMOD_EN; 22650c0d06caSMauro Carvalho Chehab tmp |= (I2C_DEMOD_EN); 22660c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22670c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22680c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22690c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22700c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22710c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22720c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22730c0d06caSMauro Carvalho Chehab 22740c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_TUNER_EN)) { 22750c0d06caSMauro Carvalho Chehab tmp |= (PWR_TUNER_EN); 22760c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22770c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22780c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22790c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22800c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22810c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22820c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22830c0d06caSMauro Carvalho Chehab } 22840c0d06caSMauro Carvalho Chehab 22850c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_AV_EN)) { 22860c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN; 22870c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22880c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22890c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 22900c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 22910c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 22920c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 22930c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 22940c0d06caSMauro Carvalho Chehab } 22950c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_ISO_EN)) { 22960c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN; 22970c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 22980c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 22990c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23000c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23010c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23020c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23030c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23040c0d06caSMauro Carvalho Chehab } 23050c0d06caSMauro Carvalho Chehab 23060c0d06caSMauro Carvalho Chehab if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 23070c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_ANALOGT_TV; 23080c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23090c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23100c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23110c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23120c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23130c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23140c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23150c0d06caSMauro Carvalho Chehab } 23160c0d06caSMauro Carvalho Chehab 23170c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type != TUNER_ABSENT) { 23180c0d06caSMauro Carvalho Chehab /* Enable tuner */ 23190c0d06caSMauro Carvalho Chehab cx231xx_enable_i2c_port_3(dev, true); 23200c0d06caSMauro Carvalho Chehab 23210c0d06caSMauro Carvalho Chehab /* reset the Tuner */ 23220c0d06caSMauro Carvalho Chehab if (dev->board.tuner_gpio) 23230c0d06caSMauro Carvalho Chehab cx231xx_gpio_set(dev, dev->board.tuner_gpio); 23240c0d06caSMauro Carvalho Chehab 23250c0d06caSMauro Carvalho Chehab if (dev->cx231xx_reset_analog_tuner) 23260c0d06caSMauro Carvalho Chehab dev->cx231xx_reset_analog_tuner(dev); 23270c0d06caSMauro Carvalho Chehab } 23280c0d06caSMauro Carvalho Chehab 23290c0d06caSMauro Carvalho Chehab break; 23300c0d06caSMauro Carvalho Chehab 23310c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_DIGITAL: 23320c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_TUNER_EN)) { 23330c0d06caSMauro Carvalho Chehab tmp |= (PWR_TUNER_EN); 23340c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23350c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23360c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23370c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23380c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23390c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23400c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23410c0d06caSMauro Carvalho Chehab } 23420c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_AV_EN)) { 23430c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN; 23440c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23450c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23460c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23470c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23480c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23490c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23500c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23510c0d06caSMauro Carvalho Chehab } 23520c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_ISO_EN)) { 23530c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN; 23540c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23550c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23560c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23570c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23580c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23590c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23600c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23610c0d06caSMauro Carvalho Chehab } 23620c0d06caSMauro Carvalho Chehab 23630c0d06caSMauro Carvalho Chehab tmp &= (~PWR_AV_MODE); 23640c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; 23650c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23660c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23670c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23680c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23690c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23700c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23710c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23720c0d06caSMauro Carvalho Chehab 23730c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_DEMOD_EN)) { 23740c0d06caSMauro Carvalho Chehab tmp |= PWR_DEMOD_EN; 23750c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 23760c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 23770c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 23780c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 23790c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 23800c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 23810c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 23820c0d06caSMauro Carvalho Chehab } 23830c0d06caSMauro Carvalho Chehab 23840c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type != TUNER_ABSENT) { 23850c0d06caSMauro Carvalho Chehab /* 23860c0d06caSMauro Carvalho Chehab * Enable tuner 23870c0d06caSMauro Carvalho Chehab * Hauppauge Exeter seems to need to do something different! 23880c0d06caSMauro Carvalho Chehab */ 23890c0d06caSMauro Carvalho Chehab if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) 23900c0d06caSMauro Carvalho Chehab cx231xx_enable_i2c_port_3(dev, false); 23910c0d06caSMauro Carvalho Chehab else 23920c0d06caSMauro Carvalho Chehab cx231xx_enable_i2c_port_3(dev, true); 23930c0d06caSMauro Carvalho Chehab 23940c0d06caSMauro Carvalho Chehab /* reset the Tuner */ 23950c0d06caSMauro Carvalho Chehab if (dev->board.tuner_gpio) 23960c0d06caSMauro Carvalho Chehab cx231xx_gpio_set(dev, dev->board.tuner_gpio); 23970c0d06caSMauro Carvalho Chehab 23980c0d06caSMauro Carvalho Chehab if (dev->cx231xx_reset_analog_tuner) 23990c0d06caSMauro Carvalho Chehab dev->cx231xx_reset_analog_tuner(dev); 24000c0d06caSMauro Carvalho Chehab } 24010c0d06caSMauro Carvalho Chehab break; 24020c0d06caSMauro Carvalho Chehab 24030c0d06caSMauro Carvalho Chehab default: 24040c0d06caSMauro Carvalho Chehab break; 24050c0d06caSMauro Carvalho Chehab } 24060c0d06caSMauro Carvalho Chehab 24070c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 24080c0d06caSMauro Carvalho Chehab 24090c0d06caSMauro Carvalho Chehab /* For power saving, only enable Pwr_resetout_n 24100c0d06caSMauro Carvalho Chehab when digital TV is selected. */ 24110c0d06caSMauro Carvalho Chehab if (mode == POLARIS_AVMODE_DIGITAL) { 24120c0d06caSMauro Carvalho Chehab tmp |= PWR_RESETOUT_EN; 24130c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 24140c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 24150c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 24160c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 24170c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 24180c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4); 24190c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL); 24200c0d06caSMauro Carvalho Chehab } 24210c0d06caSMauro Carvalho Chehab 24220c0d06caSMauro Carvalho Chehab /* update power control for afe */ 24230c0d06caSMauro Carvalho Chehab status = cx231xx_afe_update_power_control(dev, mode); 24240c0d06caSMauro Carvalho Chehab 24250c0d06caSMauro Carvalho Chehab /* update power control for i2s_blk */ 24260c0d06caSMauro Carvalho Chehab status = cx231xx_i2s_blk_update_power_control(dev, mode); 24270c0d06caSMauro Carvalho Chehab 24280c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 24290c0d06caSMauro Carvalho Chehab 4); 24300c0d06caSMauro Carvalho Chehab 24310c0d06caSMauro Carvalho Chehab return status; 24320c0d06caSMauro Carvalho Chehab } 24330c0d06caSMauro Carvalho Chehab 24340c0d06caSMauro Carvalho Chehab int cx231xx_power_suspend(struct cx231xx *dev) 24350c0d06caSMauro Carvalho Chehab { 24360c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 }; 24370c0d06caSMauro Carvalho Chehab u32 tmp = 0; 24380c0d06caSMauro Carvalho Chehab int status = 0; 24390c0d06caSMauro Carvalho Chehab 24400c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 24410c0d06caSMauro Carvalho Chehab value, 4); 24420c0d06caSMauro Carvalho Chehab if (status > 0) 24430c0d06caSMauro Carvalho Chehab return status; 24440c0d06caSMauro Carvalho Chehab 24450c0d06caSMauro Carvalho Chehab tmp = *((u32 *) value); 24460c0d06caSMauro Carvalho Chehab tmp &= (~PWR_MODE_MASK); 24470c0d06caSMauro Carvalho Chehab 24480c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 24490c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 24500c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 24510c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 24520c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 24530c0d06caSMauro Carvalho Chehab value, 4); 24540c0d06caSMauro Carvalho Chehab 24550c0d06caSMauro Carvalho Chehab return status; 24560c0d06caSMauro Carvalho Chehab } 24570c0d06caSMauro Carvalho Chehab 24580c0d06caSMauro Carvalho Chehab /****************************************************************************** 24590c0d06caSMauro Carvalho Chehab * S T R E A M C O N T R O L functions * 24600c0d06caSMauro Carvalho Chehab ******************************************************************************/ 24610c0d06caSMauro Carvalho Chehab int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 24620c0d06caSMauro Carvalho Chehab { 24630c0d06caSMauro Carvalho Chehab u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 24640c0d06caSMauro Carvalho Chehab u32 tmp = 0; 24650c0d06caSMauro Carvalho Chehab int status = 0; 24660c0d06caSMauro Carvalho Chehab 24670c0d06caSMauro Carvalho Chehab cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); 24680c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 24690c0d06caSMauro Carvalho Chehab value, 4); 24700c0d06caSMauro Carvalho Chehab if (status < 0) 24710c0d06caSMauro Carvalho Chehab return status; 24720c0d06caSMauro Carvalho Chehab 24730c0d06caSMauro Carvalho Chehab tmp = *((u32 *) value); 24740c0d06caSMauro Carvalho Chehab tmp |= ep_mask; 24750c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 24760c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 24770c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 24780c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 24790c0d06caSMauro Carvalho Chehab 24800c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 24810c0d06caSMauro Carvalho Chehab value, 4); 24820c0d06caSMauro Carvalho Chehab 24830c0d06caSMauro Carvalho Chehab return status; 24840c0d06caSMauro Carvalho Chehab } 24850c0d06caSMauro Carvalho Chehab 24860c0d06caSMauro Carvalho Chehab int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 24870c0d06caSMauro Carvalho Chehab { 24880c0d06caSMauro Carvalho Chehab u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 24890c0d06caSMauro Carvalho Chehab u32 tmp = 0; 24900c0d06caSMauro Carvalho Chehab int status = 0; 24910c0d06caSMauro Carvalho Chehab 24920c0d06caSMauro Carvalho Chehab cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); 24930c0d06caSMauro Carvalho Chehab status = 24940c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 24950c0d06caSMauro Carvalho Chehab if (status < 0) 24960c0d06caSMauro Carvalho Chehab return status; 24970c0d06caSMauro Carvalho Chehab 24980c0d06caSMauro Carvalho Chehab tmp = *((u32 *) value); 24990c0d06caSMauro Carvalho Chehab tmp &= (~ep_mask); 25000c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp; 25010c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8); 25020c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16); 25030c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24); 25040c0d06caSMauro Carvalho Chehab 25050c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 25060c0d06caSMauro Carvalho Chehab value, 4); 25070c0d06caSMauro Carvalho Chehab 25080c0d06caSMauro Carvalho Chehab return status; 25090c0d06caSMauro Carvalho Chehab } 25100c0d06caSMauro Carvalho Chehab 25110c0d06caSMauro Carvalho Chehab int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 25120c0d06caSMauro Carvalho Chehab { 25130c0d06caSMauro Carvalho Chehab int status = 0; 25140c0d06caSMauro Carvalho Chehab u32 value = 0; 25150c0d06caSMauro Carvalho Chehab u8 val[4] = { 0, 0, 0, 0 }; 25160c0d06caSMauro Carvalho Chehab 25170c0d06caSMauro Carvalho Chehab if (dev->udev->speed == USB_SPEED_HIGH) { 25180c0d06caSMauro Carvalho Chehab switch (media_type) { 25190c0d06caSMauro Carvalho Chehab case Audio: 25200c0d06caSMauro Carvalho Chehab cx231xx_info("%s: Audio enter HANC\n", __func__); 25210c0d06caSMauro Carvalho Chehab status = 25220c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 25230c0d06caSMauro Carvalho Chehab break; 25240c0d06caSMauro Carvalho Chehab 25250c0d06caSMauro Carvalho Chehab case Vbi: 25260c0d06caSMauro Carvalho Chehab cx231xx_info("%s: set vanc registers\n", __func__); 25270c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 25280c0d06caSMauro Carvalho Chehab break; 25290c0d06caSMauro Carvalho Chehab 25300c0d06caSMauro Carvalho Chehab case Sliced_cc: 25310c0d06caSMauro Carvalho Chehab cx231xx_info("%s: set hanc registers\n", __func__); 25320c0d06caSMauro Carvalho Chehab status = 25330c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 25340c0d06caSMauro Carvalho Chehab break; 25350c0d06caSMauro Carvalho Chehab 25360c0d06caSMauro Carvalho Chehab case Raw_Video: 25370c0d06caSMauro Carvalho Chehab cx231xx_info("%s: set video registers\n", __func__); 25380c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 25390c0d06caSMauro Carvalho Chehab break; 25400c0d06caSMauro Carvalho Chehab 25410c0d06caSMauro Carvalho Chehab case TS1_serial_mode: 25420c0d06caSMauro Carvalho Chehab cx231xx_info("%s: set ts1 registers", __func__); 25430c0d06caSMauro Carvalho Chehab 25440c0d06caSMauro Carvalho Chehab if (dev->board.has_417) { 25450c0d06caSMauro Carvalho Chehab cx231xx_info(" MPEG\n"); 25460c0d06caSMauro Carvalho Chehab value &= 0xFFFFFFFC; 25470c0d06caSMauro Carvalho Chehab value |= 0x3; 25480c0d06caSMauro Carvalho Chehab 25490c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, value); 25500c0d06caSMauro Carvalho Chehab 25510c0d06caSMauro Carvalho Chehab val[0] = 0x04; 25520c0d06caSMauro Carvalho Chehab val[1] = 0xA3; 25530c0d06caSMauro Carvalho Chehab val[2] = 0x3B; 25540c0d06caSMauro Carvalho Chehab val[3] = 0x00; 25550c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 25560c0d06caSMauro Carvalho Chehab TS1_CFG_REG, val, 4); 25570c0d06caSMauro Carvalho Chehab 25580c0d06caSMauro Carvalho Chehab val[0] = 0x00; 25590c0d06caSMauro Carvalho Chehab val[1] = 0x08; 25600c0d06caSMauro Carvalho Chehab val[2] = 0x00; 25610c0d06caSMauro Carvalho Chehab val[3] = 0x08; 25620c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 25630c0d06caSMauro Carvalho Chehab TS1_LENGTH_REG, val, 4); 25640c0d06caSMauro Carvalho Chehab 25650c0d06caSMauro Carvalho Chehab } else { 25660c0d06caSMauro Carvalho Chehab cx231xx_info(" BDA\n"); 25670c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 25680c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); 25690c0d06caSMauro Carvalho Chehab } 25700c0d06caSMauro Carvalho Chehab break; 25710c0d06caSMauro Carvalho Chehab 25720c0d06caSMauro Carvalho Chehab case TS1_parallel_mode: 25730c0d06caSMauro Carvalho Chehab cx231xx_info("%s: set ts1 parallel mode registers\n", 25740c0d06caSMauro Carvalho Chehab __func__); 25750c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 25760c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 25770c0d06caSMauro Carvalho Chehab break; 25780c0d06caSMauro Carvalho Chehab } 25790c0d06caSMauro Carvalho Chehab } else { 25800c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 25810c0d06caSMauro Carvalho Chehab } 25820c0d06caSMauro Carvalho Chehab 25830c0d06caSMauro Carvalho Chehab return status; 25840c0d06caSMauro Carvalho Chehab } 25850c0d06caSMauro Carvalho Chehab 25860c0d06caSMauro Carvalho Chehab int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 25870c0d06caSMauro Carvalho Chehab { 25880c0d06caSMauro Carvalho Chehab int rc = -1; 25890c0d06caSMauro Carvalho Chehab u32 ep_mask = -1; 25900c0d06caSMauro Carvalho Chehab struct pcb_config *pcb_config; 25910c0d06caSMauro Carvalho Chehab 25920c0d06caSMauro Carvalho Chehab /* get EP for media type */ 25930c0d06caSMauro Carvalho Chehab pcb_config = (struct pcb_config *)&dev->current_pcb_config; 25940c0d06caSMauro Carvalho Chehab 25950c0d06caSMauro Carvalho Chehab if (pcb_config->config_num) { 25960c0d06caSMauro Carvalho Chehab switch (media_type) { 25970c0d06caSMauro Carvalho Chehab case Raw_Video: 25980c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 25990c0d06caSMauro Carvalho Chehab break; 26000c0d06caSMauro Carvalho Chehab case Audio: 26010c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 26020c0d06caSMauro Carvalho Chehab break; 26030c0d06caSMauro Carvalho Chehab case Vbi: 26040c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 26050c0d06caSMauro Carvalho Chehab break; 26060c0d06caSMauro Carvalho Chehab case Sliced_cc: 26070c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 26080c0d06caSMauro Carvalho Chehab break; 26090c0d06caSMauro Carvalho Chehab case TS1_serial_mode: 26100c0d06caSMauro Carvalho Chehab case TS1_parallel_mode: 26110c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 26120c0d06caSMauro Carvalho Chehab break; 26130c0d06caSMauro Carvalho Chehab case TS2: 26140c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 26150c0d06caSMauro Carvalho Chehab break; 26160c0d06caSMauro Carvalho Chehab } 26170c0d06caSMauro Carvalho Chehab } 26180c0d06caSMauro Carvalho Chehab 26190c0d06caSMauro Carvalho Chehab if (start) { 26200c0d06caSMauro Carvalho Chehab rc = cx231xx_initialize_stream_xfer(dev, media_type); 26210c0d06caSMauro Carvalho Chehab 26220c0d06caSMauro Carvalho Chehab if (rc < 0) 26230c0d06caSMauro Carvalho Chehab return rc; 26240c0d06caSMauro Carvalho Chehab 26250c0d06caSMauro Carvalho Chehab /* enable video capture */ 26260c0d06caSMauro Carvalho Chehab if (ep_mask > 0) 26270c0d06caSMauro Carvalho Chehab rc = cx231xx_start_stream(dev, ep_mask); 26280c0d06caSMauro Carvalho Chehab } else { 26290c0d06caSMauro Carvalho Chehab /* disable video capture */ 26300c0d06caSMauro Carvalho Chehab if (ep_mask > 0) 26310c0d06caSMauro Carvalho Chehab rc = cx231xx_stop_stream(dev, ep_mask); 26320c0d06caSMauro Carvalho Chehab } 26330c0d06caSMauro Carvalho Chehab 26340c0d06caSMauro Carvalho Chehab if (dev->mode == CX231XX_ANALOG_MODE) 26350c0d06caSMauro Carvalho Chehab ;/* do any in Analog mode */ 26360c0d06caSMauro Carvalho Chehab else 26370c0d06caSMauro Carvalho Chehab ;/* do any in digital mode */ 26380c0d06caSMauro Carvalho Chehab 26390c0d06caSMauro Carvalho Chehab return rc; 26400c0d06caSMauro Carvalho Chehab } 26410c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_capture_start); 26420c0d06caSMauro Carvalho Chehab 26430c0d06caSMauro Carvalho Chehab /***************************************************************************** 26440c0d06caSMauro Carvalho Chehab * G P I O B I T control functions * 26450c0d06caSMauro Carvalho Chehab ******************************************************************************/ 26460c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) 26470c0d06caSMauro Carvalho Chehab { 26480c0d06caSMauro Carvalho Chehab int status = 0; 26490c0d06caSMauro Carvalho Chehab 26500c0d06caSMauro Carvalho Chehab status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); 26510c0d06caSMauro Carvalho Chehab 26520c0d06caSMauro Carvalho Chehab return status; 26530c0d06caSMauro Carvalho Chehab } 26540c0d06caSMauro Carvalho Chehab 26550c0d06caSMauro Carvalho Chehab int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) 26560c0d06caSMauro Carvalho Chehab { 26570c0d06caSMauro Carvalho Chehab int status = 0; 26580c0d06caSMauro Carvalho Chehab 26590c0d06caSMauro Carvalho Chehab status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); 26600c0d06caSMauro Carvalho Chehab 26610c0d06caSMauro Carvalho Chehab return status; 26620c0d06caSMauro Carvalho Chehab } 26630c0d06caSMauro Carvalho Chehab 26640c0d06caSMauro Carvalho Chehab /* 26650c0d06caSMauro Carvalho Chehab * cx231xx_set_gpio_direction 26660c0d06caSMauro Carvalho Chehab * Sets the direction of the GPIO pin to input or output 26670c0d06caSMauro Carvalho Chehab * 26680c0d06caSMauro Carvalho Chehab * Parameters : 26690c0d06caSMauro Carvalho Chehab * pin_number : The GPIO Pin number to program the direction for 26700c0d06caSMauro Carvalho Chehab * from 0 to 31 26710c0d06caSMauro Carvalho Chehab * pin_value : The Direction of the GPIO Pin under reference. 26720c0d06caSMauro Carvalho Chehab * 0 = Input direction 26730c0d06caSMauro Carvalho Chehab * 1 = Output direction 26740c0d06caSMauro Carvalho Chehab */ 26750c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_direction(struct cx231xx *dev, 26760c0d06caSMauro Carvalho Chehab int pin_number, int pin_value) 26770c0d06caSMauro Carvalho Chehab { 26780c0d06caSMauro Carvalho Chehab int status = 0; 26790c0d06caSMauro Carvalho Chehab u32 value = 0; 26800c0d06caSMauro Carvalho Chehab 26810c0d06caSMauro Carvalho Chehab /* Check for valid pin_number - if 32 , bail out */ 26820c0d06caSMauro Carvalho Chehab if (pin_number >= 32) 26830c0d06caSMauro Carvalho Chehab return -EINVAL; 26840c0d06caSMauro Carvalho Chehab 26850c0d06caSMauro Carvalho Chehab /* input */ 26860c0d06caSMauro Carvalho Chehab if (pin_value == 0) 26870c0d06caSMauro Carvalho Chehab value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 26880c0d06caSMauro Carvalho Chehab else 26890c0d06caSMauro Carvalho Chehab value = dev->gpio_dir | (1 << pin_number); 26900c0d06caSMauro Carvalho Chehab 26910c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val); 26920c0d06caSMauro Carvalho Chehab 26930c0d06caSMauro Carvalho Chehab /* cache the value for future */ 26940c0d06caSMauro Carvalho Chehab dev->gpio_dir = value; 26950c0d06caSMauro Carvalho Chehab 26960c0d06caSMauro Carvalho Chehab return status; 26970c0d06caSMauro Carvalho Chehab } 26980c0d06caSMauro Carvalho Chehab 26990c0d06caSMauro Carvalho Chehab /* 27000c0d06caSMauro Carvalho Chehab * cx231xx_set_gpio_value 27010c0d06caSMauro Carvalho Chehab * Sets the value of the GPIO pin to Logic high or low. The Pin under 27020c0d06caSMauro Carvalho Chehab * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 27030c0d06caSMauro Carvalho Chehab * 27040c0d06caSMauro Carvalho Chehab * Parameters : 27050c0d06caSMauro Carvalho Chehab * pin_number : The GPIO Pin number to program the direction for 27060c0d06caSMauro Carvalho Chehab * pin_value : The value of the GPIO Pin under reference. 27070c0d06caSMauro Carvalho Chehab * 0 = set it to 0 27080c0d06caSMauro Carvalho Chehab * 1 = set it to 1 27090c0d06caSMauro Carvalho Chehab */ 27100c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 27110c0d06caSMauro Carvalho Chehab { 27120c0d06caSMauro Carvalho Chehab int status = 0; 27130c0d06caSMauro Carvalho Chehab u32 value = 0; 27140c0d06caSMauro Carvalho Chehab 27150c0d06caSMauro Carvalho Chehab /* Check for valid pin_number - if 0xFF , bail out */ 27160c0d06caSMauro Carvalho Chehab if (pin_number >= 32) 27170c0d06caSMauro Carvalho Chehab return -EINVAL; 27180c0d06caSMauro Carvalho Chehab 27190c0d06caSMauro Carvalho Chehab /* first do a sanity check - if the Pin is not output, make it output */ 27200c0d06caSMauro Carvalho Chehab if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 27210c0d06caSMauro Carvalho Chehab /* It was in input mode */ 27220c0d06caSMauro Carvalho Chehab value = dev->gpio_dir | (1 << pin_number); 27230c0d06caSMauro Carvalho Chehab dev->gpio_dir = value; 27240c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 27250c0d06caSMauro Carvalho Chehab (u8 *) &dev->gpio_val); 27260c0d06caSMauro Carvalho Chehab value = 0; 27270c0d06caSMauro Carvalho Chehab } 27280c0d06caSMauro Carvalho Chehab 27290c0d06caSMauro Carvalho Chehab if (pin_value == 0) 27300c0d06caSMauro Carvalho Chehab value = dev->gpio_val & (~(1 << pin_number)); 27310c0d06caSMauro Carvalho Chehab else 27320c0d06caSMauro Carvalho Chehab value = dev->gpio_val | (1 << pin_number); 27330c0d06caSMauro Carvalho Chehab 27340c0d06caSMauro Carvalho Chehab /* store the value */ 27350c0d06caSMauro Carvalho Chehab dev->gpio_val = value; 27360c0d06caSMauro Carvalho Chehab 27370c0d06caSMauro Carvalho Chehab /* toggle bit0 of GP_IO */ 27380c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 27390c0d06caSMauro Carvalho Chehab 27400c0d06caSMauro Carvalho Chehab return status; 27410c0d06caSMauro Carvalho Chehab } 27420c0d06caSMauro Carvalho Chehab 27430c0d06caSMauro Carvalho Chehab /***************************************************************************** 27440c0d06caSMauro Carvalho Chehab * G P I O I2C related functions * 27450c0d06caSMauro Carvalho Chehab ******************************************************************************/ 27460c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_start(struct cx231xx *dev) 27470c0d06caSMauro Carvalho Chehab { 27480c0d06caSMauro Carvalho Chehab int status = 0; 27490c0d06caSMauro Carvalho Chehab 27500c0d06caSMauro Carvalho Chehab /* set SCL to output 1 ; set SDA to output 1 */ 27510c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 27520c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 27530c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 27540c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 27550c0d06caSMauro Carvalho Chehab 27560c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 27570c0d06caSMauro Carvalho Chehab if (status < 0) 27580c0d06caSMauro Carvalho Chehab return -EINVAL; 27590c0d06caSMauro Carvalho Chehab 27600c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */ 27610c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 27620c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 27630c0d06caSMauro Carvalho Chehab 27640c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 27650c0d06caSMauro Carvalho Chehab if (status < 0) 27660c0d06caSMauro Carvalho Chehab return -EINVAL; 27670c0d06caSMauro Carvalho Chehab 27680c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 27690c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 27700c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 27710c0d06caSMauro Carvalho Chehab 27720c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 27730c0d06caSMauro Carvalho Chehab if (status < 0) 27740c0d06caSMauro Carvalho Chehab return -EINVAL; 27750c0d06caSMauro Carvalho Chehab 27760c0d06caSMauro Carvalho Chehab return status; 27770c0d06caSMauro Carvalho Chehab } 27780c0d06caSMauro Carvalho Chehab 27790c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_end(struct cx231xx *dev) 27800c0d06caSMauro Carvalho Chehab { 27810c0d06caSMauro Carvalho Chehab int status = 0; 27820c0d06caSMauro Carvalho Chehab 27830c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 27840c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 27850c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 27860c0d06caSMauro Carvalho Chehab 27870c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 27880c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 27890c0d06caSMauro Carvalho Chehab 27900c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 27910c0d06caSMauro Carvalho Chehab if (status < 0) 27920c0d06caSMauro Carvalho Chehab return -EINVAL; 27930c0d06caSMauro Carvalho Chehab 27940c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */ 27950c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 27960c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 27970c0d06caSMauro Carvalho Chehab 27980c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 27990c0d06caSMauro Carvalho Chehab if (status < 0) 28000c0d06caSMauro Carvalho Chehab return -EINVAL; 28010c0d06caSMauro Carvalho Chehab 28020c0d06caSMauro Carvalho Chehab /* set SCL to input ,release SCL cable control 28030c0d06caSMauro Carvalho Chehab set SDA to input ,release SDA cable control */ 28040c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 28050c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 28060c0d06caSMauro Carvalho Chehab 28070c0d06caSMauro Carvalho Chehab status = 28080c0d06caSMauro Carvalho Chehab cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 28090c0d06caSMauro Carvalho Chehab if (status < 0) 28100c0d06caSMauro Carvalho Chehab return -EINVAL; 28110c0d06caSMauro Carvalho Chehab 28120c0d06caSMauro Carvalho Chehab return status; 28130c0d06caSMauro Carvalho Chehab } 28140c0d06caSMauro Carvalho Chehab 28150c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 28160c0d06caSMauro Carvalho Chehab { 28170c0d06caSMauro Carvalho Chehab int status = 0; 28180c0d06caSMauro Carvalho Chehab u8 i; 28190c0d06caSMauro Carvalho Chehab 28200c0d06caSMauro Carvalho Chehab /* set SCL to output ; set SDA to output */ 28210c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 28220c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 28230c0d06caSMauro Carvalho Chehab 28240c0d06caSMauro Carvalho Chehab for (i = 0; i < 8; i++) { 28250c0d06caSMauro Carvalho Chehab if (((data << i) & 0x80) == 0) { 28260c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 28270c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28280c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 28290c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28300c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28310c0d06caSMauro Carvalho Chehab 28320c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */ 28330c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28340c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28350c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28360c0d06caSMauro Carvalho Chehab 28370c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */ 28380c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28390c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28400c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28410c0d06caSMauro Carvalho Chehab } else { 28420c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 1 */ 28430c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28440c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 28450c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28460c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28470c0d06caSMauro Carvalho Chehab 28480c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 1 */ 28490c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28500c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28510c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28520c0d06caSMauro Carvalho Chehab 28530c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 1 */ 28540c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28550c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28560c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28570c0d06caSMauro Carvalho Chehab } 28580c0d06caSMauro Carvalho Chehab } 28590c0d06caSMauro Carvalho Chehab return status; 28600c0d06caSMauro Carvalho Chehab } 28610c0d06caSMauro Carvalho Chehab 28620c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 28630c0d06caSMauro Carvalho Chehab { 28640c0d06caSMauro Carvalho Chehab u8 value = 0; 28650c0d06caSMauro Carvalho Chehab int status = 0; 28660c0d06caSMauro Carvalho Chehab u32 gpio_logic_value = 0; 28670c0d06caSMauro Carvalho Chehab u8 i; 28680c0d06caSMauro Carvalho Chehab 28690c0d06caSMauro Carvalho Chehab /* read byte */ 28700c0d06caSMauro Carvalho Chehab for (i = 0; i < 8; i++) { /* send write I2c addr */ 28710c0d06caSMauro Carvalho Chehab 28720c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to input */ 28730c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28740c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28750c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28760c0d06caSMauro Carvalho Chehab 28770c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to input */ 28780c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 28790c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 28800c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28810c0d06caSMauro Carvalho Chehab 28820c0d06caSMauro Carvalho Chehab /* get SDA data bit */ 28830c0d06caSMauro Carvalho Chehab gpio_logic_value = dev->gpio_val; 28840c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 28850c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 28860c0d06caSMauro Carvalho Chehab if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 28870c0d06caSMauro Carvalho Chehab value |= (1 << (8 - i - 1)); 28880c0d06caSMauro Carvalho Chehab 28890c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 28900c0d06caSMauro Carvalho Chehab } 28910c0d06caSMauro Carvalho Chehab 28920c0d06caSMauro Carvalho Chehab /* set SCL to output 0,finish the read latest SCL signal. 28930c0d06caSMauro Carvalho Chehab !!!set SDA to input, never to modify SDA direction at 28940c0d06caSMauro Carvalho Chehab the same times */ 28950c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 28960c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 28970c0d06caSMauro Carvalho Chehab 28980c0d06caSMauro Carvalho Chehab /* store the value */ 28990c0d06caSMauro Carvalho Chehab *buf = value & 0xff; 29000c0d06caSMauro Carvalho Chehab 29010c0d06caSMauro Carvalho Chehab return status; 29020c0d06caSMauro Carvalho Chehab } 29030c0d06caSMauro Carvalho Chehab 29040c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 29050c0d06caSMauro Carvalho Chehab { 29060c0d06caSMauro Carvalho Chehab int status = 0; 29070c0d06caSMauro Carvalho Chehab u32 gpio_logic_value = 0; 29080c0d06caSMauro Carvalho Chehab int nCnt = 10; 29090c0d06caSMauro Carvalho Chehab int nInit = nCnt; 29100c0d06caSMauro Carvalho Chehab 29110c0d06caSMauro Carvalho Chehab /* clock stretch; set SCL to input; set SDA to input; 29120c0d06caSMauro Carvalho Chehab get SCL value till SCL = 1 */ 29130c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 29140c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 29150c0d06caSMauro Carvalho Chehab 29160c0d06caSMauro Carvalho Chehab gpio_logic_value = dev->gpio_val; 29170c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29180c0d06caSMauro Carvalho Chehab 29190c0d06caSMauro Carvalho Chehab do { 29200c0d06caSMauro Carvalho Chehab msleep(2); 29210c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 29220c0d06caSMauro Carvalho Chehab (u8 *)&dev->gpio_val); 29230c0d06caSMauro Carvalho Chehab nCnt--; 29240c0d06caSMauro Carvalho Chehab } while (((dev->gpio_val & 29250c0d06caSMauro Carvalho Chehab (1 << dev->board.tuner_scl_gpio)) == 0) && 29260c0d06caSMauro Carvalho Chehab (nCnt > 0)); 29270c0d06caSMauro Carvalho Chehab 29280c0d06caSMauro Carvalho Chehab if (nCnt == 0) 29290c0d06caSMauro Carvalho Chehab cx231xx_info("No ACK after %d msec -GPIO I2C failed!", 29300c0d06caSMauro Carvalho Chehab nInit * 10); 29310c0d06caSMauro Carvalho Chehab 29320c0d06caSMauro Carvalho Chehab /* 29330c0d06caSMauro Carvalho Chehab * readAck 29340c0d06caSMauro Carvalho Chehab * through clock stretch, slave has given a SCL signal, 29350c0d06caSMauro Carvalho Chehab * so the SDA data can be directly read. 29360c0d06caSMauro Carvalho Chehab */ 29370c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29380c0d06caSMauro Carvalho Chehab 29390c0d06caSMauro Carvalho Chehab if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 29400c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29410c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 29420c0d06caSMauro Carvalho Chehab status = 0; 29430c0d06caSMauro Carvalho Chehab } else { 29440c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29450c0d06caSMauro Carvalho Chehab dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 29460c0d06caSMauro Carvalho Chehab } 29470c0d06caSMauro Carvalho Chehab 29480c0d06caSMauro Carvalho Chehab /* read SDA end, set the SCL to output 0, after this operation, 29490c0d06caSMauro Carvalho Chehab SDA direction can be changed. */ 29500c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value; 29510c0d06caSMauro Carvalho Chehab dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 29520c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29530c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29540c0d06caSMauro Carvalho Chehab 29550c0d06caSMauro Carvalho Chehab return status; 29560c0d06caSMauro Carvalho Chehab } 29570c0d06caSMauro Carvalho Chehab 29580c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 29590c0d06caSMauro Carvalho Chehab { 29600c0d06caSMauro Carvalho Chehab int status = 0; 29610c0d06caSMauro Carvalho Chehab 29620c0d06caSMauro Carvalho Chehab /* set SDA to ouput */ 29630c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 29640c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29650c0d06caSMauro Carvalho Chehab 29660c0d06caSMauro Carvalho Chehab /* set SCL = 0 (output); set SDA = 0 (output) */ 29670c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 29680c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29690c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29700c0d06caSMauro Carvalho Chehab 29710c0d06caSMauro Carvalho Chehab /* set SCL = 1 (output); set SDA = 0 (output) */ 29720c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 29730c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29740c0d06caSMauro Carvalho Chehab 29750c0d06caSMauro Carvalho Chehab /* set SCL = 0 (output); set SDA = 0 (output) */ 29760c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29770c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29780c0d06caSMauro Carvalho Chehab 29790c0d06caSMauro Carvalho Chehab /* set SDA to input,and then the slave will read data from SDA. */ 29800c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 29810c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29820c0d06caSMauro Carvalho Chehab 29830c0d06caSMauro Carvalho Chehab return status; 29840c0d06caSMauro Carvalho Chehab } 29850c0d06caSMauro Carvalho Chehab 29860c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 29870c0d06caSMauro Carvalho Chehab { 29880c0d06caSMauro Carvalho Chehab int status = 0; 29890c0d06caSMauro Carvalho Chehab 29900c0d06caSMauro Carvalho Chehab /* set scl to output ; set sda to input */ 29910c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 29920c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 29930c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29940c0d06caSMauro Carvalho Chehab 29950c0d06caSMauro Carvalho Chehab /* set scl to output 0; set sda to input */ 29960c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 29970c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 29980c0d06caSMauro Carvalho Chehab 29990c0d06caSMauro Carvalho Chehab /* set scl to output 1; set sda to input */ 30000c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 30010c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 30020c0d06caSMauro Carvalho Chehab 30030c0d06caSMauro Carvalho Chehab return status; 30040c0d06caSMauro Carvalho Chehab } 30050c0d06caSMauro Carvalho Chehab 30060c0d06caSMauro Carvalho Chehab /***************************************************************************** 30070c0d06caSMauro Carvalho Chehab * G P I O I2C related functions * 30080c0d06caSMauro Carvalho Chehab ******************************************************************************/ 30090c0d06caSMauro Carvalho Chehab /* cx231xx_gpio_i2c_read 30100c0d06caSMauro Carvalho Chehab * Function to read data from gpio based I2C interface 30110c0d06caSMauro Carvalho Chehab */ 30120c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 30130c0d06caSMauro Carvalho Chehab { 30140c0d06caSMauro Carvalho Chehab int status = 0; 30150c0d06caSMauro Carvalho Chehab int i = 0; 30160c0d06caSMauro Carvalho Chehab 30170c0d06caSMauro Carvalho Chehab /* get the lock */ 30180c0d06caSMauro Carvalho Chehab mutex_lock(&dev->gpio_i2c_lock); 30190c0d06caSMauro Carvalho Chehab 30200c0d06caSMauro Carvalho Chehab /* start */ 30210c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_start(dev); 30220c0d06caSMauro Carvalho Chehab 30230c0d06caSMauro Carvalho Chehab /* write dev_addr */ 30240c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 30250c0d06caSMauro Carvalho Chehab 30260c0d06caSMauro Carvalho Chehab /* readAck */ 30270c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_read_ack(dev); 30280c0d06caSMauro Carvalho Chehab 30290c0d06caSMauro Carvalho Chehab /* read data */ 30300c0d06caSMauro Carvalho Chehab for (i = 0; i < len; i++) { 30310c0d06caSMauro Carvalho Chehab /* read data */ 30320c0d06caSMauro Carvalho Chehab buf[i] = 0; 30330c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 30340c0d06caSMauro Carvalho Chehab 30350c0d06caSMauro Carvalho Chehab if ((i + 1) != len) { 30360c0d06caSMauro Carvalho Chehab /* only do write ack if we more length */ 30370c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_ack(dev); 30380c0d06caSMauro Carvalho Chehab } 30390c0d06caSMauro Carvalho Chehab } 30400c0d06caSMauro Carvalho Chehab 30410c0d06caSMauro Carvalho Chehab /* write NAK - inform reads are complete */ 30420c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_nak(dev); 30430c0d06caSMauro Carvalho Chehab 30440c0d06caSMauro Carvalho Chehab /* write end */ 30450c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_end(dev); 30460c0d06caSMauro Carvalho Chehab 30470c0d06caSMauro Carvalho Chehab /* release the lock */ 30480c0d06caSMauro Carvalho Chehab mutex_unlock(&dev->gpio_i2c_lock); 30490c0d06caSMauro Carvalho Chehab 30500c0d06caSMauro Carvalho Chehab return status; 30510c0d06caSMauro Carvalho Chehab } 30520c0d06caSMauro Carvalho Chehab 30530c0d06caSMauro Carvalho Chehab /* cx231xx_gpio_i2c_write 30540c0d06caSMauro Carvalho Chehab * Function to write data to gpio based I2C interface 30550c0d06caSMauro Carvalho Chehab */ 30560c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 30570c0d06caSMauro Carvalho Chehab { 30580c0d06caSMauro Carvalho Chehab int i = 0; 30590c0d06caSMauro Carvalho Chehab 30600c0d06caSMauro Carvalho Chehab /* get the lock */ 30610c0d06caSMauro Carvalho Chehab mutex_lock(&dev->gpio_i2c_lock); 30620c0d06caSMauro Carvalho Chehab 30630c0d06caSMauro Carvalho Chehab /* start */ 30640c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_start(dev); 30650c0d06caSMauro Carvalho Chehab 30660c0d06caSMauro Carvalho Chehab /* write dev_addr */ 30670c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 30680c0d06caSMauro Carvalho Chehab 30690c0d06caSMauro Carvalho Chehab /* read Ack */ 30700c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_read_ack(dev); 30710c0d06caSMauro Carvalho Chehab 30720c0d06caSMauro Carvalho Chehab for (i = 0; i < len; i++) { 30730c0d06caSMauro Carvalho Chehab /* Write data */ 30740c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_write_byte(dev, buf[i]); 30750c0d06caSMauro Carvalho Chehab 30760c0d06caSMauro Carvalho Chehab /* read Ack */ 30770c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_read_ack(dev); 30780c0d06caSMauro Carvalho Chehab } 30790c0d06caSMauro Carvalho Chehab 30800c0d06caSMauro Carvalho Chehab /* write End */ 30810c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_end(dev); 30820c0d06caSMauro Carvalho Chehab 30830c0d06caSMauro Carvalho Chehab /* release the lock */ 30840c0d06caSMauro Carvalho Chehab mutex_unlock(&dev->gpio_i2c_lock); 30850c0d06caSMauro Carvalho Chehab 30860c0d06caSMauro Carvalho Chehab return 0; 30870c0d06caSMauro Carvalho Chehab } 3088