174ba9207SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
20c0d06caSMauro Carvalho Chehab /*
30c0d06caSMauro Carvalho Chehab cx231xx_avcore.c - driver for Conexant Cx23100/101/102
40c0d06caSMauro Carvalho Chehab USB video capture devices
50c0d06caSMauro Carvalho Chehab
60c0d06caSMauro Carvalho Chehab Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
70c0d06caSMauro Carvalho Chehab
80c0d06caSMauro Carvalho Chehab This program contains the specific code to control the avdecoder chip and
90c0d06caSMauro Carvalho Chehab other related usb control functions for cx231xx based chipset.
100c0d06caSMauro Carvalho Chehab
110c0d06caSMauro Carvalho Chehab */
120c0d06caSMauro Carvalho Chehab
13589dadf2SMauro Carvalho Chehab #include "cx231xx.h"
140c0d06caSMauro Carvalho Chehab #include <linux/init.h>
150c0d06caSMauro Carvalho Chehab #include <linux/list.h>
160c0d06caSMauro Carvalho Chehab #include <linux/module.h>
170c0d06caSMauro Carvalho Chehab #include <linux/kernel.h>
180c0d06caSMauro Carvalho Chehab #include <linux/bitmap.h>
190c0d06caSMauro Carvalho Chehab #include <linux/i2c.h>
200c0d06caSMauro Carvalho Chehab #include <linux/mm.h>
210c0d06caSMauro Carvalho Chehab #include <linux/mutex.h>
220c0d06caSMauro Carvalho Chehab #include <media/tuner.h>
230c0d06caSMauro Carvalho Chehab
240c0d06caSMauro Carvalho Chehab #include <media/v4l2-common.h>
250c0d06caSMauro Carvalho Chehab #include <media/v4l2-ioctl.h>
260c0d06caSMauro Carvalho Chehab
270c0d06caSMauro Carvalho Chehab #include "cx231xx-dif.h"
280c0d06caSMauro Carvalho Chehab
290c0d06caSMauro Carvalho Chehab #define TUNER_MODE_FM_RADIO 0
300c0d06caSMauro Carvalho Chehab /******************************************************************************
310c0d06caSMauro Carvalho Chehab -: BLOCK ARRANGEMENT :-
320c0d06caSMauro Carvalho Chehab I2S block ----------------------|
330c0d06caSMauro Carvalho Chehab [I2S audio] |
340c0d06caSMauro Carvalho Chehab |
350c0d06caSMauro Carvalho Chehab Analog Front End --> Direct IF -|-> Cx25840 --> Audio
360c0d06caSMauro Carvalho Chehab [video & audio] | [Audio]
370c0d06caSMauro Carvalho Chehab |
380c0d06caSMauro Carvalho Chehab |-> Cx25840 --> Video
390c0d06caSMauro Carvalho Chehab [Video]
400c0d06caSMauro Carvalho Chehab
410c0d06caSMauro Carvalho Chehab *******************************************************************************/
420c0d06caSMauro Carvalho Chehab /******************************************************************************
430c0d06caSMauro Carvalho Chehab * VERVE REGISTER *
440c0d06caSMauro Carvalho Chehab * *
450c0d06caSMauro Carvalho Chehab ******************************************************************************/
verve_write_byte(struct cx231xx * dev,u8 saddr,u8 data)460c0d06caSMauro Carvalho Chehab static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
470c0d06caSMauro Carvalho Chehab {
480c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
490c0d06caSMauro Carvalho Chehab saddr, 1, data, 1);
500c0d06caSMauro Carvalho Chehab }
510c0d06caSMauro Carvalho Chehab
verve_read_byte(struct cx231xx * dev,u8 saddr,u8 * data)520c0d06caSMauro Carvalho Chehab static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
530c0d06caSMauro Carvalho Chehab {
540c0d06caSMauro Carvalho Chehab int status;
550c0d06caSMauro Carvalho Chehab u32 temp = 0;
560c0d06caSMauro Carvalho Chehab
570c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
580c0d06caSMauro Carvalho Chehab saddr, 1, &temp, 1);
590c0d06caSMauro Carvalho Chehab *data = (u8) temp;
600c0d06caSMauro Carvalho Chehab return status;
610c0d06caSMauro Carvalho Chehab }
initGPIO(struct cx231xx * dev)620c0d06caSMauro Carvalho Chehab void initGPIO(struct cx231xx *dev)
630c0d06caSMauro Carvalho Chehab {
640c0d06caSMauro Carvalho Chehab u32 _gpio_direction = 0;
650c0d06caSMauro Carvalho Chehab u32 value = 0;
660c0d06caSMauro Carvalho Chehab u8 val = 0;
670c0d06caSMauro Carvalho Chehab
680c0d06caSMauro Carvalho Chehab _gpio_direction = _gpio_direction & 0xFC0003FF;
690c0d06caSMauro Carvalho Chehab _gpio_direction = _gpio_direction | 0x03FDFC00;
700c0d06caSMauro Carvalho Chehab cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
710c0d06caSMauro Carvalho Chehab
720c0d06caSMauro Carvalho Chehab verve_read_byte(dev, 0x07, &val);
73336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
740c0d06caSMauro Carvalho Chehab verve_write_byte(dev, 0x07, 0xF4);
750c0d06caSMauro Carvalho Chehab verve_read_byte(dev, 0x07, &val);
76336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "verve_read_byte address0x07=0x%x\n", val);
770c0d06caSMauro Carvalho Chehab
780c0d06caSMauro Carvalho Chehab cx231xx_capture_start(dev, 1, Vbi);
790c0d06caSMauro Carvalho Chehab
800c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
810c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
820c0d06caSMauro Carvalho Chehab
830c0d06caSMauro Carvalho Chehab }
uninitGPIO(struct cx231xx * dev)840c0d06caSMauro Carvalho Chehab void uninitGPIO(struct cx231xx *dev)
850c0d06caSMauro Carvalho Chehab {
860c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 };
870c0d06caSMauro Carvalho Chehab
880c0d06caSMauro Carvalho Chehab cx231xx_capture_start(dev, 0, Vbi);
890c0d06caSMauro Carvalho Chehab verve_write_byte(dev, 0x07, 0x14);
900c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
910c0d06caSMauro Carvalho Chehab 0x68, value, 4);
920c0d06caSMauro Carvalho Chehab }
930c0d06caSMauro Carvalho Chehab
940c0d06caSMauro Carvalho Chehab /******************************************************************************
950c0d06caSMauro Carvalho Chehab * A F E - B L O C K C O N T R O L functions *
960c0d06caSMauro Carvalho Chehab * [ANALOG FRONT END] *
970c0d06caSMauro Carvalho Chehab ******************************************************************************/
afe_write_byte(struct cx231xx * dev,u16 saddr,u8 data)980c0d06caSMauro Carvalho Chehab static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
990c0d06caSMauro Carvalho Chehab {
1000c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
1010c0d06caSMauro Carvalho Chehab saddr, 2, data, 1);
1020c0d06caSMauro Carvalho Chehab }
1030c0d06caSMauro Carvalho Chehab
afe_read_byte(struct cx231xx * dev,u16 saddr,u8 * data)1040c0d06caSMauro Carvalho Chehab static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
1050c0d06caSMauro Carvalho Chehab {
1060c0d06caSMauro Carvalho Chehab int status;
1070c0d06caSMauro Carvalho Chehab u32 temp = 0;
1080c0d06caSMauro Carvalho Chehab
1090c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
1100c0d06caSMauro Carvalho Chehab saddr, 2, &temp, 1);
1110c0d06caSMauro Carvalho Chehab *data = (u8) temp;
1120c0d06caSMauro Carvalho Chehab return status;
1130c0d06caSMauro Carvalho Chehab }
1140c0d06caSMauro Carvalho Chehab
cx231xx_afe_init_super_block(struct cx231xx * dev,u32 ref_count)1150c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
1160c0d06caSMauro Carvalho Chehab {
1170c0d06caSMauro Carvalho Chehab int status = 0;
1180c0d06caSMauro Carvalho Chehab u8 temp = 0;
1190c0d06caSMauro Carvalho Chehab u8 afe_power_status = 0;
1200c0d06caSMauro Carvalho Chehab int i = 0;
1210c0d06caSMauro Carvalho Chehab
1220c0d06caSMauro Carvalho Chehab /* super block initialize */
1230c0d06caSMauro Carvalho Chehab temp = (u8) (ref_count & 0xff);
1240c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
1250c0d06caSMauro Carvalho Chehab if (status < 0)
1260c0d06caSMauro Carvalho Chehab return status;
1270c0d06caSMauro Carvalho Chehab
1280c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
1290c0d06caSMauro Carvalho Chehab if (status < 0)
1300c0d06caSMauro Carvalho Chehab return status;
1310c0d06caSMauro Carvalho Chehab
1320c0d06caSMauro Carvalho Chehab temp = (u8) ((ref_count & 0x300) >> 8);
1330c0d06caSMauro Carvalho Chehab temp |= 0x40;
1340c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
1350c0d06caSMauro Carvalho Chehab if (status < 0)
1360c0d06caSMauro Carvalho Chehab return status;
1370c0d06caSMauro Carvalho Chehab
1380c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
1390c0d06caSMauro Carvalho Chehab if (status < 0)
1400c0d06caSMauro Carvalho Chehab return status;
1410c0d06caSMauro Carvalho Chehab
1420c0d06caSMauro Carvalho Chehab /* enable pll */
1430c0d06caSMauro Carvalho Chehab while (afe_power_status != 0x18) {
1440c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
1450c0d06caSMauro Carvalho Chehab if (status < 0) {
146336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
147b7085c08SMauro Carvalho Chehab "%s: Init Super Block failed in send cmd\n",
148ed0e3729SMauro Carvalho Chehab __func__);
1490c0d06caSMauro Carvalho Chehab break;
1500c0d06caSMauro Carvalho Chehab }
1510c0d06caSMauro Carvalho Chehab
1520c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
1530c0d06caSMauro Carvalho Chehab afe_power_status &= 0xff;
1540c0d06caSMauro Carvalho Chehab if (status < 0) {
155336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
156b7085c08SMauro Carvalho Chehab "%s: Init Super Block failed in receive cmd\n",
157ed0e3729SMauro Carvalho Chehab __func__);
1580c0d06caSMauro Carvalho Chehab break;
1590c0d06caSMauro Carvalho Chehab }
1600c0d06caSMauro Carvalho Chehab i++;
1610c0d06caSMauro Carvalho Chehab if (i == 10) {
162336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
163b7085c08SMauro Carvalho Chehab "%s: Init Super Block force break in loop !!!!\n",
164ed0e3729SMauro Carvalho Chehab __func__);
1650c0d06caSMauro Carvalho Chehab status = -1;
1660c0d06caSMauro Carvalho Chehab break;
1670c0d06caSMauro Carvalho Chehab }
1680c0d06caSMauro Carvalho Chehab }
1690c0d06caSMauro Carvalho Chehab
1700c0d06caSMauro Carvalho Chehab if (status < 0)
1710c0d06caSMauro Carvalho Chehab return status;
1720c0d06caSMauro Carvalho Chehab
1730c0d06caSMauro Carvalho Chehab /* start tuning filter */
1740c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
1750c0d06caSMauro Carvalho Chehab if (status < 0)
1760c0d06caSMauro Carvalho Chehab return status;
1770c0d06caSMauro Carvalho Chehab
1780c0d06caSMauro Carvalho Chehab msleep(5);
1790c0d06caSMauro Carvalho Chehab
1800c0d06caSMauro Carvalho Chehab /* exit tuning */
1810c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
1820c0d06caSMauro Carvalho Chehab
1830c0d06caSMauro Carvalho Chehab return status;
1840c0d06caSMauro Carvalho Chehab }
1850c0d06caSMauro Carvalho Chehab
cx231xx_afe_init_channels(struct cx231xx * dev)1860c0d06caSMauro Carvalho Chehab int cx231xx_afe_init_channels(struct cx231xx *dev)
1870c0d06caSMauro Carvalho Chehab {
1880c0d06caSMauro Carvalho Chehab int status = 0;
1890c0d06caSMauro Carvalho Chehab
1900c0d06caSMauro Carvalho Chehab /* power up all 3 channels, clear pd_buffer */
1910c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
1920c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
1930c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
1940c0d06caSMauro Carvalho Chehab
1950c0d06caSMauro Carvalho Chehab /* Enable quantizer calibration */
1960c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
1970c0d06caSMauro Carvalho Chehab
1980c0d06caSMauro Carvalho Chehab /* channel initialize, force modulator (fb) reset */
1990c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
2000c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
2010c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
2020c0d06caSMauro Carvalho Chehab
2030c0d06caSMauro Carvalho Chehab /* start quantilizer calibration */
2040c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
2050c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
2060c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
2070c0d06caSMauro Carvalho Chehab msleep(5);
2080c0d06caSMauro Carvalho Chehab
2090c0d06caSMauro Carvalho Chehab /* exit modulator (fb) reset */
2100c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
2110c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
2120c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
2130c0d06caSMauro Carvalho Chehab
2140c0d06caSMauro Carvalho Chehab /* enable the pre_clamp in each channel for single-ended input */
2150c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
2160c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
2170c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
2180c0d06caSMauro Carvalho Chehab
2190c0d06caSMauro Carvalho Chehab /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
2200c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
2210c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
2220c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
2230c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
2240c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
2250c0d06caSMauro Carvalho Chehab ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
2260c0d06caSMauro Carvalho Chehab
2270c0d06caSMauro Carvalho Chehab /* dynamic element matching off */
2280c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
2290c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
2300c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
2310c0d06caSMauro Carvalho Chehab
2320c0d06caSMauro Carvalho Chehab return status;
2330c0d06caSMauro Carvalho Chehab }
2340c0d06caSMauro Carvalho Chehab
cx231xx_afe_setup_AFE_for_baseband(struct cx231xx * dev)2350c0d06caSMauro Carvalho Chehab int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
2360c0d06caSMauro Carvalho Chehab {
2370c0d06caSMauro Carvalho Chehab u8 c_value = 0;
2380c0d06caSMauro Carvalho Chehab int status = 0;
2390c0d06caSMauro Carvalho Chehab
2400c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
2410c0d06caSMauro Carvalho Chehab c_value &= (~(0x50));
2420c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
2430c0d06caSMauro Carvalho Chehab
2440c0d06caSMauro Carvalho Chehab return status;
2450c0d06caSMauro Carvalho Chehab }
2460c0d06caSMauro Carvalho Chehab
2470c0d06caSMauro Carvalho Chehab /*
2480c0d06caSMauro Carvalho Chehab The Analog Front End in Cx231xx has 3 channels. These
2490c0d06caSMauro Carvalho Chehab channels are used to share between different inputs
2500c0d06caSMauro Carvalho Chehab like tuner, s-video and composite inputs.
2510c0d06caSMauro Carvalho Chehab
2520c0d06caSMauro Carvalho Chehab channel 1 ----- pin 1 to pin4(in reg is 1-4)
2530c0d06caSMauro Carvalho Chehab channel 2 ----- pin 5 to pin8(in reg is 5-8)
2540c0d06caSMauro Carvalho Chehab channel 3 ----- pin 9 to pin 12(in reg is 9-11)
2550c0d06caSMauro Carvalho Chehab */
cx231xx_afe_set_input_mux(struct cx231xx * dev,u32 input_mux)2560c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
2570c0d06caSMauro Carvalho Chehab {
2580c0d06caSMauro Carvalho Chehab u8 ch1_setting = (u8) input_mux;
2590c0d06caSMauro Carvalho Chehab u8 ch2_setting = (u8) (input_mux >> 8);
2600c0d06caSMauro Carvalho Chehab u8 ch3_setting = (u8) (input_mux >> 16);
2610c0d06caSMauro Carvalho Chehab int status = 0;
2620c0d06caSMauro Carvalho Chehab u8 value = 0;
2630c0d06caSMauro Carvalho Chehab
2640c0d06caSMauro Carvalho Chehab if (ch1_setting != 0) {
2650c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
2660c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK;
2670c0d06caSMauro Carvalho Chehab value |= (ch1_setting - 1) << 4;
2680c0d06caSMauro Carvalho Chehab value &= 0xff;
2690c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH1, value);
2700c0d06caSMauro Carvalho Chehab }
2710c0d06caSMauro Carvalho Chehab
2720c0d06caSMauro Carvalho Chehab if (ch2_setting != 0) {
2730c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
2740c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK;
2750c0d06caSMauro Carvalho Chehab value |= (ch2_setting - 1) << 4;
2760c0d06caSMauro Carvalho Chehab value &= 0xff;
2770c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH2, value);
2780c0d06caSMauro Carvalho Chehab }
2790c0d06caSMauro Carvalho Chehab
2800c0d06caSMauro Carvalho Chehab /* For ch3_setting, the value to put in the register is
2810c0d06caSMauro Carvalho Chehab 7 less than the input number */
2820c0d06caSMauro Carvalho Chehab if (ch3_setting != 0) {
2830c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
2840c0d06caSMauro Carvalho Chehab value &= ~INPUT_SEL_MASK;
2850c0d06caSMauro Carvalho Chehab value |= (ch3_setting - 1) << 4;
2860c0d06caSMauro Carvalho Chehab value &= 0xff;
2870c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_INPUT_CH3, value);
2880c0d06caSMauro Carvalho Chehab }
2890c0d06caSMauro Carvalho Chehab
2900c0d06caSMauro Carvalho Chehab return status;
2910c0d06caSMauro Carvalho Chehab }
2920c0d06caSMauro Carvalho Chehab
cx231xx_afe_set_mode(struct cx231xx * dev,enum AFE_MODE mode)2930c0d06caSMauro Carvalho Chehab int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
2940c0d06caSMauro Carvalho Chehab {
2950c0d06caSMauro Carvalho Chehab int status = 0;
2960c0d06caSMauro Carvalho Chehab
2970c0d06caSMauro Carvalho Chehab /*
2980c0d06caSMauro Carvalho Chehab * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
2990c0d06caSMauro Carvalho Chehab * Currently, only baseband works.
3000c0d06caSMauro Carvalho Chehab */
3010c0d06caSMauro Carvalho Chehab
3020c0d06caSMauro Carvalho Chehab switch (mode) {
3030c0d06caSMauro Carvalho Chehab case AFE_MODE_LOW_IF:
3040c0d06caSMauro Carvalho Chehab cx231xx_Setup_AFE_for_LowIF(dev);
3050c0d06caSMauro Carvalho Chehab break;
3060c0d06caSMauro Carvalho Chehab case AFE_MODE_BASEBAND:
3070c0d06caSMauro Carvalho Chehab status = cx231xx_afe_setup_AFE_for_baseband(dev);
3080c0d06caSMauro Carvalho Chehab break;
3090c0d06caSMauro Carvalho Chehab case AFE_MODE_EU_HI_IF:
3100c0d06caSMauro Carvalho Chehab /* SetupAFEforEuHiIF(); */
3110c0d06caSMauro Carvalho Chehab break;
3120c0d06caSMauro Carvalho Chehab case AFE_MODE_US_HI_IF:
3130c0d06caSMauro Carvalho Chehab /* SetupAFEforUsHiIF(); */
3140c0d06caSMauro Carvalho Chehab break;
3150c0d06caSMauro Carvalho Chehab case AFE_MODE_JAPAN_HI_IF:
3160c0d06caSMauro Carvalho Chehab /* SetupAFEforJapanHiIF(); */
3170c0d06caSMauro Carvalho Chehab break;
3180c0d06caSMauro Carvalho Chehab }
3190c0d06caSMauro Carvalho Chehab
3200c0d06caSMauro Carvalho Chehab if ((mode != dev->afe_mode) &&
3210c0d06caSMauro Carvalho Chehab (dev->video_input == CX231XX_VMUX_TELEVISION))
3220c0d06caSMauro Carvalho Chehab status = cx231xx_afe_adjust_ref_count(dev,
3230c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION);
3240c0d06caSMauro Carvalho Chehab
3250c0d06caSMauro Carvalho Chehab dev->afe_mode = mode;
3260c0d06caSMauro Carvalho Chehab
3270c0d06caSMauro Carvalho Chehab return status;
3280c0d06caSMauro Carvalho Chehab }
3290c0d06caSMauro Carvalho Chehab
cx231xx_afe_update_power_control(struct cx231xx * dev,enum AV_MODE avmode)3300c0d06caSMauro Carvalho Chehab int cx231xx_afe_update_power_control(struct cx231xx *dev,
3310c0d06caSMauro Carvalho Chehab enum AV_MODE avmode)
3320c0d06caSMauro Carvalho Chehab {
3330c0d06caSMauro Carvalho Chehab u8 afe_power_status = 0;
3340c0d06caSMauro Carvalho Chehab int status = 0;
3350c0d06caSMauro Carvalho Chehab
3360c0d06caSMauro Carvalho Chehab switch (dev->model) {
3370c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_CARRAERA:
3380c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_250:
3390c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_SHELBY:
3400c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_250:
3410c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_253S:
3420c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_253S:
3430c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
3440c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_EXETER:
345dd2e7dd2SMatthias Schwarzott case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
3460c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
3470c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
3480c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
3490c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
3503ead1ba3SMatt Gomboc case CX231XX_BOARD_OTG102:
3510c0d06caSMauro Carvalho Chehab if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
3520c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
3530c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) {
3540c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN,
3550c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS |
3560c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL);
3570c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN,
3580c0d06caSMauro Carvalho Chehab &afe_power_status);
3590c0d06caSMauro Carvalho Chehab if (status < 0)
3600c0d06caSMauro Carvalho Chehab break;
3610c0d06caSMauro Carvalho Chehab }
3620c0d06caSMauro Carvalho Chehab
3630c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
3640c0d06caSMauro Carvalho Chehab 0x00);
3650c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
3660c0d06caSMauro Carvalho Chehab 0x00);
3670c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
3680c0d06caSMauro Carvalho Chehab 0x00);
3690c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_DIGITAL) {
3700c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
3710c0d06caSMauro Carvalho Chehab 0x70);
3720c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
3730c0d06caSMauro Carvalho Chehab 0x70);
3740c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
3750c0d06caSMauro Carvalho Chehab 0x70);
3760c0d06caSMauro Carvalho Chehab
3770c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN,
3780c0d06caSMauro Carvalho Chehab &afe_power_status);
3790c0d06caSMauro Carvalho Chehab afe_power_status |= FLD_PWRDN_PD_BANDGAP |
3800c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_BIAS |
3810c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_TUNECK;
3820c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, SUP_BLK_PWRDN,
3830c0d06caSMauro Carvalho Chehab afe_power_status);
3840c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
3850c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
3860c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) {
3870c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN,
3880c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS |
3890c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL);
3900c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN,
3910c0d06caSMauro Carvalho Chehab &afe_power_status);
3920c0d06caSMauro Carvalho Chehab if (status < 0)
3930c0d06caSMauro Carvalho Chehab break;
3940c0d06caSMauro Carvalho Chehab }
3950c0d06caSMauro Carvalho Chehab
3960c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
3970c0d06caSMauro Carvalho Chehab 0x00);
3980c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
3990c0d06caSMauro Carvalho Chehab 0x00);
4000c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
4010c0d06caSMauro Carvalho Chehab 0x00);
4020c0d06caSMauro Carvalho Chehab } else {
403336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Invalid AV mode input\n");
4040c0d06caSMauro Carvalho Chehab status = -1;
4050c0d06caSMauro Carvalho Chehab }
4060c0d06caSMauro Carvalho Chehab break;
4070c0d06caSMauro Carvalho Chehab default:
4080c0d06caSMauro Carvalho Chehab if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
4090c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
4100c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) {
4110c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN,
4120c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS |
4130c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL);
4140c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN,
4150c0d06caSMauro Carvalho Chehab &afe_power_status);
4160c0d06caSMauro Carvalho Chehab if (status < 0)
4170c0d06caSMauro Carvalho Chehab break;
4180c0d06caSMauro Carvalho Chehab }
4190c0d06caSMauro Carvalho Chehab
4200c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
4210c0d06caSMauro Carvalho Chehab 0x40);
4220c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
4230c0d06caSMauro Carvalho Chehab 0x40);
4240c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
4250c0d06caSMauro Carvalho Chehab 0x00);
4260c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_DIGITAL) {
4270c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
4280c0d06caSMauro Carvalho Chehab 0x70);
4290c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
4300c0d06caSMauro Carvalho Chehab 0x70);
4310c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
4320c0d06caSMauro Carvalho Chehab 0x70);
4330c0d06caSMauro Carvalho Chehab
4340c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN,
4350c0d06caSMauro Carvalho Chehab &afe_power_status);
4360c0d06caSMauro Carvalho Chehab afe_power_status |= FLD_PWRDN_PD_BANDGAP |
4370c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_BIAS |
4380c0d06caSMauro Carvalho Chehab FLD_PWRDN_PD_TUNECK;
4390c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, SUP_BLK_PWRDN,
4400c0d06caSMauro Carvalho Chehab afe_power_status);
4410c0d06caSMauro Carvalho Chehab } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
4420c0d06caSMauro Carvalho Chehab while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
4430c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL)) {
4440c0d06caSMauro Carvalho Chehab status = afe_write_byte(dev, SUP_BLK_PWRDN,
4450c0d06caSMauro Carvalho Chehab FLD_PWRDN_TUNING_BIAS |
4460c0d06caSMauro Carvalho Chehab FLD_PWRDN_ENABLE_PLL);
4470c0d06caSMauro Carvalho Chehab status |= afe_read_byte(dev, SUP_BLK_PWRDN,
4480c0d06caSMauro Carvalho Chehab &afe_power_status);
4490c0d06caSMauro Carvalho Chehab if (status < 0)
4500c0d06caSMauro Carvalho Chehab break;
4510c0d06caSMauro Carvalho Chehab }
4520c0d06caSMauro Carvalho Chehab
4530c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
4540c0d06caSMauro Carvalho Chehab 0x00);
4550c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
4560c0d06caSMauro Carvalho Chehab 0x00);
4570c0d06caSMauro Carvalho Chehab status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
4580c0d06caSMauro Carvalho Chehab 0x40);
4590c0d06caSMauro Carvalho Chehab } else {
460336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Invalid AV mode input\n");
4610c0d06caSMauro Carvalho Chehab status = -1;
4620c0d06caSMauro Carvalho Chehab }
4630c0d06caSMauro Carvalho Chehab } /* switch */
4640c0d06caSMauro Carvalho Chehab
4650c0d06caSMauro Carvalho Chehab return status;
4660c0d06caSMauro Carvalho Chehab }
4670c0d06caSMauro Carvalho Chehab
cx231xx_afe_adjust_ref_count(struct cx231xx * dev,u32 video_input)4680c0d06caSMauro Carvalho Chehab int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
4690c0d06caSMauro Carvalho Chehab {
4700c0d06caSMauro Carvalho Chehab u8 input_mode = 0;
4710c0d06caSMauro Carvalho Chehab u8 ntf_mode = 0;
4720c0d06caSMauro Carvalho Chehab int status = 0;
4730c0d06caSMauro Carvalho Chehab
4740c0d06caSMauro Carvalho Chehab dev->video_input = video_input;
4750c0d06caSMauro Carvalho Chehab
4760c0d06caSMauro Carvalho Chehab if (video_input == CX231XX_VMUX_TELEVISION) {
4770c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
4780c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
4790c0d06caSMauro Carvalho Chehab &ntf_mode);
4800c0d06caSMauro Carvalho Chehab } else {
4810c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
4820c0d06caSMauro Carvalho Chehab status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
4830c0d06caSMauro Carvalho Chehab &ntf_mode);
4840c0d06caSMauro Carvalho Chehab }
4850c0d06caSMauro Carvalho Chehab
4860c0d06caSMauro Carvalho Chehab input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
4870c0d06caSMauro Carvalho Chehab
4880c0d06caSMauro Carvalho Chehab switch (input_mode) {
4890c0d06caSMauro Carvalho Chehab case SINGLE_ENDED:
4900c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x23C;
4910c0d06caSMauro Carvalho Chehab break;
4920c0d06caSMauro Carvalho Chehab case LOW_IF:
4930c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x24C;
4940c0d06caSMauro Carvalho Chehab break;
4950c0d06caSMauro Carvalho Chehab case EU_IF:
4960c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x258;
4970c0d06caSMauro Carvalho Chehab break;
4980c0d06caSMauro Carvalho Chehab case US_IF:
4990c0d06caSMauro Carvalho Chehab dev->afe_ref_count = 0x260;
5000c0d06caSMauro Carvalho Chehab break;
5010c0d06caSMauro Carvalho Chehab default:
5020c0d06caSMauro Carvalho Chehab break;
5030c0d06caSMauro Carvalho Chehab }
5040c0d06caSMauro Carvalho Chehab
5050c0d06caSMauro Carvalho Chehab status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
5060c0d06caSMauro Carvalho Chehab
5070c0d06caSMauro Carvalho Chehab return status;
5080c0d06caSMauro Carvalho Chehab }
5090c0d06caSMauro Carvalho Chehab
5100c0d06caSMauro Carvalho Chehab /******************************************************************************
5110c0d06caSMauro Carvalho Chehab * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
5120c0d06caSMauro Carvalho Chehab ******************************************************************************/
vid_blk_write_byte(struct cx231xx * dev,u16 saddr,u8 data)5130c0d06caSMauro Carvalho Chehab static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
5140c0d06caSMauro Carvalho Chehab {
5150c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
5160c0d06caSMauro Carvalho Chehab saddr, 2, data, 1);
5170c0d06caSMauro Carvalho Chehab }
5180c0d06caSMauro Carvalho Chehab
vid_blk_read_byte(struct cx231xx * dev,u16 saddr,u8 * data)5190c0d06caSMauro Carvalho Chehab static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
5200c0d06caSMauro Carvalho Chehab {
5210c0d06caSMauro Carvalho Chehab int status;
5220c0d06caSMauro Carvalho Chehab u32 temp = 0;
5230c0d06caSMauro Carvalho Chehab
5240c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
5250c0d06caSMauro Carvalho Chehab saddr, 2, &temp, 1);
5260c0d06caSMauro Carvalho Chehab *data = (u8) temp;
5270c0d06caSMauro Carvalho Chehab return status;
5280c0d06caSMauro Carvalho Chehab }
5290c0d06caSMauro Carvalho Chehab
vid_blk_write_word(struct cx231xx * dev,u16 saddr,u32 data)5300c0d06caSMauro Carvalho Chehab static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
5310c0d06caSMauro Carvalho Chehab {
5320c0d06caSMauro Carvalho Chehab return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
5330c0d06caSMauro Carvalho Chehab saddr, 2, data, 4);
5340c0d06caSMauro Carvalho Chehab }
5350c0d06caSMauro Carvalho Chehab
vid_blk_read_word(struct cx231xx * dev,u16 saddr,u32 * data)5360c0d06caSMauro Carvalho Chehab static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
5370c0d06caSMauro Carvalho Chehab {
5380c0d06caSMauro Carvalho Chehab return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
5390c0d06caSMauro Carvalho Chehab saddr, 2, data, 4);
5400c0d06caSMauro Carvalho Chehab }
cx231xx_check_fw(struct cx231xx * dev)5410c0d06caSMauro Carvalho Chehab int cx231xx_check_fw(struct cx231xx *dev)
5420c0d06caSMauro Carvalho Chehab {
5430c0d06caSMauro Carvalho Chehab u8 temp = 0;
5440c0d06caSMauro Carvalho Chehab int status = 0;
5450c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
5460c0d06caSMauro Carvalho Chehab if (status < 0)
5470c0d06caSMauro Carvalho Chehab return status;
5480c0d06caSMauro Carvalho Chehab else
5490c0d06caSMauro Carvalho Chehab return temp;
5500c0d06caSMauro Carvalho Chehab
5510c0d06caSMauro Carvalho Chehab }
5520c0d06caSMauro Carvalho Chehab
cx231xx_set_video_input_mux(struct cx231xx * dev,u8 input)5530c0d06caSMauro Carvalho Chehab int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
5540c0d06caSMauro Carvalho Chehab {
5550c0d06caSMauro Carvalho Chehab int status = 0;
5560c0d06caSMauro Carvalho Chehab
5570c0d06caSMauro Carvalho Chehab switch (INPUT(input)->type) {
5580c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_COMPOSITE1:
5590c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_SVIDEO:
5600c0d06caSMauro Carvalho Chehab if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
5610c0d06caSMauro Carvalho Chehab (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
5620c0d06caSMauro Carvalho Chehab /* External AV */
5630c0d06caSMauro Carvalho Chehab status = cx231xx_set_power_mode(dev,
5640c0d06caSMauro Carvalho Chehab POLARIS_AVMODE_ENXTERNAL_AV);
5650c0d06caSMauro Carvalho Chehab if (status < 0) {
566336fea92SMauro Carvalho Chehab dev_err(dev->dev,
567b7085c08SMauro Carvalho Chehab "%s: Failed to set Power - errCode [%d]!\n",
5680c0d06caSMauro Carvalho Chehab __func__, status);
5690c0d06caSMauro Carvalho Chehab return status;
5700c0d06caSMauro Carvalho Chehab }
5710c0d06caSMauro Carvalho Chehab }
5720c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev,
5730c0d06caSMauro Carvalho Chehab INPUT(input)->type,
5740c0d06caSMauro Carvalho Chehab INPUT(input)->vmux);
5750c0d06caSMauro Carvalho Chehab break;
5760c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_TELEVISION:
5770c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_CABLE:
5780c0d06caSMauro Carvalho Chehab if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
5790c0d06caSMauro Carvalho Chehab (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
5800c0d06caSMauro Carvalho Chehab /* Tuner */
5810c0d06caSMauro Carvalho Chehab status = cx231xx_set_power_mode(dev,
5820c0d06caSMauro Carvalho Chehab POLARIS_AVMODE_ANALOGT_TV);
5830c0d06caSMauro Carvalho Chehab if (status < 0) {
584336fea92SMauro Carvalho Chehab dev_err(dev->dev,
585b7085c08SMauro Carvalho Chehab "%s: Failed to set Power - errCode [%d]!\n",
5860c0d06caSMauro Carvalho Chehab __func__, status);
5870c0d06caSMauro Carvalho Chehab return status;
5880c0d06caSMauro Carvalho Chehab }
5890c0d06caSMauro Carvalho Chehab }
5903c1ccbadSBrad Love switch (dev->model) { /* i2c device tuners */
5913c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx:
5923c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_935C:
5933c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_955Q:
5943c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_975:
5953c1ccbadSBrad Love case CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD:
5963c1ccbadSBrad Love status = cx231xx_set_decoder_video_input(dev,
5973c1ccbadSBrad Love CX231XX_VMUX_TELEVISION,
5983c1ccbadSBrad Love INPUT(input)->vmux);
5993c1ccbadSBrad Love break;
6003c1ccbadSBrad Love default:
6010c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271)
6020c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev,
6030c0d06caSMauro Carvalho Chehab CX231XX_VMUX_TELEVISION,
6040c0d06caSMauro Carvalho Chehab INPUT(input)->vmux);
6050c0d06caSMauro Carvalho Chehab else
6060c0d06caSMauro Carvalho Chehab status = cx231xx_set_decoder_video_input(dev,
6070c0d06caSMauro Carvalho Chehab CX231XX_VMUX_COMPOSITE1,
6080c0d06caSMauro Carvalho Chehab INPUT(input)->vmux);
6093c1ccbadSBrad Love break;
610149d65e5SZou Wei }
6110c0d06caSMauro Carvalho Chehab
6120c0d06caSMauro Carvalho Chehab break;
6130c0d06caSMauro Carvalho Chehab default:
614336fea92SMauro Carvalho Chehab dev_err(dev->dev, "%s: Unknown Input %d !\n",
6150c0d06caSMauro Carvalho Chehab __func__, INPUT(input)->type);
6160c0d06caSMauro Carvalho Chehab break;
6170c0d06caSMauro Carvalho Chehab }
6180c0d06caSMauro Carvalho Chehab
6190c0d06caSMauro Carvalho Chehab /* save the selection */
6200c0d06caSMauro Carvalho Chehab dev->video_input = input;
6210c0d06caSMauro Carvalho Chehab
6220c0d06caSMauro Carvalho Chehab return status;
6230c0d06caSMauro Carvalho Chehab }
6240c0d06caSMauro Carvalho Chehab
cx231xx_set_decoder_video_input(struct cx231xx * dev,u8 pin_type,u8 input)6250c0d06caSMauro Carvalho Chehab int cx231xx_set_decoder_video_input(struct cx231xx *dev,
6260c0d06caSMauro Carvalho Chehab u8 pin_type, u8 input)
6270c0d06caSMauro Carvalho Chehab {
6280c0d06caSMauro Carvalho Chehab int status = 0;
6290c0d06caSMauro Carvalho Chehab u32 value = 0;
6300c0d06caSMauro Carvalho Chehab
6310c0d06caSMauro Carvalho Chehab if (pin_type != dev->video_input) {
6320c0d06caSMauro Carvalho Chehab status = cx231xx_afe_adjust_ref_count(dev, pin_type);
6330c0d06caSMauro Carvalho Chehab if (status < 0) {
634336fea92SMauro Carvalho Chehab dev_err(dev->dev,
635b7085c08SMauro Carvalho Chehab "%s: adjust_ref_count :Failed to set AFE input mux - errCode [%d]!\n",
6360c0d06caSMauro Carvalho Chehab __func__, status);
6370c0d06caSMauro Carvalho Chehab return status;
6380c0d06caSMauro Carvalho Chehab }
6390c0d06caSMauro Carvalho Chehab }
6400c0d06caSMauro Carvalho Chehab
6410c0d06caSMauro Carvalho Chehab /* call afe block to set video inputs */
6420c0d06caSMauro Carvalho Chehab status = cx231xx_afe_set_input_mux(dev, input);
6430c0d06caSMauro Carvalho Chehab if (status < 0) {
644336fea92SMauro Carvalho Chehab dev_err(dev->dev,
645b7085c08SMauro Carvalho Chehab "%s: set_input_mux :Failed to set AFE input mux - errCode [%d]!\n",
6460c0d06caSMauro Carvalho Chehab __func__, status);
6470c0d06caSMauro Carvalho Chehab return status;
6480c0d06caSMauro Carvalho Chehab }
6490c0d06caSMauro Carvalho Chehab
6500c0d06caSMauro Carvalho Chehab switch (pin_type) {
6510c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_COMPOSITE1:
6520c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value);
6530c0d06caSMauro Carvalho Chehab value |= (0 << 13) | (1 << 4);
6540c0d06caSMauro Carvalho Chehab value &= ~(1 << 5);
6550c0d06caSMauro Carvalho Chehab
6560c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */
6570c0d06caSMauro Carvalho Chehab value &= (~(0x1ff8000));
6580c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
6590c0d06caSMauro Carvalho Chehab value |= 0x1000000;
6600c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value);
6610c0d06caSMauro Carvalho Chehab
6620c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value);
6630c0d06caSMauro Carvalho Chehab value |= (1 << 7);
6640c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value);
6650c0d06caSMauro Carvalho Chehab
6660c0d06caSMauro Carvalho Chehab /* Set output mode */
6670c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
6680c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
6690c0d06caSMauro Carvalho Chehab OUT_CTRL1,
6700c0d06caSMauro Carvalho Chehab FLD_OUT_MODE,
6710c0d06caSMauro Carvalho Chehab dev->board.output_mode);
6720c0d06caSMauro Carvalho Chehab
6730c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */
6740c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
6750c0d06caSMauro Carvalho Chehab if (status < 0) {
676336fea92SMauro Carvalho Chehab dev_err(dev->dev,
677b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
6780c0d06caSMauro Carvalho Chehab __func__, status);
6790c0d06caSMauro Carvalho Chehab return status;
6800c0d06caSMauro Carvalho Chehab }
6810c0d06caSMauro Carvalho Chehab
6820c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */
6830c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value);
6840c0d06caSMauro Carvalho Chehab
6850c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */
6860c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN;
6870c0d06caSMauro Carvalho Chehab
6880c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */
6890c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN;
6900c0d06caSMauro Carvalho Chehab
6910c0d06caSMauro Carvalho Chehab /* Write it back */
6920c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value);
6930c0d06caSMauro Carvalho Chehab
6940c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */
6950c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
6960c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
6970c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS,
6980c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1));
6990c0d06caSMauro Carvalho Chehab
7000c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */
7010c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
7020c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
7030c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE,
7040c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
7050c0d06caSMauro Carvalho Chehab break;
7060c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_SVIDEO:
7070c0d06caSMauro Carvalho Chehab /* Disable the use of DIF */
7080c0d06caSMauro Carvalho Chehab
7090c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value);
7100c0d06caSMauro Carvalho Chehab
7110c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */
7120c0d06caSMauro Carvalho Chehab value &= (~(0x1ff8000));
7130c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2
7140c0d06caSMauro Carvalho Chehab IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
7150c0d06caSMauro Carvalho Chehab value |= 0x1000010;
7160c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value);
7170c0d06caSMauro Carvalho Chehab
7180c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */
7190c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
7200c0d06caSMauro Carvalho Chehab if (status < 0) {
721336fea92SMauro Carvalho Chehab dev_err(dev->dev,
722b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
7230c0d06caSMauro Carvalho Chehab __func__, status);
7240c0d06caSMauro Carvalho Chehab return status;
7250c0d06caSMauro Carvalho Chehab }
7260c0d06caSMauro Carvalho Chehab
7270c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */
7280c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value);
7290c0d06caSMauro Carvalho Chehab
7300c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */
7310c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN;
7320c0d06caSMauro Carvalho Chehab
7330c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */
7340c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN;
7350c0d06caSMauro Carvalho Chehab
7360c0d06caSMauro Carvalho Chehab /* Write it back */
7370c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value);
7380c0d06caSMauro Carvalho Chehab
7390c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */
7400c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
7410c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
7420c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS,
7430c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1));
7440c0d06caSMauro Carvalho Chehab
7450c0d06caSMauro Carvalho Chehab /* Set YC input mode */
7460c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
7470c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
7480c0d06caSMauro Carvalho Chehab MODE_CTRL,
7490c0d06caSMauro Carvalho Chehab FLD_INPUT_MODE,
7500c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
7510c0d06caSMauro Carvalho Chehab
7520c0d06caSMauro Carvalho Chehab /* Chroma to ADC2 */
7530c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value);
7540c0d06caSMauro Carvalho Chehab value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
7550c0d06caSMauro Carvalho Chehab
7560c0d06caSMauro Carvalho Chehab /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
7570c0d06caSMauro Carvalho Chehab This sets them to use video
7580c0d06caSMauro Carvalho Chehab rather than audio. Only one of the two will be in use. */
7590c0d06caSMauro Carvalho Chehab value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
7600c0d06caSMauro Carvalho Chehab
7610c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value);
7620c0d06caSMauro Carvalho Chehab
7630c0d06caSMauro Carvalho Chehab status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
7640c0d06caSMauro Carvalho Chehab break;
7650c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_TELEVISION:
7660c0d06caSMauro Carvalho Chehab case CX231XX_VMUX_CABLE:
7670c0d06caSMauro Carvalho Chehab default:
7680c0d06caSMauro Carvalho Chehab /* TODO: Test if this is also needed for xc2028/xc3028 */
7690c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type == TUNER_XC5000) {
7700c0d06caSMauro Carvalho Chehab /* Disable the use of DIF */
7710c0d06caSMauro Carvalho Chehab
7720c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value);
7730c0d06caSMauro Carvalho Chehab value |= (0 << 13) | (1 << 4);
7740c0d06caSMauro Carvalho Chehab value &= ~(1 << 5);
7750c0d06caSMauro Carvalho Chehab
7760c0d06caSMauro Carvalho Chehab /* set [24:23] [22:15] to 0 */
7770c0d06caSMauro Carvalho Chehab value &= (~(0x1FF8000));
7780c0d06caSMauro Carvalho Chehab /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
7790c0d06caSMauro Carvalho Chehab value |= 0x1000000;
7800c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value);
7810c0d06caSMauro Carvalho Chehab
7820c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value);
7830c0d06caSMauro Carvalho Chehab value |= (1 << 7);
7840c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value);
7850c0d06caSMauro Carvalho Chehab
7860c0d06caSMauro Carvalho Chehab /* Set output mode */
7870c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
7880c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
7890c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_OUT_MODE,
7900c0d06caSMauro Carvalho Chehab dev->board.output_mode);
7910c0d06caSMauro Carvalho Chehab
7920c0d06caSMauro Carvalho Chehab /* Tell DIF object to go to baseband mode */
7930c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev,
7940c0d06caSMauro Carvalho Chehab DIF_USE_BASEBAND);
7950c0d06caSMauro Carvalho Chehab if (status < 0) {
796336fea92SMauro Carvalho Chehab dev_err(dev->dev,
797b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
7980c0d06caSMauro Carvalho Chehab __func__, status);
7990c0d06caSMauro Carvalho Chehab return status;
8000c0d06caSMauro Carvalho Chehab }
8010c0d06caSMauro Carvalho Chehab
8020c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */
8030c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value);
8040c0d06caSMauro Carvalho Chehab
8050c0d06caSMauro Carvalho Chehab /* enable the VBI_GATE_EN */
8060c0d06caSMauro Carvalho Chehab value |= FLD_VBI_GATE_EN;
8070c0d06caSMauro Carvalho Chehab
8080c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable */
8090c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN;
8100c0d06caSMauro Carvalho Chehab
8110c0d06caSMauro Carvalho Chehab /* Write it back */
8120c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value);
8130c0d06caSMauro Carvalho Chehab
8140c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */
8150c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
8160c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
8170c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS,
8180c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1));
8190c0d06caSMauro Carvalho Chehab
8200c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */
8210c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
8220c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
8230c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE,
8240c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE,
8250c0d06caSMauro Carvalho Chehab INPUT_MODE_CVBS_0));
8260c0d06caSMauro Carvalho Chehab } else {
8270c0d06caSMauro Carvalho Chehab /* Enable the DIF for the tuner */
8280c0d06caSMauro Carvalho Chehab
8290c0d06caSMauro Carvalho Chehab /* Reinitialize the DIF */
8300c0d06caSMauro Carvalho Chehab status = cx231xx_dif_set_standard(dev, dev->norm);
8310c0d06caSMauro Carvalho Chehab if (status < 0) {
832336fea92SMauro Carvalho Chehab dev_err(dev->dev,
833b7085c08SMauro Carvalho Chehab "%s: cx231xx_dif set to By pass mode- errCode [%d]!\n",
8340c0d06caSMauro Carvalho Chehab __func__, status);
8350c0d06caSMauro Carvalho Chehab return status;
8360c0d06caSMauro Carvalho Chehab }
8370c0d06caSMauro Carvalho Chehab
8380c0d06caSMauro Carvalho Chehab /* Make sure bypass is cleared */
8390c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
8400c0d06caSMauro Carvalho Chehab
8410c0d06caSMauro Carvalho Chehab /* Clear the bypass bit */
8420c0d06caSMauro Carvalho Chehab value &= ~FLD_DIF_DIF_BYPASS;
8430c0d06caSMauro Carvalho Chehab
8440c0d06caSMauro Carvalho Chehab /* Enable the use of the DIF block */
8450c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
8460c0d06caSMauro Carvalho Chehab
8470c0d06caSMauro Carvalho Chehab /* Read the DFE_CTRL1 register */
8480c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DFE_CTRL1, &value);
8490c0d06caSMauro Carvalho Chehab
8500c0d06caSMauro Carvalho Chehab /* Disable the VBI_GATE_EN */
8510c0d06caSMauro Carvalho Chehab value &= ~FLD_VBI_GATE_EN;
8520c0d06caSMauro Carvalho Chehab
8530c0d06caSMauro Carvalho Chehab /* Enable the auto-VGA enable, AGC, and
8540c0d06caSMauro Carvalho Chehab set the skip count to 2 */
8550c0d06caSMauro Carvalho Chehab value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
8560c0d06caSMauro Carvalho Chehab
8570c0d06caSMauro Carvalho Chehab /* Write it back */
8580c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value);
8590c0d06caSMauro Carvalho Chehab
8600c0d06caSMauro Carvalho Chehab /* Wait until AGC locks up */
8610c0d06caSMauro Carvalho Chehab msleep(1);
8620c0d06caSMauro Carvalho Chehab
8630c0d06caSMauro Carvalho Chehab /* Disable the auto-VGA enable AGC */
8640c0d06caSMauro Carvalho Chehab value &= ~(FLD_VGA_AUTO_EN);
8650c0d06caSMauro Carvalho Chehab
8660c0d06caSMauro Carvalho Chehab /* Write it back */
8670c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL1, value);
8680c0d06caSMauro Carvalho Chehab
8690c0d06caSMauro Carvalho Chehab /* Enable Polaris B0 AGC output */
8700c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, &value);
8710c0d06caSMauro Carvalho Chehab value |= (FLD_OEF_AGC_RF) |
8720c0d06caSMauro Carvalho Chehab (FLD_OEF_AGC_IFVGA) |
8730c0d06caSMauro Carvalho Chehab (FLD_OEF_AGC_IF);
8740c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, value);
8750c0d06caSMauro Carvalho Chehab
8760c0d06caSMauro Carvalho Chehab /* Set output mode */
8770c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
8780c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
8790c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_OUT_MODE,
8800c0d06caSMauro Carvalho Chehab dev->board.output_mode);
8810c0d06caSMauro Carvalho Chehab
8820c0d06caSMauro Carvalho Chehab /* Disable auto config of registers */
8830c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
8840c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
8850c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_ACFG_DIS,
8860c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_ACFG_DIS, 1));
8870c0d06caSMauro Carvalho Chehab
8880c0d06caSMauro Carvalho Chehab /* Set CVBS input mode */
8890c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
8900c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
8910c0d06caSMauro Carvalho Chehab MODE_CTRL, FLD_INPUT_MODE,
8920c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_INPUT_MODE,
8930c0d06caSMauro Carvalho Chehab INPUT_MODE_CVBS_0));
8940c0d06caSMauro Carvalho Chehab
8950c0d06caSMauro Carvalho Chehab /* Set some bits in AFE_CTRL so that channel 2 or 3
8960c0d06caSMauro Carvalho Chehab * is ready to receive audio */
8970c0d06caSMauro Carvalho Chehab /* Clear clamp for channels 2 and 3 (bit 16-17) */
8980c0d06caSMauro Carvalho Chehab /* Clear droop comp (bit 19-20) */
8990c0d06caSMauro Carvalho Chehab /* Set VGA_SEL (for audio control) (bit 7-8) */
9000c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL, &value);
9010c0d06caSMauro Carvalho Chehab
9020c0d06caSMauro Carvalho Chehab /*Set Func mode:01-DIF 10-baseband 11-YUV*/
9030c0d06caSMauro Carvalho Chehab value &= (~(FLD_FUNC_MODE));
9040c0d06caSMauro Carvalho Chehab value |= 0x800000;
9050c0d06caSMauro Carvalho Chehab
9060c0d06caSMauro Carvalho Chehab value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
9070c0d06caSMauro Carvalho Chehab
9080c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AFE_CTRL, value);
9090c0d06caSMauro Carvalho Chehab
9100c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) {
9110c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL,
9120c0d06caSMauro Carvalho Chehab &value);
9130c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL,
9140c0d06caSMauro Carvalho Chehab (value & 0xFFFFFFEF));
9150c0d06caSMauro Carvalho Chehab }
9160c0d06caSMauro Carvalho Chehab
9170c0d06caSMauro Carvalho Chehab break;
9180c0d06caSMauro Carvalho Chehab
9190c0d06caSMauro Carvalho Chehab }
9200c0d06caSMauro Carvalho Chehab break;
9210c0d06caSMauro Carvalho Chehab }
9220c0d06caSMauro Carvalho Chehab
9230c0d06caSMauro Carvalho Chehab /* Set raw VBI mode */
9240c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
9250c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
9260c0d06caSMauro Carvalho Chehab OUT_CTRL1, FLD_VBIHACTRAW_EN,
9270c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
9280c0d06caSMauro Carvalho Chehab
9290c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, OUT_CTRL1, &value);
9300c0d06caSMauro Carvalho Chehab if (value & 0x02) {
9310c0d06caSMauro Carvalho Chehab value |= (1 << 19);
9320c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, OUT_CTRL1, value);
9330c0d06caSMauro Carvalho Chehab }
9340c0d06caSMauro Carvalho Chehab
9350c0d06caSMauro Carvalho Chehab return status;
9360c0d06caSMauro Carvalho Chehab }
9370c0d06caSMauro Carvalho Chehab
cx231xx_enable656(struct cx231xx * dev)9380c0d06caSMauro Carvalho Chehab void cx231xx_enable656(struct cx231xx *dev)
9390c0d06caSMauro Carvalho Chehab {
9400c0d06caSMauro Carvalho Chehab u8 temp = 0;
9410c0d06caSMauro Carvalho Chehab /*enable TS1 data[0:7] as output to export 656*/
9420c0d06caSMauro Carvalho Chehab
9430c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
9440c0d06caSMauro Carvalho Chehab
9450c0d06caSMauro Carvalho Chehab /*enable TS1 clock as output to export 656*/
9460c0d06caSMauro Carvalho Chehab
9470c0d06caSMauro Carvalho Chehab vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
9480c0d06caSMauro Carvalho Chehab temp = temp|0x04;
9490c0d06caSMauro Carvalho Chehab
9500c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
9510c0d06caSMauro Carvalho Chehab }
9520c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_enable656);
9530c0d06caSMauro Carvalho Chehab
cx231xx_disable656(struct cx231xx * dev)9540c0d06caSMauro Carvalho Chehab void cx231xx_disable656(struct cx231xx *dev)
9550c0d06caSMauro Carvalho Chehab {
9560c0d06caSMauro Carvalho Chehab u8 temp = 0;
9570c0d06caSMauro Carvalho Chehab
9580c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
9590c0d06caSMauro Carvalho Chehab
9600c0d06caSMauro Carvalho Chehab vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
9610c0d06caSMauro Carvalho Chehab temp = temp&0xFB;
9620c0d06caSMauro Carvalho Chehab
9630c0d06caSMauro Carvalho Chehab vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
9640c0d06caSMauro Carvalho Chehab }
9650c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_disable656);
9660c0d06caSMauro Carvalho Chehab
9670c0d06caSMauro Carvalho Chehab /*
9680c0d06caSMauro Carvalho Chehab * Handle any video-mode specific overrides that are different
9690c0d06caSMauro Carvalho Chehab * on a per video standards basis after touching the MODE_CTRL
9700c0d06caSMauro Carvalho Chehab * register which resets many values for autodetect
9710c0d06caSMauro Carvalho Chehab */
cx231xx_do_mode_ctrl_overrides(struct cx231xx * dev)9720c0d06caSMauro Carvalho Chehab int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
9730c0d06caSMauro Carvalho Chehab {
9740c0d06caSMauro Carvalho Chehab int status = 0;
9750c0d06caSMauro Carvalho Chehab
976336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: 0x%x\n",
977ed0e3729SMauro Carvalho Chehab __func__, (unsigned int)dev->norm);
9780c0d06caSMauro Carvalho Chehab
9790c0d06caSMauro Carvalho Chehab /* Change the DFE_CTRL3 bp_percent to fix flagging */
9800c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
9810c0d06caSMauro Carvalho Chehab
9820c0d06caSMauro Carvalho Chehab if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
983336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: NTSC\n", __func__);
9840c0d06caSMauro Carvalho Chehab
9850c0d06caSMauro Carvalho Chehab /* Move the close caption lines out of active video,
9860c0d06caSMauro Carvalho Chehab adjust the active video start point */
9870c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
9880c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
9890c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
9900c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x18);
9910c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
9920c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
9930c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
9940c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT,
9950c0d06caSMauro Carvalho Chehab 0x1E7000);
9960c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
9970c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
9980c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
9990c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT,
10000c0d06caSMauro Carvalho Chehab 0x1C000000);
10010c0d06caSMauro Carvalho Chehab
10020c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10030c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10040c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL,
10050c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT,
10060c0d06caSMauro Carvalho Chehab cx231xx_set_field
10070c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x79));
10080c0d06caSMauro Carvalho Chehab
10090c0d06caSMauro Carvalho Chehab } else if (dev->norm & V4L2_STD_SECAM) {
1010336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: SECAM\n", __func__);
10110c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10120c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10130c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
10140c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x20);
10150c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10160c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10170c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
10180c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT,
10190c0d06caSMauro Carvalho Chehab cx231xx_set_field
10200c0d06caSMauro Carvalho Chehab (FLD_VACTIVE_CNT,
10210c0d06caSMauro Carvalho Chehab 0x244));
10220c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10230c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10240c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
10250c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT,
10260c0d06caSMauro Carvalho Chehab cx231xx_set_field
10270c0d06caSMauro Carvalho Chehab (FLD_V656BLANK_CNT,
10280c0d06caSMauro Carvalho Chehab 0x24));
10290c0d06caSMauro Carvalho Chehab /* Adjust the active video horizontal start point */
10300c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10310c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10320c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL,
10330c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT,
10340c0d06caSMauro Carvalho Chehab cx231xx_set_field
10350c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x85));
10360c0d06caSMauro Carvalho Chehab } else {
1037336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: PAL\n", __func__);
10380c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10390c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10400c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
10410c0d06caSMauro Carvalho Chehab FLD_VBLANK_CNT, 0x20);
10420c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10430c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10440c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
10450c0d06caSMauro Carvalho Chehab FLD_VACTIVE_CNT,
10460c0d06caSMauro Carvalho Chehab cx231xx_set_field
10470c0d06caSMauro Carvalho Chehab (FLD_VACTIVE_CNT,
10480c0d06caSMauro Carvalho Chehab 0x244));
10490c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10500c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10510c0d06caSMauro Carvalho Chehab VERT_TIM_CTRL,
10520c0d06caSMauro Carvalho Chehab FLD_V656BLANK_CNT,
10530c0d06caSMauro Carvalho Chehab cx231xx_set_field
10540c0d06caSMauro Carvalho Chehab (FLD_V656BLANK_CNT,
10550c0d06caSMauro Carvalho Chehab 0x24));
10560c0d06caSMauro Carvalho Chehab /* Adjust the active video horizontal start point */
10570c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
10580c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
10590c0d06caSMauro Carvalho Chehab HORIZ_TIM_CTRL,
10600c0d06caSMauro Carvalho Chehab FLD_HBLANK_CNT,
10610c0d06caSMauro Carvalho Chehab cx231xx_set_field
10620c0d06caSMauro Carvalho Chehab (FLD_HBLANK_CNT, 0x85));
10630c0d06caSMauro Carvalho Chehab
10640c0d06caSMauro Carvalho Chehab }
10650c0d06caSMauro Carvalho Chehab
10660c0d06caSMauro Carvalho Chehab return status;
10670c0d06caSMauro Carvalho Chehab }
10680c0d06caSMauro Carvalho Chehab
cx231xx_unmute_audio(struct cx231xx * dev)10690c0d06caSMauro Carvalho Chehab int cx231xx_unmute_audio(struct cx231xx *dev)
10700c0d06caSMauro Carvalho Chehab {
10710c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
10720c0d06caSMauro Carvalho Chehab }
10730c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
10740c0d06caSMauro Carvalho Chehab
stopAudioFirmware(struct cx231xx * dev)1075d4c06133SMauro Carvalho Chehab static int stopAudioFirmware(struct cx231xx *dev)
10760c0d06caSMauro Carvalho Chehab {
10770c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
10780c0d06caSMauro Carvalho Chehab }
10790c0d06caSMauro Carvalho Chehab
restartAudioFirmware(struct cx231xx * dev)1080d4c06133SMauro Carvalho Chehab static int restartAudioFirmware(struct cx231xx *dev)
10810c0d06caSMauro Carvalho Chehab {
10820c0d06caSMauro Carvalho Chehab return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
10830c0d06caSMauro Carvalho Chehab }
10840c0d06caSMauro Carvalho Chehab
cx231xx_set_audio_input(struct cx231xx * dev,u8 input)10850c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
10860c0d06caSMauro Carvalho Chehab {
10870c0d06caSMauro Carvalho Chehab int status = 0;
10880c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
10890c0d06caSMauro Carvalho Chehab
10900c0d06caSMauro Carvalho Chehab switch (INPUT(input)->amux) {
10910c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_VIDEO:
10920c0d06caSMauro Carvalho Chehab ainput = AUDIO_INPUT_TUNER_TV;
10930c0d06caSMauro Carvalho Chehab break;
10940c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_LINE_IN:
10950c0d06caSMauro Carvalho Chehab status = cx231xx_i2s_blk_set_audio_input(dev, input);
10960c0d06caSMauro Carvalho Chehab ainput = AUDIO_INPUT_LINE;
10970c0d06caSMauro Carvalho Chehab break;
10980c0d06caSMauro Carvalho Chehab default:
10990c0d06caSMauro Carvalho Chehab break;
11000c0d06caSMauro Carvalho Chehab }
11010c0d06caSMauro Carvalho Chehab
11020c0d06caSMauro Carvalho Chehab status = cx231xx_set_audio_decoder_input(dev, ainput);
11030c0d06caSMauro Carvalho Chehab
11040c0d06caSMauro Carvalho Chehab return status;
11050c0d06caSMauro Carvalho Chehab }
11060c0d06caSMauro Carvalho Chehab
cx231xx_set_audio_decoder_input(struct cx231xx * dev,enum AUDIO_INPUT audio_input)11070c0d06caSMauro Carvalho Chehab int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
11080c0d06caSMauro Carvalho Chehab enum AUDIO_INPUT audio_input)
11090c0d06caSMauro Carvalho Chehab {
11100c0d06caSMauro Carvalho Chehab u32 dwval;
11110c0d06caSMauro Carvalho Chehab int status;
11120c0d06caSMauro Carvalho Chehab u8 gen_ctrl;
11130c0d06caSMauro Carvalho Chehab u32 value = 0;
11140c0d06caSMauro Carvalho Chehab
11150c0d06caSMauro Carvalho Chehab /* Put it in soft reset */
11160c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
11170c0d06caSMauro Carvalho Chehab gen_ctrl |= 1;
11180c0d06caSMauro Carvalho Chehab status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
11190c0d06caSMauro Carvalho Chehab
11200c0d06caSMauro Carvalho Chehab switch (audio_input) {
11210c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_LINE:
11220c0d06caSMauro Carvalho Chehab /* setup AUD_IO control from Merlin paralle output */
11230c0d06caSMauro Carvalho Chehab value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
11240c0d06caSMauro Carvalho Chehab AUD_CHAN_SRC_PARALLEL);
11250c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
11260c0d06caSMauro Carvalho Chehab
11270c0d06caSMauro Carvalho Chehab /* setup input to Merlin, SRC2 connect to AC97
11280c0d06caSMauro Carvalho Chehab bypass upsample-by-2, slave mode, sony mode, left justify
11290c0d06caSMauro Carvalho Chehab adr 091c, dat 01000000 */
11300c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AC97_CTL, &dwval);
11310c0d06caSMauro Carvalho Chehab
11320c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AC97_CTL,
11330c0d06caSMauro Carvalho Chehab (dwval | FLD_AC97_UP2X_BYPASS));
11340c0d06caSMauro Carvalho Chehab
11350c0d06caSMauro Carvalho Chehab /* select the parallel1 and SRC3 */
11360c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, BAND_OUT_SEL,
11370c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
11380c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
11390c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
11400c0d06caSMauro Carvalho Chehab
11410c0d06caSMauro Carvalho Chehab /* unmute all, AC97 in, independence mode
11420c0d06caSMauro Carvalho Chehab adr 08d0, data 0x00063073 */
11430c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
11440c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
11450c0d06caSMauro Carvalho Chehab
11460c0d06caSMauro Carvalho Chehab /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
11470c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
11480c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_VOL_CTL,
11490c0d06caSMauro Carvalho Chehab (dwval | FLD_PATH1_AVC_THRESHOLD));
11500c0d06caSMauro Carvalho Chehab
11510c0d06caSMauro Carvalho Chehab /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
11520c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
11530c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_SC_CTL,
11540c0d06caSMauro Carvalho Chehab (dwval | FLD_PATH1_SC_THRESHOLD));
11550c0d06caSMauro Carvalho Chehab break;
11560c0d06caSMauro Carvalho Chehab
11570c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_TUNER_TV:
11580c0d06caSMauro Carvalho Chehab default:
11590c0d06caSMauro Carvalho Chehab status = stopAudioFirmware(dev);
11600c0d06caSMauro Carvalho Chehab /* Setup SRC sources and clocks */
11610c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, BAND_OUT_SEL,
11620c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
11630c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
11640c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
11650c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
11660c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
11670c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
11680c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
11690c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
11700c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
11710c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
11720c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
11730c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
11740c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
11750c0d06caSMauro Carvalho Chehab
11760c0d06caSMauro Carvalho Chehab /* Setup the AUD_IO control */
11770c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, AUD_IO_CTRL,
11780c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
11790c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
11800c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
11810c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
11820c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
11830c0d06caSMauro Carvalho Chehab
11840c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
11850c0d06caSMauro Carvalho Chehab
11860c0d06caSMauro Carvalho Chehab /* setAudioStandard(_audio_standard); */
11870c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
11880c0d06caSMauro Carvalho Chehab
11890c0d06caSMauro Carvalho Chehab status = restartAudioFirmware(dev);
11900c0d06caSMauro Carvalho Chehab
11910c0d06caSMauro Carvalho Chehab switch (dev->board.tuner_type) {
11920c0d06caSMauro Carvalho Chehab case TUNER_XC5000:
11930c0d06caSMauro Carvalho Chehab /* SIF passthrough at 28.6363 MHz sample rate */
11940c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
11950c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
11960c0d06caSMauro Carvalho Chehab CHIP_CTRL,
11970c0d06caSMauro Carvalho Chehab FLD_SIF_EN,
11980c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SIF_EN, 1));
11990c0d06caSMauro Carvalho Chehab break;
12000c0d06caSMauro Carvalho Chehab case TUNER_NXP_TDA18271:
12010c0d06caSMauro Carvalho Chehab /* Normal mode: SIF passthrough at 14.32 MHz */
12020c0d06caSMauro Carvalho Chehab status = cx231xx_read_modify_write_i2c_dword(dev,
12030c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS,
12040c0d06caSMauro Carvalho Chehab CHIP_CTRL,
12050c0d06caSMauro Carvalho Chehab FLD_SIF_EN,
12060c0d06caSMauro Carvalho Chehab cx231xx_set_field(FLD_SIF_EN, 0));
12070c0d06caSMauro Carvalho Chehab break;
12080c0d06caSMauro Carvalho Chehab default:
12093c1ccbadSBrad Love switch (dev->model) { /* i2c device tuners */
12103c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx:
12113c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_935C:
12123c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_955Q:
12133c1ccbadSBrad Love case CX231XX_BOARD_HAUPPAUGE_975:
12143c1ccbadSBrad Love case CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD:
12153c1ccbadSBrad Love /* TODO: Normal mode: SIF passthrough at 14.32 MHz?? */
12163c1ccbadSBrad Love break;
12173c1ccbadSBrad Love default:
12180c0d06caSMauro Carvalho Chehab /* This is just a casual suggestion to people adding
12190c0d06caSMauro Carvalho Chehab new boards in case they use a tuner type we don't
12200c0d06caSMauro Carvalho Chehab currently know about */
1221336fea92SMauro Carvalho Chehab dev_info(dev->dev,
12223b795d01SMauro Carvalho Chehab "Unknown tuner type configuring SIF");
12230c0d06caSMauro Carvalho Chehab break;
12240c0d06caSMauro Carvalho Chehab }
12253c1ccbadSBrad Love }
12260c0d06caSMauro Carvalho Chehab break;
12270c0d06caSMauro Carvalho Chehab
12280c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_TUNER_FM:
12290c0d06caSMauro Carvalho Chehab /* use SIF for FM radio
12300c0d06caSMauro Carvalho Chehab setupFM();
12310c0d06caSMauro Carvalho Chehab setAudioStandard(_audio_standard);
12320c0d06caSMauro Carvalho Chehab */
12330c0d06caSMauro Carvalho Chehab break;
12340c0d06caSMauro Carvalho Chehab
12350c0d06caSMauro Carvalho Chehab case AUDIO_INPUT_MUTE:
12360c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
12370c0d06caSMauro Carvalho Chehab break;
12380c0d06caSMauro Carvalho Chehab }
12390c0d06caSMauro Carvalho Chehab
12400c0d06caSMauro Carvalho Chehab /* Take it out of soft reset */
12410c0d06caSMauro Carvalho Chehab status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
12420c0d06caSMauro Carvalho Chehab gen_ctrl &= ~1;
12430c0d06caSMauro Carvalho Chehab status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
12440c0d06caSMauro Carvalho Chehab
12450c0d06caSMauro Carvalho Chehab return status;
12460c0d06caSMauro Carvalho Chehab }
12470c0d06caSMauro Carvalho Chehab
12480c0d06caSMauro Carvalho Chehab /******************************************************************************
12490c0d06caSMauro Carvalho Chehab * C H I P Specific C O N T R O L functions *
12500c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_init_ctrl_pin_status(struct cx231xx * dev)12510c0d06caSMauro Carvalho Chehab int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
12520c0d06caSMauro Carvalho Chehab {
12530c0d06caSMauro Carvalho Chehab u32 value;
12540c0d06caSMauro Carvalho Chehab int status = 0;
12550c0d06caSMauro Carvalho Chehab
12560c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, PIN_CTRL, &value);
12570c0d06caSMauro Carvalho Chehab value |= (~dev->board.ctl_pin_status_mask);
12580c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, PIN_CTRL, value);
12590c0d06caSMauro Carvalho Chehab
12600c0d06caSMauro Carvalho Chehab return status;
12610c0d06caSMauro Carvalho Chehab }
12620c0d06caSMauro Carvalho Chehab
cx231xx_set_agc_analog_digital_mux_select(struct cx231xx * dev,u8 analog_or_digital)12630c0d06caSMauro Carvalho Chehab int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
12640c0d06caSMauro Carvalho Chehab u8 analog_or_digital)
12650c0d06caSMauro Carvalho Chehab {
12661438d3c1SColin Ian King int status;
12670c0d06caSMauro Carvalho Chehab
12680c0d06caSMauro Carvalho Chehab /* first set the direction to output */
12690c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_direction(dev,
12700c0d06caSMauro Carvalho Chehab dev->board.
12710c0d06caSMauro Carvalho Chehab agc_analog_digital_select_gpio, 1);
12720c0d06caSMauro Carvalho Chehab
12730c0d06caSMauro Carvalho Chehab /* 0 - demod ; 1 - Analog mode */
12740c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_value(dev,
12750c0d06caSMauro Carvalho Chehab dev->board.agc_analog_digital_select_gpio,
12760c0d06caSMauro Carvalho Chehab analog_or_digital);
12770c0d06caSMauro Carvalho Chehab
12781871d718SMauro Carvalho Chehab if (status < 0)
12790c0d06caSMauro Carvalho Chehab return status;
12801871d718SMauro Carvalho Chehab
12811871d718SMauro Carvalho Chehab return 0;
12820c0d06caSMauro Carvalho Chehab }
12830c0d06caSMauro Carvalho Chehab
cx231xx_enable_i2c_port_3(struct cx231xx * dev,bool is_port_3)12840c0d06caSMauro Carvalho Chehab int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
12850c0d06caSMauro Carvalho Chehab {
12860c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 };
12870c0d06caSMauro Carvalho Chehab int status = 0;
12880c0d06caSMauro Carvalho Chehab bool current_is_port_3;
12890c0d06caSMauro Carvalho Chehab
1290a1f26765SMatthias Schwarzott /*
1291a1f26765SMatthias Schwarzott * Should this code check dev->port_3_switch_enabled first
1292a1f26765SMatthias Schwarzott * to skip unnecessary reading of the register?
1293a1f26765SMatthias Schwarzott * If yes, the flag dev->port_3_switch_enabled must be initialized
1294a1f26765SMatthias Schwarzott * correctly.
1295a1f26765SMatthias Schwarzott */
1296a1f26765SMatthias Schwarzott
12970c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
12980c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
12990c0d06caSMauro Carvalho Chehab if (status < 0)
13000c0d06caSMauro Carvalho Chehab return status;
13010c0d06caSMauro Carvalho Chehab
13020c0d06caSMauro Carvalho Chehab current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
13030c0d06caSMauro Carvalho Chehab
13040c0d06caSMauro Carvalho Chehab /* Just return, if already using the right port */
13050c0d06caSMauro Carvalho Chehab if (current_is_port_3 == is_port_3)
13060c0d06caSMauro Carvalho Chehab return 0;
13070c0d06caSMauro Carvalho Chehab
13080c0d06caSMauro Carvalho Chehab if (is_port_3)
13090c0d06caSMauro Carvalho Chehab value[0] |= I2C_DEMOD_EN;
13100c0d06caSMauro Carvalho Chehab else
13110c0d06caSMauro Carvalho Chehab value[0] &= ~I2C_DEMOD_EN;
13120c0d06caSMauro Carvalho Chehab
13130c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
13140c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
13150c0d06caSMauro Carvalho Chehab
1316a1f26765SMatthias Schwarzott /* remember status of the switch for usage in is_tuner */
1317a1f26765SMatthias Schwarzott if (status >= 0)
1318a1f26765SMatthias Schwarzott dev->port_3_switch_enabled = is_port_3;
1319a1f26765SMatthias Schwarzott
13200c0d06caSMauro Carvalho Chehab return status;
13210c0d06caSMauro Carvalho Chehab
13220c0d06caSMauro Carvalho Chehab }
13230c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
13240c0d06caSMauro Carvalho Chehab
update_HH_register_after_set_DIF(struct cx231xx * dev)13250c0d06caSMauro Carvalho Chehab void update_HH_register_after_set_DIF(struct cx231xx *dev)
13260c0d06caSMauro Carvalho Chehab {
13270c0d06caSMauro Carvalho Chehab /*
13280c0d06caSMauro Carvalho Chehab u8 status = 0;
13290c0d06caSMauro Carvalho Chehab u32 value = 0;
13300c0d06caSMauro Carvalho Chehab
13310c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
13320c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
13330c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
13340c0d06caSMauro Carvalho Chehab
13350c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
13360c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
13370c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
13380c0d06caSMauro Carvalho Chehab */
13390c0d06caSMauro Carvalho Chehab }
13400c0d06caSMauro Carvalho Chehab
cx231xx_dump_HH_reg(struct cx231xx * dev)13410c0d06caSMauro Carvalho Chehab void cx231xx_dump_HH_reg(struct cx231xx *dev)
13420c0d06caSMauro Carvalho Chehab {
13430c0d06caSMauro Carvalho Chehab u32 value = 0;
13440c0d06caSMauro Carvalho Chehab u16 i = 0;
13450c0d06caSMauro Carvalho Chehab
13460c0d06caSMauro Carvalho Chehab value = 0x45005390;
13470c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, 0x104, value);
13480c0d06caSMauro Carvalho Chehab
13490c0d06caSMauro Carvalho Chehab for (i = 0x100; i < 0x140; i++) {
13500c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value);
1351336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
13520c0d06caSMauro Carvalho Chehab i = i+3;
13530c0d06caSMauro Carvalho Chehab }
13540c0d06caSMauro Carvalho Chehab
13550c0d06caSMauro Carvalho Chehab for (i = 0x300; i < 0x400; i++) {
13560c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value);
1357336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
13580c0d06caSMauro Carvalho Chehab i = i+3;
13590c0d06caSMauro Carvalho Chehab }
13600c0d06caSMauro Carvalho Chehab
13610c0d06caSMauro Carvalho Chehab for (i = 0x400; i < 0x440; i++) {
13620c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, i, &value);
1363336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "reg0x%x=0x%x\n", i, value);
13640c0d06caSMauro Carvalho Chehab i = i+3;
13650c0d06caSMauro Carvalho Chehab }
13660c0d06caSMauro Carvalho Chehab
13670c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1368336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
13690c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
13700c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1371336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
13720c0d06caSMauro Carvalho Chehab }
13730c0d06caSMauro Carvalho Chehab
1374ed0e3729SMauro Carvalho Chehab #if 0
1375ed0e3729SMauro Carvalho Chehab static void cx231xx_dump_SC_reg(struct cx231xx *dev)
13760c0d06caSMauro Carvalho Chehab {
13770c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 };
1378336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s!\n", __func__);
13790c0d06caSMauro Carvalho Chehab
13800c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
13810c0d06caSMauro Carvalho Chehab value, 4);
1382336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1383b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
13840c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
13850c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
13860c0d06caSMauro Carvalho Chehab value, 4);
1387336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1388b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
13890c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
13900c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
13910c0d06caSMauro Carvalho Chehab value, 4);
1392336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1393b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
13940c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
13950c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
13960c0d06caSMauro Carvalho Chehab value, 4);
1397336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1398b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
13990c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14000c0d06caSMauro Carvalho Chehab
14010c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
14020c0d06caSMauro Carvalho Chehab value, 4);
1403336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1404b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
14050c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14060c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
14070c0d06caSMauro Carvalho Chehab value, 4);
1408336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1409b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
14100c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14110c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
14120c0d06caSMauro Carvalho Chehab value, 4);
1413336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1414b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
14150c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14160c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
14170c0d06caSMauro Carvalho Chehab value, 4);
1418336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1419b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
14200c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14210c0d06caSMauro Carvalho Chehab
14220c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
14230c0d06caSMauro Carvalho Chehab value, 4);
1424336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1425b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
14260c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14270c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
14280c0d06caSMauro Carvalho Chehab value, 4);
1429336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1430b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
14310c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14320c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
14330c0d06caSMauro Carvalho Chehab value, 4);
1434336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1435b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
14360c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14370c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
14380c0d06caSMauro Carvalho Chehab value, 4);
1439336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1440b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
14410c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14420c0d06caSMauro Carvalho Chehab
14430c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
14440c0d06caSMauro Carvalho Chehab value, 4);
1445336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1446b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
14470c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14480c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
14490c0d06caSMauro Carvalho Chehab value, 4);
1450336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1451b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
14520c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14530c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
14540c0d06caSMauro Carvalho Chehab value, 4);
1455336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1456b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
14570c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14580c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
14590c0d06caSMauro Carvalho Chehab value, 4);
1460336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1461b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
14620c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14630c0d06caSMauro Carvalho Chehab
14640c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
14650c0d06caSMauro Carvalho Chehab value, 4);
1466336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1467b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
14680c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14690c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
14700c0d06caSMauro Carvalho Chehab value, 4);
1471336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
1472b7085c08SMauro Carvalho Chehab "reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
14730c0d06caSMauro Carvalho Chehab value[1], value[2], value[3]);
14740c0d06caSMauro Carvalho Chehab }
1475ed0e3729SMauro Carvalho Chehab #endif
14760c0d06caSMauro Carvalho Chehab
cx231xx_Setup_AFE_for_LowIF(struct cx231xx * dev)14770c0d06caSMauro Carvalho Chehab void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
14780c0d06caSMauro Carvalho Chehab
14790c0d06caSMauro Carvalho Chehab {
14800c0d06caSMauro Carvalho Chehab u8 value = 0;
14810c0d06caSMauro Carvalho Chehab
14820c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_STATUS2_CH3, &value);
14830c0d06caSMauro Carvalho Chehab value = (value & 0xFE)|0x01;
14840c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_STATUS2_CH3, value);
14850c0d06caSMauro Carvalho Chehab
14860c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_STATUS2_CH3, &value);
14870c0d06caSMauro Carvalho Chehab value = (value & 0xFE)|0x00;
14880c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_STATUS2_CH3, value);
14890c0d06caSMauro Carvalho Chehab
14900c0d06caSMauro Carvalho Chehab
14910c0d06caSMauro Carvalho Chehab /*
14920c0d06caSMauro Carvalho Chehab config colibri to lo-if mode
14930c0d06caSMauro Carvalho Chehab
14940c0d06caSMauro Carvalho Chehab FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
14950c0d06caSMauro Carvalho Chehab the diff IF input by half,
14960c0d06caSMauro Carvalho Chehab
14970c0d06caSMauro Carvalho Chehab for low-if agc defect
14980c0d06caSMauro Carvalho Chehab */
14990c0d06caSMauro Carvalho Chehab
15000c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
15010c0d06caSMauro Carvalho Chehab value = (value & 0xFC)|0x00;
15020c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
15030c0d06caSMauro Carvalho Chehab
15040c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_INPUT_CH3, &value);
15050c0d06caSMauro Carvalho Chehab value = (value & 0xF9)|0x02;
15060c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_INPUT_CH3, value);
15070c0d06caSMauro Carvalho Chehab
15080c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
15090c0d06caSMauro Carvalho Chehab value = (value & 0xFB)|0x04;
15100c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
15110c0d06caSMauro Carvalho Chehab
15120c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
15130c0d06caSMauro Carvalho Chehab value = (value & 0xFC)|0x03;
15140c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
15150c0d06caSMauro Carvalho Chehab
15160c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
15170c0d06caSMauro Carvalho Chehab value = (value & 0xFB)|0x04;
15180c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
15190c0d06caSMauro Carvalho Chehab
15200c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
15210c0d06caSMauro Carvalho Chehab value = (value & 0xF8)|0x06;
15220c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
15230c0d06caSMauro Carvalho Chehab
15240c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
15250c0d06caSMauro Carvalho Chehab value = (value & 0x8F)|0x40;
15260c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
15270c0d06caSMauro Carvalho Chehab
15280c0d06caSMauro Carvalho Chehab afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
15290c0d06caSMauro Carvalho Chehab value = (value & 0xDF)|0x20;
15300c0d06caSMauro Carvalho Chehab afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
15310c0d06caSMauro Carvalho Chehab }
15320c0d06caSMauro Carvalho Chehab
cx231xx_set_Colibri_For_LowIF(struct cx231xx * dev,u32 if_freq,u8 spectral_invert,u32 mode)15330c0d06caSMauro Carvalho Chehab void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
15340c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode)
15350c0d06caSMauro Carvalho Chehab {
15360c0d06caSMauro Carvalho Chehab u32 colibri_carrier_offset = 0;
15370c0d06caSMauro Carvalho Chehab u32 func_mode = 0x01; /* Device has a DIF if this function is called */
15380c0d06caSMauro Carvalho Chehab u32 standard = 0;
15390c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 };
15400c0d06caSMauro Carvalho Chehab
1541336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Enter cx231xx_set_Colibri_For_LowIF()\n");
15420c0d06caSMauro Carvalho Chehab value[0] = (u8) 0x6F;
15430c0d06caSMauro Carvalho Chehab value[1] = (u8) 0x6F;
15440c0d06caSMauro Carvalho Chehab value[2] = (u8) 0x6F;
15450c0d06caSMauro Carvalho Chehab value[3] = (u8) 0x6F;
15460c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
15470c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
15480c0d06caSMauro Carvalho Chehab
15490c0d06caSMauro Carvalho Chehab /*Set colibri for low IF*/
15500c0d06caSMauro Carvalho Chehab cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
15510c0d06caSMauro Carvalho Chehab
15520c0d06caSMauro Carvalho Chehab /* Set C2HH for low IF operation.*/
15530c0d06caSMauro Carvalho Chehab standard = dev->norm;
15540c0d06caSMauro Carvalho Chehab cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
15550c0d06caSMauro Carvalho Chehab func_mode, standard);
15560c0d06caSMauro Carvalho Chehab
15570c0d06caSMauro Carvalho Chehab /* Get colibri offsets.*/
15580c0d06caSMauro Carvalho Chehab colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
15590c0d06caSMauro Carvalho Chehab standard);
15600c0d06caSMauro Carvalho Chehab
1561336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "colibri_carrier_offset=%d, standard=0x%x\n",
15620c0d06caSMauro Carvalho Chehab colibri_carrier_offset, standard);
15630c0d06caSMauro Carvalho Chehab
15640c0d06caSMauro Carvalho Chehab /* Set the band Pass filter for DIF*/
15650c0d06caSMauro Carvalho Chehab cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
15660c0d06caSMauro Carvalho Chehab spectral_invert, mode);
15670c0d06caSMauro Carvalho Chehab }
15680c0d06caSMauro Carvalho Chehab
cx231xx_Get_Colibri_CarrierOffset(u32 mode,u32 standerd)15690c0d06caSMauro Carvalho Chehab u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
15700c0d06caSMauro Carvalho Chehab {
15710c0d06caSMauro Carvalho Chehab u32 colibri_carrier_offset = 0;
15720c0d06caSMauro Carvalho Chehab
15730c0d06caSMauro Carvalho Chehab if (mode == TUNER_MODE_FM_RADIO) {
15740c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 1100000;
15750c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
15760c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 4832000; /*4.83MHz */
15770c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
15780c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 2700000; /*2.70MHz */
15790c0d06caSMauro Carvalho Chehab } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
15800c0d06caSMauro Carvalho Chehab | V4L2_STD_SECAM)) {
15810c0d06caSMauro Carvalho Chehab colibri_carrier_offset = 2100000; /*2.10MHz */
15820c0d06caSMauro Carvalho Chehab }
15830c0d06caSMauro Carvalho Chehab
15840c0d06caSMauro Carvalho Chehab return colibri_carrier_offset;
15850c0d06caSMauro Carvalho Chehab }
15860c0d06caSMauro Carvalho Chehab
cx231xx_set_DIF_bandpass(struct cx231xx * dev,u32 if_freq,u8 spectral_invert,u32 mode)15870c0d06caSMauro Carvalho Chehab void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
15880c0d06caSMauro Carvalho Chehab u8 spectral_invert, u32 mode)
15890c0d06caSMauro Carvalho Chehab {
15900c0d06caSMauro Carvalho Chehab unsigned long pll_freq_word;
15910c0d06caSMauro Carvalho Chehab u32 dif_misc_ctrl_value = 0;
15920c0d06caSMauro Carvalho Chehab u64 pll_freq_u64 = 0;
15930c0d06caSMauro Carvalho Chehab u32 i = 0;
15940c0d06caSMauro Carvalho Chehab
1595336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
15960c0d06caSMauro Carvalho Chehab if_freq, spectral_invert, mode);
15970c0d06caSMauro Carvalho Chehab
15980c0d06caSMauro Carvalho Chehab
15990c0d06caSMauro Carvalho Chehab if (mode == TUNER_MODE_FM_RADIO) {
16000c0d06caSMauro Carvalho Chehab pll_freq_word = 0x905A1CAC;
16010c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
16020c0d06caSMauro Carvalho Chehab
16030c0d06caSMauro Carvalho Chehab } else /*KSPROPERTY_TUNER_MODE_TV*/{
16040c0d06caSMauro Carvalho Chehab /* Calculate the PLL frequency word based on the adjusted if_freq*/
16050c0d06caSMauro Carvalho Chehab pll_freq_word = if_freq;
16060c0d06caSMauro Carvalho Chehab pll_freq_u64 = (u64)pll_freq_word << 28L;
16070c0d06caSMauro Carvalho Chehab do_div(pll_freq_u64, 50000000);
16080c0d06caSMauro Carvalho Chehab pll_freq_word = (u32)pll_freq_u64;
16090c0d06caSMauro Carvalho Chehab /*pll_freq_word = 0x3463497;*/
16100c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
16110c0d06caSMauro Carvalho Chehab
16120c0d06caSMauro Carvalho Chehab if (spectral_invert) {
16130c0d06caSMauro Carvalho Chehab if_freq -= 400000;
16140c0d06caSMauro Carvalho Chehab /* Enable Spectral Invert*/
16150c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, DIF_MISC_CTRL,
16160c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value);
16170c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
16180c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL,
16190c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value);
16200c0d06caSMauro Carvalho Chehab } else {
16210c0d06caSMauro Carvalho Chehab if_freq += 400000;
16220c0d06caSMauro Carvalho Chehab /* Disable Spectral Invert*/
16230c0d06caSMauro Carvalho Chehab vid_blk_read_word(dev, DIF_MISC_CTRL,
16240c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value);
16250c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
16260c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev, DIF_MISC_CTRL,
16270c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value);
16280c0d06caSMauro Carvalho Chehab }
16290c0d06caSMauro Carvalho Chehab
16300c0d06caSMauro Carvalho Chehab if_freq = (if_freq / 100000) * 100000;
16310c0d06caSMauro Carvalho Chehab
16320c0d06caSMauro Carvalho Chehab if (if_freq < 3000000)
16330c0d06caSMauro Carvalho Chehab if_freq = 3000000;
16340c0d06caSMauro Carvalho Chehab
16350c0d06caSMauro Carvalho Chehab if (if_freq > 16000000)
16360c0d06caSMauro Carvalho Chehab if_freq = 16000000;
16370c0d06caSMauro Carvalho Chehab }
16380c0d06caSMauro Carvalho Chehab
1639336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "Enter IF=%zu\n", ARRAY_SIZE(Dif_set_array));
16400c0d06caSMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) {
16410c0d06caSMauro Carvalho Chehab if (Dif_set_array[i].if_freq == if_freq) {
16420c0d06caSMauro Carvalho Chehab vid_blk_write_word(dev,
16430c0d06caSMauro Carvalho Chehab Dif_set_array[i].register_address, Dif_set_array[i].value);
16440c0d06caSMauro Carvalho Chehab }
16450c0d06caSMauro Carvalho Chehab }
16460c0d06caSMauro Carvalho Chehab }
16470c0d06caSMauro Carvalho Chehab
16480c0d06caSMauro Carvalho Chehab /******************************************************************************
16490c0d06caSMauro Carvalho Chehab * D I F - B L O C K C O N T R O L functions *
16500c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx * dev,u32 mode,u32 function_mode,u32 standard)16510c0d06caSMauro Carvalho Chehab int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
16520c0d06caSMauro Carvalho Chehab u32 function_mode, u32 standard)
16530c0d06caSMauro Carvalho Chehab {
16540c0d06caSMauro Carvalho Chehab int status = 0;
16550c0d06caSMauro Carvalho Chehab
16560c0d06caSMauro Carvalho Chehab
16570c0d06caSMauro Carvalho Chehab if (mode == V4L2_TUNER_RADIO) {
16580c0d06caSMauro Carvalho Chehab /* C2HH */
16590c0d06caSMauro Carvalho Chehab /* lo if big signal */
16600c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16610c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16620c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
16630c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */
16640c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16650c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16660c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
16670c0d06caSMauro Carvalho Chehab /* IF_MODE */
16680c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16690c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16700c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
16710c0d06caSMauro Carvalho Chehab /* no inv */
16720c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16730c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16740c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
16750c0d06caSMauro Carvalho Chehab } else if (standard != DIF_USE_BASEBAND) {
16760c0d06caSMauro Carvalho Chehab if (standard & V4L2_STD_MN) {
16770c0d06caSMauro Carvalho Chehab /* lo if big signal */
16780c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16790c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16800c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
16810c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */
16820c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16830c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16840c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
16850c0d06caSMauro Carvalho Chehab function_mode);
16860c0d06caSMauro Carvalho Chehab /* IF_MODE */
16870c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16880c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16890c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
16900c0d06caSMauro Carvalho Chehab /* no inv */
16910c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16920c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16930c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
16940c0d06caSMauro Carvalho Chehab /* 0x124, AUD_CHAN1_SRC = 0x3 */
16950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
16960c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
16970c0d06caSMauro Carvalho Chehab AUD_IO_CTRL, 0, 31, 0x00000003);
16980c0d06caSMauro Carvalho Chehab } else if ((standard == V4L2_STD_PAL_I) |
16990c0d06caSMauro Carvalho Chehab (standard & V4L2_STD_PAL_D) |
17000c0d06caSMauro Carvalho Chehab (standard & V4L2_STD_SECAM)) {
17010c0d06caSMauro Carvalho Chehab /* C2HH setup */
17020c0d06caSMauro Carvalho Chehab /* lo if big signal */
17030c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17040c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17050c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
17060c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */
17070c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17080c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17090c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
17100c0d06caSMauro Carvalho Chehab function_mode);
17110c0d06caSMauro Carvalho Chehab /* IF_MODE */
17120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17130c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17140c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
17150c0d06caSMauro Carvalho Chehab /* no inv */
17160c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17170c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17180c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
17190c0d06caSMauro Carvalho Chehab } else {
17200c0d06caSMauro Carvalho Chehab /* default PAL BG */
17210c0d06caSMauro Carvalho Chehab /* C2HH setup */
17220c0d06caSMauro Carvalho Chehab /* lo if big signal */
17230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17240c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17250c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
17260c0d06caSMauro Carvalho Chehab /* FUNC_MODE = DIF */
17270c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17280c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17290c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
17300c0d06caSMauro Carvalho Chehab function_mode);
17310c0d06caSMauro Carvalho Chehab /* IF_MODE */
17320c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17330c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17340c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
17350c0d06caSMauro Carvalho Chehab /* no inv */
17360c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev,
17370c0d06caSMauro Carvalho Chehab VID_BLK_I2C_ADDRESS, 32,
17380c0d06caSMauro Carvalho Chehab AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
17390c0d06caSMauro Carvalho Chehab }
17400c0d06caSMauro Carvalho Chehab }
17410c0d06caSMauro Carvalho Chehab
17420c0d06caSMauro Carvalho Chehab return status;
17430c0d06caSMauro Carvalho Chehab }
17440c0d06caSMauro Carvalho Chehab
cx231xx_dif_set_standard(struct cx231xx * dev,u32 standard)17450c0d06caSMauro Carvalho Chehab int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
17460c0d06caSMauro Carvalho Chehab {
17470c0d06caSMauro Carvalho Chehab int status = 0;
17480c0d06caSMauro Carvalho Chehab u32 dif_misc_ctrl_value = 0;
17490c0d06caSMauro Carvalho Chehab u32 func_mode = 0;
17500c0d06caSMauro Carvalho Chehab
1751336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: setStandard to %x\n", __func__, standard);
17520c0d06caSMauro Carvalho Chehab
17530c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
17540c0d06caSMauro Carvalho Chehab if (standard != DIF_USE_BASEBAND)
17550c0d06caSMauro Carvalho Chehab dev->norm = standard;
17560c0d06caSMauro Carvalho Chehab
17570c0d06caSMauro Carvalho Chehab switch (dev->model) {
17580c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_CARRAERA:
17590c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_250:
17600c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_SHELBY:
17610c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_250:
17620c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
17630c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_EXETER:
17643ead1ba3SMatt Gomboc case CX231XX_BOARD_OTG102:
17650c0d06caSMauro Carvalho Chehab func_mode = 0x03;
17660c0d06caSMauro Carvalho Chehab break;
17670c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDE_253S:
17680c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_CNXT_RDU_253S:
17690c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
17700c0d06caSMauro Carvalho Chehab case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
17710c0d06caSMauro Carvalho Chehab func_mode = 0x01;
17720c0d06caSMauro Carvalho Chehab break;
17730c0d06caSMauro Carvalho Chehab default:
17740c0d06caSMauro Carvalho Chehab func_mode = 0x01;
17750c0d06caSMauro Carvalho Chehab }
17760c0d06caSMauro Carvalho Chehab
17770c0d06caSMauro Carvalho Chehab status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
17780c0d06caSMauro Carvalho Chehab func_mode, standard);
17790c0d06caSMauro Carvalho Chehab
17800c0d06caSMauro Carvalho Chehab if (standard == DIF_USE_BASEBAND) { /* base band */
17810c0d06caSMauro Carvalho Chehab /* There is a different SRC_PHASE_INC value
17820c0d06caSMauro Carvalho Chehab for baseband vs. DIF */
17830c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
17840c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_MISC_CTRL,
17850c0d06caSMauro Carvalho Chehab &dif_misc_ctrl_value);
17860c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
17870c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL,
17880c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value);
17890c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_D) {
17900c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
17910c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
17920c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
17930c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
17940c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
17950c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
17960c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
17970c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800);
17980c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
17990c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380);
18000c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18010c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
18020c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18030c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
18040c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18050c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
18060c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18070c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31,
18080c0d06caSMauro Carvalho Chehab 0x26001700);
18090c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18100c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31,
18110c0d06caSMauro Carvalho Chehab 0x00002660);
18120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18130c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31,
18140c0d06caSMauro Carvalho Chehab 0x72500800);
18150c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18160c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31,
18170c0d06caSMauro Carvalho Chehab 0x27000100);
18180c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18190c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
18200c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18210c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31,
18220c0d06caSMauro Carvalho Chehab 0x00000000);
18230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18240c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31,
18250c0d06caSMauro Carvalho Chehab 0x1befbf06);
18260c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18270c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31,
18280c0d06caSMauro Carvalho Chehab 0x000035e8);
18290c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18300c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000);
18310c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
18320c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
18330c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11;
18340c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_I) {
18350c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18360c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
18370c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18380c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
18390c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18400c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
18410c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18420c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800);
18430c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18440c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380);
18450c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18460c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
18470c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18480c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
18490c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18500c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
18510c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18520c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31,
18530c0d06caSMauro Carvalho Chehab 0x26001700);
18540c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18550c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31,
18560c0d06caSMauro Carvalho Chehab 0x00002660);
18570c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18580c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31,
18590c0d06caSMauro Carvalho Chehab 0x72500800);
18600c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18610c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31,
18620c0d06caSMauro Carvalho Chehab 0x27000100);
18630c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18640c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
18650c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18660c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31,
18670c0d06caSMauro Carvalho Chehab 0x00000000);
18680c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18690c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31,
18700c0d06caSMauro Carvalho Chehab 0x1befbf06);
18710c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18720c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31,
18730c0d06caSMauro Carvalho Chehab 0x000035e8);
18740c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
18750c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000);
18760c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
18770c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
18780c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a033F11;
18790c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_PAL_M) {
18800c0d06caSMauro Carvalho Chehab /* improved Low Frequency Phase Noise */
18810c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
18820c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
18830c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
18840c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
18850c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
18860c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
18870c0d06caSMauro Carvalho Chehab 0x26001700);
18880c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
18890c0d06caSMauro Carvalho Chehab 0x00002660);
18900c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
18910c0d06caSMauro Carvalho Chehab 0x72500800);
18920c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
18930c0d06caSMauro Carvalho Chehab 0x27000100);
18940c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
18950c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
18960c0d06caSMauro Carvalho Chehab 0x009f50c1);
18970c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
18980c0d06caSMauro Carvalho Chehab 0x1befbf06);
18990c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
19000c0d06caSMauro Carvalho Chehab 0x000035e8);
19010c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
19020c0d06caSMauro Carvalho Chehab 0x00000000);
19030c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
19040c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
19050c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3A0A3F10;
19060c0d06caSMauro Carvalho Chehab } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
19070c0d06caSMauro Carvalho Chehab /* improved Low Frequency Phase Noise */
19080c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
19090c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
19100c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
19110c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
19120c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
19130c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
19140c0d06caSMauro Carvalho Chehab 0x26001700);
19150c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
19160c0d06caSMauro Carvalho Chehab 0x00002660);
19170c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
19180c0d06caSMauro Carvalho Chehab 0x72500800);
19190c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
19200c0d06caSMauro Carvalho Chehab 0x27000100);
19210c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
19220c0d06caSMauro Carvalho Chehab 0x012c405d);
19230c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
19240c0d06caSMauro Carvalho Chehab 0x009f50c1);
19250c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
19260c0d06caSMauro Carvalho Chehab 0x1befbf06);
19270c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
19280c0d06caSMauro Carvalho Chehab 0x000035e8);
19290c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
19300c0d06caSMauro Carvalho Chehab 0x00000000);
19310c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
19320c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
19330c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = 0x3A093F10;
19340c0d06caSMauro Carvalho Chehab } else if (standard &
19350c0d06caSMauro Carvalho Chehab (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
19360c0d06caSMauro Carvalho Chehab V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
19370c0d06caSMauro Carvalho Chehab
19380c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19390c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
19400c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19410c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
19420c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19430c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
19440c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19450c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800);
19460c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19470c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x888C0380);
19480c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19490c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
19500c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19510c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
19520c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19530c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
19540c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19550c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31,
19560c0d06caSMauro Carvalho Chehab 0x26001700);
19570c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19580c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31,
19590c0d06caSMauro Carvalho Chehab 0x00002660);
19600c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19610c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31,
19620c0d06caSMauro Carvalho Chehab 0x27000100);
19630c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19640c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
19650c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19660c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31,
19670c0d06caSMauro Carvalho Chehab 0x00000000);
19680c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19690c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31,
19700c0d06caSMauro Carvalho Chehab 0x1befbf06);
19710c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19720c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31,
19730c0d06caSMauro Carvalho Chehab 0x000035e8);
19740c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19750c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000);
19760c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19770c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31,
19780c0d06caSMauro Carvalho Chehab 0xf4000000);
19790c0d06caSMauro Carvalho Chehab
19800c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
19810c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
19820c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11;
19830c0d06caSMauro Carvalho Chehab } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
19840c0d06caSMauro Carvalho Chehab /* Is it SECAM_L1? */
19850c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19860c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
19870c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19880c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
19890c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19900c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
19910c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19920c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800);
19930c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19940c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x888C0380);
19950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19960c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
19970c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
19980c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
19990c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20000c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
20010c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20020c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31,
20030c0d06caSMauro Carvalho Chehab 0x26001700);
20040c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20050c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31,
20060c0d06caSMauro Carvalho Chehab 0x00002660);
20070c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20080c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31,
20090c0d06caSMauro Carvalho Chehab 0x27000100);
20100c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20110c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
20120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20130c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31,
20140c0d06caSMauro Carvalho Chehab 0x00000000);
20150c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20160c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31,
20170c0d06caSMauro Carvalho Chehab 0x1befbf06);
20180c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20190c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31,
20200c0d06caSMauro Carvalho Chehab 0x000035e8);
20210c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20220c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000);
20230c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20240c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31,
20250c0d06caSMauro Carvalho Chehab 0xf2560000);
20260c0d06caSMauro Carvalho Chehab
20270c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
20280c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
20290c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a023F11;
20300c0d06caSMauro Carvalho Chehab
20310c0d06caSMauro Carvalho Chehab } else if (standard & V4L2_STD_NTSC_M) {
20320c0d06caSMauro Carvalho Chehab /* V4L2_STD_NTSC_M (75 IRE Setup) Or
20330c0d06caSMauro Carvalho Chehab V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
20340c0d06caSMauro Carvalho Chehab
20350c0d06caSMauro Carvalho Chehab /* For NTSC the centre frequency of video coming out of
20360c0d06caSMauro Carvalho Chehab sidewinder is around 7.1MHz or 3.6MHz depending on the
20370c0d06caSMauro Carvalho Chehab spectral inversion. so for a non spectrally inverted channel
20380c0d06caSMauro Carvalho Chehab the pll freq word is 0x03420c49
20390c0d06caSMauro Carvalho Chehab */
20400c0d06caSMauro Carvalho Chehab
20410c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
20420c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
20430c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
20440c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
20450c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
20460c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
20470c0d06caSMauro Carvalho Chehab 0x26001700);
20480c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
20490c0d06caSMauro Carvalho Chehab 0x00002660);
20500c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
20510c0d06caSMauro Carvalho Chehab 0x04000800);
20520c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
20530c0d06caSMauro Carvalho Chehab 0x27000100);
20540c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
20550c0d06caSMauro Carvalho Chehab
20560c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
20570c0d06caSMauro Carvalho Chehab 0x009f50c1);
20580c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
20590c0d06caSMauro Carvalho Chehab 0x1befbf06);
20600c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
20610c0d06caSMauro Carvalho Chehab 0x000035e8);
20620c0d06caSMauro Carvalho Chehab
20630c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
20640c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
20650c0d06caSMauro Carvalho Chehab 0xC2262600);
20660c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
20670c0d06caSMauro Carvalho Chehab
20680c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
20690c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
20700c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a003F10;
20710c0d06caSMauro Carvalho Chehab } else {
20720c0d06caSMauro Carvalho Chehab /* default PAL BG */
20730c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20740c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
20750c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20760c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
20770c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20780c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
20790c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20800c0d06caSMauro Carvalho Chehab DIF_PLL_CTRL3, 0, 31, 0x00008800);
20810c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20820c0d06caSMauro Carvalho Chehab DIF_AGC_IF_REF, 0, 31, 0x444C1380);
20830c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20840c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
20850c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20860c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
20870c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20880c0d06caSMauro Carvalho Chehab DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
20890c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20900c0d06caSMauro Carvalho Chehab DIF_AGC_IF_INT_CURRENT, 0, 31,
20910c0d06caSMauro Carvalho Chehab 0x26001700);
20920c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20930c0d06caSMauro Carvalho Chehab DIF_AGC_RF_CURRENT, 0, 31,
20940c0d06caSMauro Carvalho Chehab 0x00002660);
20950c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20960c0d06caSMauro Carvalho Chehab DIF_VIDEO_AGC_CTRL, 0, 31,
20970c0d06caSMauro Carvalho Chehab 0x72500800);
20980c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
20990c0d06caSMauro Carvalho Chehab DIF_VID_AUD_OVERRIDE, 0, 31,
21000c0d06caSMauro Carvalho Chehab 0x27000100);
21010c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
21020c0d06caSMauro Carvalho Chehab DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
21030c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
21040c0d06caSMauro Carvalho Chehab DIF_COMP_FLT_CTRL, 0, 31,
21050c0d06caSMauro Carvalho Chehab 0x00A653A8);
21060c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
21070c0d06caSMauro Carvalho Chehab DIF_SRC_PHASE_INC, 0, 31,
21080c0d06caSMauro Carvalho Chehab 0x1befbf06);
21090c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
21100c0d06caSMauro Carvalho Chehab DIF_SRC_GAIN_CONTROL, 0, 31,
21110c0d06caSMauro Carvalho Chehab 0x000035e8);
21120c0d06caSMauro Carvalho Chehab status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
21130c0d06caSMauro Carvalho Chehab DIF_RPT_VARIANCE, 0, 31, 0x00000000);
21140c0d06caSMauro Carvalho Chehab /* Save the Spec Inversion value */
21150c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
21160c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value |= 0x3a013F11;
21170c0d06caSMauro Carvalho Chehab }
21180c0d06caSMauro Carvalho Chehab
21190c0d06caSMauro Carvalho Chehab /* The AGC values should be the same for all standards,
21200c0d06caSMauro Carvalho Chehab AUD_SRC_SEL[19] should always be disabled */
21210c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
21220c0d06caSMauro Carvalho Chehab
21230c0d06caSMauro Carvalho Chehab /* It is still possible to get Set Standard calls even when we
21240c0d06caSMauro Carvalho Chehab are in FM mode.
21250c0d06caSMauro Carvalho Chehab This is done to override the value for FM. */
21260c0d06caSMauro Carvalho Chehab if (dev->active_mode == V4L2_TUNER_RADIO)
21270c0d06caSMauro Carvalho Chehab dif_misc_ctrl_value = 0x7a080000;
21280c0d06caSMauro Carvalho Chehab
21290c0d06caSMauro Carvalho Chehab /* Write the calculated value for misc ontrol register */
21300c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
21310c0d06caSMauro Carvalho Chehab
21320c0d06caSMauro Carvalho Chehab return status;
21330c0d06caSMauro Carvalho Chehab }
21340c0d06caSMauro Carvalho Chehab
cx231xx_tuner_pre_channel_change(struct cx231xx * dev)21350c0d06caSMauro Carvalho Chehab int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
21360c0d06caSMauro Carvalho Chehab {
21370c0d06caSMauro Carvalho Chehab int status = 0;
21380c0d06caSMauro Carvalho Chehab u32 dwval;
21390c0d06caSMauro Carvalho Chehab
21400c0d06caSMauro Carvalho Chehab /* Set the RF and IF k_agc values to 3 */
21410c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
21420c0d06caSMauro Carvalho Chehab dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
21430c0d06caSMauro Carvalho Chehab dwval |= 0x33000000;
21440c0d06caSMauro Carvalho Chehab
21450c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
21460c0d06caSMauro Carvalho Chehab
21470c0d06caSMauro Carvalho Chehab return status;
21480c0d06caSMauro Carvalho Chehab }
21490c0d06caSMauro Carvalho Chehab
cx231xx_tuner_post_channel_change(struct cx231xx * dev)21500c0d06caSMauro Carvalho Chehab int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
21510c0d06caSMauro Carvalho Chehab {
21520c0d06caSMauro Carvalho Chehab int status = 0;
21530c0d06caSMauro Carvalho Chehab u32 dwval;
2154336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: dev->tuner_type =0%d\n",
2155ed0e3729SMauro Carvalho Chehab __func__, dev->tuner_type);
21560c0d06caSMauro Carvalho Chehab /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
21570c0d06caSMauro Carvalho Chehab * SECAM L/B/D standards */
21580c0d06caSMauro Carvalho Chehab status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
21590c0d06caSMauro Carvalho Chehab dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
21600c0d06caSMauro Carvalho Chehab
21610c0d06caSMauro Carvalho Chehab if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
21620c0d06caSMauro Carvalho Chehab V4L2_STD_SECAM_D)) {
21630c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) {
21640c0d06caSMauro Carvalho Chehab dwval &= ~FLD_DIF_IF_REF;
21650c0d06caSMauro Carvalho Chehab dwval |= 0x88000300;
21660c0d06caSMauro Carvalho Chehab } else
21670c0d06caSMauro Carvalho Chehab dwval |= 0x88000000;
21680c0d06caSMauro Carvalho Chehab } else {
21690c0d06caSMauro Carvalho Chehab if (dev->tuner_type == TUNER_NXP_TDA18271) {
21700c0d06caSMauro Carvalho Chehab dwval &= ~FLD_DIF_IF_REF;
21710c0d06caSMauro Carvalho Chehab dwval |= 0xCC000300;
21720c0d06caSMauro Carvalho Chehab } else
21730c0d06caSMauro Carvalho Chehab dwval |= 0x44000000;
21740c0d06caSMauro Carvalho Chehab }
21750c0d06caSMauro Carvalho Chehab
21760c0d06caSMauro Carvalho Chehab status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
21770c0d06caSMauro Carvalho Chehab
2178b251f957SHans Verkuil return status == sizeof(dwval) ? 0 : -EIO;
21790c0d06caSMauro Carvalho Chehab }
21800c0d06caSMauro Carvalho Chehab
21810c0d06caSMauro Carvalho Chehab /******************************************************************************
21820c0d06caSMauro Carvalho Chehab * I 2 S - B L O C K C O N T R O L functions *
21830c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_i2s_blk_initialize(struct cx231xx * dev)21840c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
21850c0d06caSMauro Carvalho Chehab {
21860c0d06caSMauro Carvalho Chehab int status = 0;
21870c0d06caSMauro Carvalho Chehab u32 value;
21880c0d06caSMauro Carvalho Chehab
21890c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
21900c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, &value, 1);
21910c0d06caSMauro Carvalho Chehab /* enables clock to delta-sigma and decimation filter */
21920c0d06caSMauro Carvalho Chehab value |= 0x80;
21930c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
21940c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, value, 1);
21950c0d06caSMauro Carvalho Chehab /* power up all channel */
21960c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
21970c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1);
21980c0d06caSMauro Carvalho Chehab
21990c0d06caSMauro Carvalho Chehab return status;
22000c0d06caSMauro Carvalho Chehab }
22010c0d06caSMauro Carvalho Chehab
cx231xx_i2s_blk_update_power_control(struct cx231xx * dev,enum AV_MODE avmode)22020c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
22030c0d06caSMauro Carvalho Chehab enum AV_MODE avmode)
22040c0d06caSMauro Carvalho Chehab {
22050c0d06caSMauro Carvalho Chehab int status = 0;
22060c0d06caSMauro Carvalho Chehab u32 value = 0;
22070c0d06caSMauro Carvalho Chehab
22080c0d06caSMauro Carvalho Chehab if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
22090c0d06caSMauro Carvalho Chehab status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
22100c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, &value, 1);
22110c0d06caSMauro Carvalho Chehab value |= 0xfe;
22120c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
22130c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, value, 1);
22140c0d06caSMauro Carvalho Chehab } else {
22150c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
22160c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1);
22170c0d06caSMauro Carvalho Chehab }
22180c0d06caSMauro Carvalho Chehab
22190c0d06caSMauro Carvalho Chehab return status;
22200c0d06caSMauro Carvalho Chehab }
22210c0d06caSMauro Carvalho Chehab
22220c0d06caSMauro Carvalho Chehab /* set i2s_blk for audio input types */
cx231xx_i2s_blk_set_audio_input(struct cx231xx * dev,u8 audio_input)22230c0d06caSMauro Carvalho Chehab int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
22240c0d06caSMauro Carvalho Chehab {
22250c0d06caSMauro Carvalho Chehab int status = 0;
22260c0d06caSMauro Carvalho Chehab
22270c0d06caSMauro Carvalho Chehab switch (audio_input) {
22280c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_LINE_IN:
22290c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
22300c0d06caSMauro Carvalho Chehab CH_PWR_CTRL2, 1, 0x00, 1);
22310c0d06caSMauro Carvalho Chehab status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
22320c0d06caSMauro Carvalho Chehab CH_PWR_CTRL1, 1, 0x80, 1);
22330c0d06caSMauro Carvalho Chehab break;
22340c0d06caSMauro Carvalho Chehab case CX231XX_AMUX_VIDEO:
22350c0d06caSMauro Carvalho Chehab default:
22360c0d06caSMauro Carvalho Chehab break;
22370c0d06caSMauro Carvalho Chehab }
22380c0d06caSMauro Carvalho Chehab
22390c0d06caSMauro Carvalho Chehab dev->ctl_ainput = audio_input;
22400c0d06caSMauro Carvalho Chehab
22410c0d06caSMauro Carvalho Chehab return status;
22420c0d06caSMauro Carvalho Chehab }
22430c0d06caSMauro Carvalho Chehab
22440c0d06caSMauro Carvalho Chehab /******************************************************************************
22450c0d06caSMauro Carvalho Chehab * P O W E R C O N T R O L functions *
22460c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_set_power_mode(struct cx231xx * dev,enum AV_MODE mode)22470c0d06caSMauro Carvalho Chehab int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
22480c0d06caSMauro Carvalho Chehab {
22490c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 };
22500c0d06caSMauro Carvalho Chehab u32 tmp = 0;
22510c0d06caSMauro Carvalho Chehab int status = 0;
22520c0d06caSMauro Carvalho Chehab
22530c0d06caSMauro Carvalho Chehab if (dev->power_mode != mode)
22540c0d06caSMauro Carvalho Chehab dev->power_mode = mode;
22550c0d06caSMauro Carvalho Chehab else {
2256336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: mode = %d, No Change req.\n",
2257ed0e3729SMauro Carvalho Chehab __func__, mode);
22580c0d06caSMauro Carvalho Chehab return 0;
22590c0d06caSMauro Carvalho Chehab }
22600c0d06caSMauro Carvalho Chehab
22610c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
22620c0d06caSMauro Carvalho Chehab 4);
22630c0d06caSMauro Carvalho Chehab if (status < 0)
22640c0d06caSMauro Carvalho Chehab return status;
22650c0d06caSMauro Carvalho Chehab
22663f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value));
22670c0d06caSMauro Carvalho Chehab
22680c0d06caSMauro Carvalho Chehab switch (mode) {
22690c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_ENXTERNAL_AV:
22700c0d06caSMauro Carvalho Chehab
22710c0d06caSMauro Carvalho Chehab tmp &= (~PWR_MODE_MASK);
22720c0d06caSMauro Carvalho Chehab
22730c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN;
22740c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
22750c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
22760c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
22770c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
22780c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
22790c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
22800c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
22810c0d06caSMauro Carvalho Chehab
22820c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN;
22830c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
22840c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
22850c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
22860c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
22870c0d06caSMauro Carvalho Chehab status =
22880c0d06caSMauro Carvalho Chehab cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
22890c0d06caSMauro Carvalho Chehab value, 4);
22900c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
22910c0d06caSMauro Carvalho Chehab
22920c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
22930c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
22940c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
22950c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
22960c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
22970c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
22980c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
22990c0d06caSMauro Carvalho Chehab
23000c0d06caSMauro Carvalho Chehab /* reset state of xceive tuner */
23010c0d06caSMauro Carvalho Chehab dev->xc_fw_load_done = 0;
23020c0d06caSMauro Carvalho Chehab break;
23030c0d06caSMauro Carvalho Chehab
23040c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_ANALOGT_TV:
23050c0d06caSMauro Carvalho Chehab
23060c0d06caSMauro Carvalho Chehab tmp |= PWR_DEMOD_EN;
23070c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23080c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23090c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23100c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23110c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23120c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23130c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23140c0d06caSMauro Carvalho Chehab
23150c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_TUNER_EN)) {
23160c0d06caSMauro Carvalho Chehab tmp |= (PWR_TUNER_EN);
23170c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23180c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23190c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23200c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23210c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23220c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23230c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23240c0d06caSMauro Carvalho Chehab }
23250c0d06caSMauro Carvalho Chehab
23260c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_AV_EN)) {
23270c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN;
23280c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23290c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23300c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23310c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23320c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23330c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23340c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23350c0d06caSMauro Carvalho Chehab }
23360c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_ISO_EN)) {
23370c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN;
23380c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23390c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23400c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23410c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23420c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23430c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23440c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23450c0d06caSMauro Carvalho Chehab }
23460c0d06caSMauro Carvalho Chehab
23470c0d06caSMauro Carvalho Chehab if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
23480c0d06caSMauro Carvalho Chehab tmp |= POLARIS_AVMODE_ANALOGT_TV;
23490c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23500c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23510c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23520c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23530c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23540c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23550c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23560c0d06caSMauro Carvalho Chehab }
23570c0d06caSMauro Carvalho Chehab
23580c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type != TUNER_ABSENT) {
23590c0d06caSMauro Carvalho Chehab /* reset the Tuner */
23600c0d06caSMauro Carvalho Chehab if (dev->board.tuner_gpio)
23610c0d06caSMauro Carvalho Chehab cx231xx_gpio_set(dev, dev->board.tuner_gpio);
23620c0d06caSMauro Carvalho Chehab
23630c0d06caSMauro Carvalho Chehab if (dev->cx231xx_reset_analog_tuner)
23640c0d06caSMauro Carvalho Chehab dev->cx231xx_reset_analog_tuner(dev);
23650c0d06caSMauro Carvalho Chehab }
23660c0d06caSMauro Carvalho Chehab
23670c0d06caSMauro Carvalho Chehab break;
23680c0d06caSMauro Carvalho Chehab
23690c0d06caSMauro Carvalho Chehab case POLARIS_AVMODE_DIGITAL:
23700c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_TUNER_EN)) {
23710c0d06caSMauro Carvalho Chehab tmp |= (PWR_TUNER_EN);
23720c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23730c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23740c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23750c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23760c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23770c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23780c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23790c0d06caSMauro Carvalho Chehab }
23800c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_AV_EN)) {
23810c0d06caSMauro Carvalho Chehab tmp |= PWR_AV_EN;
23820c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23830c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23840c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23850c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23860c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23870c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23880c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23890c0d06caSMauro Carvalho Chehab }
23900c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_ISO_EN)) {
23910c0d06caSMauro Carvalho Chehab tmp |= PWR_ISO_EN;
23920c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
23930c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
23940c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
23950c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
23960c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
23970c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
23980c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
23990c0d06caSMauro Carvalho Chehab }
24000c0d06caSMauro Carvalho Chehab
24010c0d06caSMauro Carvalho Chehab tmp &= (~PWR_AV_MODE);
2402082417d1SMatthias Schwarzott tmp |= POLARIS_AVMODE_DIGITAL;
24030c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
24040c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
24050c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
24060c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
24070c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
24080c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
24090c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
24100c0d06caSMauro Carvalho Chehab
24110c0d06caSMauro Carvalho Chehab if (!(tmp & PWR_DEMOD_EN)) {
24120c0d06caSMauro Carvalho Chehab tmp |= PWR_DEMOD_EN;
24130c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
24140c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
24150c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
24160c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
24170c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
24180c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
24190c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
24200c0d06caSMauro Carvalho Chehab }
24210c0d06caSMauro Carvalho Chehab
24220c0d06caSMauro Carvalho Chehab if (dev->board.tuner_type != TUNER_ABSENT) {
24230c0d06caSMauro Carvalho Chehab /* reset the Tuner */
24240c0d06caSMauro Carvalho Chehab if (dev->board.tuner_gpio)
24250c0d06caSMauro Carvalho Chehab cx231xx_gpio_set(dev, dev->board.tuner_gpio);
24260c0d06caSMauro Carvalho Chehab
24270c0d06caSMauro Carvalho Chehab if (dev->cx231xx_reset_analog_tuner)
24280c0d06caSMauro Carvalho Chehab dev->cx231xx_reset_analog_tuner(dev);
24290c0d06caSMauro Carvalho Chehab }
24300c0d06caSMauro Carvalho Chehab break;
24310c0d06caSMauro Carvalho Chehab
24320c0d06caSMauro Carvalho Chehab default:
24330c0d06caSMauro Carvalho Chehab break;
24340c0d06caSMauro Carvalho Chehab }
24350c0d06caSMauro Carvalho Chehab
24360c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
24370c0d06caSMauro Carvalho Chehab
24380c0d06caSMauro Carvalho Chehab /* For power saving, only enable Pwr_resetout_n
24390c0d06caSMauro Carvalho Chehab when digital TV is selected. */
24400c0d06caSMauro Carvalho Chehab if (mode == POLARIS_AVMODE_DIGITAL) {
24410c0d06caSMauro Carvalho Chehab tmp |= PWR_RESETOUT_EN;
24420c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
24430c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
24440c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
24450c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
24460c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
24470c0d06caSMauro Carvalho Chehab PWR_CTL_EN, value, 4);
24480c0d06caSMauro Carvalho Chehab msleep(PWR_SLEEP_INTERVAL);
24490c0d06caSMauro Carvalho Chehab }
24500c0d06caSMauro Carvalho Chehab
24510c0d06caSMauro Carvalho Chehab /* update power control for afe */
24520c0d06caSMauro Carvalho Chehab status = cx231xx_afe_update_power_control(dev, mode);
24530c0d06caSMauro Carvalho Chehab
24540c0d06caSMauro Carvalho Chehab /* update power control for i2s_blk */
24550c0d06caSMauro Carvalho Chehab status = cx231xx_i2s_blk_update_power_control(dev, mode);
24560c0d06caSMauro Carvalho Chehab
24570c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
24580c0d06caSMauro Carvalho Chehab 4);
24590c0d06caSMauro Carvalho Chehab
24600c0d06caSMauro Carvalho Chehab return status;
24610c0d06caSMauro Carvalho Chehab }
24620c0d06caSMauro Carvalho Chehab
cx231xx_power_suspend(struct cx231xx * dev)24630c0d06caSMauro Carvalho Chehab int cx231xx_power_suspend(struct cx231xx *dev)
24640c0d06caSMauro Carvalho Chehab {
24650c0d06caSMauro Carvalho Chehab u8 value[4] = { 0, 0, 0, 0 };
24660c0d06caSMauro Carvalho Chehab u32 tmp = 0;
24670c0d06caSMauro Carvalho Chehab int status = 0;
24680c0d06caSMauro Carvalho Chehab
24690c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
24700c0d06caSMauro Carvalho Chehab value, 4);
24710c0d06caSMauro Carvalho Chehab if (status > 0)
24720c0d06caSMauro Carvalho Chehab return status;
24730c0d06caSMauro Carvalho Chehab
24743f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value));
24750c0d06caSMauro Carvalho Chehab tmp &= (~PWR_MODE_MASK);
24760c0d06caSMauro Carvalho Chehab
24770c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
24780c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
24790c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
24800c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
24810c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
24820c0d06caSMauro Carvalho Chehab value, 4);
24830c0d06caSMauro Carvalho Chehab
24840c0d06caSMauro Carvalho Chehab return status;
24850c0d06caSMauro Carvalho Chehab }
24860c0d06caSMauro Carvalho Chehab
24870c0d06caSMauro Carvalho Chehab /******************************************************************************
24880c0d06caSMauro Carvalho Chehab * S T R E A M C O N T R O L functions *
24890c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_start_stream(struct cx231xx * dev,u32 ep_mask)24900c0d06caSMauro Carvalho Chehab int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
24910c0d06caSMauro Carvalho Chehab {
24920c0d06caSMauro Carvalho Chehab u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
24930c0d06caSMauro Carvalho Chehab u32 tmp = 0;
24940c0d06caSMauro Carvalho Chehab int status = 0;
24950c0d06caSMauro Carvalho Chehab
2496336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
24970c0d06caSMauro Carvalho Chehab status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
24980c0d06caSMauro Carvalho Chehab value, 4);
24990c0d06caSMauro Carvalho Chehab if (status < 0)
25000c0d06caSMauro Carvalho Chehab return status;
25010c0d06caSMauro Carvalho Chehab
25023f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value));
25030c0d06caSMauro Carvalho Chehab tmp |= ep_mask;
25040c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
25050c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
25060c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
25070c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
25080c0d06caSMauro Carvalho Chehab
25090c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
25100c0d06caSMauro Carvalho Chehab value, 4);
25110c0d06caSMauro Carvalho Chehab
25120c0d06caSMauro Carvalho Chehab return status;
25130c0d06caSMauro Carvalho Chehab }
25140c0d06caSMauro Carvalho Chehab
cx231xx_stop_stream(struct cx231xx * dev,u32 ep_mask)25150c0d06caSMauro Carvalho Chehab int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
25160c0d06caSMauro Carvalho Chehab {
25170c0d06caSMauro Carvalho Chehab u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
25180c0d06caSMauro Carvalho Chehab u32 tmp = 0;
25190c0d06caSMauro Carvalho Chehab int status = 0;
25200c0d06caSMauro Carvalho Chehab
2521336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: ep_mask = %x\n", __func__, ep_mask);
25220c0d06caSMauro Carvalho Chehab status =
25230c0d06caSMauro Carvalho Chehab cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
25240c0d06caSMauro Carvalho Chehab if (status < 0)
25250c0d06caSMauro Carvalho Chehab return status;
25260c0d06caSMauro Carvalho Chehab
25273f9280a8SHans Verkuil tmp = le32_to_cpu(*((__le32 *) value));
25280c0d06caSMauro Carvalho Chehab tmp &= (~ep_mask);
25290c0d06caSMauro Carvalho Chehab value[0] = (u8) tmp;
25300c0d06caSMauro Carvalho Chehab value[1] = (u8) (tmp >> 8);
25310c0d06caSMauro Carvalho Chehab value[2] = (u8) (tmp >> 16);
25320c0d06caSMauro Carvalho Chehab value[3] = (u8) (tmp >> 24);
25330c0d06caSMauro Carvalho Chehab
25340c0d06caSMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
25350c0d06caSMauro Carvalho Chehab value, 4);
25360c0d06caSMauro Carvalho Chehab
25370c0d06caSMauro Carvalho Chehab return status;
25380c0d06caSMauro Carvalho Chehab }
25390c0d06caSMauro Carvalho Chehab
cx231xx_initialize_stream_xfer(struct cx231xx * dev,u32 media_type)25400c0d06caSMauro Carvalho Chehab int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
25410c0d06caSMauro Carvalho Chehab {
25420c0d06caSMauro Carvalho Chehab int status = 0;
25430c0d06caSMauro Carvalho Chehab u32 value = 0;
25440c0d06caSMauro Carvalho Chehab u8 val[4] = { 0, 0, 0, 0 };
25450c0d06caSMauro Carvalho Chehab
25460c0d06caSMauro Carvalho Chehab if (dev->udev->speed == USB_SPEED_HIGH) {
25470c0d06caSMauro Carvalho Chehab switch (media_type) {
25480c0d06caSMauro Carvalho Chehab case Audio:
2549336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2550b7085c08SMauro Carvalho Chehab "%s: Audio enter HANC\n", __func__);
25510c0d06caSMauro Carvalho Chehab status =
25520c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
25530c0d06caSMauro Carvalho Chehab break;
25540c0d06caSMauro Carvalho Chehab
25550c0d06caSMauro Carvalho Chehab case Vbi:
2556336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2557b7085c08SMauro Carvalho Chehab "%s: set vanc registers\n", __func__);
25580c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
25590c0d06caSMauro Carvalho Chehab break;
25600c0d06caSMauro Carvalho Chehab
25610c0d06caSMauro Carvalho Chehab case Sliced_cc:
2562336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2563b7085c08SMauro Carvalho Chehab "%s: set hanc registers\n", __func__);
25640c0d06caSMauro Carvalho Chehab status =
25650c0d06caSMauro Carvalho Chehab cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
25660c0d06caSMauro Carvalho Chehab break;
25670c0d06caSMauro Carvalho Chehab
25680c0d06caSMauro Carvalho Chehab case Raw_Video:
2569336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2570b7085c08SMauro Carvalho Chehab "%s: set video registers\n", __func__);
25710c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
25720c0d06caSMauro Carvalho Chehab break;
25730c0d06caSMauro Carvalho Chehab
25740c0d06caSMauro Carvalho Chehab case TS1_serial_mode:
2575336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2576b7085c08SMauro Carvalho Chehab "%s: set ts1 registers", __func__);
25770c0d06caSMauro Carvalho Chehab
25780c0d06caSMauro Carvalho Chehab if (dev->board.has_417) {
2579336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2580b7085c08SMauro Carvalho Chehab "%s: MPEG\n", __func__);
25810c0d06caSMauro Carvalho Chehab value &= 0xFFFFFFFC;
25820c0d06caSMauro Carvalho Chehab value |= 0x3;
25830c0d06caSMauro Carvalho Chehab
258488538bb5SMauro Carvalho Chehab status = cx231xx_mode_register(dev,
258588538bb5SMauro Carvalho Chehab TS_MODE_REG, value);
25860c0d06caSMauro Carvalho Chehab
25870c0d06caSMauro Carvalho Chehab val[0] = 0x04;
25880c0d06caSMauro Carvalho Chehab val[1] = 0xA3;
25890c0d06caSMauro Carvalho Chehab val[2] = 0x3B;
25900c0d06caSMauro Carvalho Chehab val[3] = 0x00;
259188538bb5SMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev,
259288538bb5SMauro Carvalho Chehab VRT_SET_REGISTER,
25930c0d06caSMauro Carvalho Chehab TS1_CFG_REG, val, 4);
25940c0d06caSMauro Carvalho Chehab
25950c0d06caSMauro Carvalho Chehab val[0] = 0x00;
25960c0d06caSMauro Carvalho Chehab val[1] = 0x08;
25970c0d06caSMauro Carvalho Chehab val[2] = 0x00;
25980c0d06caSMauro Carvalho Chehab val[3] = 0x08;
259988538bb5SMauro Carvalho Chehab status = cx231xx_write_ctrl_reg(dev,
260088538bb5SMauro Carvalho Chehab VRT_SET_REGISTER,
26010c0d06caSMauro Carvalho Chehab TS1_LENGTH_REG, val, 4);
26020c0d06caSMauro Carvalho Chehab } else {
2603336fea92SMauro Carvalho Chehab dev_dbg(dev->dev, "%s: BDA\n", __func__);
260488538bb5SMauro Carvalho Chehab status = cx231xx_mode_register(dev,
260588538bb5SMauro Carvalho Chehab TS_MODE_REG, 0x101);
260688538bb5SMauro Carvalho Chehab status = cx231xx_mode_register(dev,
260788538bb5SMauro Carvalho Chehab TS1_CFG_REG, 0x010);
26080c0d06caSMauro Carvalho Chehab }
26090c0d06caSMauro Carvalho Chehab break;
26100c0d06caSMauro Carvalho Chehab
26110c0d06caSMauro Carvalho Chehab case TS1_parallel_mode:
2612336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2613b7085c08SMauro Carvalho Chehab "%s: set ts1 parallel mode registers\n",
26140c0d06caSMauro Carvalho Chehab __func__);
26150c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
26160c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
26170c0d06caSMauro Carvalho Chehab break;
26180c0d06caSMauro Carvalho Chehab }
26190c0d06caSMauro Carvalho Chehab } else {
26200c0d06caSMauro Carvalho Chehab status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
26210c0d06caSMauro Carvalho Chehab }
26220c0d06caSMauro Carvalho Chehab
26230c0d06caSMauro Carvalho Chehab return status;
26240c0d06caSMauro Carvalho Chehab }
26250c0d06caSMauro Carvalho Chehab
cx231xx_capture_start(struct cx231xx * dev,int start,u8 media_type)26260c0d06caSMauro Carvalho Chehab int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
26270c0d06caSMauro Carvalho Chehab {
26280c0d06caSMauro Carvalho Chehab int rc = -1;
26290c0d06caSMauro Carvalho Chehab u32 ep_mask = -1;
26300c0d06caSMauro Carvalho Chehab struct pcb_config *pcb_config;
26310c0d06caSMauro Carvalho Chehab
26320c0d06caSMauro Carvalho Chehab /* get EP for media type */
26330c0d06caSMauro Carvalho Chehab pcb_config = (struct pcb_config *)&dev->current_pcb_config;
26340c0d06caSMauro Carvalho Chehab
26350c0d06caSMauro Carvalho Chehab if (pcb_config->config_num) {
26360c0d06caSMauro Carvalho Chehab switch (media_type) {
26370c0d06caSMauro Carvalho Chehab case Raw_Video:
26380c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
26390c0d06caSMauro Carvalho Chehab break;
26400c0d06caSMauro Carvalho Chehab case Audio:
26410c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
26420c0d06caSMauro Carvalho Chehab break;
26430c0d06caSMauro Carvalho Chehab case Vbi:
26440c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
26450c0d06caSMauro Carvalho Chehab break;
26460c0d06caSMauro Carvalho Chehab case Sliced_cc:
26470c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
26480c0d06caSMauro Carvalho Chehab break;
26490c0d06caSMauro Carvalho Chehab case TS1_serial_mode:
26500c0d06caSMauro Carvalho Chehab case TS1_parallel_mode:
26510c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
26520c0d06caSMauro Carvalho Chehab break;
26530c0d06caSMauro Carvalho Chehab case TS2:
26540c0d06caSMauro Carvalho Chehab ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
26550c0d06caSMauro Carvalho Chehab break;
26560c0d06caSMauro Carvalho Chehab }
26570c0d06caSMauro Carvalho Chehab }
26580c0d06caSMauro Carvalho Chehab
26590c0d06caSMauro Carvalho Chehab if (start) {
26600c0d06caSMauro Carvalho Chehab rc = cx231xx_initialize_stream_xfer(dev, media_type);
26610c0d06caSMauro Carvalho Chehab
26620c0d06caSMauro Carvalho Chehab if (rc < 0)
26630c0d06caSMauro Carvalho Chehab return rc;
26640c0d06caSMauro Carvalho Chehab
26650c0d06caSMauro Carvalho Chehab /* enable video capture */
26660c0d06caSMauro Carvalho Chehab if (ep_mask > 0)
26670c0d06caSMauro Carvalho Chehab rc = cx231xx_start_stream(dev, ep_mask);
26680c0d06caSMauro Carvalho Chehab } else {
26690c0d06caSMauro Carvalho Chehab /* disable video capture */
26700c0d06caSMauro Carvalho Chehab if (ep_mask > 0)
26710c0d06caSMauro Carvalho Chehab rc = cx231xx_stop_stream(dev, ep_mask);
26720c0d06caSMauro Carvalho Chehab }
26730c0d06caSMauro Carvalho Chehab
26740c0d06caSMauro Carvalho Chehab return rc;
26750c0d06caSMauro Carvalho Chehab }
26760c0d06caSMauro Carvalho Chehab EXPORT_SYMBOL_GPL(cx231xx_capture_start);
26770c0d06caSMauro Carvalho Chehab
26780c0d06caSMauro Carvalho Chehab /*****************************************************************************
26790c0d06caSMauro Carvalho Chehab * G P I O B I T control functions *
26800c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_set_gpio_bit(struct cx231xx * dev,u32 gpio_bit,u32 gpio_val)26816b236a37SHans Verkuil static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val)
26820c0d06caSMauro Carvalho Chehab {
26830c0d06caSMauro Carvalho Chehab int status = 0;
26840c0d06caSMauro Carvalho Chehab
26853f9280a8SHans Verkuil gpio_val = (__force u32)cpu_to_le32(gpio_val);
26866b236a37SHans Verkuil status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
26870c0d06caSMauro Carvalho Chehab
26880c0d06caSMauro Carvalho Chehab return status;
26890c0d06caSMauro Carvalho Chehab }
26900c0d06caSMauro Carvalho Chehab
cx231xx_get_gpio_bit(struct cx231xx * dev,u32 gpio_bit,u32 * gpio_val)26916b236a37SHans Verkuil static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val)
26920c0d06caSMauro Carvalho Chehab {
26933f9280a8SHans Verkuil __le32 tmp;
26940c0d06caSMauro Carvalho Chehab int status = 0;
26950c0d06caSMauro Carvalho Chehab
26966b236a37SHans Verkuil status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
26976b236a37SHans Verkuil *gpio_val = le32_to_cpu(tmp);
26980c0d06caSMauro Carvalho Chehab
26990c0d06caSMauro Carvalho Chehab return status;
27000c0d06caSMauro Carvalho Chehab }
27010c0d06caSMauro Carvalho Chehab
27020c0d06caSMauro Carvalho Chehab /*
27030c0d06caSMauro Carvalho Chehab * cx231xx_set_gpio_direction
27040c0d06caSMauro Carvalho Chehab * Sets the direction of the GPIO pin to input or output
27050c0d06caSMauro Carvalho Chehab *
27060c0d06caSMauro Carvalho Chehab * Parameters :
27070c0d06caSMauro Carvalho Chehab * pin_number : The GPIO Pin number to program the direction for
27080c0d06caSMauro Carvalho Chehab * from 0 to 31
27090c0d06caSMauro Carvalho Chehab * pin_value : The Direction of the GPIO Pin under reference.
27100c0d06caSMauro Carvalho Chehab * 0 = Input direction
27110c0d06caSMauro Carvalho Chehab * 1 = Output direction
27120c0d06caSMauro Carvalho Chehab */
cx231xx_set_gpio_direction(struct cx231xx * dev,int pin_number,int pin_value)27130c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_direction(struct cx231xx *dev,
27140c0d06caSMauro Carvalho Chehab int pin_number, int pin_value)
27150c0d06caSMauro Carvalho Chehab {
27160c0d06caSMauro Carvalho Chehab int status = 0;
27170c0d06caSMauro Carvalho Chehab u32 value = 0;
27180c0d06caSMauro Carvalho Chehab
27190c0d06caSMauro Carvalho Chehab /* Check for valid pin_number - if 32 , bail out */
27200c0d06caSMauro Carvalho Chehab if (pin_number >= 32)
27210c0d06caSMauro Carvalho Chehab return -EINVAL;
27220c0d06caSMauro Carvalho Chehab
27230c0d06caSMauro Carvalho Chehab /* input */
27240c0d06caSMauro Carvalho Chehab if (pin_value == 0)
27250c0d06caSMauro Carvalho Chehab value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
27260c0d06caSMauro Carvalho Chehab else
27270c0d06caSMauro Carvalho Chehab value = dev->gpio_dir | (1 << pin_number);
27280c0d06caSMauro Carvalho Chehab
27296b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
27300c0d06caSMauro Carvalho Chehab
27310c0d06caSMauro Carvalho Chehab /* cache the value for future */
27320c0d06caSMauro Carvalho Chehab dev->gpio_dir = value;
27330c0d06caSMauro Carvalho Chehab
27340c0d06caSMauro Carvalho Chehab return status;
27350c0d06caSMauro Carvalho Chehab }
27360c0d06caSMauro Carvalho Chehab
27370c0d06caSMauro Carvalho Chehab /*
27380c0d06caSMauro Carvalho Chehab * cx231xx_set_gpio_value
27390c0d06caSMauro Carvalho Chehab * Sets the value of the GPIO pin to Logic high or low. The Pin under
27400c0d06caSMauro Carvalho Chehab * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
27410c0d06caSMauro Carvalho Chehab *
27420c0d06caSMauro Carvalho Chehab * Parameters :
27430c0d06caSMauro Carvalho Chehab * pin_number : The GPIO Pin number to program the direction for
27440c0d06caSMauro Carvalho Chehab * pin_value : The value of the GPIO Pin under reference.
27450c0d06caSMauro Carvalho Chehab * 0 = set it to 0
27460c0d06caSMauro Carvalho Chehab * 1 = set it to 1
27470c0d06caSMauro Carvalho Chehab */
cx231xx_set_gpio_value(struct cx231xx * dev,int pin_number,int pin_value)27480c0d06caSMauro Carvalho Chehab int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
27490c0d06caSMauro Carvalho Chehab {
27500c0d06caSMauro Carvalho Chehab int status = 0;
27510c0d06caSMauro Carvalho Chehab u32 value = 0;
27520c0d06caSMauro Carvalho Chehab
27530c0d06caSMauro Carvalho Chehab /* Check for valid pin_number - if 0xFF , bail out */
27540c0d06caSMauro Carvalho Chehab if (pin_number >= 32)
27550c0d06caSMauro Carvalho Chehab return -EINVAL;
27560c0d06caSMauro Carvalho Chehab
27570c0d06caSMauro Carvalho Chehab /* first do a sanity check - if the Pin is not output, make it output */
27580c0d06caSMauro Carvalho Chehab if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
27590c0d06caSMauro Carvalho Chehab /* It was in input mode */
27600c0d06caSMauro Carvalho Chehab value = dev->gpio_dir | (1 << pin_number);
27610c0d06caSMauro Carvalho Chehab dev->gpio_dir = value;
27620c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
27636b236a37SHans Verkuil dev->gpio_val);
27640c0d06caSMauro Carvalho Chehab value = 0;
27650c0d06caSMauro Carvalho Chehab }
27660c0d06caSMauro Carvalho Chehab
27670c0d06caSMauro Carvalho Chehab if (pin_value == 0)
27680c0d06caSMauro Carvalho Chehab value = dev->gpio_val & (~(1 << pin_number));
27690c0d06caSMauro Carvalho Chehab else
27700c0d06caSMauro Carvalho Chehab value = dev->gpio_val | (1 << pin_number);
27710c0d06caSMauro Carvalho Chehab
27720c0d06caSMauro Carvalho Chehab /* store the value */
27730c0d06caSMauro Carvalho Chehab dev->gpio_val = value;
27740c0d06caSMauro Carvalho Chehab
27750c0d06caSMauro Carvalho Chehab /* toggle bit0 of GP_IO */
27766b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
27770c0d06caSMauro Carvalho Chehab
27780c0d06caSMauro Carvalho Chehab return status;
27790c0d06caSMauro Carvalho Chehab }
27800c0d06caSMauro Carvalho Chehab
27810c0d06caSMauro Carvalho Chehab /*****************************************************************************
27820c0d06caSMauro Carvalho Chehab * G P I O I2C related functions *
27830c0d06caSMauro Carvalho Chehab ******************************************************************************/
cx231xx_gpio_i2c_start(struct cx231xx * dev)27840c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_start(struct cx231xx *dev)
27850c0d06caSMauro Carvalho Chehab {
27860c0d06caSMauro Carvalho Chehab int status = 0;
27870c0d06caSMauro Carvalho Chehab
27880c0d06caSMauro Carvalho Chehab /* set SCL to output 1 ; set SDA to output 1 */
27890c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
27900c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
27910c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
27920c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
27930c0d06caSMauro Carvalho Chehab
27946b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
27950c0d06caSMauro Carvalho Chehab if (status < 0)
27960c0d06caSMauro Carvalho Chehab return -EINVAL;
27970c0d06caSMauro Carvalho Chehab
27980c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */
27990c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
28000c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
28010c0d06caSMauro Carvalho Chehab
28026b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
28030c0d06caSMauro Carvalho Chehab if (status < 0)
28040c0d06caSMauro Carvalho Chehab return -EINVAL;
28050c0d06caSMauro Carvalho Chehab
28060c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */
28070c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
28080c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
28090c0d06caSMauro Carvalho Chehab
28106b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
28110c0d06caSMauro Carvalho Chehab if (status < 0)
28120c0d06caSMauro Carvalho Chehab return -EINVAL;
28130c0d06caSMauro Carvalho Chehab
28140c0d06caSMauro Carvalho Chehab return status;
28150c0d06caSMauro Carvalho Chehab }
28160c0d06caSMauro Carvalho Chehab
cx231xx_gpio_i2c_end(struct cx231xx * dev)28170c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_end(struct cx231xx *dev)
28180c0d06caSMauro Carvalho Chehab {
28190c0d06caSMauro Carvalho Chehab int status = 0;
28200c0d06caSMauro Carvalho Chehab
28210c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */
28220c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
28230c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
28240c0d06caSMauro Carvalho Chehab
28250c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
28260c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
28270c0d06caSMauro Carvalho Chehab
28286b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
28290c0d06caSMauro Carvalho Chehab if (status < 0)
28300c0d06caSMauro Carvalho Chehab return -EINVAL;
28310c0d06caSMauro Carvalho Chehab
28320c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */
28330c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
28340c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
28350c0d06caSMauro Carvalho Chehab
28366b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
28370c0d06caSMauro Carvalho Chehab if (status < 0)
28380c0d06caSMauro Carvalho Chehab return -EINVAL;
28390c0d06caSMauro Carvalho Chehab
28400c0d06caSMauro Carvalho Chehab /* set SCL to input ,release SCL cable control
28410c0d06caSMauro Carvalho Chehab set SDA to input ,release SDA cable control */
28420c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
28430c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
28440c0d06caSMauro Carvalho Chehab
28450c0d06caSMauro Carvalho Chehab status =
28466b236a37SHans Verkuil cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
28470c0d06caSMauro Carvalho Chehab if (status < 0)
28480c0d06caSMauro Carvalho Chehab return -EINVAL;
28490c0d06caSMauro Carvalho Chehab
28500c0d06caSMauro Carvalho Chehab return status;
28510c0d06caSMauro Carvalho Chehab }
28520c0d06caSMauro Carvalho Chehab
cx231xx_gpio_i2c_write_byte(struct cx231xx * dev,u8 data)28530c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
28540c0d06caSMauro Carvalho Chehab {
28550c0d06caSMauro Carvalho Chehab int status = 0;
28560c0d06caSMauro Carvalho Chehab u8 i;
28570c0d06caSMauro Carvalho Chehab
28580c0d06caSMauro Carvalho Chehab /* set SCL to output ; set SDA to output */
28590c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
28600c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
28610c0d06caSMauro Carvalho Chehab
28620c0d06caSMauro Carvalho Chehab for (i = 0; i < 8; i++) {
28630c0d06caSMauro Carvalho Chehab if (((data << i) & 0x80) == 0) {
28640c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */
28650c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
28660c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
28670c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
28686b236a37SHans Verkuil dev->gpio_val);
28690c0d06caSMauro Carvalho Chehab
28700c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 0 */
28710c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
28720c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
28736b236a37SHans Verkuil dev->gpio_val);
28740c0d06caSMauro Carvalho Chehab
28750c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 0 */
28760c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
28770c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
28786b236a37SHans Verkuil dev->gpio_val);
28790c0d06caSMauro Carvalho Chehab } else {
28800c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 1 */
28810c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
28820c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
28830c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
28846b236a37SHans Verkuil dev->gpio_val);
28850c0d06caSMauro Carvalho Chehab
28860c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to output 1 */
28870c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
28880c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
28896b236a37SHans Verkuil dev->gpio_val);
28900c0d06caSMauro Carvalho Chehab
28910c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to output 1 */
28920c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
28930c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
28946b236a37SHans Verkuil dev->gpio_val);
28950c0d06caSMauro Carvalho Chehab }
28960c0d06caSMauro Carvalho Chehab }
28970c0d06caSMauro Carvalho Chehab return status;
28980c0d06caSMauro Carvalho Chehab }
28990c0d06caSMauro Carvalho Chehab
cx231xx_gpio_i2c_read_byte(struct cx231xx * dev,u8 * buf)29000c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
29010c0d06caSMauro Carvalho Chehab {
29020c0d06caSMauro Carvalho Chehab u8 value = 0;
29030c0d06caSMauro Carvalho Chehab int status = 0;
29040c0d06caSMauro Carvalho Chehab u32 gpio_logic_value = 0;
29050c0d06caSMauro Carvalho Chehab u8 i;
29060c0d06caSMauro Carvalho Chehab
29070c0d06caSMauro Carvalho Chehab /* read byte */
29080c0d06caSMauro Carvalho Chehab for (i = 0; i < 8; i++) { /* send write I2c addr */
29090c0d06caSMauro Carvalho Chehab
29100c0d06caSMauro Carvalho Chehab /* set SCL to output 0; set SDA to input */
29110c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
29120c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
29136b236a37SHans Verkuil dev->gpio_val);
29140c0d06caSMauro Carvalho Chehab
29150c0d06caSMauro Carvalho Chehab /* set SCL to output 1; set SDA to input */
29160c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
29170c0d06caSMauro Carvalho Chehab status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
29186b236a37SHans Verkuil dev->gpio_val);
29190c0d06caSMauro Carvalho Chehab
29200c0d06caSMauro Carvalho Chehab /* get SDA data bit */
29210c0d06caSMauro Carvalho Chehab gpio_logic_value = dev->gpio_val;
29220c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
29236b236a37SHans Verkuil &dev->gpio_val);
29240c0d06caSMauro Carvalho Chehab if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
29250c0d06caSMauro Carvalho Chehab value |= (1 << (8 - i - 1));
29260c0d06caSMauro Carvalho Chehab
29270c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value;
29280c0d06caSMauro Carvalho Chehab }
29290c0d06caSMauro Carvalho Chehab
29300c0d06caSMauro Carvalho Chehab /* set SCL to output 0,finish the read latest SCL signal.
29310c0d06caSMauro Carvalho Chehab !!!set SDA to input, never to modify SDA direction at
29320c0d06caSMauro Carvalho Chehab the same times */
29330c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
29346b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
29350c0d06caSMauro Carvalho Chehab
29360c0d06caSMauro Carvalho Chehab /* store the value */
29370c0d06caSMauro Carvalho Chehab *buf = value & 0xff;
29380c0d06caSMauro Carvalho Chehab
29390c0d06caSMauro Carvalho Chehab return status;
29400c0d06caSMauro Carvalho Chehab }
29410c0d06caSMauro Carvalho Chehab
cx231xx_gpio_i2c_read_ack(struct cx231xx * dev)29420c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
29430c0d06caSMauro Carvalho Chehab {
29440c0d06caSMauro Carvalho Chehab int status = 0;
29450c0d06caSMauro Carvalho Chehab u32 gpio_logic_value = 0;
29460c0d06caSMauro Carvalho Chehab int nCnt = 10;
29470c0d06caSMauro Carvalho Chehab int nInit = nCnt;
29480c0d06caSMauro Carvalho Chehab
29490c0d06caSMauro Carvalho Chehab /* clock stretch; set SCL to input; set SDA to input;
29500c0d06caSMauro Carvalho Chehab get SCL value till SCL = 1 */
29510c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
29520c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
29530c0d06caSMauro Carvalho Chehab
29540c0d06caSMauro Carvalho Chehab gpio_logic_value = dev->gpio_val;
29556b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
29560c0d06caSMauro Carvalho Chehab
29570c0d06caSMauro Carvalho Chehab do {
29580c0d06caSMauro Carvalho Chehab msleep(2);
29590c0d06caSMauro Carvalho Chehab status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
29606b236a37SHans Verkuil &dev->gpio_val);
29610c0d06caSMauro Carvalho Chehab nCnt--;
29620c0d06caSMauro Carvalho Chehab } while (((dev->gpio_val &
29630c0d06caSMauro Carvalho Chehab (1 << dev->board.tuner_scl_gpio)) == 0) &&
29640c0d06caSMauro Carvalho Chehab (nCnt > 0));
29650c0d06caSMauro Carvalho Chehab
29660c0d06caSMauro Carvalho Chehab if (nCnt == 0)
2967336fea92SMauro Carvalho Chehab dev_dbg(dev->dev,
2968b7085c08SMauro Carvalho Chehab "No ACK after %d msec -GPIO I2C failed!",
29690c0d06caSMauro Carvalho Chehab nInit * 10);
29700c0d06caSMauro Carvalho Chehab
29710c0d06caSMauro Carvalho Chehab /*
29720c0d06caSMauro Carvalho Chehab * readAck
29730c0d06caSMauro Carvalho Chehab * through clock stretch, slave has given a SCL signal,
29740c0d06caSMauro Carvalho Chehab * so the SDA data can be directly read.
29750c0d06caSMauro Carvalho Chehab */
29766b236a37SHans Verkuil status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
29770c0d06caSMauro Carvalho Chehab
29780c0d06caSMauro Carvalho Chehab if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
29790c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value;
29800c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
29810c0d06caSMauro Carvalho Chehab status = 0;
29820c0d06caSMauro Carvalho Chehab } else {
29830c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value;
29840c0d06caSMauro Carvalho Chehab dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
29850c0d06caSMauro Carvalho Chehab }
29860c0d06caSMauro Carvalho Chehab
29870c0d06caSMauro Carvalho Chehab /* read SDA end, set the SCL to output 0, after this operation,
29880c0d06caSMauro Carvalho Chehab SDA direction can be changed. */
29890c0d06caSMauro Carvalho Chehab dev->gpio_val = gpio_logic_value;
29900c0d06caSMauro Carvalho Chehab dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
29910c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
29926b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
29930c0d06caSMauro Carvalho Chehab
29940c0d06caSMauro Carvalho Chehab return status;
29950c0d06caSMauro Carvalho Chehab }
29960c0d06caSMauro Carvalho Chehab
cx231xx_gpio_i2c_write_ack(struct cx231xx * dev)29970c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
29980c0d06caSMauro Carvalho Chehab {
29990c0d06caSMauro Carvalho Chehab int status = 0;
30000c0d06caSMauro Carvalho Chehab
30013e4d8f48SMauro Carvalho Chehab /* set SDA to output */
30020c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
30036b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30040c0d06caSMauro Carvalho Chehab
30050c0d06caSMauro Carvalho Chehab /* set SCL = 0 (output); set SDA = 0 (output) */
30060c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
30070c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
30086b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30090c0d06caSMauro Carvalho Chehab
30100c0d06caSMauro Carvalho Chehab /* set SCL = 1 (output); set SDA = 0 (output) */
30110c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
30126b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30130c0d06caSMauro Carvalho Chehab
30140c0d06caSMauro Carvalho Chehab /* set SCL = 0 (output); set SDA = 0 (output) */
30150c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
30166b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30170c0d06caSMauro Carvalho Chehab
30180c0d06caSMauro Carvalho Chehab /* set SDA to input,and then the slave will read data from SDA. */
30190c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
30206b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30210c0d06caSMauro Carvalho Chehab
30220c0d06caSMauro Carvalho Chehab return status;
30230c0d06caSMauro Carvalho Chehab }
30240c0d06caSMauro Carvalho Chehab
cx231xx_gpio_i2c_write_nak(struct cx231xx * dev)30250c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
30260c0d06caSMauro Carvalho Chehab {
30270c0d06caSMauro Carvalho Chehab int status = 0;
30280c0d06caSMauro Carvalho Chehab
30290c0d06caSMauro Carvalho Chehab /* set scl to output ; set sda to input */
30300c0d06caSMauro Carvalho Chehab dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
30310c0d06caSMauro Carvalho Chehab dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
30326b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30330c0d06caSMauro Carvalho Chehab
30340c0d06caSMauro Carvalho Chehab /* set scl to output 0; set sda to input */
30350c0d06caSMauro Carvalho Chehab dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
30366b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30370c0d06caSMauro Carvalho Chehab
30380c0d06caSMauro Carvalho Chehab /* set scl to output 1; set sda to input */
30390c0d06caSMauro Carvalho Chehab dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
30406b236a37SHans Verkuil status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
30410c0d06caSMauro Carvalho Chehab
30420c0d06caSMauro Carvalho Chehab return status;
30430c0d06caSMauro Carvalho Chehab }
30440c0d06caSMauro Carvalho Chehab
30450c0d06caSMauro Carvalho Chehab /*****************************************************************************
30460c0d06caSMauro Carvalho Chehab * G P I O I2C related functions *
30470c0d06caSMauro Carvalho Chehab ******************************************************************************/
30480c0d06caSMauro Carvalho Chehab /* cx231xx_gpio_i2c_read
30490c0d06caSMauro Carvalho Chehab * Function to read data from gpio based I2C interface
30500c0d06caSMauro Carvalho Chehab */
cx231xx_gpio_i2c_read(struct cx231xx * dev,u8 dev_addr,u8 * buf,u8 len)30510c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
30520c0d06caSMauro Carvalho Chehab {
30530c0d06caSMauro Carvalho Chehab int status = 0;
30540c0d06caSMauro Carvalho Chehab int i = 0;
30550c0d06caSMauro Carvalho Chehab
30560c0d06caSMauro Carvalho Chehab /* get the lock */
30570c0d06caSMauro Carvalho Chehab mutex_lock(&dev->gpio_i2c_lock);
30580c0d06caSMauro Carvalho Chehab
30590c0d06caSMauro Carvalho Chehab /* start */
30600c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_start(dev);
30610c0d06caSMauro Carvalho Chehab
30620c0d06caSMauro Carvalho Chehab /* write dev_addr */
30630c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
30640c0d06caSMauro Carvalho Chehab
30650c0d06caSMauro Carvalho Chehab /* readAck */
30660c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_read_ack(dev);
30670c0d06caSMauro Carvalho Chehab
30680c0d06caSMauro Carvalho Chehab /* read data */
30690c0d06caSMauro Carvalho Chehab for (i = 0; i < len; i++) {
30700c0d06caSMauro Carvalho Chehab /* read data */
30710c0d06caSMauro Carvalho Chehab buf[i] = 0;
30720c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
30730c0d06caSMauro Carvalho Chehab
30740c0d06caSMauro Carvalho Chehab if ((i + 1) != len) {
30750c0d06caSMauro Carvalho Chehab /* only do write ack if we more length */
30760c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_ack(dev);
30770c0d06caSMauro Carvalho Chehab }
30780c0d06caSMauro Carvalho Chehab }
30790c0d06caSMauro Carvalho Chehab
30800c0d06caSMauro Carvalho Chehab /* write NAK - inform reads are complete */
30810c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_write_nak(dev);
30820c0d06caSMauro Carvalho Chehab
30830c0d06caSMauro Carvalho Chehab /* write end */
30840c0d06caSMauro Carvalho Chehab status = cx231xx_gpio_i2c_end(dev);
30850c0d06caSMauro Carvalho Chehab
30860c0d06caSMauro Carvalho Chehab /* release the lock */
30870c0d06caSMauro Carvalho Chehab mutex_unlock(&dev->gpio_i2c_lock);
30880c0d06caSMauro Carvalho Chehab
30890c0d06caSMauro Carvalho Chehab return status;
30900c0d06caSMauro Carvalho Chehab }
30910c0d06caSMauro Carvalho Chehab
30920c0d06caSMauro Carvalho Chehab /* cx231xx_gpio_i2c_write
30930c0d06caSMauro Carvalho Chehab * Function to write data to gpio based I2C interface
30940c0d06caSMauro Carvalho Chehab */
cx231xx_gpio_i2c_write(struct cx231xx * dev,u8 dev_addr,u8 * buf,u8 len)30950c0d06caSMauro Carvalho Chehab int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
30960c0d06caSMauro Carvalho Chehab {
30970c0d06caSMauro Carvalho Chehab int i = 0;
30980c0d06caSMauro Carvalho Chehab
30990c0d06caSMauro Carvalho Chehab /* get the lock */
31000c0d06caSMauro Carvalho Chehab mutex_lock(&dev->gpio_i2c_lock);
31010c0d06caSMauro Carvalho Chehab
31020c0d06caSMauro Carvalho Chehab /* start */
31030c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_start(dev);
31040c0d06caSMauro Carvalho Chehab
31050c0d06caSMauro Carvalho Chehab /* write dev_addr */
31060c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
31070c0d06caSMauro Carvalho Chehab
31080c0d06caSMauro Carvalho Chehab /* read Ack */
31090c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_read_ack(dev);
31100c0d06caSMauro Carvalho Chehab
31110c0d06caSMauro Carvalho Chehab for (i = 0; i < len; i++) {
31120c0d06caSMauro Carvalho Chehab /* Write data */
31130c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_write_byte(dev, buf[i]);
31140c0d06caSMauro Carvalho Chehab
31150c0d06caSMauro Carvalho Chehab /* read Ack */
31160c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_read_ack(dev);
31170c0d06caSMauro Carvalho Chehab }
31180c0d06caSMauro Carvalho Chehab
31190c0d06caSMauro Carvalho Chehab /* write End */
31200c0d06caSMauro Carvalho Chehab cx231xx_gpio_i2c_end(dev);
31210c0d06caSMauro Carvalho Chehab
31220c0d06caSMauro Carvalho Chehab /* release the lock */
31230c0d06caSMauro Carvalho Chehab mutex_unlock(&dev->gpio_i2c_lock);
31240c0d06caSMauro Carvalho Chehab
31250c0d06caSMauro Carvalho Chehab return 0;
31260c0d06caSMauro Carvalho Chehab }
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