1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *
4  *  Support for a cx23417 mpeg encoder via cx231xx host port.
5  *
6  *    (c) 2004 Jelle Foks <jelle@foks.us>
7  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
8  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
9  *      - CX23885/7/8 support
10  *
11  *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
12  */
13 
14 #include "cx231xx.h"
15 
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/init.h>
19 #include <linux/fs.h>
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include <linux/firmware.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <media/v4l2-common.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/v4l2-event.h>
28 #include <media/drv-intf/cx2341x.h>
29 #include <media/tuner.h>
30 
31 #define CX231xx_FIRM_IMAGE_SIZE 376836
32 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
33 
34 /* for polaris ITVC */
35 #define ITVC_WRITE_DIR          0x03FDFC00
36 #define ITVC_READ_DIR            0x0001FC00
37 
38 #define  MCI_MEMORY_DATA_BYTE0          0x00
39 #define  MCI_MEMORY_DATA_BYTE1          0x08
40 #define  MCI_MEMORY_DATA_BYTE2          0x10
41 #define  MCI_MEMORY_DATA_BYTE3          0x18
42 
43 #define  MCI_MEMORY_ADDRESS_BYTE2       0x20
44 #define  MCI_MEMORY_ADDRESS_BYTE1       0x28
45 #define  MCI_MEMORY_ADDRESS_BYTE0       0x30
46 
47 #define  MCI_REGISTER_DATA_BYTE0        0x40
48 #define  MCI_REGISTER_DATA_BYTE1        0x48
49 #define  MCI_REGISTER_DATA_BYTE2        0x50
50 #define  MCI_REGISTER_DATA_BYTE3        0x58
51 
52 #define  MCI_REGISTER_ADDRESS_BYTE0     0x60
53 #define  MCI_REGISTER_ADDRESS_BYTE1     0x68
54 
55 #define  MCI_REGISTER_MODE              0x70
56 
57 /* Read and write modes for polaris ITVC */
58 #define  MCI_MODE_REGISTER_READ         0x000
59 #define  MCI_MODE_REGISTER_WRITE        0x100
60 #define  MCI_MODE_MEMORY_READ           0x000
61 #define  MCI_MODE_MEMORY_WRITE          0x4000
62 
63 static unsigned int mpegbufs = 8;
64 module_param(mpegbufs, int, 0644);
65 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
66 
67 static unsigned int mpeglines = 128;
68 module_param(mpeglines, int, 0644);
69 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
70 
71 static unsigned int mpeglinesize = 512;
72 module_param(mpeglinesize, int, 0644);
73 MODULE_PARM_DESC(mpeglinesize,
74 	"number of bytes in each line of an MPEG buffer, range 512-1024");
75 
76 static unsigned int v4l_debug = 1;
77 module_param(v4l_debug, int, 0644);
78 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
79 
80 #define dprintk(level, fmt, arg...)	\
81 	do {				\
82 		if (v4l_debug >= level) \
83 			printk(KERN_DEBUG pr_fmt(fmt), ## arg); \
84 	} while (0)
85 
86 static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
87 	{
88 		.name      = "NTSC-M",
89 		.id        = V4L2_STD_NTSC_M,
90 	}, {
91 		.name      = "NTSC-JP",
92 		.id        = V4L2_STD_NTSC_M_JP,
93 	}, {
94 		.name      = "PAL-BG",
95 		.id        = V4L2_STD_PAL_BG,
96 	}, {
97 		.name      = "PAL-DK",
98 		.id        = V4L2_STD_PAL_DK,
99 	}, {
100 		.name      = "PAL-I",
101 		.id        = V4L2_STD_PAL_I,
102 	}, {
103 		.name      = "PAL-M",
104 		.id        = V4L2_STD_PAL_M,
105 	}, {
106 		.name      = "PAL-N",
107 		.id        = V4L2_STD_PAL_N,
108 	}, {
109 		.name      = "PAL-Nc",
110 		.id        = V4L2_STD_PAL_Nc,
111 	}, {
112 		.name      = "PAL-60",
113 		.id        = V4L2_STD_PAL_60,
114 	}, {
115 		.name      = "SECAM-L",
116 		.id        = V4L2_STD_SECAM_L,
117 	}, {
118 		.name      = "SECAM-DK",
119 		.id        = V4L2_STD_SECAM_DK,
120 	}
121 };
122 
123 /* ------------------------------------------------------------------ */
124 
125 enum cx231xx_capture_type {
126 	CX231xx_MPEG_CAPTURE,
127 	CX231xx_RAW_CAPTURE,
128 	CX231xx_RAW_PASSTHRU_CAPTURE
129 };
130 
131 enum cx231xx_capture_bits {
132 	CX231xx_RAW_BITS_NONE             = 0x00,
133 	CX231xx_RAW_BITS_YUV_CAPTURE      = 0x01,
134 	CX231xx_RAW_BITS_PCM_CAPTURE      = 0x02,
135 	CX231xx_RAW_BITS_VBI_CAPTURE      = 0x04,
136 	CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
137 	CX231xx_RAW_BITS_TO_HOST_CAPTURE  = 0x10
138 };
139 
140 enum cx231xx_capture_end {
141 	CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
142 	CX231xx_END_NOW, /* stop immediately, no irq */
143 };
144 
145 enum cx231xx_framerate {
146 	CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
147 	CX231xx_FRAMERATE_PAL_25   /* PAL: 25fps */
148 };
149 
150 enum cx231xx_stream_port {
151 	CX231xx_OUTPUT_PORT_MEMORY,
152 	CX231xx_OUTPUT_PORT_STREAMING,
153 	CX231xx_OUTPUT_PORT_SERIAL
154 };
155 
156 enum cx231xx_data_xfer_status {
157 	CX231xx_MORE_BUFFERS_FOLLOW,
158 	CX231xx_LAST_BUFFER,
159 };
160 
161 enum cx231xx_picture_mask {
162 	CX231xx_PICTURE_MASK_NONE,
163 	CX231xx_PICTURE_MASK_I_FRAMES,
164 	CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
165 	CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
166 };
167 
168 enum cx231xx_vbi_mode_bits {
169 	CX231xx_VBI_BITS_SLICED,
170 	CX231xx_VBI_BITS_RAW,
171 };
172 
173 enum cx231xx_vbi_insertion_bits {
174 	CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
175 	CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
176 	CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
177 	CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
178 	CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
179 };
180 
181 enum cx231xx_dma_unit {
182 	CX231xx_DMA_BYTES,
183 	CX231xx_DMA_FRAMES,
184 };
185 
186 enum cx231xx_dma_transfer_status_bits {
187 	CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
188 	CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
189 	CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
190 };
191 
192 enum cx231xx_pause {
193 	CX231xx_PAUSE_ENCODING,
194 	CX231xx_RESUME_ENCODING,
195 };
196 
197 enum cx231xx_copyright {
198 	CX231xx_COPYRIGHT_OFF,
199 	CX231xx_COPYRIGHT_ON,
200 };
201 
202 enum cx231xx_notification_type {
203 	CX231xx_NOTIFICATION_REFRESH,
204 };
205 
206 enum cx231xx_notification_status {
207 	CX231xx_NOTIFICATION_OFF,
208 	CX231xx_NOTIFICATION_ON,
209 };
210 
211 enum cx231xx_notification_mailbox {
212 	CX231xx_NOTIFICATION_NO_MAILBOX = -1,
213 };
214 
215 enum cx231xx_field1_lines {
216 	CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
217 	CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
218 	CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
219 };
220 
221 enum cx231xx_field2_lines {
222 	CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
223 	CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
224 	CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
225 };
226 
227 enum cx231xx_custom_data_type {
228 	CX231xx_CUSTOM_EXTENSION_USR_DATA,
229 	CX231xx_CUSTOM_PRIVATE_PACKET,
230 };
231 
232 enum cx231xx_mute {
233 	CX231xx_UNMUTE,
234 	CX231xx_MUTE,
235 };
236 
237 enum cx231xx_mute_video_mask {
238 	CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
239 	CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
240 	CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
241 };
242 
243 enum cx231xx_mute_video_shift {
244 	CX231xx_MUTE_VIDEO_V_SHIFT = 8,
245 	CX231xx_MUTE_VIDEO_U_SHIFT = 16,
246 	CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
247 };
248 
249 /* defines below are from ivtv-driver.h */
250 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
251 
252 /* Firmware API commands */
253 #define IVTV_API_STD_TIMEOUT 500
254 
255 /* Registers */
256 /* IVTV_REG_OFFSET */
257 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
258 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
259 #define IVTV_REG_SPU (0x9050)
260 #define IVTV_REG_HW_BLOCKS (0x9054)
261 #define IVTV_REG_VPU (0x9058)
262 #define IVTV_REG_APU (0xA064)
263 
264 /*
265  * Bit definitions for MC417_RWD and MC417_OEN registers
266  *
267  * bits 31-16
268  *+-----------+
269  *| Reserved  |
270  *|+-----------+
271  *|  bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
272  *|+-------+-------+-------+-------+-------+-------+-------+-------+
273  *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
274  *|+-------+-------+-------+-------+-------+-------+-------+-------+
275  *| bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
276  *|+-------+-------+-------+-------+-------+-------+-------+-------+
277  *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
278  *|+-------+-------+-------+-------+-------+-------+-------+-------+
279  */
280 #define MC417_MIWR	0x8000
281 #define MC417_MIRD	0x4000
282 #define MC417_MICS	0x2000
283 #define MC417_MIRDY	0x1000
284 #define MC417_MIADDR	0x0F00
285 #define MC417_MIDATA	0x00FF
286 
287 
288 /* Bit definitions for MC417_CTL register ****
289  *bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
290  *+--------+-------------+--------+--------------+------------+
291  *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
292  *+--------+-------------+--------+--------------+------------+
293  */
294 #define MC417_SPD_CTL(x)	(((x) << 4) & 0x00000030)
295 #define MC417_GPIO_SEL(x)	(((x) << 1) & 0x00000006)
296 #define MC417_UART_GPIO_EN	0x00000001
297 
298 /* Values for speed control */
299 #define MC417_SPD_CTL_SLOW	0x1
300 #define MC417_SPD_CTL_MEDIUM	0x0
301 #define MC417_SPD_CTL_FAST	0x3     /* b'1x, but we use b'11 */
302 
303 /* Values for GPIO select */
304 #define MC417_GPIO_SEL_GPIO3	0x3
305 #define MC417_GPIO_SEL_GPIO2	0x2
306 #define MC417_GPIO_SEL_GPIO1	0x1
307 #define MC417_GPIO_SEL_GPIO0	0x0
308 
309 
310 #define CX23417_GPIO_MASK 0xFC0003FF
311 
312 static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value)
313 {
314 	int status = 0;
315 	u32 _gpio_direction = 0;
316 
317 	_gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
318 	_gpio_direction = _gpio_direction | gpio_direction;
319 	status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
320 			 (u8 *)&value, 4, 0, 0);
321 	return status;
322 }
323 
324 static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr)
325 {
326 	int status = 0;
327 	u32 _gpio_direction = 0;
328 
329 	_gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
330 	_gpio_direction = _gpio_direction | gpio_direction;
331 
332 	status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
333 		 (u8 *)val_ptr, 4, 0, 1);
334 	return status;
335 }
336 
337 static int wait_for_mci_complete(struct cx231xx *dev)
338 {
339 	u32 gpio;
340 	u32 gpio_direction = 0;
341 	u8 count = 0;
342 	get_itvc_reg(dev, gpio_direction, &gpio);
343 
344 	while (!(gpio&0x020000)) {
345 		msleep(10);
346 
347 		get_itvc_reg(dev, gpio_direction, &gpio);
348 
349 		if (count++ > 100) {
350 			dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
351 			return -EIO;
352 		}
353 	}
354 	return 0;
355 }
356 
357 static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
358 {
359 	u32 temp;
360 	int status = 0;
361 
362 	temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8);
363 	temp = temp << 10;
364 	status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
365 	if (status < 0)
366 		return status;
367 	temp = temp | (0x05 << 10);
368 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
369 
370 	/*write data byte 1;*/
371 	temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00);
372 	temp = temp << 10;
373 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
374 	temp = temp | (0x05 << 10);
375 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
376 
377 	/*write data byte 2;*/
378 	temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
379 	temp = temp << 10;
380 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
381 	temp = temp | (0x05 << 10);
382 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
383 
384 	/*write data byte 3;*/
385 	temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
386 	temp = temp << 10;
387 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
388 	temp = temp | (0x05 << 10);
389 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
390 
391 	/*write address byte 0;*/
392 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8);
393 	temp = temp << 10;
394 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
395 	temp = temp | (0x05 << 10);
396 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
397 
398 	/*write address byte 1;*/
399 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00);
400 	temp = temp << 10;
401 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
402 	temp = temp | (0x05 << 10);
403 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
404 
405 	/*Write that the mode is write.*/
406 	temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
407 	temp = temp << 10;
408 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
409 	temp = temp | (0x05 << 10);
410 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
411 
412 	return wait_for_mci_complete(dev);
413 }
414 
415 static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
416 {
417 	/*write address byte 0;*/
418 	u32 temp;
419 	u32 return_value = 0;
420 	int ret = 0;
421 
422 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
423 	temp = temp << 10;
424 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
425 	temp = temp | ((0x05) << 10);
426 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
427 
428 	/*write address byte 1;*/
429 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
430 	temp = temp << 10;
431 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
432 	temp = temp | ((0x05) << 10);
433 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
434 
435 	/*write that the mode is read;*/
436 	temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
437 	temp = temp << 10;
438 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
439 	temp = temp | ((0x05) << 10);
440 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
441 
442 	/*wait for the MIRDY line to be asserted ,
443 	signalling that the read is done;*/
444 	ret = wait_for_mci_complete(dev);
445 
446 	/*switch the DATA- GPIO to input mode;*/
447 
448 	/*Read data byte 0;*/
449 	temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
450 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
451 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
452 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
453 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
454 	return_value |= ((temp & 0x03FC0000) >> 18);
455 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
456 
457 	/* Read data byte 1;*/
458 	temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
459 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
460 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
461 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
462 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
463 
464 	return_value |= ((temp & 0x03FC0000) >> 10);
465 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
466 
467 	/*Read data byte 2;*/
468 	temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
469 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
470 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
471 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
472 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
473 	return_value |= ((temp & 0x03FC0000) >> 2);
474 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
475 
476 	/*Read data byte 3;*/
477 	temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
478 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
479 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
480 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
481 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
482 	return_value |= ((temp & 0x03FC0000) << 6);
483 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
484 
485 	*value  = return_value;
486 	return ret;
487 }
488 
489 static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
490 {
491 	/*write data byte 0;*/
492 
493 	u32 temp;
494 	int ret = 0;
495 
496 	temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
497 	temp = temp << 10;
498 	ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
499 	if (ret < 0)
500 		return ret;
501 	temp = temp | (0x05 << 10);
502 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
503 
504 	/*write data byte 1;*/
505 	temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
506 	temp = temp << 10;
507 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
508 	temp = temp | (0x05 << 10);
509 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
510 
511 	/*write data byte 2;*/
512 	temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
513 	temp = temp << 10;
514 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
515 	temp = temp | (0x05 << 10);
516 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
517 
518 	/*write data byte 3;*/
519 	temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
520 	temp = temp << 10;
521 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
522 	temp = temp | (0x05 << 10);
523 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
524 
525 	/* write address byte 2;*/
526 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
527 		((address & 0x003F0000) >> 8);
528 	temp = temp << 10;
529 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
530 	temp = temp | (0x05 << 10);
531 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
532 
533 	/* write address byte 1;*/
534 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
535 	temp = temp << 10;
536 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
537 	temp = temp | (0x05 << 10);
538 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
539 
540 	/* write address byte 0;*/
541 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
542 	temp = temp << 10;
543 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
544 	temp = temp | (0x05 << 10);
545 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
546 
547 	/*wait for MIRDY line;*/
548 	wait_for_mci_complete(dev);
549 
550 	return 0;
551 }
552 
553 static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
554 {
555 	u32 temp = 0;
556 	u32 return_value = 0;
557 	int ret = 0;
558 
559 	/*write address byte 2;*/
560 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
561 		((address & 0x003F0000) >> 8);
562 	temp = temp << 10;
563 	ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
564 	if (ret < 0)
565 		return ret;
566 	temp = temp | (0x05 << 10);
567 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
568 
569 	/*write address byte 1*/
570 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
571 	temp = temp << 10;
572 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
573 	temp = temp | (0x05 << 10);
574 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
575 
576 	/*write address byte 0*/
577 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
578 	temp = temp << 10;
579 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
580 	temp = temp | (0x05 << 10);
581 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
582 
583 	/*Wait for MIRDY line*/
584 	ret = wait_for_mci_complete(dev);
585 
586 
587 	/*Read data byte 3;*/
588 	temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10;
589 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
590 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10);
591 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
592 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
593 	return_value |= ((temp & 0x03FC0000) << 6);
594 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
595 
596 	/*Read data byte 2;*/
597 	temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10;
598 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
599 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10);
600 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
601 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
602 	return_value |= ((temp & 0x03FC0000) >> 2);
603 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
604 
605 	/* Read data byte 1;*/
606 	temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10;
607 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
608 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10);
609 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
610 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
611 	return_value |= ((temp & 0x03FC0000) >> 10);
612 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
613 
614 	/*Read data byte 0;*/
615 	temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10;
616 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
617 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10);
618 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
619 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
620 	return_value |= ((temp & 0x03FC0000) >> 18);
621 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
622 
623 	*value  = return_value;
624 	return ret;
625 }
626 
627 /* ------------------------------------------------------------------ */
628 
629 /* MPEG encoder API */
630 static char *cmd_to_str(int cmd)
631 {
632 	switch (cmd) {
633 	case CX2341X_ENC_PING_FW:
634 		return "PING_FW";
635 	case CX2341X_ENC_START_CAPTURE:
636 		return "START_CAPTURE";
637 	case CX2341X_ENC_STOP_CAPTURE:
638 		return "STOP_CAPTURE";
639 	case CX2341X_ENC_SET_AUDIO_ID:
640 		return "SET_AUDIO_ID";
641 	case CX2341X_ENC_SET_VIDEO_ID:
642 		return "SET_VIDEO_ID";
643 	case CX2341X_ENC_SET_PCR_ID:
644 		return "SET_PCR_PID";
645 	case CX2341X_ENC_SET_FRAME_RATE:
646 		return "SET_FRAME_RATE";
647 	case CX2341X_ENC_SET_FRAME_SIZE:
648 		return "SET_FRAME_SIZE";
649 	case CX2341X_ENC_SET_BIT_RATE:
650 		return "SET_BIT_RATE";
651 	case CX2341X_ENC_SET_GOP_PROPERTIES:
652 		return "SET_GOP_PROPERTIES";
653 	case CX2341X_ENC_SET_ASPECT_RATIO:
654 		return "SET_ASPECT_RATIO";
655 	case CX2341X_ENC_SET_DNR_FILTER_MODE:
656 		return "SET_DNR_FILTER_PROPS";
657 	case CX2341X_ENC_SET_DNR_FILTER_PROPS:
658 		return "SET_DNR_FILTER_PROPS";
659 	case CX2341X_ENC_SET_CORING_LEVELS:
660 		return "SET_CORING_LEVELS";
661 	case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
662 		return "SET_SPATIAL_FILTER_TYPE";
663 	case CX2341X_ENC_SET_VBI_LINE:
664 		return "SET_VBI_LINE";
665 	case CX2341X_ENC_SET_STREAM_TYPE:
666 		return "SET_STREAM_TYPE";
667 	case CX2341X_ENC_SET_OUTPUT_PORT:
668 		return "SET_OUTPUT_PORT";
669 	case CX2341X_ENC_SET_AUDIO_PROPERTIES:
670 		return "SET_AUDIO_PROPERTIES";
671 	case CX2341X_ENC_HALT_FW:
672 		return "HALT_FW";
673 	case CX2341X_ENC_GET_VERSION:
674 		return "GET_VERSION";
675 	case CX2341X_ENC_SET_GOP_CLOSURE:
676 		return "SET_GOP_CLOSURE";
677 	case CX2341X_ENC_GET_SEQ_END:
678 		return "GET_SEQ_END";
679 	case CX2341X_ENC_SET_PGM_INDEX_INFO:
680 		return "SET_PGM_INDEX_INFO";
681 	case CX2341X_ENC_SET_VBI_CONFIG:
682 		return "SET_VBI_CONFIG";
683 	case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
684 		return "SET_DMA_BLOCK_SIZE";
685 	case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
686 		return "GET_PREV_DMA_INFO_MB_10";
687 	case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
688 		return "GET_PREV_DMA_INFO_MB_9";
689 	case CX2341X_ENC_SCHED_DMA_TO_HOST:
690 		return "SCHED_DMA_TO_HOST";
691 	case CX2341X_ENC_INITIALIZE_INPUT:
692 		return "INITIALIZE_INPUT";
693 	case CX2341X_ENC_SET_FRAME_DROP_RATE:
694 		return "SET_FRAME_DROP_RATE";
695 	case CX2341X_ENC_PAUSE_ENCODER:
696 		return "PAUSE_ENCODER";
697 	case CX2341X_ENC_REFRESH_INPUT:
698 		return "REFRESH_INPUT";
699 	case CX2341X_ENC_SET_COPYRIGHT:
700 		return "SET_COPYRIGHT";
701 	case CX2341X_ENC_SET_EVENT_NOTIFICATION:
702 		return "SET_EVENT_NOTIFICATION";
703 	case CX2341X_ENC_SET_NUM_VSYNC_LINES:
704 		return "SET_NUM_VSYNC_LINES";
705 	case CX2341X_ENC_SET_PLACEHOLDER:
706 		return "SET_PLACEHOLDER";
707 	case CX2341X_ENC_MUTE_VIDEO:
708 		return "MUTE_VIDEO";
709 	case CX2341X_ENC_MUTE_AUDIO:
710 		return "MUTE_AUDIO";
711 	case CX2341X_ENC_MISC:
712 		return "MISC";
713 	default:
714 		return "UNKNOWN";
715 	}
716 }
717 
718 static int cx231xx_mbox_func(void *priv, u32 command, int in, int out,
719 			     u32 data[CX2341X_MBOX_MAX_DATA])
720 {
721 	struct cx231xx *dev = priv;
722 	unsigned long timeout;
723 	u32 value, flag, retval = 0;
724 	int i;
725 
726 	dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
727 		cmd_to_str(command));
728 
729 	/* this may not be 100% safe if we can't read any memory location
730 	   without side effects */
731 	mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
732 	if (value != 0x12345678) {
733 		dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n",
734 			value, cmd_to_str(command));
735 		return -EIO;
736 	}
737 
738 	/* This read looks at 32 bits, but flag is only 8 bits.
739 	 * Seems we also bail if CMD or TIMEOUT bytes are set???
740 	 */
741 	mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
742 	if (flag) {
743 		dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n",
744 				flag, cmd_to_str(command));
745 		return -EBUSY;
746 	}
747 
748 	flag |= 1; /* tell 'em we're working on it */
749 	mc417_memory_write(dev, dev->cx23417_mailbox, flag);
750 
751 	/* write command + args + fill remaining with zeros */
752 	/* command code */
753 	mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
754 	mc417_memory_write(dev, dev->cx23417_mailbox + 3,
755 		IVTV_API_STD_TIMEOUT); /* timeout */
756 	for (i = 0; i < in; i++) {
757 		mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
758 		dprintk(3, "API Input %d = %d\n", i, data[i]);
759 	}
760 	for (; i < CX2341X_MBOX_MAX_DATA; i++)
761 		mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
762 
763 	flag |= 3; /* tell 'em we're done writing */
764 	mc417_memory_write(dev, dev->cx23417_mailbox, flag);
765 
766 	/* wait for firmware to handle the API command */
767 	timeout = jiffies + msecs_to_jiffies(10);
768 	for (;;) {
769 		mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
770 		if (0 != (flag & 4))
771 			break;
772 		if (time_after(jiffies, timeout)) {
773 			dprintk(3, "ERROR: API Mailbox timeout\n");
774 			return -EIO;
775 		}
776 		udelay(10);
777 	}
778 
779 	/* read output values */
780 	for (i = 0; i < out; i++) {
781 		mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
782 		dprintk(3, "API Output %d = %d\n", i, data[i]);
783 	}
784 
785 	mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
786 	dprintk(3, "API result = %d\n", retval);
787 
788 	flag = 0;
789 	mc417_memory_write(dev, dev->cx23417_mailbox, flag);
790 
791 	return 0;
792 }
793 
794 /* We don't need to call the API often, so using just one
795  * mailbox will probably suffice
796  */
797 static int cx231xx_api_cmd(struct cx231xx *dev, u32 command,
798 		u32 inputcnt, u32 outputcnt, ...)
799 {
800 	u32 data[CX2341X_MBOX_MAX_DATA];
801 	va_list vargs;
802 	int i, err;
803 
804 	dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
805 
806 	va_start(vargs, outputcnt);
807 	for (i = 0; i < inputcnt; i++)
808 		data[i] = va_arg(vargs, int);
809 
810 	err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
811 	for (i = 0; i < outputcnt; i++) {
812 		int *vptr = va_arg(vargs, int *);
813 		*vptr = data[i];
814 	}
815 	va_end(vargs);
816 
817 	return err;
818 }
819 
820 
821 static int cx231xx_find_mailbox(struct cx231xx *dev)
822 {
823 	u32 signature[4] = {
824 		0x12345678, 0x34567812, 0x56781234, 0x78123456
825 	};
826 	int signaturecnt = 0;
827 	u32 value;
828 	int i;
829 	int ret = 0;
830 
831 	dprintk(2, "%s()\n", __func__);
832 
833 	for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
834 		ret = mc417_memory_read(dev, i, &value);
835 		if (ret < 0)
836 			return ret;
837 		if (value == signature[signaturecnt])
838 			signaturecnt++;
839 		else
840 			signaturecnt = 0;
841 		if (4 == signaturecnt) {
842 			dprintk(1, "Mailbox signature found at 0x%x\n", i + 1);
843 			return i + 1;
844 		}
845 	}
846 	dprintk(3, "Mailbox signature values not found!\n");
847 	return -EIO;
848 }
849 
850 static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value,
851 		u32 *p_fw_image)
852 {
853 	u32 temp = 0;
854 	int i = 0;
855 
856 	temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
857 	temp = temp << 10;
858 	*p_fw_image = temp;
859 	p_fw_image++;
860 	temp = temp | (0x05 << 10);
861 	*p_fw_image = temp;
862 	p_fw_image++;
863 
864 	/*write data byte 1;*/
865 	temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
866 	temp = temp << 10;
867 	*p_fw_image = temp;
868 	p_fw_image++;
869 	temp = temp | (0x05 << 10);
870 	*p_fw_image = temp;
871 	p_fw_image++;
872 
873 	/*write data byte 2;*/
874 	temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
875 	temp = temp << 10;
876 	*p_fw_image = temp;
877 	p_fw_image++;
878 	temp = temp | (0x05 << 10);
879 	*p_fw_image = temp;
880 	p_fw_image++;
881 
882 	/*write data byte 3;*/
883 	temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
884 	temp = temp << 10;
885 	*p_fw_image = temp;
886 	p_fw_image++;
887 	temp = temp | (0x05 << 10);
888 	*p_fw_image = temp;
889 	p_fw_image++;
890 
891 	/* write address byte 2;*/
892 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
893 		((address & 0x003F0000) >> 8);
894 	temp = temp << 10;
895 	*p_fw_image = temp;
896 	p_fw_image++;
897 	temp = temp | (0x05 << 10);
898 	*p_fw_image = temp;
899 	p_fw_image++;
900 
901 	/* write address byte 1;*/
902 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
903 	temp = temp << 10;
904 	*p_fw_image = temp;
905 	p_fw_image++;
906 	temp = temp | (0x05 << 10);
907 	*p_fw_image = temp;
908 	p_fw_image++;
909 
910 	/* write address byte 0;*/
911 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
912 	temp = temp << 10;
913 	*p_fw_image = temp;
914 	p_fw_image++;
915 	temp = temp | (0x05 << 10);
916 	*p_fw_image = temp;
917 	p_fw_image++;
918 
919 	for (i = 0; i < 6; i++) {
920 		*p_fw_image = 0xFFFFFFFF;
921 		p_fw_image++;
922 	}
923 }
924 
925 
926 static int cx231xx_load_firmware(struct cx231xx *dev)
927 {
928 	static const unsigned char magic[8] = {
929 		0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
930 	};
931 	const struct firmware *firmware;
932 	int i, retval = 0;
933 	u32 value = 0;
934 	u32 gpio_output = 0;
935 	/*u32 checksum = 0;*/
936 	/*u32 *dataptr;*/
937 	u32 transfer_size = 0;
938 	u32 fw_data = 0;
939 	u32 address = 0;
940 	/*u32 current_fw[800];*/
941 	u32 *p_current_fw, *p_fw;
942 	u32 *p_fw_data;
943 	int frame = 0;
944 	u16 _buffer_size = 4096;
945 	u8 *p_buffer;
946 
947 	p_current_fw = vmalloc(1884180 * 4);
948 	p_fw = p_current_fw;
949 	if (p_current_fw == NULL) {
950 		dprintk(2, "FAIL!!!\n");
951 		return -ENOMEM;
952 	}
953 
954 	p_buffer = vmalloc(4096);
955 	if (p_buffer == NULL) {
956 		dprintk(2, "FAIL!!!\n");
957 		vfree(p_current_fw);
958 		return -ENOMEM;
959 	}
960 
961 	dprintk(2, "%s()\n", __func__);
962 
963 	/* Save GPIO settings before reset of APU */
964 	retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
965 	retval |= mc417_memory_read(dev, 0x900C, &value);
966 
967 	retval  = mc417_register_write(dev,
968 		IVTV_REG_VPU, 0xFFFFFFED);
969 	retval |= mc417_register_write(dev,
970 		IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
971 	retval |= mc417_register_write(dev,
972 		IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
973 	retval |= mc417_register_write(dev,
974 		IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
975 	retval |= mc417_register_write(dev,
976 		IVTV_REG_APU, 0);
977 
978 	if (retval != 0) {
979 		dev_err(dev->dev,
980 			"%s: Error with mc417_register_write\n", __func__);
981 		vfree(p_current_fw);
982 		vfree(p_buffer);
983 		return retval;
984 	}
985 
986 	retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
987 				  dev->dev);
988 
989 	if (retval != 0) {
990 		dev_err(dev->dev,
991 			"ERROR: Hotplug firmware request failed (%s).\n",
992 			CX231xx_FIRM_IMAGE_NAME);
993 		dev_err(dev->dev,
994 			"Please fix your hotplug setup, the board will not work without firmware loaded!\n");
995 		vfree(p_current_fw);
996 		vfree(p_buffer);
997 		return retval;
998 	}
999 
1000 	if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1001 		dev_err(dev->dev,
1002 			"ERROR: Firmware size mismatch (have %zd, expected %d)\n",
1003 			firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1004 		release_firmware(firmware);
1005 		vfree(p_current_fw);
1006 		vfree(p_buffer);
1007 		return -EINVAL;
1008 	}
1009 
1010 	if (0 != memcmp(firmware->data, magic, 8)) {
1011 		dev_err(dev->dev,
1012 			"ERROR: Firmware magic mismatch, wrong file?\n");
1013 		release_firmware(firmware);
1014 		vfree(p_current_fw);
1015 		vfree(p_buffer);
1016 		return -EINVAL;
1017 	}
1018 
1019 	initGPIO(dev);
1020 
1021 	/* transfer to the chip */
1022 	dprintk(2, "Loading firmware to GPIO...\n");
1023 	p_fw_data = (u32 *)firmware->data;
1024 	dprintk(2, "firmware->size=%zd\n", firmware->size);
1025 	for (transfer_size = 0; transfer_size < firmware->size;
1026 		 transfer_size += 4) {
1027 		fw_data = *p_fw_data;
1028 
1029 		mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw);
1030 		address = address + 1;
1031 		p_current_fw += 20;
1032 		p_fw_data += 1;
1033 	}
1034 
1035 	/*download the firmware by ep5-out*/
1036 
1037 	for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1038 	     frame++) {
1039 		for (i = 0; i < _buffer_size; i++) {
1040 			*(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1041 			i++;
1042 			*(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1043 			i++;
1044 			*(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1045 			i++;
1046 			*(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
1047 		}
1048 		cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1049 	}
1050 
1051 	p_current_fw = p_fw;
1052 	vfree(p_current_fw);
1053 	p_current_fw = NULL;
1054 	vfree(p_buffer);
1055 	uninitGPIO(dev);
1056 	release_firmware(firmware);
1057 	dprintk(1, "Firmware upload successful.\n");
1058 
1059 	retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1060 		IVTV_CMD_HW_BLOCKS_RST);
1061 	if (retval < 0) {
1062 		dev_err(dev->dev,
1063 			"%s: Error with mc417_register_write\n",
1064 			__func__);
1065 		return retval;
1066 	}
1067 	/* F/W power up disturbs the GPIOs, restore state */
1068 	retval |= mc417_register_write(dev, 0x9020, gpio_output);
1069 	retval |= mc417_register_write(dev, 0x900C, value);
1070 
1071 	retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1072 	retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1073 
1074 	if (retval < 0) {
1075 		dev_err(dev->dev,
1076 			"%s: Error with mc417_register_write\n",
1077 			__func__);
1078 		return retval;
1079 	}
1080 	return 0;
1081 }
1082 
1083 static void cx231xx_417_check_encoder(struct cx231xx *dev)
1084 {
1085 	u32 status, seq;
1086 
1087 	status = 0;
1088 	seq = 0;
1089 	cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1090 	dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1091 }
1092 
1093 static void cx231xx_codec_settings(struct cx231xx *dev)
1094 {
1095 	dprintk(1, "%s()\n", __func__);
1096 
1097 	/* assign frame size */
1098 	cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1099 				dev->ts1.height, dev->ts1.width);
1100 
1101 	dev->mpeg_ctrl_handler.width = dev->ts1.width;
1102 	dev->mpeg_ctrl_handler.height = dev->ts1.height;
1103 
1104 	cx2341x_handler_setup(&dev->mpeg_ctrl_handler);
1105 
1106 	cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1107 	cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1108 }
1109 
1110 static int cx231xx_initialize_codec(struct cx231xx *dev)
1111 {
1112 	int version;
1113 	int retval;
1114 	u32 i;
1115 	u32 val = 0;
1116 
1117 	dprintk(1, "%s()\n", __func__);
1118 	cx231xx_disable656(dev);
1119 	retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1120 	if (retval < 0) {
1121 		dprintk(2, "%s: PING OK\n", __func__);
1122 		retval = cx231xx_load_firmware(dev);
1123 		if (retval < 0) {
1124 			dev_err(dev->dev,
1125 				"%s: f/w load failed\n", __func__);
1126 			return retval;
1127 		}
1128 		retval = cx231xx_find_mailbox(dev);
1129 		if (retval < 0) {
1130 			dev_err(dev->dev, "%s: mailbox < 0, error\n",
1131 				__func__);
1132 			return retval;
1133 		}
1134 		dev->cx23417_mailbox = retval;
1135 		retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1136 		if (retval < 0) {
1137 			dev_err(dev->dev,
1138 				"ERROR: cx23417 firmware ping failed!\n");
1139 			return retval;
1140 		}
1141 		retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1142 			&version);
1143 		if (retval < 0) {
1144 			dev_err(dev->dev,
1145 				"ERROR: cx23417 firmware get encoder: version failed!\n");
1146 			return retval;
1147 		}
1148 		dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1149 		msleep(200);
1150 	}
1151 
1152 	for (i = 0; i < 1; i++) {
1153 		retval = mc417_register_read(dev, 0x20f8, &val);
1154 		dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n",
1155 				 val);
1156 		if (retval < 0)
1157 			return retval;
1158 	}
1159 
1160 	cx231xx_enable656(dev);
1161 
1162 	/* stop mpeg capture */
1163 	cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, 1, 3, 4);
1164 
1165 	cx231xx_codec_settings(dev);
1166 	msleep(60);
1167 
1168 /*	cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1169 		CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1170 	cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1171 		CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1172 		0, 0);
1173 */
1174 
1175 #if 0
1176 	/* TODO */
1177 	u32 data[7];
1178 
1179 	/* Setup to capture VBI */
1180 	data[0] = 0x0001BD00;
1181 	data[1] = 1;          /* frames per interrupt */
1182 	data[2] = 4;          /* total bufs */
1183 	data[3] = 0x91559155; /* start codes */
1184 	data[4] = 0x206080C0; /* stop codes */
1185 	data[5] = 6;          /* lines */
1186 	data[6] = 64;         /* BPL */
1187 
1188 	cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1189 		data[2], data[3], data[4], data[5], data[6]);
1190 
1191 	for (i = 2; i <= 24; i++) {
1192 		int valid;
1193 
1194 		valid = ((i >= 19) && (i <= 21));
1195 		cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1196 				valid, 0 , 0, 0);
1197 		cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1198 				i | 0x80000000, valid, 0, 0, 0);
1199 	}
1200 #endif
1201 /*	cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1202 	msleep(60);
1203 */
1204 	/* initialize the video input */
1205 	retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1206 	if (retval < 0)
1207 		return retval;
1208 	msleep(60);
1209 
1210 	/* Enable VIP style pixel invalidation so we work with scaled mode */
1211 	mc417_memory_write(dev, 2120, 0x00000080);
1212 
1213 	/* start capturing to the host interface */
1214 	retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1215 		CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1216 	if (retval < 0)
1217 		return retval;
1218 	msleep(10);
1219 
1220 	for (i = 0; i < 1; i++) {
1221 		mc417_register_read(dev, 0x20f8, &val);
1222 		dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1223 	}
1224 
1225 	return 0;
1226 }
1227 
1228 /* ------------------------------------------------------------------ */
1229 
1230 static int bb_buf_setup(struct videobuf_queue *q,
1231 	unsigned int *count, unsigned int *size)
1232 {
1233 	struct cx231xx_fh *fh = q->priv_data;
1234 
1235 	fh->dev->ts1.ts_packet_size  = mpeglinesize;
1236 	fh->dev->ts1.ts_packet_count = mpeglines;
1237 
1238 	*size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1239 	*count = mpegbufs;
1240 
1241 	return 0;
1242 }
1243 
1244 static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1245 {
1246 	struct cx231xx_fh *fh = vq->priv_data;
1247 	struct cx231xx *dev = fh->dev;
1248 	unsigned long flags = 0;
1249 
1250 	BUG_ON(in_interrupt());
1251 
1252 	spin_lock_irqsave(&dev->video_mode.slock, flags);
1253 	if (dev->USE_ISO) {
1254 		if (dev->video_mode.isoc_ctl.buf == buf)
1255 			dev->video_mode.isoc_ctl.buf = NULL;
1256 	} else {
1257 		if (dev->video_mode.bulk_ctl.buf == buf)
1258 			dev->video_mode.bulk_ctl.buf = NULL;
1259 	}
1260 	spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1261 	videobuf_waiton(vq, &buf->vb, 0, 0);
1262 	videobuf_vmalloc_free(&buf->vb);
1263 	buf->vb.state = VIDEOBUF_NEEDS_INIT;
1264 }
1265 
1266 static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1267 		struct cx231xx_dmaqueue *dma_q)
1268 {
1269 	void *vbuf;
1270 	struct cx231xx_buffer *buf;
1271 	u32 tail_data = 0;
1272 	char *p_data;
1273 
1274 	if (dma_q->mpeg_buffer_done == 0) {
1275 		if (list_empty(&dma_q->active))
1276 			return;
1277 
1278 		buf = list_entry(dma_q->active.next,
1279 				struct cx231xx_buffer, vb.queue);
1280 		dev->video_mode.isoc_ctl.buf = buf;
1281 		dma_q->mpeg_buffer_done = 1;
1282 	}
1283 	/* Fill buffer */
1284 	buf = dev->video_mode.isoc_ctl.buf;
1285 	vbuf = videobuf_to_vmalloc(&buf->vb);
1286 
1287 	if ((dma_q->mpeg_buffer_completed+len) <
1288 			mpeglines*mpeglinesize) {
1289 		if (dma_q->add_ps_package_head ==
1290 				CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1291 			memcpy(vbuf+dma_q->mpeg_buffer_completed,
1292 					dma_q->ps_head, 3);
1293 			dma_q->mpeg_buffer_completed =
1294 				dma_q->mpeg_buffer_completed + 3;
1295 			dma_q->add_ps_package_head =
1296 				CX231XX_NONEED_PS_PACKAGE_HEAD;
1297 		}
1298 		memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1299 		dma_q->mpeg_buffer_completed =
1300 			dma_q->mpeg_buffer_completed + len;
1301 	} else {
1302 		dma_q->mpeg_buffer_done = 0;
1303 
1304 		tail_data =
1305 			mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1306 		memcpy(vbuf+dma_q->mpeg_buffer_completed,
1307 				data, tail_data);
1308 
1309 		buf->vb.state = VIDEOBUF_DONE;
1310 		buf->vb.field_count++;
1311 		buf->vb.ts = ktime_get_ns();
1312 		list_del(&buf->vb.queue);
1313 		wake_up(&buf->vb.done);
1314 		dma_q->mpeg_buffer_completed = 0;
1315 
1316 		if (len - tail_data > 0) {
1317 			p_data = data + tail_data;
1318 			dma_q->left_data_count = len - tail_data;
1319 			memcpy(dma_q->p_left_data,
1320 					p_data, len - tail_data);
1321 		}
1322 	}
1323 }
1324 
1325 static void buffer_filled(char *data, int len, struct urb *urb,
1326 		struct cx231xx_dmaqueue *dma_q)
1327 {
1328 	void *vbuf;
1329 	struct cx231xx_buffer *buf;
1330 
1331 	if (list_empty(&dma_q->active))
1332 		return;
1333 
1334 	buf = list_entry(dma_q->active.next,
1335 			struct cx231xx_buffer, vb.queue);
1336 
1337 	/* Fill buffer */
1338 	vbuf = videobuf_to_vmalloc(&buf->vb);
1339 	memcpy(vbuf, data, len);
1340 	buf->vb.state = VIDEOBUF_DONE;
1341 	buf->vb.field_count++;
1342 	buf->vb.ts = ktime_get_ns();
1343 	list_del(&buf->vb.queue);
1344 	wake_up(&buf->vb.done);
1345 }
1346 
1347 static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1348 {
1349 	struct cx231xx_dmaqueue *dma_q = urb->context;
1350 	unsigned char *p_buffer;
1351 	u32 buffer_size = 0;
1352 	u32 i = 0;
1353 
1354 	for (i = 0; i < urb->number_of_packets; i++) {
1355 		if (dma_q->left_data_count > 0) {
1356 			buffer_copy(dev, dma_q->p_left_data,
1357 				    dma_q->left_data_count, urb, dma_q);
1358 			dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1359 			dma_q->left_data_count = 0;
1360 		}
1361 
1362 		p_buffer = urb->transfer_buffer +
1363 				urb->iso_frame_desc[i].offset;
1364 		buffer_size = urb->iso_frame_desc[i].actual_length;
1365 
1366 		if (buffer_size > 0)
1367 			buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1368 	}
1369 
1370 	return 0;
1371 }
1372 
1373 static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1374 {
1375 	struct cx231xx_dmaqueue *dma_q = urb->context;
1376 	unsigned char *p_buffer, *buffer;
1377 	u32 buffer_size = 0;
1378 
1379 	p_buffer = urb->transfer_buffer;
1380 	buffer_size = urb->actual_length;
1381 
1382 	buffer = kmalloc(buffer_size, GFP_ATOMIC);
1383 	if (!buffer)
1384 		return -ENOMEM;
1385 
1386 	memcpy(buffer, dma_q->ps_head, 3);
1387 	memcpy(buffer+3, p_buffer, buffer_size-3);
1388 	memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1389 
1390 	p_buffer = buffer;
1391 	buffer_filled(p_buffer, buffer_size, urb, dma_q);
1392 
1393 	kfree(buffer);
1394 	return 0;
1395 }
1396 
1397 static int bb_buf_prepare(struct videobuf_queue *q,
1398 	struct videobuf_buffer *vb, enum v4l2_field field)
1399 {
1400 	struct cx231xx_fh *fh = q->priv_data;
1401 	struct cx231xx_buffer *buf =
1402 	    container_of(vb, struct cx231xx_buffer, vb);
1403 	struct cx231xx *dev = fh->dev;
1404 	int rc = 0, urb_init = 0;
1405 	int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1406 
1407 	if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1408 		return -EINVAL;
1409 	buf->vb.width = fh->dev->ts1.ts_packet_size;
1410 	buf->vb.height = fh->dev->ts1.ts_packet_count;
1411 	buf->vb.size = size;
1412 	buf->vb.field = field;
1413 
1414 	if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1415 		rc = videobuf_iolock(q, &buf->vb, NULL);
1416 		if (rc < 0)
1417 			goto fail;
1418 	}
1419 
1420 	if (dev->USE_ISO) {
1421 		if (!dev->video_mode.isoc_ctl.num_bufs)
1422 			urb_init = 1;
1423 	} else {
1424 		if (!dev->video_mode.bulk_ctl.num_bufs)
1425 			urb_init = 1;
1426 	}
1427 	dev_dbg(dev->dev,
1428 		"urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1429 		urb_init, dev->video_mode.max_pkt_size);
1430 	dev->mode_tv = 1;
1431 
1432 	if (urb_init) {
1433 		rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1434 		rc = cx231xx_unmute_audio(dev);
1435 		if (dev->USE_ISO) {
1436 			cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1437 			rc = cx231xx_init_isoc(dev, mpeglines,
1438 				       mpegbufs,
1439 				       dev->ts1_mode.max_pkt_size,
1440 				       cx231xx_isoc_copy);
1441 		} else {
1442 			cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1443 			rc = cx231xx_init_bulk(dev, mpeglines,
1444 				       mpegbufs,
1445 				       dev->ts1_mode.max_pkt_size,
1446 				       cx231xx_bulk_copy);
1447 		}
1448 		if (rc < 0)
1449 			goto fail;
1450 	}
1451 
1452 	buf->vb.state = VIDEOBUF_PREPARED;
1453 	return 0;
1454 
1455 fail:
1456 	free_buffer(q, buf);
1457 	return rc;
1458 }
1459 
1460 static void bb_buf_queue(struct videobuf_queue *q,
1461 	struct videobuf_buffer *vb)
1462 {
1463 	struct cx231xx_fh *fh = q->priv_data;
1464 
1465 	struct cx231xx_buffer *buf =
1466 	    container_of(vb, struct cx231xx_buffer, vb);
1467 	struct cx231xx *dev = fh->dev;
1468 	struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1469 
1470 	buf->vb.state = VIDEOBUF_QUEUED;
1471 	list_add_tail(&buf->vb.queue, &vidq->active);
1472 
1473 }
1474 
1475 static void bb_buf_release(struct videobuf_queue *q,
1476 	struct videobuf_buffer *vb)
1477 {
1478 	struct cx231xx_buffer *buf =
1479 	    container_of(vb, struct cx231xx_buffer, vb);
1480 	/*struct cx231xx_fh *fh = q->priv_data;*/
1481 	/*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1482 
1483 	free_buffer(q, buf);
1484 }
1485 
1486 static const struct videobuf_queue_ops cx231xx_qops = {
1487 	.buf_setup    = bb_buf_setup,
1488 	.buf_prepare  = bb_buf_prepare,
1489 	.buf_queue    = bb_buf_queue,
1490 	.buf_release  = bb_buf_release,
1491 };
1492 
1493 /* ------------------------------------------------------------------ */
1494 
1495 static int vidioc_g_pixelaspect(struct file *file, void *priv,
1496 				int type, struct v4l2_fract *f)
1497 {
1498 	struct cx231xx_fh *fh = priv;
1499 	struct cx231xx *dev = fh->dev;
1500 	bool is_50hz = dev->encodernorm.id & V4L2_STD_625_50;
1501 
1502 	if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1503 		return -EINVAL;
1504 
1505 	f->numerator = is_50hz ? 54 : 11;
1506 	f->denominator = is_50hz ? 59 : 10;
1507 
1508 	return 0;
1509 }
1510 
1511 static int vidioc_g_selection(struct file *file, void *priv,
1512 			      struct v4l2_selection *s)
1513 {
1514 	struct cx231xx_fh *fh = priv;
1515 	struct cx231xx *dev = fh->dev;
1516 
1517 	if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1518 		return -EINVAL;
1519 
1520 	switch (s->target) {
1521 	case V4L2_SEL_TGT_CROP_BOUNDS:
1522 	case V4L2_SEL_TGT_CROP_DEFAULT:
1523 		s->r.left = 0;
1524 		s->r.top = 0;
1525 		s->r.width = dev->ts1.width;
1526 		s->r.height = dev->ts1.height;
1527 		break;
1528 	default:
1529 		return -EINVAL;
1530 	}
1531 	return 0;
1532 }
1533 
1534 static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1535 {
1536 	struct cx231xx_fh  *fh  = file->private_data;
1537 	struct cx231xx *dev = fh->dev;
1538 
1539 	*norm = dev->encodernorm.id;
1540 	return 0;
1541 }
1542 
1543 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id)
1544 {
1545 	struct cx231xx_fh  *fh  = file->private_data;
1546 	struct cx231xx *dev = fh->dev;
1547 	unsigned int i;
1548 
1549 	for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1550 		if (id & cx231xx_tvnorms[i].id)
1551 			break;
1552 	if (i == ARRAY_SIZE(cx231xx_tvnorms))
1553 		return -EINVAL;
1554 	dev->encodernorm = cx231xx_tvnorms[i];
1555 
1556 	if (dev->encodernorm.id & 0xb000) {
1557 		dprintk(3, "encodernorm set to NTSC\n");
1558 		dev->norm = V4L2_STD_NTSC;
1559 		dev->ts1.height = 480;
1560 		cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
1561 	} else {
1562 		dprintk(3, "encodernorm set to PAL\n");
1563 		dev->norm = V4L2_STD_PAL_B;
1564 		dev->ts1.height = 576;
1565 		cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, true);
1566 	}
1567 	call_all(dev, video, s_std, dev->norm);
1568 	/* do mode control overrides */
1569 	cx231xx_do_mode_ctrl_overrides(dev);
1570 
1571 	dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1572 	return 0;
1573 }
1574 
1575 static int vidioc_s_ctrl(struct file *file, void *priv,
1576 				struct v4l2_control *ctl)
1577 {
1578 	struct cx231xx_fh  *fh  = file->private_data;
1579 	struct cx231xx *dev = fh->dev;
1580 	struct v4l2_subdev *sd;
1581 
1582 	dprintk(3, "enter vidioc_s_ctrl()\n");
1583 	/* Update the A/V core */
1584 	v4l2_device_for_each_subdev(sd, &dev->v4l2_dev)
1585 		v4l2_s_ctrl(NULL, sd->ctrl_handler, ctl);
1586 	dprintk(3, "exit vidioc_s_ctrl()\n");
1587 	return 0;
1588 }
1589 
1590 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1591 					struct v4l2_fmtdesc *f)
1592 {
1593 	if (f->index != 0)
1594 		return -EINVAL;
1595 
1596 	f->pixelformat = V4L2_PIX_FMT_MPEG;
1597 
1598 	return 0;
1599 }
1600 
1601 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1602 				struct v4l2_format *f)
1603 {
1604 	struct cx231xx_fh  *fh  = file->private_data;
1605 	struct cx231xx *dev = fh->dev;
1606 
1607 	dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1608 	f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1609 	f->fmt.pix.bytesperline = 0;
1610 	f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1611 	f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1612 	f->fmt.pix.width = dev->ts1.width;
1613 	f->fmt.pix.height = dev->ts1.height;
1614 	f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1615 	dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n",
1616 		dev->ts1.width, dev->ts1.height);
1617 	dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1618 	return 0;
1619 }
1620 
1621 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1622 				struct v4l2_format *f)
1623 {
1624 	struct cx231xx_fh  *fh  = file->private_data;
1625 	struct cx231xx *dev = fh->dev;
1626 
1627 	dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1628 	f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1629 	f->fmt.pix.bytesperline = 0;
1630 	f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1631 	f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1632 	f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1633 	dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n",
1634 		dev->ts1.width, dev->ts1.height);
1635 	dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1636 	return 0;
1637 }
1638 
1639 static int vidioc_reqbufs(struct file *file, void *priv,
1640 				struct v4l2_requestbuffers *p)
1641 {
1642 	struct cx231xx_fh  *fh  = file->private_data;
1643 
1644 	return videobuf_reqbufs(&fh->vidq, p);
1645 }
1646 
1647 static int vidioc_querybuf(struct file *file, void *priv,
1648 				struct v4l2_buffer *p)
1649 {
1650 	struct cx231xx_fh  *fh  = file->private_data;
1651 
1652 	return videobuf_querybuf(&fh->vidq, p);
1653 }
1654 
1655 static int vidioc_qbuf(struct file *file, void *priv,
1656 				struct v4l2_buffer *p)
1657 {
1658 	struct cx231xx_fh  *fh  = file->private_data;
1659 
1660 	return videobuf_qbuf(&fh->vidq, p);
1661 }
1662 
1663 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1664 {
1665 	struct cx231xx_fh  *fh  = priv;
1666 
1667 	return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1668 }
1669 
1670 
1671 static int vidioc_streamon(struct file *file, void *priv,
1672 				enum v4l2_buf_type i)
1673 {
1674 	struct cx231xx_fh  *fh  = file->private_data;
1675 	struct cx231xx *dev = fh->dev;
1676 
1677 	dprintk(3, "enter vidioc_streamon()\n");
1678 	cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1679 	cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1680 	if (dev->USE_ISO)
1681 		cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1682 				CX231XX_NUM_BUFS,
1683 				dev->video_mode.max_pkt_size,
1684 				cx231xx_isoc_copy);
1685 	else {
1686 		cx231xx_init_bulk(dev, 320,
1687 				5,
1688 				dev->ts1_mode.max_pkt_size,
1689 				cx231xx_bulk_copy);
1690 	}
1691 	dprintk(3, "exit vidioc_streamon()\n");
1692 	return videobuf_streamon(&fh->vidq);
1693 }
1694 
1695 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1696 {
1697 	struct cx231xx_fh  *fh  = file->private_data;
1698 
1699 	return videobuf_streamoff(&fh->vidq);
1700 }
1701 
1702 static int vidioc_log_status(struct file *file, void *priv)
1703 {
1704 	struct cx231xx_fh  *fh  = priv;
1705 	struct cx231xx *dev = fh->dev;
1706 
1707 	call_all(dev, core, log_status);
1708 	return v4l2_ctrl_log_status(file, priv);
1709 }
1710 
1711 static int mpeg_open(struct file *file)
1712 {
1713 	struct video_device *vdev = video_devdata(file);
1714 	struct cx231xx *dev = video_drvdata(file);
1715 	struct cx231xx_fh *fh;
1716 
1717 	dprintk(2, "%s()\n", __func__);
1718 
1719 	if (mutex_lock_interruptible(&dev->lock))
1720 		return -ERESTARTSYS;
1721 
1722 	/* allocate + initialize per filehandle data */
1723 	fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1724 	if (NULL == fh) {
1725 		mutex_unlock(&dev->lock);
1726 		return -ENOMEM;
1727 	}
1728 
1729 	file->private_data = fh;
1730 	v4l2_fh_init(&fh->fh, vdev);
1731 	fh->dev = dev;
1732 
1733 
1734 	videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1735 			    NULL, &dev->video_mode.slock,
1736 			    V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1737 			    sizeof(struct cx231xx_buffer), fh, &dev->lock);
1738 /*
1739 	videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1740 			    dev->dev, &dev->ts1.slock,
1741 			    V4L2_BUF_TYPE_VIDEO_CAPTURE,
1742 			    V4L2_FIELD_INTERLACED,
1743 			    sizeof(struct cx231xx_buffer),
1744 			    fh, &dev->lock);
1745 */
1746 
1747 	cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1748 	cx231xx_set_gpio_value(dev, 2, 0);
1749 
1750 	cx231xx_initialize_codec(dev);
1751 
1752 	mutex_unlock(&dev->lock);
1753 	v4l2_fh_add(&fh->fh);
1754 	cx231xx_start_TS1(dev);
1755 
1756 	return 0;
1757 }
1758 
1759 static int mpeg_release(struct file *file)
1760 {
1761 	struct cx231xx_fh  *fh  = file->private_data;
1762 	struct cx231xx *dev = fh->dev;
1763 
1764 	dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
1765 
1766 	mutex_lock(&dev->lock);
1767 
1768 	cx231xx_stop_TS1(dev);
1769 
1770 	/* do this before setting alternate! */
1771 	if (dev->USE_ISO)
1772 		cx231xx_uninit_isoc(dev);
1773 	else
1774 		cx231xx_uninit_bulk(dev);
1775 	cx231xx_set_mode(dev, CX231XX_SUSPEND);
1776 
1777 	cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1778 			CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
1779 			CX231xx_RAW_BITS_NONE);
1780 
1781 	/* FIXME: Review this crap */
1782 	/* Shut device down on last close */
1783 	if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1784 		if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1785 			/* stop mpeg capture */
1786 
1787 			msleep(500);
1788 			cx231xx_417_check_encoder(dev);
1789 
1790 		}
1791 	}
1792 
1793 	if (fh->vidq.streaming)
1794 		videobuf_streamoff(&fh->vidq);
1795 	if (fh->vidq.reading)
1796 		videobuf_read_stop(&fh->vidq);
1797 
1798 	videobuf_mmap_free(&fh->vidq);
1799 	v4l2_fh_del(&fh->fh);
1800 	v4l2_fh_exit(&fh->fh);
1801 	kfree(fh);
1802 	mutex_unlock(&dev->lock);
1803 	return 0;
1804 }
1805 
1806 static ssize_t mpeg_read(struct file *file, char __user *data,
1807 	size_t count, loff_t *ppos)
1808 {
1809 	struct cx231xx_fh *fh = file->private_data;
1810 	struct cx231xx *dev = fh->dev;
1811 
1812 	/* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1813 	/* Start mpeg encoder on first read. */
1814 	if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1815 		if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1816 			if (cx231xx_initialize_codec(dev) < 0)
1817 				return -EINVAL;
1818 		}
1819 	}
1820 
1821 	return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
1822 				    file->f_flags & O_NONBLOCK);
1823 }
1824 
1825 static __poll_t mpeg_poll(struct file *file,
1826 	struct poll_table_struct *wait)
1827 {
1828 	__poll_t req_events = poll_requested_events(wait);
1829 	struct cx231xx_fh *fh = file->private_data;
1830 	struct cx231xx *dev = fh->dev;
1831 	__poll_t res = 0;
1832 
1833 	if (v4l2_event_pending(&fh->fh))
1834 		res |= EPOLLPRI;
1835 	else
1836 		poll_wait(file, &fh->fh.wait, wait);
1837 
1838 	if (!(req_events & (EPOLLIN | EPOLLRDNORM)))
1839 		return res;
1840 
1841 	mutex_lock(&dev->lock);
1842 	res |= videobuf_poll_stream(file, &fh->vidq, wait);
1843 	mutex_unlock(&dev->lock);
1844 	return res;
1845 }
1846 
1847 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1848 {
1849 	struct cx231xx_fh *fh = file->private_data;
1850 
1851 	dprintk(2, "%s()\n", __func__);
1852 
1853 	return videobuf_mmap_mapper(&fh->vidq, vma);
1854 }
1855 
1856 static const struct v4l2_file_operations mpeg_fops = {
1857 	.owner	       = THIS_MODULE,
1858 	.open	       = mpeg_open,
1859 	.release       = mpeg_release,
1860 	.read	       = mpeg_read,
1861 	.poll          = mpeg_poll,
1862 	.mmap	       = mpeg_mmap,
1863 	.unlocked_ioctl = video_ioctl2,
1864 };
1865 
1866 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1867 	.vidioc_s_std		 = vidioc_s_std,
1868 	.vidioc_g_std		 = vidioc_g_std,
1869 	.vidioc_g_tuner          = cx231xx_g_tuner,
1870 	.vidioc_s_tuner          = cx231xx_s_tuner,
1871 	.vidioc_g_frequency      = cx231xx_g_frequency,
1872 	.vidioc_s_frequency      = cx231xx_s_frequency,
1873 	.vidioc_enum_input	 = cx231xx_enum_input,
1874 	.vidioc_g_input		 = cx231xx_g_input,
1875 	.vidioc_s_input		 = cx231xx_s_input,
1876 	.vidioc_s_ctrl		 = vidioc_s_ctrl,
1877 	.vidioc_g_pixelaspect	 = vidioc_g_pixelaspect,
1878 	.vidioc_g_selection	 = vidioc_g_selection,
1879 	.vidioc_querycap	 = cx231xx_querycap,
1880 	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1881 	.vidioc_g_fmt_vid_cap	 = vidioc_g_fmt_vid_cap,
1882 	.vidioc_try_fmt_vid_cap	 = vidioc_try_fmt_vid_cap,
1883 	.vidioc_s_fmt_vid_cap	 = vidioc_try_fmt_vid_cap,
1884 	.vidioc_reqbufs		 = vidioc_reqbufs,
1885 	.vidioc_querybuf	 = vidioc_querybuf,
1886 	.vidioc_qbuf		 = vidioc_qbuf,
1887 	.vidioc_dqbuf		 = vidioc_dqbuf,
1888 	.vidioc_streamon	 = vidioc_streamon,
1889 	.vidioc_streamoff	 = vidioc_streamoff,
1890 	.vidioc_log_status	 = vidioc_log_status,
1891 #ifdef CONFIG_VIDEO_ADV_DEBUG
1892 	.vidioc_g_register	 = cx231xx_g_register,
1893 	.vidioc_s_register	 = cx231xx_s_register,
1894 #endif
1895 	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1896 	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1897 };
1898 
1899 static struct video_device cx231xx_mpeg_template = {
1900 	.name          = "cx231xx",
1901 	.fops          = &mpeg_fops,
1902 	.ioctl_ops     = &mpeg_ioctl_ops,
1903 	.minor         = -1,
1904 	.tvnorms       = V4L2_STD_ALL,
1905 };
1906 
1907 void cx231xx_417_unregister(struct cx231xx *dev)
1908 {
1909 	dprintk(1, "%s()\n", __func__);
1910 	dprintk(3, "%s()\n", __func__);
1911 
1912 	if (video_is_registered(&dev->v4l_device)) {
1913 		video_unregister_device(&dev->v4l_device);
1914 		v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1915 	}
1916 }
1917 
1918 static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val)
1919 {
1920 	struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1921 	int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1;
1922 	struct v4l2_subdev_format format = {
1923 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
1924 	};
1925 
1926 	/* fix videodecoder resolution */
1927 	format.format.width = cxhdl->width / (is_mpeg1 ? 2 : 1);
1928 	format.format.height = cxhdl->height;
1929 	format.format.code = MEDIA_BUS_FMT_FIXED;
1930 	v4l2_subdev_call(dev->sd_cx25840, pad, set_fmt, NULL, &format);
1931 	return 0;
1932 }
1933 
1934 static int cx231xx_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx)
1935 {
1936 	static const u32 freqs[3] = { 44100, 48000, 32000 };
1937 	struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1938 
1939 	/* The audio clock of the digitizer must match the codec sample
1940 	   rate otherwise you get some very strange effects. */
1941 	if (idx < ARRAY_SIZE(freqs))
1942 		call_all(dev, audio, s_clock_freq, freqs[idx]);
1943 	return 0;
1944 }
1945 
1946 static const struct cx2341x_handler_ops cx231xx_ops = {
1947 	/* needed for the video clock freq */
1948 	.s_audio_sampling_freq = cx231xx_s_audio_sampling_freq,
1949 	/* needed for setting up the video resolution */
1950 	.s_video_encoding = cx231xx_s_video_encoding,
1951 };
1952 
1953 static void cx231xx_video_dev_init(
1954 	struct cx231xx *dev,
1955 	struct usb_device *usbdev,
1956 	struct video_device *vfd,
1957 	const struct video_device *template,
1958 	const char *type)
1959 {
1960 	dprintk(1, "%s()\n", __func__);
1961 	*vfd = *template;
1962 	snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1963 		type, cx231xx_boards[dev->model].name);
1964 
1965 	vfd->v4l2_dev = &dev->v4l2_dev;
1966 	vfd->lock = &dev->lock;
1967 	vfd->release = video_device_release_empty;
1968 	vfd->ctrl_handler = &dev->mpeg_ctrl_handler.hdl;
1969 	video_set_drvdata(vfd, dev);
1970 	if (dev->tuner_type == TUNER_ABSENT) {
1971 		v4l2_disable_ioctl(vfd, VIDIOC_G_FREQUENCY);
1972 		v4l2_disable_ioctl(vfd, VIDIOC_S_FREQUENCY);
1973 		v4l2_disable_ioctl(vfd, VIDIOC_G_TUNER);
1974 		v4l2_disable_ioctl(vfd, VIDIOC_S_TUNER);
1975 	}
1976 }
1977 
1978 int cx231xx_417_register(struct cx231xx *dev)
1979 {
1980 	/* FIXME: Port1 hardcoded here */
1981 	int err = -ENODEV;
1982 	struct cx231xx_tsport *tsport = &dev->ts1;
1983 
1984 	dprintk(1, "%s()\n", __func__);
1985 
1986 	/* Set default TV standard */
1987 	dev->encodernorm = cx231xx_tvnorms[0];
1988 
1989 	if (dev->encodernorm.id & V4L2_STD_525_60)
1990 		tsport->height = 480;
1991 	else
1992 		tsport->height = 576;
1993 
1994 	tsport->width = 720;
1995 	err = cx2341x_handler_init(&dev->mpeg_ctrl_handler, 50);
1996 	if (err) {
1997 		dprintk(3, "%s: can't init cx2341x controls\n", dev->name);
1998 		return err;
1999 	}
2000 	dev->mpeg_ctrl_handler.func = cx231xx_mbox_func;
2001 	dev->mpeg_ctrl_handler.priv = dev;
2002 	dev->mpeg_ctrl_handler.ops = &cx231xx_ops;
2003 	if (dev->sd_cx25840)
2004 		v4l2_ctrl_add_handler(&dev->mpeg_ctrl_handler.hdl,
2005 				dev->sd_cx25840->ctrl_handler, NULL, false);
2006 	if (dev->mpeg_ctrl_handler.hdl.error) {
2007 		err = dev->mpeg_ctrl_handler.hdl.error;
2008 		dprintk(3, "%s: can't add cx25840 controls\n", dev->name);
2009 		v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
2010 		return err;
2011 	}
2012 	dev->norm = V4L2_STD_NTSC;
2013 
2014 	dev->mpeg_ctrl_handler.port = CX2341X_PORT_SERIAL;
2015 	cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
2016 
2017 	/* Allocate and initialize V4L video device */
2018 	cx231xx_video_dev_init(dev, dev->udev,
2019 			&dev->v4l_device, &cx231xx_mpeg_template, "mpeg");
2020 	err = video_register_device(&dev->v4l_device,
2021 		VFL_TYPE_GRABBER, -1);
2022 	if (err < 0) {
2023 		dprintk(3, "%s: can't register mpeg device\n", dev->name);
2024 		v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
2025 		return err;
2026 	}
2027 
2028 	dprintk(3, "%s: registered device video%d [mpeg]\n",
2029 	       dev->name, dev->v4l_device.num);
2030 
2031 	return 0;
2032 }
2033 
2034 MODULE_FIRMWARE(CX231xx_FIRM_IMAGE_NAME);
2035