1 /*
2  *
3  *  Support for a cx23417 mpeg encoder via cx231xx host port.
4  *
5  *    (c) 2004 Jelle Foks <jelle@foks.us>
6  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
8  *      - CX23885/7/8 support
9  *
10  *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11  *
12  *  This program is free software; you can redistribute it and/or modify
13  *  it under the terms of the GNU General Public License as published by
14  *  the Free Software Foundation; either version 2 of the License, or
15  *  (at your option) any later version.
16  *
17  *  This program is distributed in the hope that it will be useful,
18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *  GNU General Public License for more details.
21  *
22  *  You should have received a copy of the GNU General Public License
23  *  along with this program; if not, write to the Free Software
24  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25  */
26 
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/fs.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <linux/firmware.h>
34 #include <linux/vmalloc.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/v4l2-event.h>
38 #include <media/cx2341x.h>
39 #include <media/tuner.h>
40 #include <linux/usb.h>
41 
42 #include "cx231xx.h"
43 
44 #define CX231xx_FIRM_IMAGE_SIZE 376836
45 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
46 
47 /* for polaris ITVC */
48 #define ITVC_WRITE_DIR          0x03FDFC00
49 #define ITVC_READ_DIR            0x0001FC00
50 
51 #define  MCI_MEMORY_DATA_BYTE0          0x00
52 #define  MCI_MEMORY_DATA_BYTE1          0x08
53 #define  MCI_MEMORY_DATA_BYTE2          0x10
54 #define  MCI_MEMORY_DATA_BYTE3          0x18
55 
56 #define  MCI_MEMORY_ADDRESS_BYTE2       0x20
57 #define  MCI_MEMORY_ADDRESS_BYTE1       0x28
58 #define  MCI_MEMORY_ADDRESS_BYTE0       0x30
59 
60 #define  MCI_REGISTER_DATA_BYTE0        0x40
61 #define  MCI_REGISTER_DATA_BYTE1        0x48
62 #define  MCI_REGISTER_DATA_BYTE2        0x50
63 #define  MCI_REGISTER_DATA_BYTE3        0x58
64 
65 #define  MCI_REGISTER_ADDRESS_BYTE0     0x60
66 #define  MCI_REGISTER_ADDRESS_BYTE1     0x68
67 
68 #define  MCI_REGISTER_MODE              0x70
69 
70 /* Read and write modes for polaris ITVC */
71 #define  MCI_MODE_REGISTER_READ         0x000
72 #define  MCI_MODE_REGISTER_WRITE        0x100
73 #define  MCI_MODE_MEMORY_READ           0x000
74 #define  MCI_MODE_MEMORY_WRITE          0x4000
75 
76 static unsigned int mpegbufs = 8;
77 module_param(mpegbufs, int, 0644);
78 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
79 
80 static unsigned int mpeglines = 128;
81 module_param(mpeglines, int, 0644);
82 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
83 
84 static unsigned int mpeglinesize = 512;
85 module_param(mpeglinesize, int, 0644);
86 MODULE_PARM_DESC(mpeglinesize,
87 	"number of bytes in each line of an MPEG buffer, range 512-1024");
88 
89 static unsigned int v4l_debug = 1;
90 module_param(v4l_debug, int, 0644);
91 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
92 
93 #define dprintk(level, fmt, arg...)\
94 	do { if (v4l_debug >= level) \
95 		pr_info("%s: " fmt, \
96 		(dev) ? dev->name : "cx231xx[?]", ## arg); \
97 	} while (0)
98 
99 static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
100 	{
101 		.name      = "NTSC-M",
102 		.id        = V4L2_STD_NTSC_M,
103 	}, {
104 		.name      = "NTSC-JP",
105 		.id        = V4L2_STD_NTSC_M_JP,
106 	}, {
107 		.name      = "PAL-BG",
108 		.id        = V4L2_STD_PAL_BG,
109 	}, {
110 		.name      = "PAL-DK",
111 		.id        = V4L2_STD_PAL_DK,
112 	}, {
113 		.name      = "PAL-I",
114 		.id        = V4L2_STD_PAL_I,
115 	}, {
116 		.name      = "PAL-M",
117 		.id        = V4L2_STD_PAL_M,
118 	}, {
119 		.name      = "PAL-N",
120 		.id        = V4L2_STD_PAL_N,
121 	}, {
122 		.name      = "PAL-Nc",
123 		.id        = V4L2_STD_PAL_Nc,
124 	}, {
125 		.name      = "PAL-60",
126 		.id        = V4L2_STD_PAL_60,
127 	}, {
128 		.name      = "SECAM-L",
129 		.id        = V4L2_STD_SECAM_L,
130 	}, {
131 		.name      = "SECAM-DK",
132 		.id        = V4L2_STD_SECAM_DK,
133 	}
134 };
135 
136 /* ------------------------------------------------------------------ */
137 
138 enum cx231xx_capture_type {
139 	CX231xx_MPEG_CAPTURE,
140 	CX231xx_RAW_CAPTURE,
141 	CX231xx_RAW_PASSTHRU_CAPTURE
142 };
143 
144 enum cx231xx_capture_bits {
145 	CX231xx_RAW_BITS_NONE             = 0x00,
146 	CX231xx_RAW_BITS_YUV_CAPTURE      = 0x01,
147 	CX231xx_RAW_BITS_PCM_CAPTURE      = 0x02,
148 	CX231xx_RAW_BITS_VBI_CAPTURE      = 0x04,
149 	CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
150 	CX231xx_RAW_BITS_TO_HOST_CAPTURE  = 0x10
151 };
152 
153 enum cx231xx_capture_end {
154 	CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
155 	CX231xx_END_NOW, /* stop immediately, no irq */
156 };
157 
158 enum cx231xx_framerate {
159 	CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
160 	CX231xx_FRAMERATE_PAL_25   /* PAL: 25fps */
161 };
162 
163 enum cx231xx_stream_port {
164 	CX231xx_OUTPUT_PORT_MEMORY,
165 	CX231xx_OUTPUT_PORT_STREAMING,
166 	CX231xx_OUTPUT_PORT_SERIAL
167 };
168 
169 enum cx231xx_data_xfer_status {
170 	CX231xx_MORE_BUFFERS_FOLLOW,
171 	CX231xx_LAST_BUFFER,
172 };
173 
174 enum cx231xx_picture_mask {
175 	CX231xx_PICTURE_MASK_NONE,
176 	CX231xx_PICTURE_MASK_I_FRAMES,
177 	CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
178 	CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
179 };
180 
181 enum cx231xx_vbi_mode_bits {
182 	CX231xx_VBI_BITS_SLICED,
183 	CX231xx_VBI_BITS_RAW,
184 };
185 
186 enum cx231xx_vbi_insertion_bits {
187 	CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
188 	CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
189 	CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
190 	CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
191 	CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
192 };
193 
194 enum cx231xx_dma_unit {
195 	CX231xx_DMA_BYTES,
196 	CX231xx_DMA_FRAMES,
197 };
198 
199 enum cx231xx_dma_transfer_status_bits {
200 	CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
201 	CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
202 	CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
203 };
204 
205 enum cx231xx_pause {
206 	CX231xx_PAUSE_ENCODING,
207 	CX231xx_RESUME_ENCODING,
208 };
209 
210 enum cx231xx_copyright {
211 	CX231xx_COPYRIGHT_OFF,
212 	CX231xx_COPYRIGHT_ON,
213 };
214 
215 enum cx231xx_notification_type {
216 	CX231xx_NOTIFICATION_REFRESH,
217 };
218 
219 enum cx231xx_notification_status {
220 	CX231xx_NOTIFICATION_OFF,
221 	CX231xx_NOTIFICATION_ON,
222 };
223 
224 enum cx231xx_notification_mailbox {
225 	CX231xx_NOTIFICATION_NO_MAILBOX = -1,
226 };
227 
228 enum cx231xx_field1_lines {
229 	CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
230 	CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
231 	CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
232 };
233 
234 enum cx231xx_field2_lines {
235 	CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
236 	CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
237 	CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
238 };
239 
240 enum cx231xx_custom_data_type {
241 	CX231xx_CUSTOM_EXTENSION_USR_DATA,
242 	CX231xx_CUSTOM_PRIVATE_PACKET,
243 };
244 
245 enum cx231xx_mute {
246 	CX231xx_UNMUTE,
247 	CX231xx_MUTE,
248 };
249 
250 enum cx231xx_mute_video_mask {
251 	CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
252 	CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
253 	CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
254 };
255 
256 enum cx231xx_mute_video_shift {
257 	CX231xx_MUTE_VIDEO_V_SHIFT = 8,
258 	CX231xx_MUTE_VIDEO_U_SHIFT = 16,
259 	CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
260 };
261 
262 /* defines below are from ivtv-driver.h */
263 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
264 
265 /* Firmware API commands */
266 #define IVTV_API_STD_TIMEOUT 500
267 
268 /* Registers */
269 /* IVTV_REG_OFFSET */
270 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
271 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
272 #define IVTV_REG_SPU (0x9050)
273 #define IVTV_REG_HW_BLOCKS (0x9054)
274 #define IVTV_REG_VPU (0x9058)
275 #define IVTV_REG_APU (0xA064)
276 
277 /*
278  * Bit definitions for MC417_RWD and MC417_OEN registers
279  *
280  * bits 31-16
281  *+-----------+
282  *| Reserved  |
283  *|+-----------+
284  *|  bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
285  *|+-------+-------+-------+-------+-------+-------+-------+-------+
286  *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
287  *|+-------+-------+-------+-------+-------+-------+-------+-------+
288  *| bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
289  *|+-------+-------+-------+-------+-------+-------+-------+-------+
290  *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
291  *|+-------+-------+-------+-------+-------+-------+-------+-------+
292  */
293 #define MC417_MIWR	0x8000
294 #define MC417_MIRD	0x4000
295 #define MC417_MICS	0x2000
296 #define MC417_MIRDY	0x1000
297 #define MC417_MIADDR	0x0F00
298 #define MC417_MIDATA	0x00FF
299 
300 
301 /* Bit definitions for MC417_CTL register ****
302  *bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
303  *+--------+-------------+--------+--------------+------------+
304  *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
305  *+--------+-------------+--------+--------------+------------+
306  */
307 #define MC417_SPD_CTL(x)	(((x) << 4) & 0x00000030)
308 #define MC417_GPIO_SEL(x)	(((x) << 1) & 0x00000006)
309 #define MC417_UART_GPIO_EN	0x00000001
310 
311 /* Values for speed control */
312 #define MC417_SPD_CTL_SLOW	0x1
313 #define MC417_SPD_CTL_MEDIUM	0x0
314 #define MC417_SPD_CTL_FAST	0x3     /* b'1x, but we use b'11 */
315 
316 /* Values for GPIO select */
317 #define MC417_GPIO_SEL_GPIO3	0x3
318 #define MC417_GPIO_SEL_GPIO2	0x2
319 #define MC417_GPIO_SEL_GPIO1	0x1
320 #define MC417_GPIO_SEL_GPIO0	0x0
321 
322 
323 #define CX23417_GPIO_MASK 0xFC0003FF
324 
325 static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value)
326 {
327 	int status = 0;
328 	u32 _gpio_direction = 0;
329 
330 	_gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
331 	_gpio_direction = _gpio_direction | gpio_direction;
332 	status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
333 			 (u8 *)&value, 4, 0, 0);
334 	return status;
335 }
336 
337 static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr)
338 {
339 	int status = 0;
340 	u32 _gpio_direction = 0;
341 
342 	_gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
343 	_gpio_direction = _gpio_direction | gpio_direction;
344 
345 	status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
346 		 (u8 *)val_ptr, 4, 0, 1);
347 	return status;
348 }
349 
350 static int wait_for_mci_complete(struct cx231xx *dev)
351 {
352 	u32 gpio;
353 	u32 gpio_direction = 0;
354 	u8 count = 0;
355 	get_itvc_reg(dev, gpio_direction, &gpio);
356 
357 	while (!(gpio&0x020000)) {
358 		msleep(10);
359 
360 		get_itvc_reg(dev, gpio_direction, &gpio);
361 
362 		if (count++ > 100) {
363 			dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
364 			return -1;
365 		}
366 	}
367 	return 0;
368 }
369 
370 static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
371 {
372 	u32 temp;
373 	int status = 0;
374 
375 	temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8);
376 	temp = temp << 10;
377 	status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
378 	if (status < 0)
379 		return status;
380 	temp = temp | (0x05 << 10);
381 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
382 
383 	/*write data byte 1;*/
384 	temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00);
385 	temp = temp << 10;
386 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
387 	temp = temp | (0x05 << 10);
388 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
389 
390 	/*write data byte 2;*/
391 	temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
392 	temp = temp << 10;
393 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
394 	temp = temp | (0x05 << 10);
395 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
396 
397 	/*write data byte 3;*/
398 	temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
399 	temp = temp << 10;
400 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
401 	temp = temp | (0x05 << 10);
402 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
403 
404 	/*write address byte 0;*/
405 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8);
406 	temp = temp << 10;
407 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
408 	temp = temp | (0x05 << 10);
409 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
410 
411 	/*write address byte 1;*/
412 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00);
413 	temp = temp << 10;
414 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
415 	temp = temp | (0x05 << 10);
416 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
417 
418 	/*Write that the mode is write.*/
419 	temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
420 	temp = temp << 10;
421 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
422 	temp = temp | (0x05 << 10);
423 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
424 
425 	return wait_for_mci_complete(dev);
426 }
427 
428 static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
429 {
430 	/*write address byte 0;*/
431 	u32 temp;
432 	u32 return_value = 0;
433 	int ret = 0;
434 
435 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
436 	temp = temp << 10;
437 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
438 	temp = temp | ((0x05) << 10);
439 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
440 
441 	/*write address byte 1;*/
442 	temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
443 	temp = temp << 10;
444 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
445 	temp = temp | ((0x05) << 10);
446 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
447 
448 	/*write that the mode is read;*/
449 	temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
450 	temp = temp << 10;
451 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
452 	temp = temp | ((0x05) << 10);
453 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
454 
455 	/*wait for the MIRDY line to be asserted ,
456 	signalling that the read is done;*/
457 	ret = wait_for_mci_complete(dev);
458 
459 	/*switch the DATA- GPIO to input mode;*/
460 
461 	/*Read data byte 0;*/
462 	temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
463 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
464 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
465 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
466 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
467 	return_value |= ((temp & 0x03FC0000) >> 18);
468 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
469 
470 	/* Read data byte 1;*/
471 	temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
472 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
473 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
474 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
475 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
476 
477 	return_value |= ((temp & 0x03FC0000) >> 10);
478 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
479 
480 	/*Read data byte 2;*/
481 	temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
482 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
483 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
484 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
485 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
486 	return_value |= ((temp & 0x03FC0000) >> 2);
487 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
488 
489 	/*Read data byte 3;*/
490 	temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
491 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
492 	temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
493 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
494 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
495 	return_value |= ((temp & 0x03FC0000) << 6);
496 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
497 
498 	*value  = return_value;
499 	return ret;
500 }
501 
502 static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
503 {
504 	/*write data byte 0;*/
505 
506 	u32 temp;
507 	int ret = 0;
508 
509 	temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
510 	temp = temp << 10;
511 	ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
512 	if (ret < 0)
513 		return ret;
514 	temp = temp | (0x05 << 10);
515 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
516 
517 	/*write data byte 1;*/
518 	temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
519 	temp = temp << 10;
520 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
521 	temp = temp | (0x05 << 10);
522 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
523 
524 	/*write data byte 2;*/
525 	temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
526 	temp = temp << 10;
527 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
528 	temp = temp | (0x05 << 10);
529 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
530 
531 	/*write data byte 3;*/
532 	temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
533 	temp = temp << 10;
534 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
535 	temp = temp | (0x05 << 10);
536 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
537 
538 	/* write address byte 2;*/
539 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
540 		((address & 0x003F0000) >> 8);
541 	temp = temp << 10;
542 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
543 	temp = temp | (0x05 << 10);
544 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
545 
546 	/* write address byte 1;*/
547 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
548 	temp = temp << 10;
549 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
550 	temp = temp | (0x05 << 10);
551 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
552 
553 	/* write address byte 0;*/
554 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
555 	temp = temp << 10;
556 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
557 	temp = temp | (0x05 << 10);
558 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
559 
560 	/*wait for MIRDY line;*/
561 	wait_for_mci_complete(dev);
562 
563 	return 0;
564 }
565 
566 static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
567 {
568 	u32 temp = 0;
569 	u32 return_value = 0;
570 	int ret = 0;
571 
572 	/*write address byte 2;*/
573 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
574 		((address & 0x003F0000) >> 8);
575 	temp = temp << 10;
576 	ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
577 	if (ret < 0)
578 		return ret;
579 	temp = temp | (0x05 << 10);
580 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
581 
582 	/*write address byte 1*/
583 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
584 	temp = temp << 10;
585 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
586 	temp = temp | (0x05 << 10);
587 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
588 
589 	/*write address byte 0*/
590 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
591 	temp = temp << 10;
592 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
593 	temp = temp | (0x05 << 10);
594 	set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
595 
596 	/*Wait for MIRDY line*/
597 	ret = wait_for_mci_complete(dev);
598 
599 
600 	/*Read data byte 3;*/
601 	temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10;
602 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
603 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10);
604 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
605 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
606 	return_value |= ((temp & 0x03FC0000) << 6);
607 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
608 
609 	/*Read data byte 2;*/
610 	temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10;
611 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
612 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10);
613 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
614 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
615 	return_value |= ((temp & 0x03FC0000) >> 2);
616 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
617 
618 	/* Read data byte 1;*/
619 	temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10;
620 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
621 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10);
622 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
623 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
624 	return_value |= ((temp & 0x03FC0000) >> 10);
625 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
626 
627 	/*Read data byte 0;*/
628 	temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10;
629 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
630 	temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10);
631 	set_itvc_reg(dev, ITVC_READ_DIR, temp);
632 	get_itvc_reg(dev, ITVC_READ_DIR, &temp);
633 	return_value |= ((temp & 0x03FC0000) >> 18);
634 	set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
635 
636 	*value  = return_value;
637 	return ret;
638 }
639 
640 /* ------------------------------------------------------------------ */
641 
642 /* MPEG encoder API */
643 static char *cmd_to_str(int cmd)
644 {
645 	switch (cmd) {
646 	case CX2341X_ENC_PING_FW:
647 		return "PING_FW";
648 	case CX2341X_ENC_START_CAPTURE:
649 		return "START_CAPTURE";
650 	case CX2341X_ENC_STOP_CAPTURE:
651 		return "STOP_CAPTURE";
652 	case CX2341X_ENC_SET_AUDIO_ID:
653 		return "SET_AUDIO_ID";
654 	case CX2341X_ENC_SET_VIDEO_ID:
655 		return "SET_VIDEO_ID";
656 	case CX2341X_ENC_SET_PCR_ID:
657 		return "SET_PCR_PID";
658 	case CX2341X_ENC_SET_FRAME_RATE:
659 		return "SET_FRAME_RATE";
660 	case CX2341X_ENC_SET_FRAME_SIZE:
661 		return "SET_FRAME_SIZE";
662 	case CX2341X_ENC_SET_BIT_RATE:
663 		return "SET_BIT_RATE";
664 	case CX2341X_ENC_SET_GOP_PROPERTIES:
665 		return "SET_GOP_PROPERTIES";
666 	case CX2341X_ENC_SET_ASPECT_RATIO:
667 		return "SET_ASPECT_RATIO";
668 	case CX2341X_ENC_SET_DNR_FILTER_MODE:
669 		return "SET_DNR_FILTER_PROPS";
670 	case CX2341X_ENC_SET_DNR_FILTER_PROPS:
671 		return "SET_DNR_FILTER_PROPS";
672 	case CX2341X_ENC_SET_CORING_LEVELS:
673 		return "SET_CORING_LEVELS";
674 	case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
675 		return "SET_SPATIAL_FILTER_TYPE";
676 	case CX2341X_ENC_SET_VBI_LINE:
677 		return "SET_VBI_LINE";
678 	case CX2341X_ENC_SET_STREAM_TYPE:
679 		return "SET_STREAM_TYPE";
680 	case CX2341X_ENC_SET_OUTPUT_PORT:
681 		return "SET_OUTPUT_PORT";
682 	case CX2341X_ENC_SET_AUDIO_PROPERTIES:
683 		return "SET_AUDIO_PROPERTIES";
684 	case CX2341X_ENC_HALT_FW:
685 		return "HALT_FW";
686 	case CX2341X_ENC_GET_VERSION:
687 		return "GET_VERSION";
688 	case CX2341X_ENC_SET_GOP_CLOSURE:
689 		return "SET_GOP_CLOSURE";
690 	case CX2341X_ENC_GET_SEQ_END:
691 		return "GET_SEQ_END";
692 	case CX2341X_ENC_SET_PGM_INDEX_INFO:
693 		return "SET_PGM_INDEX_INFO";
694 	case CX2341X_ENC_SET_VBI_CONFIG:
695 		return "SET_VBI_CONFIG";
696 	case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
697 		return "SET_DMA_BLOCK_SIZE";
698 	case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
699 		return "GET_PREV_DMA_INFO_MB_10";
700 	case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
701 		return "GET_PREV_DMA_INFO_MB_9";
702 	case CX2341X_ENC_SCHED_DMA_TO_HOST:
703 		return "SCHED_DMA_TO_HOST";
704 	case CX2341X_ENC_INITIALIZE_INPUT:
705 		return "INITIALIZE_INPUT";
706 	case CX2341X_ENC_SET_FRAME_DROP_RATE:
707 		return "SET_FRAME_DROP_RATE";
708 	case CX2341X_ENC_PAUSE_ENCODER:
709 		return "PAUSE_ENCODER";
710 	case CX2341X_ENC_REFRESH_INPUT:
711 		return "REFRESH_INPUT";
712 	case CX2341X_ENC_SET_COPYRIGHT:
713 		return "SET_COPYRIGHT";
714 	case CX2341X_ENC_SET_EVENT_NOTIFICATION:
715 		return "SET_EVENT_NOTIFICATION";
716 	case CX2341X_ENC_SET_NUM_VSYNC_LINES:
717 		return "SET_NUM_VSYNC_LINES";
718 	case CX2341X_ENC_SET_PLACEHOLDER:
719 		return "SET_PLACEHOLDER";
720 	case CX2341X_ENC_MUTE_VIDEO:
721 		return "MUTE_VIDEO";
722 	case CX2341X_ENC_MUTE_AUDIO:
723 		return "MUTE_AUDIO";
724 	case CX2341X_ENC_MISC:
725 		return "MISC";
726 	default:
727 		return "UNKNOWN";
728 	}
729 }
730 
731 static int cx231xx_mbox_func(void *priv, u32 command, int in, int out,
732 			     u32 data[CX2341X_MBOX_MAX_DATA])
733 {
734 	struct cx231xx *dev = priv;
735 	unsigned long timeout;
736 	u32 value, flag, retval = 0;
737 	int i;
738 
739 	dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
740 		cmd_to_str(command));
741 
742 	/* this may not be 100% safe if we can't read any memory location
743 	   without side effects */
744 	mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
745 	if (value != 0x12345678) {
746 		dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n",
747 			value, cmd_to_str(command));
748 		return -EIO;
749 	}
750 
751 	/* This read looks at 32 bits, but flag is only 8 bits.
752 	 * Seems we also bail if CMD or TIMEOUT bytes are set???
753 	 */
754 	mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
755 	if (flag) {
756 		dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n",
757 				flag, cmd_to_str(command));
758 		return -EBUSY;
759 	}
760 
761 	flag |= 1; /* tell 'em we're working on it */
762 	mc417_memory_write(dev, dev->cx23417_mailbox, flag);
763 
764 	/* write command + args + fill remaining with zeros */
765 	/* command code */
766 	mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
767 	mc417_memory_write(dev, dev->cx23417_mailbox + 3,
768 		IVTV_API_STD_TIMEOUT); /* timeout */
769 	for (i = 0; i < in; i++) {
770 		mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
771 		dprintk(3, "API Input %d = %d\n", i, data[i]);
772 	}
773 	for (; i < CX2341X_MBOX_MAX_DATA; i++)
774 		mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
775 
776 	flag |= 3; /* tell 'em we're done writing */
777 	mc417_memory_write(dev, dev->cx23417_mailbox, flag);
778 
779 	/* wait for firmware to handle the API command */
780 	timeout = jiffies + msecs_to_jiffies(10);
781 	for (;;) {
782 		mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
783 		if (0 != (flag & 4))
784 			break;
785 		if (time_after(jiffies, timeout)) {
786 			dprintk(3, "ERROR: API Mailbox timeout\n");
787 			return -EIO;
788 		}
789 		udelay(10);
790 	}
791 
792 	/* read output values */
793 	for (i = 0; i < out; i++) {
794 		mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
795 		dprintk(3, "API Output %d = %d\n", i, data[i]);
796 	}
797 
798 	mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
799 	dprintk(3, "API result = %d\n", retval);
800 
801 	flag = 0;
802 	mc417_memory_write(dev, dev->cx23417_mailbox, flag);
803 
804 	return 0;
805 }
806 
807 /* We don't need to call the API often, so using just one
808  * mailbox will probably suffice
809  */
810 static int cx231xx_api_cmd(struct cx231xx *dev, u32 command,
811 		u32 inputcnt, u32 outputcnt, ...)
812 {
813 	u32 data[CX2341X_MBOX_MAX_DATA];
814 	va_list vargs;
815 	int i, err;
816 
817 	dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
818 
819 	va_start(vargs, outputcnt);
820 	for (i = 0; i < inputcnt; i++)
821 		data[i] = va_arg(vargs, int);
822 
823 	err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
824 	for (i = 0; i < outputcnt; i++) {
825 		int *vptr = va_arg(vargs, int *);
826 		*vptr = data[i];
827 	}
828 	va_end(vargs);
829 
830 	return err;
831 }
832 
833 
834 static int cx231xx_find_mailbox(struct cx231xx *dev)
835 {
836 	u32 signature[4] = {
837 		0x12345678, 0x34567812, 0x56781234, 0x78123456
838 	};
839 	int signaturecnt = 0;
840 	u32 value;
841 	int i;
842 	int ret = 0;
843 
844 	dprintk(2, "%s()\n", __func__);
845 
846 	for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
847 		ret = mc417_memory_read(dev, i, &value);
848 		if (ret < 0)
849 			return ret;
850 		if (value == signature[signaturecnt])
851 			signaturecnt++;
852 		else
853 			signaturecnt = 0;
854 		if (4 == signaturecnt) {
855 			dprintk(1, "Mailbox signature found at 0x%x\n", i + 1);
856 			return i + 1;
857 		}
858 	}
859 	dprintk(3, "Mailbox signature values not found!\n");
860 	return -1;
861 }
862 
863 static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value,
864 		u32 *p_fw_image)
865 {
866 	u32 temp = 0;
867 	int i = 0;
868 
869 	temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
870 	temp = temp << 10;
871 	*p_fw_image = temp;
872 	p_fw_image++;
873 	temp = temp | (0x05 << 10);
874 	*p_fw_image = temp;
875 	p_fw_image++;
876 
877 	/*write data byte 1;*/
878 	temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
879 	temp = temp << 10;
880 	*p_fw_image = temp;
881 	p_fw_image++;
882 	temp = temp | (0x05 << 10);
883 	*p_fw_image = temp;
884 	p_fw_image++;
885 
886 	/*write data byte 2;*/
887 	temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
888 	temp = temp << 10;
889 	*p_fw_image = temp;
890 	p_fw_image++;
891 	temp = temp | (0x05 << 10);
892 	*p_fw_image = temp;
893 	p_fw_image++;
894 
895 	/*write data byte 3;*/
896 	temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
897 	temp = temp << 10;
898 	*p_fw_image = temp;
899 	p_fw_image++;
900 	temp = temp | (0x05 << 10);
901 	*p_fw_image = temp;
902 	p_fw_image++;
903 
904 	/* write address byte 2;*/
905 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
906 		((address & 0x003F0000) >> 8);
907 	temp = temp << 10;
908 	*p_fw_image = temp;
909 	p_fw_image++;
910 	temp = temp | (0x05 << 10);
911 	*p_fw_image = temp;
912 	p_fw_image++;
913 
914 	/* write address byte 1;*/
915 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
916 	temp = temp << 10;
917 	*p_fw_image = temp;
918 	p_fw_image++;
919 	temp = temp | (0x05 << 10);
920 	*p_fw_image = temp;
921 	p_fw_image++;
922 
923 	/* write address byte 0;*/
924 	temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
925 	temp = temp << 10;
926 	*p_fw_image = temp;
927 	p_fw_image++;
928 	temp = temp | (0x05 << 10);
929 	*p_fw_image = temp;
930 	p_fw_image++;
931 
932 	for (i = 0; i < 6; i++) {
933 		*p_fw_image = 0xFFFFFFFF;
934 		p_fw_image++;
935 	}
936 }
937 
938 
939 static int cx231xx_load_firmware(struct cx231xx *dev)
940 {
941 	static const unsigned char magic[8] = {
942 		0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
943 	};
944 	const struct firmware *firmware;
945 	int i, retval = 0;
946 	u32 value = 0;
947 	u32 gpio_output = 0;
948 	/*u32 checksum = 0;*/
949 	/*u32 *dataptr;*/
950 	u32 transfer_size = 0;
951 	u32 fw_data = 0;
952 	u32 address = 0;
953 	/*u32 current_fw[800];*/
954 	u32 *p_current_fw, *p_fw;
955 	u32 *p_fw_data;
956 	int frame = 0;
957 	u16 _buffer_size = 4096;
958 	u8 *p_buffer;
959 
960 	p_current_fw = vmalloc(1884180 * 4);
961 	p_fw = p_current_fw;
962 	if (p_current_fw == NULL) {
963 		dprintk(2, "FAIL!!!\n");
964 		return -1;
965 	}
966 
967 	p_buffer = vmalloc(4096);
968 	if (p_buffer == NULL) {
969 		dprintk(2, "FAIL!!!\n");
970 		return -1;
971 	}
972 
973 	dprintk(2, "%s()\n", __func__);
974 
975 	/* Save GPIO settings before reset of APU */
976 	retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
977 	retval |= mc417_memory_read(dev, 0x900C, &value);
978 
979 	retval  = mc417_register_write(dev,
980 		IVTV_REG_VPU, 0xFFFFFFED);
981 	retval |= mc417_register_write(dev,
982 		IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
983 	retval |= mc417_register_write(dev,
984 		IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
985 	retval |= mc417_register_write(dev,
986 		IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
987 	retval |= mc417_register_write(dev,
988 		IVTV_REG_APU, 0);
989 
990 	if (retval != 0) {
991 		pr_err("%s: Error with mc417_register_write\n", __func__);
992 		return -1;
993 	}
994 
995 	retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
996 				  &dev->udev->dev);
997 
998 	if (retval != 0) {
999 		pr_err("ERROR: Hotplug firmware request failed (%s).\n",
1000 			CX231xx_FIRM_IMAGE_NAME);
1001 		pr_err("Please fix your hotplug setup, the board will not work without firmware loaded!\n");
1002 		return -1;
1003 	}
1004 
1005 	if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1006 		pr_err("ERROR: Firmware size mismatch (have %zd, expected %d)\n",
1007 			firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1008 		release_firmware(firmware);
1009 		return -1;
1010 	}
1011 
1012 	if (0 != memcmp(firmware->data, magic, 8)) {
1013 		pr_err("ERROR: Firmware magic mismatch, wrong file?\n");
1014 		release_firmware(firmware);
1015 		return -1;
1016 	}
1017 
1018 	initGPIO(dev);
1019 
1020 	/* transfer to the chip */
1021 	dprintk(2, "Loading firmware to GPIO...\n");
1022 	p_fw_data = (u32 *)firmware->data;
1023 	dprintk(2, "firmware->size=%zd\n", firmware->size);
1024 	for (transfer_size = 0; transfer_size < firmware->size;
1025 		 transfer_size += 4) {
1026 		fw_data = *p_fw_data;
1027 
1028 		mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw);
1029 		address = address + 1;
1030 		p_current_fw += 20;
1031 		p_fw_data += 1;
1032 	}
1033 
1034 	/*download the firmware by ep5-out*/
1035 
1036 	for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1037 	     frame++) {
1038 		for (i = 0; i < _buffer_size; i++) {
1039 			*(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1040 			i++;
1041 			*(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1042 			i++;
1043 			*(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1044 			i++;
1045 			*(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
1046 		}
1047 		cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1048 	}
1049 
1050 	p_current_fw = p_fw;
1051 	vfree(p_current_fw);
1052 	p_current_fw = NULL;
1053 	uninitGPIO(dev);
1054 	release_firmware(firmware);
1055 	dprintk(1, "Firmware upload successful.\n");
1056 
1057 	retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1058 		IVTV_CMD_HW_BLOCKS_RST);
1059 	if (retval < 0) {
1060 		pr_err("%s: Error with mc417_register_write\n",
1061 			__func__);
1062 		return retval;
1063 	}
1064 	/* F/W power up disturbs the GPIOs, restore state */
1065 	retval |= mc417_register_write(dev, 0x9020, gpio_output);
1066 	retval |= mc417_register_write(dev, 0x900C, value);
1067 
1068 	retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1069 	retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1070 
1071 	if (retval < 0) {
1072 		pr_err("%s: Error with mc417_register_write\n",
1073 			__func__);
1074 		return retval;
1075 	}
1076 	return 0;
1077 }
1078 
1079 static void cx231xx_417_check_encoder(struct cx231xx *dev)
1080 {
1081 	u32 status, seq;
1082 
1083 	status = 0;
1084 	seq = 0;
1085 	cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1086 	dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1087 }
1088 
1089 static void cx231xx_codec_settings(struct cx231xx *dev)
1090 {
1091 	dprintk(1, "%s()\n", __func__);
1092 
1093 	/* assign frame size */
1094 	cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1095 				dev->ts1.height, dev->ts1.width);
1096 
1097 	dev->mpeg_ctrl_handler.width = dev->ts1.width;
1098 	dev->mpeg_ctrl_handler.height = dev->ts1.height;
1099 
1100 	cx2341x_handler_setup(&dev->mpeg_ctrl_handler);
1101 
1102 	cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1103 	cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1104 }
1105 
1106 static int cx231xx_initialize_codec(struct cx231xx *dev)
1107 {
1108 	int version;
1109 	int retval;
1110 	u32 i;
1111 	u32 val = 0;
1112 
1113 	dprintk(1, "%s()\n", __func__);
1114 	cx231xx_disable656(dev);
1115 	retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1116 	if (retval < 0) {
1117 		dprintk(2, "%s() PING OK\n", __func__);
1118 		retval = cx231xx_load_firmware(dev);
1119 		if (retval < 0) {
1120 			pr_err("%s() f/w load failed\n", __func__);
1121 			return retval;
1122 		}
1123 		retval = cx231xx_find_mailbox(dev);
1124 		if (retval < 0) {
1125 			pr_err("%s() mailbox < 0, error\n",
1126 				__func__);
1127 			return -1;
1128 		}
1129 		dev->cx23417_mailbox = retval;
1130 		retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1131 		if (retval < 0) {
1132 			pr_err("ERROR: cx23417 firmware ping failed!\n");
1133 			return -1;
1134 		}
1135 		retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1136 			&version);
1137 		if (retval < 0) {
1138 			pr_err("ERROR: cx23417 firmware get encoder: version failed!\n");
1139 			return -1;
1140 		}
1141 		dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1142 		msleep(200);
1143 	}
1144 
1145 	for (i = 0; i < 1; i++) {
1146 		retval = mc417_register_read(dev, 0x20f8, &val);
1147 		dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n",
1148 				 val);
1149 		if (retval < 0)
1150 			return retval;
1151 	}
1152 
1153 	cx231xx_enable656(dev);
1154 			/* stop mpeg capture */
1155 			cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1156 				 3, 0, 1, 3, 4);
1157 
1158 	cx231xx_codec_settings(dev);
1159 	msleep(60);
1160 
1161 /*	cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1162 		CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1163 	cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1164 		CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1165 		0, 0);
1166 */
1167 
1168 #if 0
1169 	/* TODO */
1170 	u32 data[7];
1171 
1172 	/* Setup to capture VBI */
1173 	data[0] = 0x0001BD00;
1174 	data[1] = 1;          /* frames per interrupt */
1175 	data[2] = 4;          /* total bufs */
1176 	data[3] = 0x91559155; /* start codes */
1177 	data[4] = 0x206080C0; /* stop codes */
1178 	data[5] = 6;          /* lines */
1179 	data[6] = 64;         /* BPL */
1180 
1181 	cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1182 		data[2], data[3], data[4], data[5], data[6]);
1183 
1184 	for (i = 2; i <= 24; i++) {
1185 		int valid;
1186 
1187 		valid = ((i >= 19) && (i <= 21));
1188 		cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1189 				valid, 0 , 0, 0);
1190 		cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1191 				i | 0x80000000, valid, 0, 0, 0);
1192 	}
1193 #endif
1194 /*	cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1195 	msleep(60);
1196 */
1197 	/* initialize the video input */
1198 	retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1199 	if (retval < 0)
1200 		return retval;
1201 	msleep(60);
1202 
1203 	/* Enable VIP style pixel invalidation so we work with scaled mode */
1204 	mc417_memory_write(dev, 2120, 0x00000080);
1205 
1206 	/* start capturing to the host interface */
1207 	retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1208 		CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1209 	if (retval < 0)
1210 		return retval;
1211 	msleep(10);
1212 
1213 	for (i = 0; i < 1; i++) {
1214 		mc417_register_read(dev, 0x20f8, &val);
1215 		dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1216 	}
1217 
1218 	return 0;
1219 }
1220 
1221 /* ------------------------------------------------------------------ */
1222 
1223 static int bb_buf_setup(struct videobuf_queue *q,
1224 	unsigned int *count, unsigned int *size)
1225 {
1226 	struct cx231xx_fh *fh = q->priv_data;
1227 
1228 	fh->dev->ts1.ts_packet_size  = mpeglinesize;
1229 	fh->dev->ts1.ts_packet_count = mpeglines;
1230 
1231 	*size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1232 	*count = mpegbufs;
1233 
1234 	return 0;
1235 }
1236 
1237 static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1238 {
1239 	struct cx231xx_fh *fh = vq->priv_data;
1240 	struct cx231xx *dev = fh->dev;
1241 	unsigned long flags = 0;
1242 
1243 	if (in_interrupt())
1244 		BUG();
1245 
1246 	spin_lock_irqsave(&dev->video_mode.slock, flags);
1247 	if (dev->USE_ISO) {
1248 		if (dev->video_mode.isoc_ctl.buf == buf)
1249 			dev->video_mode.isoc_ctl.buf = NULL;
1250 	} else {
1251 		if (dev->video_mode.bulk_ctl.buf == buf)
1252 			dev->video_mode.bulk_ctl.buf = NULL;
1253 	}
1254 	spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1255 	videobuf_waiton(vq, &buf->vb, 0, 0);
1256 	videobuf_vmalloc_free(&buf->vb);
1257 	buf->vb.state = VIDEOBUF_NEEDS_INIT;
1258 }
1259 
1260 static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1261 		struct cx231xx_dmaqueue *dma_q)
1262 {
1263 	void *vbuf;
1264 	struct cx231xx_buffer *buf;
1265 	u32 tail_data = 0;
1266 	char *p_data;
1267 
1268 	if (dma_q->mpeg_buffer_done == 0) {
1269 		if (list_empty(&dma_q->active))
1270 			return;
1271 
1272 		buf = list_entry(dma_q->active.next,
1273 				struct cx231xx_buffer, vb.queue);
1274 		dev->video_mode.isoc_ctl.buf = buf;
1275 		dma_q->mpeg_buffer_done = 1;
1276 	}
1277 	/* Fill buffer */
1278 	buf = dev->video_mode.isoc_ctl.buf;
1279 	vbuf = videobuf_to_vmalloc(&buf->vb);
1280 
1281 	if ((dma_q->mpeg_buffer_completed+len) <
1282 			mpeglines*mpeglinesize) {
1283 		if (dma_q->add_ps_package_head ==
1284 				CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1285 			memcpy(vbuf+dma_q->mpeg_buffer_completed,
1286 					dma_q->ps_head, 3);
1287 			dma_q->mpeg_buffer_completed =
1288 				dma_q->mpeg_buffer_completed + 3;
1289 			dma_q->add_ps_package_head =
1290 				CX231XX_NONEED_PS_PACKAGE_HEAD;
1291 		}
1292 		memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1293 		dma_q->mpeg_buffer_completed =
1294 			dma_q->mpeg_buffer_completed + len;
1295 	} else {
1296 		dma_q->mpeg_buffer_done = 0;
1297 
1298 		tail_data =
1299 			mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1300 		memcpy(vbuf+dma_q->mpeg_buffer_completed,
1301 				data, tail_data);
1302 
1303 		buf->vb.state = VIDEOBUF_DONE;
1304 		buf->vb.field_count++;
1305 		v4l2_get_timestamp(&buf->vb.ts);
1306 		list_del(&buf->vb.queue);
1307 		wake_up(&buf->vb.done);
1308 		dma_q->mpeg_buffer_completed = 0;
1309 
1310 		if (len - tail_data > 0) {
1311 			p_data = data + tail_data;
1312 			dma_q->left_data_count = len - tail_data;
1313 			memcpy(dma_q->p_left_data,
1314 					p_data, len - tail_data);
1315 		}
1316 	}
1317 }
1318 
1319 static void buffer_filled(char *data, int len, struct urb *urb,
1320 		struct cx231xx_dmaqueue *dma_q)
1321 {
1322 	void *vbuf;
1323 	struct cx231xx_buffer *buf;
1324 
1325 	if (list_empty(&dma_q->active))
1326 		return;
1327 
1328 	buf = list_entry(dma_q->active.next,
1329 			struct cx231xx_buffer, vb.queue);
1330 
1331 	/* Fill buffer */
1332 	vbuf = videobuf_to_vmalloc(&buf->vb);
1333 	memcpy(vbuf, data, len);
1334 	buf->vb.state = VIDEOBUF_DONE;
1335 	buf->vb.field_count++;
1336 	v4l2_get_timestamp(&buf->vb.ts);
1337 	list_del(&buf->vb.queue);
1338 	wake_up(&buf->vb.done);
1339 }
1340 
1341 static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1342 {
1343 	struct cx231xx_dmaqueue *dma_q = urb->context;
1344 	unsigned char *p_buffer;
1345 	u32 buffer_size = 0;
1346 	u32 i = 0;
1347 
1348 	for (i = 0; i < urb->number_of_packets; i++) {
1349 		if (dma_q->left_data_count > 0) {
1350 			buffer_copy(dev, dma_q->p_left_data,
1351 				    dma_q->left_data_count, urb, dma_q);
1352 			dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1353 			dma_q->left_data_count = 0;
1354 		}
1355 
1356 		p_buffer = urb->transfer_buffer +
1357 				urb->iso_frame_desc[i].offset;
1358 		buffer_size = urb->iso_frame_desc[i].actual_length;
1359 
1360 		if (buffer_size > 0)
1361 			buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1362 	}
1363 
1364 	return 0;
1365 }
1366 
1367 static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1368 {
1369 	struct cx231xx_dmaqueue *dma_q = urb->context;
1370 	unsigned char *p_buffer, *buffer;
1371 	u32 buffer_size = 0;
1372 
1373 	p_buffer = urb->transfer_buffer;
1374 	buffer_size = urb->actual_length;
1375 
1376 	buffer = kmalloc(buffer_size, GFP_ATOMIC);
1377 
1378 	memcpy(buffer, dma_q->ps_head, 3);
1379 	memcpy(buffer+3, p_buffer, buffer_size-3);
1380 	memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1381 
1382 	p_buffer = buffer;
1383 	buffer_filled(p_buffer, buffer_size, urb, dma_q);
1384 
1385 	kfree(buffer);
1386 	return 0;
1387 }
1388 
1389 static int bb_buf_prepare(struct videobuf_queue *q,
1390 	struct videobuf_buffer *vb, enum v4l2_field field)
1391 {
1392 	struct cx231xx_fh *fh = q->priv_data;
1393 	struct cx231xx_buffer *buf =
1394 	    container_of(vb, struct cx231xx_buffer, vb);
1395 	struct cx231xx *dev = fh->dev;
1396 	int rc = 0, urb_init = 0;
1397 	int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1398 
1399 	if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1400 		return -EINVAL;
1401 	buf->vb.width = fh->dev->ts1.ts_packet_size;
1402 	buf->vb.height = fh->dev->ts1.ts_packet_count;
1403 	buf->vb.size = size;
1404 	buf->vb.field = field;
1405 
1406 	if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1407 		rc = videobuf_iolock(q, &buf->vb, NULL);
1408 		if (rc < 0)
1409 			goto fail;
1410 	}
1411 
1412 	if (dev->USE_ISO) {
1413 		if (!dev->video_mode.isoc_ctl.num_bufs)
1414 			urb_init = 1;
1415 	} else {
1416 		if (!dev->video_mode.bulk_ctl.num_bufs)
1417 			urb_init = 1;
1418 	}
1419 	/*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1420 		urb_init, dev->video_mode.max_pkt_size);*/
1421 	dev->mode_tv = 1;
1422 
1423 	if (urb_init) {
1424 		rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1425 		rc = cx231xx_unmute_audio(dev);
1426 		if (dev->USE_ISO) {
1427 			cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1428 			rc = cx231xx_init_isoc(dev, mpeglines,
1429 				       mpegbufs,
1430 				       dev->ts1_mode.max_pkt_size,
1431 				       cx231xx_isoc_copy);
1432 		} else {
1433 			cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1434 			rc = cx231xx_init_bulk(dev, mpeglines,
1435 				       mpegbufs,
1436 				       dev->ts1_mode.max_pkt_size,
1437 				       cx231xx_bulk_copy);
1438 		}
1439 		if (rc < 0)
1440 			goto fail;
1441 	}
1442 
1443 	buf->vb.state = VIDEOBUF_PREPARED;
1444 	return 0;
1445 
1446 fail:
1447 	free_buffer(q, buf);
1448 	return rc;
1449 }
1450 
1451 static void bb_buf_queue(struct videobuf_queue *q,
1452 	struct videobuf_buffer *vb)
1453 {
1454 	struct cx231xx_fh *fh = q->priv_data;
1455 
1456 	struct cx231xx_buffer *buf =
1457 	    container_of(vb, struct cx231xx_buffer, vb);
1458 	struct cx231xx *dev = fh->dev;
1459 	struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1460 
1461 	buf->vb.state = VIDEOBUF_QUEUED;
1462 	list_add_tail(&buf->vb.queue, &vidq->active);
1463 
1464 }
1465 
1466 static void bb_buf_release(struct videobuf_queue *q,
1467 	struct videobuf_buffer *vb)
1468 {
1469 	struct cx231xx_buffer *buf =
1470 	    container_of(vb, struct cx231xx_buffer, vb);
1471 	/*struct cx231xx_fh *fh = q->priv_data;*/
1472 	/*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1473 
1474 	free_buffer(q, buf);
1475 }
1476 
1477 static struct videobuf_queue_ops cx231xx_qops = {
1478 	.buf_setup    = bb_buf_setup,
1479 	.buf_prepare  = bb_buf_prepare,
1480 	.buf_queue    = bb_buf_queue,
1481 	.buf_release  = bb_buf_release,
1482 };
1483 
1484 /* ------------------------------------------------------------------ */
1485 
1486 static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1487 {
1488 	struct cx231xx_fh  *fh  = file->private_data;
1489 	struct cx231xx *dev = fh->dev;
1490 
1491 	*norm = dev->encodernorm.id;
1492 	return 0;
1493 }
1494 
1495 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id)
1496 {
1497 	struct cx231xx_fh  *fh  = file->private_data;
1498 	struct cx231xx *dev = fh->dev;
1499 	unsigned int i;
1500 
1501 	for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1502 		if (id & cx231xx_tvnorms[i].id)
1503 			break;
1504 	if (i == ARRAY_SIZE(cx231xx_tvnorms))
1505 		return -EINVAL;
1506 	dev->encodernorm = cx231xx_tvnorms[i];
1507 
1508 	if (dev->encodernorm.id & 0xb000) {
1509 		dprintk(3, "encodernorm set to NTSC\n");
1510 		dev->norm = V4L2_STD_NTSC;
1511 		dev->ts1.height = 480;
1512 		cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
1513 	} else {
1514 		dprintk(3, "encodernorm set to PAL\n");
1515 		dev->norm = V4L2_STD_PAL_B;
1516 		dev->ts1.height = 576;
1517 		cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, true);
1518 	}
1519 	call_all(dev, video, s_std, dev->norm);
1520 	/* do mode control overrides */
1521 	cx231xx_do_mode_ctrl_overrides(dev);
1522 
1523 	dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1524 	return 0;
1525 }
1526 
1527 static int vidioc_s_ctrl(struct file *file, void *priv,
1528 				struct v4l2_control *ctl)
1529 {
1530 	struct cx231xx_fh  *fh  = file->private_data;
1531 	struct cx231xx *dev = fh->dev;
1532 
1533 	dprintk(3, "enter vidioc_s_ctrl()\n");
1534 	/* Update the A/V core */
1535 	call_all(dev, core, s_ctrl, ctl);
1536 	dprintk(3, "exit vidioc_s_ctrl()\n");
1537 	return 0;
1538 }
1539 
1540 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1541 					struct v4l2_fmtdesc *f)
1542 {
1543 	if (f->index != 0)
1544 		return -EINVAL;
1545 
1546 	strlcpy(f->description, "MPEG", sizeof(f->description));
1547 	f->pixelformat = V4L2_PIX_FMT_MPEG;
1548 
1549 	return 0;
1550 }
1551 
1552 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1553 				struct v4l2_format *f)
1554 {
1555 	struct cx231xx_fh  *fh  = file->private_data;
1556 	struct cx231xx *dev = fh->dev;
1557 
1558 	dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1559 	f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1560 	f->fmt.pix.bytesperline = 0;
1561 	f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1562 	f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1563 	f->fmt.pix.width = dev->ts1.width;
1564 	f->fmt.pix.height = dev->ts1.height;
1565 	f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1566 	dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n",
1567 		dev->ts1.width, dev->ts1.height);
1568 	dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1569 	return 0;
1570 }
1571 
1572 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1573 				struct v4l2_format *f)
1574 {
1575 	struct cx231xx_fh  *fh  = file->private_data;
1576 	struct cx231xx *dev = fh->dev;
1577 
1578 	dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1579 	f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1580 	f->fmt.pix.bytesperline = 0;
1581 	f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1582 	f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1583 	f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1584 	dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n",
1585 		dev->ts1.width, dev->ts1.height);
1586 	dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1587 	return 0;
1588 }
1589 
1590 static int vidioc_reqbufs(struct file *file, void *priv,
1591 				struct v4l2_requestbuffers *p)
1592 {
1593 	struct cx231xx_fh  *fh  = file->private_data;
1594 
1595 	return videobuf_reqbufs(&fh->vidq, p);
1596 }
1597 
1598 static int vidioc_querybuf(struct file *file, void *priv,
1599 				struct v4l2_buffer *p)
1600 {
1601 	struct cx231xx_fh  *fh  = file->private_data;
1602 
1603 	return videobuf_querybuf(&fh->vidq, p);
1604 }
1605 
1606 static int vidioc_qbuf(struct file *file, void *priv,
1607 				struct v4l2_buffer *p)
1608 {
1609 	struct cx231xx_fh  *fh  = file->private_data;
1610 
1611 	return videobuf_qbuf(&fh->vidq, p);
1612 }
1613 
1614 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1615 {
1616 	struct cx231xx_fh  *fh  = priv;
1617 
1618 	return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1619 }
1620 
1621 
1622 static int vidioc_streamon(struct file *file, void *priv,
1623 				enum v4l2_buf_type i)
1624 {
1625 	struct cx231xx_fh  *fh  = file->private_data;
1626 	struct cx231xx *dev = fh->dev;
1627 
1628 	dprintk(3, "enter vidioc_streamon()\n");
1629 	cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1630 	cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1631 	if (dev->USE_ISO)
1632 		cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1633 				CX231XX_NUM_BUFS,
1634 				dev->video_mode.max_pkt_size,
1635 				cx231xx_isoc_copy);
1636 	else {
1637 		cx231xx_init_bulk(dev, 320,
1638 				5,
1639 				dev->ts1_mode.max_pkt_size,
1640 				cx231xx_bulk_copy);
1641 	}
1642 	dprintk(3, "exit vidioc_streamon()\n");
1643 	return videobuf_streamon(&fh->vidq);
1644 }
1645 
1646 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1647 {
1648 	struct cx231xx_fh  *fh  = file->private_data;
1649 
1650 	return videobuf_streamoff(&fh->vidq);
1651 }
1652 
1653 static int vidioc_log_status(struct file *file, void *priv)
1654 {
1655 	struct cx231xx_fh  *fh  = priv;
1656 	struct cx231xx *dev = fh->dev;
1657 
1658 	call_all(dev, core, log_status);
1659 	return v4l2_ctrl_log_status(file, priv);
1660 }
1661 
1662 static int mpeg_open(struct file *file)
1663 {
1664 	struct video_device *vdev = video_devdata(file);
1665 	struct cx231xx *dev = video_drvdata(file);
1666 	struct cx231xx_fh *fh;
1667 
1668 	dprintk(2, "%s()\n", __func__);
1669 
1670 	if (mutex_lock_interruptible(&dev->lock))
1671 		return -ERESTARTSYS;
1672 
1673 	/* allocate + initialize per filehandle data */
1674 	fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1675 	if (NULL == fh) {
1676 		mutex_unlock(&dev->lock);
1677 		return -ENOMEM;
1678 	}
1679 
1680 	file->private_data = fh;
1681 	v4l2_fh_init(&fh->fh, vdev);
1682 	fh->dev = dev;
1683 
1684 
1685 	videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1686 			    NULL, &dev->video_mode.slock,
1687 			    V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1688 			    sizeof(struct cx231xx_buffer), fh, &dev->lock);
1689 /*
1690 	videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1691 			    &dev->udev->dev, &dev->ts1.slock,
1692 			    V4L2_BUF_TYPE_VIDEO_CAPTURE,
1693 			    V4L2_FIELD_INTERLACED,
1694 			    sizeof(struct cx231xx_buffer),
1695 			    fh, &dev->lock);
1696 */
1697 
1698 	cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1699 	cx231xx_set_gpio_value(dev, 2, 0);
1700 
1701 	cx231xx_initialize_codec(dev);
1702 
1703 	mutex_unlock(&dev->lock);
1704 	v4l2_fh_add(&fh->fh);
1705 	cx231xx_start_TS1(dev);
1706 
1707 	return 0;
1708 }
1709 
1710 static int mpeg_release(struct file *file)
1711 {
1712 	struct cx231xx_fh  *fh  = file->private_data;
1713 	struct cx231xx *dev = fh->dev;
1714 
1715 	dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
1716 
1717 	mutex_lock(&dev->lock);
1718 
1719 	cx231xx_stop_TS1(dev);
1720 
1721 	/* do this before setting alternate! */
1722 	if (dev->USE_ISO)
1723 		cx231xx_uninit_isoc(dev);
1724 	else
1725 		cx231xx_uninit_bulk(dev);
1726 	cx231xx_set_mode(dev, CX231XX_SUSPEND);
1727 
1728 	cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1729 			CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
1730 			CX231xx_RAW_BITS_NONE);
1731 
1732 	/* FIXME: Review this crap */
1733 	/* Shut device down on last close */
1734 	if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1735 		if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1736 			/* stop mpeg capture */
1737 
1738 			msleep(500);
1739 			cx231xx_417_check_encoder(dev);
1740 
1741 		}
1742 	}
1743 
1744 	if (fh->vidq.streaming)
1745 		videobuf_streamoff(&fh->vidq);
1746 	if (fh->vidq.reading)
1747 		videobuf_read_stop(&fh->vidq);
1748 
1749 	videobuf_mmap_free(&fh->vidq);
1750 	v4l2_fh_del(&fh->fh);
1751 	v4l2_fh_exit(&fh->fh);
1752 	kfree(fh);
1753 	mutex_unlock(&dev->lock);
1754 	return 0;
1755 }
1756 
1757 static ssize_t mpeg_read(struct file *file, char __user *data,
1758 	size_t count, loff_t *ppos)
1759 {
1760 	struct cx231xx_fh *fh = file->private_data;
1761 	struct cx231xx *dev = fh->dev;
1762 
1763 	/* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1764 	/* Start mpeg encoder on first read. */
1765 	if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1766 		if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1767 			if (cx231xx_initialize_codec(dev) < 0)
1768 				return -EINVAL;
1769 		}
1770 	}
1771 
1772 	return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
1773 				    file->f_flags & O_NONBLOCK);
1774 }
1775 
1776 static unsigned int mpeg_poll(struct file *file,
1777 	struct poll_table_struct *wait)
1778 {
1779 	unsigned long req_events = poll_requested_events(wait);
1780 	struct cx231xx_fh *fh = file->private_data;
1781 	struct cx231xx *dev = fh->dev;
1782 	unsigned int res = 0;
1783 
1784 	if (v4l2_event_pending(&fh->fh))
1785 		res |= POLLPRI;
1786 	else
1787 		poll_wait(file, &fh->fh.wait, wait);
1788 
1789 	if (!(req_events & (POLLIN | POLLRDNORM)))
1790 		return res;
1791 
1792 	mutex_lock(&dev->lock);
1793 	res |= videobuf_poll_stream(file, &fh->vidq, wait);
1794 	mutex_unlock(&dev->lock);
1795 	return res;
1796 }
1797 
1798 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1799 {
1800 	struct cx231xx_fh *fh = file->private_data;
1801 	struct cx231xx *dev = fh->dev;
1802 
1803 	dprintk(2, "%s()\n", __func__);
1804 
1805 	return videobuf_mmap_mapper(&fh->vidq, vma);
1806 }
1807 
1808 static struct v4l2_file_operations mpeg_fops = {
1809 	.owner	       = THIS_MODULE,
1810 	.open	       = mpeg_open,
1811 	.release       = mpeg_release,
1812 	.read	       = mpeg_read,
1813 	.poll          = mpeg_poll,
1814 	.mmap	       = mpeg_mmap,
1815 	.unlocked_ioctl = video_ioctl2,
1816 };
1817 
1818 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1819 	.vidioc_s_std		 = vidioc_s_std,
1820 	.vidioc_g_std		 = vidioc_g_std,
1821 	.vidioc_g_tuner          = cx231xx_g_tuner,
1822 	.vidioc_s_tuner          = cx231xx_s_tuner,
1823 	.vidioc_g_frequency      = cx231xx_g_frequency,
1824 	.vidioc_s_frequency      = cx231xx_s_frequency,
1825 	.vidioc_enum_input	 = cx231xx_enum_input,
1826 	.vidioc_g_input		 = cx231xx_g_input,
1827 	.vidioc_s_input		 = cx231xx_s_input,
1828 	.vidioc_s_ctrl		 = vidioc_s_ctrl,
1829 	.vidioc_querycap	 = cx231xx_querycap,
1830 	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1831 	.vidioc_g_fmt_vid_cap	 = vidioc_g_fmt_vid_cap,
1832 	.vidioc_try_fmt_vid_cap	 = vidioc_try_fmt_vid_cap,
1833 	.vidioc_s_fmt_vid_cap	 = vidioc_try_fmt_vid_cap,
1834 	.vidioc_reqbufs		 = vidioc_reqbufs,
1835 	.vidioc_querybuf	 = vidioc_querybuf,
1836 	.vidioc_qbuf		 = vidioc_qbuf,
1837 	.vidioc_dqbuf		 = vidioc_dqbuf,
1838 	.vidioc_streamon	 = vidioc_streamon,
1839 	.vidioc_streamoff	 = vidioc_streamoff,
1840 	.vidioc_log_status	 = vidioc_log_status,
1841 #ifdef CONFIG_VIDEO_ADV_DEBUG
1842 	.vidioc_g_register	 = cx231xx_g_register,
1843 	.vidioc_s_register	 = cx231xx_s_register,
1844 #endif
1845 	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1846 	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1847 };
1848 
1849 static struct video_device cx231xx_mpeg_template = {
1850 	.name          = "cx231xx",
1851 	.fops          = &mpeg_fops,
1852 	.ioctl_ops     = &mpeg_ioctl_ops,
1853 	.minor         = -1,
1854 	.tvnorms       = V4L2_STD_ALL,
1855 };
1856 
1857 void cx231xx_417_unregister(struct cx231xx *dev)
1858 {
1859 	dprintk(1, "%s()\n", __func__);
1860 	dprintk(3, "%s()\n", __func__);
1861 
1862 	if (dev->v4l_device) {
1863 		if (-1 != dev->v4l_device->minor)
1864 			video_unregister_device(dev->v4l_device);
1865 		else
1866 			video_device_release(dev->v4l_device);
1867 		v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1868 		dev->v4l_device = NULL;
1869 	}
1870 }
1871 
1872 static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val)
1873 {
1874 	struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1875 	int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1;
1876 	struct v4l2_mbus_framefmt fmt;
1877 
1878 	/* fix videodecoder resolution */
1879 	fmt.width = cxhdl->width / (is_mpeg1 ? 2 : 1);
1880 	fmt.height = cxhdl->height;
1881 	fmt.code = V4L2_MBUS_FMT_FIXED;
1882 	v4l2_subdev_call(dev->sd_cx25840, video, s_mbus_fmt, &fmt);
1883 	return 0;
1884 }
1885 
1886 static int cx231xx_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx)
1887 {
1888 	static const u32 freqs[3] = { 44100, 48000, 32000 };
1889 	struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1890 
1891 	/* The audio clock of the digitizer must match the codec sample
1892 	   rate otherwise you get some very strange effects. */
1893 	if (idx < ARRAY_SIZE(freqs))
1894 		call_all(dev, audio, s_clock_freq, freqs[idx]);
1895 	return 0;
1896 }
1897 
1898 static struct cx2341x_handler_ops cx231xx_ops = {
1899 	/* needed for the video clock freq */
1900 	.s_audio_sampling_freq = cx231xx_s_audio_sampling_freq,
1901 	/* needed for setting up the video resolution */
1902 	.s_video_encoding = cx231xx_s_video_encoding,
1903 };
1904 
1905 static struct video_device *cx231xx_video_dev_alloc(
1906 	struct cx231xx *dev,
1907 	struct usb_device *usbdev,
1908 	struct video_device *template,
1909 	char *type)
1910 {
1911 	struct video_device *vfd;
1912 
1913 	dprintk(1, "%s()\n", __func__);
1914 	vfd = video_device_alloc();
1915 	if (NULL == vfd)
1916 		return NULL;
1917 	*vfd = *template;
1918 	snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1919 		type, cx231xx_boards[dev->model].name);
1920 
1921 	vfd->v4l2_dev = &dev->v4l2_dev;
1922 	vfd->lock = &dev->lock;
1923 	vfd->release = video_device_release;
1924 	vfd->ctrl_handler = &dev->mpeg_ctrl_handler.hdl;
1925 	video_set_drvdata(vfd, dev);
1926 	if (dev->tuner_type == TUNER_ABSENT) {
1927 		v4l2_disable_ioctl(vfd, VIDIOC_G_FREQUENCY);
1928 		v4l2_disable_ioctl(vfd, VIDIOC_S_FREQUENCY);
1929 		v4l2_disable_ioctl(vfd, VIDIOC_G_TUNER);
1930 		v4l2_disable_ioctl(vfd, VIDIOC_S_TUNER);
1931 	}
1932 
1933 	return vfd;
1934 
1935 }
1936 
1937 int cx231xx_417_register(struct cx231xx *dev)
1938 {
1939 	/* FIXME: Port1 hardcoded here */
1940 	int err = -ENODEV;
1941 	struct cx231xx_tsport *tsport = &dev->ts1;
1942 
1943 	dprintk(1, "%s()\n", __func__);
1944 
1945 	/* Set default TV standard */
1946 	dev->encodernorm = cx231xx_tvnorms[0];
1947 
1948 	if (dev->encodernorm.id & V4L2_STD_525_60)
1949 		tsport->height = 480;
1950 	else
1951 		tsport->height = 576;
1952 
1953 	tsport->width = 720;
1954 	err = cx2341x_handler_init(&dev->mpeg_ctrl_handler, 50);
1955 	if (err) {
1956 		dprintk(3, "%s: can't init cx2341x controls\n", dev->name);
1957 		return err;
1958 	}
1959 	dev->mpeg_ctrl_handler.func = cx231xx_mbox_func;
1960 	dev->mpeg_ctrl_handler.priv = dev;
1961 	dev->mpeg_ctrl_handler.ops = &cx231xx_ops;
1962 	if (dev->sd_cx25840)
1963 		v4l2_ctrl_add_handler(&dev->mpeg_ctrl_handler.hdl,
1964 				dev->sd_cx25840->ctrl_handler, NULL);
1965 	if (dev->mpeg_ctrl_handler.hdl.error) {
1966 		err = dev->mpeg_ctrl_handler.hdl.error;
1967 		dprintk(3, "%s: can't add cx25840 controls\n", dev->name);
1968 		v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1969 		return err;
1970 	}
1971 	dev->norm = V4L2_STD_NTSC;
1972 
1973 	dev->mpeg_ctrl_handler.port = CX2341X_PORT_SERIAL;
1974 	cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
1975 
1976 	/* Allocate and initialize V4L video device */
1977 	dev->v4l_device = cx231xx_video_dev_alloc(dev,
1978 		dev->udev, &cx231xx_mpeg_template, "mpeg");
1979 	err = video_register_device(dev->v4l_device,
1980 		VFL_TYPE_GRABBER, -1);
1981 	if (err < 0) {
1982 		dprintk(3, "%s: can't register mpeg device\n", dev->name);
1983 		v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1984 		return err;
1985 	}
1986 
1987 	dprintk(3, "%s: registered device video%d [mpeg]\n",
1988 	       dev->name, dev->v4l_device->num);
1989 
1990 	return 0;
1991 }
1992 
1993 MODULE_FIRMWARE(CX231xx_FIRM_IMAGE_NAME);
1994