1 /* 2 * Rafael Micro R820T driver 3 * 4 * Copyright (C) 2013 Mauro Carvalho Chehab 5 * 6 * This driver was written from scratch, based on an existing driver 7 * that it is part of rtl-sdr git tree, released under GPLv2: 8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug 9 * https://github.com/n1gp/gr-baz 10 * 11 * From what I understood from the threads, the original driver was converted 12 * to userspace from a Realtek tree. I couldn't find the original tree. 13 * However, the original driver look awkward on my eyes. So, I decided to 14 * write a new version from it from the scratch, while trying to reproduce 15 * everything found there. 16 * 17 * TODO: 18 * After locking, the original driver seems to have some routines to 19 * improve reception. This was not implemented here yet. 20 * 21 * RF Gain set/get is not implemented. 22 * 23 * This program is free software; you can redistribute it and/or modify 24 * it under the terms of the GNU General Public License as published by 25 * the Free Software Foundation; either version 2 of the License, or 26 * (at your option) any later version. 27 * 28 * This program is distributed in the hope that it will be useful, 29 * but WITHOUT ANY WARRANTY; without even the implied warranty of 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 31 * GNU General Public License for more details. 32 * 33 */ 34 35 #include <linux/videodev2.h> 36 #include <linux/mutex.h> 37 #include <linux/slab.h> 38 #include <linux/bitrev.h> 39 40 #include "tuner-i2c.h" 41 #include "r820t.h" 42 43 /* 44 * FIXME: I think that there are only 32 registers, but better safe than 45 * sorry. After finishing the driver, we may review it. 46 */ 47 #define REG_SHADOW_START 5 48 #define NUM_REGS 27 49 #define NUM_IMR 5 50 #define IMR_TRIAL 9 51 52 #define VER_NUM 49 53 54 static int debug; 55 module_param(debug, int, 0644); 56 MODULE_PARM_DESC(debug, "enable verbose debug messages"); 57 58 static int no_imr_cal; 59 module_param(no_imr_cal, int, 0444); 60 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init"); 61 62 63 /* 64 * enums and structures 65 */ 66 67 enum xtal_cap_value { 68 XTAL_LOW_CAP_30P = 0, 69 XTAL_LOW_CAP_20P, 70 XTAL_LOW_CAP_10P, 71 XTAL_LOW_CAP_0P, 72 XTAL_HIGH_CAP_0P 73 }; 74 75 struct r820t_sect_type { 76 u8 phase_y; 77 u8 gain_x; 78 u16 value; 79 }; 80 81 struct r820t_priv { 82 struct list_head hybrid_tuner_instance_list; 83 const struct r820t_config *cfg; 84 struct tuner_i2c_props i2c_props; 85 struct mutex lock; 86 87 u8 regs[NUM_REGS]; 88 u8 buf[NUM_REGS + 1]; 89 enum xtal_cap_value xtal_cap_sel; 90 u16 pll; /* kHz */ 91 u32 int_freq; 92 u8 fil_cal_code; 93 bool imr_done; 94 bool has_lock; 95 bool init_done; 96 struct r820t_sect_type imr_data[NUM_IMR]; 97 98 /* Store current mode */ 99 u32 delsys; 100 enum v4l2_tuner_type type; 101 v4l2_std_id std; 102 u32 bw; /* in MHz */ 103 }; 104 105 struct r820t_freq_range { 106 u32 freq; 107 u8 open_d; 108 u8 rf_mux_ploy; 109 u8 tf_c; 110 u8 xtal_cap20p; 111 u8 xtal_cap10p; 112 u8 xtal_cap0p; 113 u8 imr_mem; /* Not used, currently */ 114 }; 115 116 #define VCO_POWER_REF 0x02 117 #define DIP_FREQ 32000000 118 119 /* 120 * Static constants 121 */ 122 123 static LIST_HEAD(hybrid_tuner_instance_list); 124 static DEFINE_MUTEX(r820t_list_mutex); 125 126 /* Those initial values start from REG_SHADOW_START */ 127 static const u8 r820t_init_array[NUM_REGS] = { 128 0x83, 0x32, 0x75, /* 05 to 07 */ 129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */ 130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */ 131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */ 132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */ 133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */ 134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */ 135 }; 136 137 /* Tuner frequency ranges */ 138 static const struct r820t_freq_range freq_ranges[] = { 139 { 140 .freq = 0, 141 .open_d = 0x08, /* low */ 142 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 143 .tf_c = 0xdf, /* R27[7:0] band2,band0 */ 144 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 145 .xtal_cap10p = 0x01, 146 .xtal_cap0p = 0x00, 147 .imr_mem = 0, 148 }, { 149 .freq = 50, /* Start freq, in MHz */ 150 .open_d = 0x08, /* low */ 151 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 152 .tf_c = 0xbe, /* R27[7:0] band4,band1 */ 153 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 154 .xtal_cap10p = 0x01, 155 .xtal_cap0p = 0x00, 156 .imr_mem = 0, 157 }, { 158 .freq = 55, /* Start freq, in MHz */ 159 .open_d = 0x08, /* low */ 160 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 161 .tf_c = 0x8b, /* R27[7:0] band7,band4 */ 162 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 163 .xtal_cap10p = 0x01, 164 .xtal_cap0p = 0x00, 165 .imr_mem = 0, 166 }, { 167 .freq = 60, /* Start freq, in MHz */ 168 .open_d = 0x08, /* low */ 169 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 170 .tf_c = 0x7b, /* R27[7:0] band8,band4 */ 171 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 172 .xtal_cap10p = 0x01, 173 .xtal_cap0p = 0x00, 174 .imr_mem = 0, 175 }, { 176 .freq = 65, /* Start freq, in MHz */ 177 .open_d = 0x08, /* low */ 178 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 179 .tf_c = 0x69, /* R27[7:0] band9,band6 */ 180 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 181 .xtal_cap10p = 0x01, 182 .xtal_cap0p = 0x00, 183 .imr_mem = 0, 184 }, { 185 .freq = 70, /* Start freq, in MHz */ 186 .open_d = 0x08, /* low */ 187 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 188 .tf_c = 0x58, /* R27[7:0] band10,band7 */ 189 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 190 .xtal_cap10p = 0x01, 191 .xtal_cap0p = 0x00, 192 .imr_mem = 0, 193 }, { 194 .freq = 75, /* Start freq, in MHz */ 195 .open_d = 0x00, /* high */ 196 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 197 .tf_c = 0x44, /* R27[7:0] band11,band11 */ 198 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 199 .xtal_cap10p = 0x01, 200 .xtal_cap0p = 0x00, 201 .imr_mem = 0, 202 }, { 203 .freq = 80, /* Start freq, in MHz */ 204 .open_d = 0x00, /* high */ 205 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 206 .tf_c = 0x44, /* R27[7:0] band11,band11 */ 207 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 208 .xtal_cap10p = 0x01, 209 .xtal_cap0p = 0x00, 210 .imr_mem = 0, 211 }, { 212 .freq = 90, /* Start freq, in MHz */ 213 .open_d = 0x00, /* high */ 214 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 215 .tf_c = 0x34, /* R27[7:0] band12,band11 */ 216 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 217 .xtal_cap10p = 0x01, 218 .xtal_cap0p = 0x00, 219 .imr_mem = 0, 220 }, { 221 .freq = 100, /* Start freq, in MHz */ 222 .open_d = 0x00, /* high */ 223 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 224 .tf_c = 0x34, /* R27[7:0] band12,band11 */ 225 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 226 .xtal_cap10p = 0x01, 227 .xtal_cap0p = 0x00, 228 .imr_mem = 0, 229 }, { 230 .freq = 110, /* Start freq, in MHz */ 231 .open_d = 0x00, /* high */ 232 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 233 .tf_c = 0x24, /* R27[7:0] band13,band11 */ 234 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 235 .xtal_cap10p = 0x01, 236 .xtal_cap0p = 0x00, 237 .imr_mem = 1, 238 }, { 239 .freq = 120, /* Start freq, in MHz */ 240 .open_d = 0x00, /* high */ 241 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 242 .tf_c = 0x24, /* R27[7:0] band13,band11 */ 243 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 244 .xtal_cap10p = 0x01, 245 .xtal_cap0p = 0x00, 246 .imr_mem = 1, 247 }, { 248 .freq = 140, /* Start freq, in MHz */ 249 .open_d = 0x00, /* high */ 250 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 251 .tf_c = 0x14, /* R27[7:0] band14,band11 */ 252 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 253 .xtal_cap10p = 0x01, 254 .xtal_cap0p = 0x00, 255 .imr_mem = 1, 256 }, { 257 .freq = 180, /* Start freq, in MHz */ 258 .open_d = 0x00, /* high */ 259 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 260 .tf_c = 0x13, /* R27[7:0] band14,band12 */ 261 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 262 .xtal_cap10p = 0x00, 263 .xtal_cap0p = 0x00, 264 .imr_mem = 1, 265 }, { 266 .freq = 220, /* Start freq, in MHz */ 267 .open_d = 0x00, /* high */ 268 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 269 .tf_c = 0x13, /* R27[7:0] band14,band12 */ 270 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 271 .xtal_cap10p = 0x00, 272 .xtal_cap0p = 0x00, 273 .imr_mem = 2, 274 }, { 275 .freq = 250, /* Start freq, in MHz */ 276 .open_d = 0x00, /* high */ 277 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 278 .tf_c = 0x11, /* R27[7:0] highest,highest */ 279 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 280 .xtal_cap10p = 0x00, 281 .xtal_cap0p = 0x00, 282 .imr_mem = 2, 283 }, { 284 .freq = 280, /* Start freq, in MHz */ 285 .open_d = 0x00, /* high */ 286 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 287 .tf_c = 0x00, /* R27[7:0] highest,highest */ 288 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 289 .xtal_cap10p = 0x00, 290 .xtal_cap0p = 0x00, 291 .imr_mem = 2, 292 }, { 293 .freq = 310, /* Start freq, in MHz */ 294 .open_d = 0x00, /* high */ 295 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 296 .tf_c = 0x00, /* R27[7:0] highest,highest */ 297 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 298 .xtal_cap10p = 0x00, 299 .xtal_cap0p = 0x00, 300 .imr_mem = 2, 301 }, { 302 .freq = 450, /* Start freq, in MHz */ 303 .open_d = 0x00, /* high */ 304 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 305 .tf_c = 0x00, /* R27[7:0] highest,highest */ 306 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 307 .xtal_cap10p = 0x00, 308 .xtal_cap0p = 0x00, 309 .imr_mem = 3, 310 }, { 311 .freq = 588, /* Start freq, in MHz */ 312 .open_d = 0x00, /* high */ 313 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 314 .tf_c = 0x00, /* R27[7:0] highest,highest */ 315 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 316 .xtal_cap10p = 0x00, 317 .xtal_cap0p = 0x00, 318 .imr_mem = 3, 319 }, { 320 .freq = 650, /* Start freq, in MHz */ 321 .open_d = 0x00, /* high */ 322 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 323 .tf_c = 0x00, /* R27[7:0] highest,highest */ 324 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 325 .xtal_cap10p = 0x00, 326 .xtal_cap0p = 0x00, 327 .imr_mem = 4, 328 } 329 }; 330 331 static int r820t_xtal_capacitor[][2] = { 332 { 0x0b, XTAL_LOW_CAP_30P }, 333 { 0x02, XTAL_LOW_CAP_20P }, 334 { 0x01, XTAL_LOW_CAP_10P }, 335 { 0x00, XTAL_LOW_CAP_0P }, 336 { 0x10, XTAL_HIGH_CAP_0P }, 337 }; 338 339 /* 340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm 341 * input power, for raw results see: 342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/ 343 */ 344 345 static const int r820t_lna_gain_steps[] = { 346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13 347 }; 348 349 static const int r820t_mixer_gain_steps[] = { 350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8 351 }; 352 353 /* 354 * I2C read/write code and shadow registers logic 355 */ 356 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val, 357 int len) 358 { 359 int r = reg - REG_SHADOW_START; 360 361 if (r < 0) { 362 len += r; 363 r = 0; 364 } 365 if (len <= 0) 366 return; 367 if (len > NUM_REGS - r) 368 len = NUM_REGS - r; 369 370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n", 371 __func__, r + REG_SHADOW_START, len, len, val); 372 373 memcpy(&priv->regs[r], val, len); 374 } 375 376 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val, 377 int len) 378 { 379 int rc, size, pos = 0; 380 381 /* Store the shadow registers */ 382 shadow_store(priv, reg, val, len); 383 384 do { 385 if (len > priv->cfg->max_i2c_msg_len - 1) 386 size = priv->cfg->max_i2c_msg_len - 1; 387 else 388 size = len; 389 390 /* Fill I2C buffer */ 391 priv->buf[0] = reg; 392 memcpy(&priv->buf[1], &val[pos], size); 393 394 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1); 395 if (rc != size + 1) { 396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n", 397 __func__, rc, reg, size, size, &priv->buf[1]); 398 if (rc < 0) 399 return rc; 400 return -EREMOTEIO; 401 } 402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n", 403 __func__, reg, size, size, &priv->buf[1]); 404 405 reg += size; 406 len -= size; 407 pos += size; 408 } while (len > 0); 409 410 return 0; 411 } 412 413 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val) 414 { 415 return r820t_write(priv, reg, &val, 1); 416 } 417 418 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg) 419 { 420 reg -= REG_SHADOW_START; 421 422 if (reg >= 0 && reg < NUM_REGS) 423 return priv->regs[reg]; 424 else 425 return -EINVAL; 426 } 427 428 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val, 429 u8 bit_mask) 430 { 431 int rc = r820t_read_cache_reg(priv, reg); 432 433 if (rc < 0) 434 return rc; 435 436 val = (rc & ~bit_mask) | (val & bit_mask); 437 438 return r820t_write(priv, reg, &val, 1); 439 } 440 441 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len) 442 { 443 int rc, i; 444 u8 *p = &priv->buf[1]; 445 446 priv->buf[0] = reg; 447 448 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len); 449 if (rc != len) { 450 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n", 451 __func__, rc, reg, len, len, p); 452 if (rc < 0) 453 return rc; 454 return -EREMOTEIO; 455 } 456 457 /* Copy data to the output buffer */ 458 for (i = 0; i < len; i++) 459 val[i] = bitrev8(p[i]); 460 461 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n", 462 __func__, reg, len, len, val); 463 464 return 0; 465 } 466 467 /* 468 * r820t tuning logic 469 */ 470 471 static int r820t_set_mux(struct r820t_priv *priv, u32 freq) 472 { 473 const struct r820t_freq_range *range; 474 int i, rc; 475 u8 val, reg08, reg09; 476 477 /* Get the proper frequency range */ 478 freq = freq / 1000000; 479 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) { 480 if (freq < freq_ranges[i + 1].freq) 481 break; 482 } 483 range = &freq_ranges[i]; 484 485 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq); 486 487 /* Open Drain */ 488 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08); 489 if (rc < 0) 490 return rc; 491 492 /* RF_MUX,Polymux */ 493 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3); 494 if (rc < 0) 495 return rc; 496 497 /* TF BAND */ 498 rc = r820t_write_reg(priv, 0x1b, range->tf_c); 499 if (rc < 0) 500 return rc; 501 502 /* XTAL CAP & Drive */ 503 switch (priv->xtal_cap_sel) { 504 case XTAL_LOW_CAP_30P: 505 case XTAL_LOW_CAP_20P: 506 val = range->xtal_cap20p | 0x08; 507 break; 508 case XTAL_LOW_CAP_10P: 509 val = range->xtal_cap10p | 0x08; 510 break; 511 case XTAL_HIGH_CAP_0P: 512 val = range->xtal_cap0p | 0x00; 513 break; 514 default: 515 case XTAL_LOW_CAP_0P: 516 val = range->xtal_cap0p | 0x08; 517 break; 518 } 519 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b); 520 if (rc < 0) 521 return rc; 522 523 if (priv->imr_done) { 524 reg08 = priv->imr_data[range->imr_mem].gain_x; 525 reg09 = priv->imr_data[range->imr_mem].phase_y; 526 } else { 527 reg08 = 0; 528 reg09 = 0; 529 } 530 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f); 531 if (rc < 0) 532 return rc; 533 534 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f); 535 536 return rc; 537 } 538 539 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type, 540 u32 freq) 541 { 542 u32 vco_freq; 543 int rc, i; 544 unsigned sleep_time = 10000; 545 u32 vco_fra; /* VCO contribution by SDM (kHz) */ 546 u32 vco_min = 1770000; 547 u32 vco_max = vco_min * 2; 548 u32 pll_ref; 549 u16 n_sdm = 2; 550 u16 sdm = 0; 551 u8 mix_div = 2; 552 u8 div_buf = 0; 553 u8 div_num = 0; 554 u8 refdiv2 = 0; 555 u8 ni, si, nint, vco_fine_tune, val; 556 u8 data[5]; 557 558 /* Frequency in kHz */ 559 freq = freq / 1000; 560 pll_ref = priv->cfg->xtal / 1000; 561 562 #if 0 563 /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */ 564 if ((priv->cfg->rafael_chip == CHIP_R620D) || 565 (priv->cfg->rafael_chip == CHIP_R828D) || 566 (priv->cfg->rafael_chip == CHIP_R828)) { 567 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */ 568 if (type != V4L2_TUNER_DIGITAL_TV) { 569 pll_ref /= 2; 570 refdiv2 = 0x10; 571 sleep_time = 20000; 572 } 573 } else { 574 if (priv->cfg->xtal > 24000000) { 575 pll_ref /= 2; 576 refdiv2 = 0x10; 577 } 578 } 579 #endif 580 581 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10); 582 if (rc < 0) 583 return rc; 584 585 /* set pll autotune = 128kHz */ 586 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); 587 if (rc < 0) 588 return rc; 589 590 /* set VCO current = 100 */ 591 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0); 592 if (rc < 0) 593 return rc; 594 595 /* Calculate divider */ 596 while (mix_div <= 64) { 597 if (((freq * mix_div) >= vco_min) && 598 ((freq * mix_div) < vco_max)) { 599 div_buf = mix_div; 600 while (div_buf > 2) { 601 div_buf = div_buf >> 1; 602 div_num++; 603 } 604 break; 605 } 606 mix_div = mix_div << 1; 607 } 608 609 rc = r820t_read(priv, 0x00, data, sizeof(data)); 610 if (rc < 0) 611 return rc; 612 613 vco_fine_tune = (data[4] & 0x30) >> 4; 614 615 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n", 616 mix_div, div_num, vco_fine_tune); 617 618 /* 619 * XXX: R828D/16MHz seems to have always vco_fine_tune=1. 620 * Due to that, this calculation goes wrong. 621 */ 622 if (priv->cfg->rafael_chip != CHIP_R828D) { 623 if (vco_fine_tune > VCO_POWER_REF) 624 div_num = div_num - 1; 625 else if (vco_fine_tune < VCO_POWER_REF) 626 div_num = div_num + 1; 627 } 628 629 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0); 630 if (rc < 0) 631 return rc; 632 633 vco_freq = freq * mix_div; 634 nint = vco_freq / (2 * pll_ref); 635 vco_fra = vco_freq - 2 * pll_ref * nint; 636 637 /* boundary spur prevention */ 638 if (vco_fra < pll_ref / 64) { 639 vco_fra = 0; 640 } else if (vco_fra > pll_ref * 127 / 64) { 641 vco_fra = 0; 642 nint++; 643 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) { 644 vco_fra = pll_ref * 127 / 128; 645 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) { 646 vco_fra = pll_ref * 129 / 128; 647 } 648 649 ni = (nint - 13) / 4; 650 si = nint - 4 * ni - 13; 651 652 rc = r820t_write_reg(priv, 0x14, ni + (si << 6)); 653 if (rc < 0) 654 return rc; 655 656 /* pw_sdm */ 657 if (!vco_fra) 658 val = 0x08; 659 else 660 val = 0x00; 661 662 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08); 663 if (rc < 0) 664 return rc; 665 666 /* sdm calculator */ 667 while (vco_fra > 1) { 668 if (vco_fra > (2 * pll_ref / n_sdm)) { 669 sdm = sdm + 32768 / (n_sdm / 2); 670 vco_fra = vco_fra - 2 * pll_ref / n_sdm; 671 if (n_sdm >= 0x8000) 672 break; 673 } 674 n_sdm = n_sdm << 1; 675 } 676 677 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n", 678 freq, pll_ref, refdiv2 ? " / 2" : "", sdm); 679 680 rc = r820t_write_reg(priv, 0x16, sdm >> 8); 681 if (rc < 0) 682 return rc; 683 rc = r820t_write_reg(priv, 0x15, sdm & 0xff); 684 if (rc < 0) 685 return rc; 686 687 for (i = 0; i < 2; i++) { 688 usleep_range(sleep_time, sleep_time + 1000); 689 690 /* Check if PLL has locked */ 691 rc = r820t_read(priv, 0x00, data, 3); 692 if (rc < 0) 693 return rc; 694 if (data[2] & 0x40) 695 break; 696 697 if (!i) { 698 /* Didn't lock. Increase VCO current */ 699 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0); 700 if (rc < 0) 701 return rc; 702 } 703 } 704 705 if (!(data[2] & 0x40)) { 706 priv->has_lock = false; 707 return 0; 708 } 709 710 priv->has_lock = true; 711 tuner_dbg("tuner has lock at frequency %d kHz\n", freq); 712 713 /* set pll autotune = 8kHz */ 714 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08); 715 716 return rc; 717 } 718 719 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq, 720 enum v4l2_tuner_type type, 721 v4l2_std_id std, 722 u32 delsys) 723 { 724 int rc; 725 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l; 726 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur; 727 728 tuner_dbg("adjusting tuner parameters for the standard\n"); 729 730 switch (delsys) { 731 case SYS_DVBT: 732 if ((freq == 506000000) || (freq == 666000000) || 733 (freq == 818000000)) { 734 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */ 735 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 736 cp_cur = 0x28; /* 101, 0.2 */ 737 div_buf_cur = 0x20; /* 10, 200u */ 738 } else { 739 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 740 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 741 cp_cur = 0x38; /* 111, auto */ 742 div_buf_cur = 0x30; /* 11, 150u */ 743 } 744 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 745 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 746 air_cable1_in = 0x00; 747 cable2_in = 0x00; 748 pre_dect = 0x40; 749 lna_discharge = 14; 750 filter_cur = 0x40; /* 10, low */ 751 break; 752 case SYS_DVBT2: 753 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 754 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 755 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 756 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 757 air_cable1_in = 0x00; 758 cable2_in = 0x00; 759 pre_dect = 0x40; 760 lna_discharge = 14; 761 cp_cur = 0x38; /* 111, auto */ 762 div_buf_cur = 0x30; /* 11, 150u */ 763 filter_cur = 0x40; /* 10, low */ 764 break; 765 case SYS_ISDBT: 766 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 767 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 768 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */ 769 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 770 air_cable1_in = 0x00; 771 cable2_in = 0x00; 772 pre_dect = 0x40; 773 lna_discharge = 14; 774 cp_cur = 0x38; /* 111, auto */ 775 div_buf_cur = 0x30; /* 11, 150u */ 776 filter_cur = 0x40; /* 10, low */ 777 break; 778 default: /* DVB-T 8M */ 779 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 780 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 781 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 782 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 783 air_cable1_in = 0x00; 784 cable2_in = 0x00; 785 pre_dect = 0x40; 786 lna_discharge = 14; 787 cp_cur = 0x38; /* 111, auto */ 788 div_buf_cur = 0x30; /* 11, 150u */ 789 filter_cur = 0x40; /* 10, low */ 790 break; 791 } 792 793 if (priv->cfg->use_diplexer && 794 ((priv->cfg->rafael_chip == CHIP_R820T) || 795 (priv->cfg->rafael_chip == CHIP_R828S) || 796 (priv->cfg->rafael_chip == CHIP_R820C))) { 797 if (freq > DIP_FREQ) 798 air_cable1_in = 0x00; 799 else 800 air_cable1_in = 0x60; 801 cable2_in = 0x00; 802 } 803 804 805 if (priv->cfg->use_predetect) { 806 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40); 807 if (rc < 0) 808 return rc; 809 } 810 811 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7); 812 if (rc < 0) 813 return rc; 814 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8); 815 if (rc < 0) 816 return rc; 817 rc = r820t_write_reg(priv, 0x0d, lna_vth_l); 818 if (rc < 0) 819 return rc; 820 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l); 821 if (rc < 0) 822 return rc; 823 824 /* Air-IN only for Astrometa */ 825 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60); 826 if (rc < 0) 827 return rc; 828 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08); 829 if (rc < 0) 830 return rc; 831 832 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38); 833 if (rc < 0) 834 return rc; 835 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30); 836 if (rc < 0) 837 return rc; 838 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60); 839 if (rc < 0) 840 return rc; 841 /* 842 * Original driver initializes regs 0x05 and 0x06 with the 843 * same value again on this point. Probably, it is just an 844 * error there 845 */ 846 847 /* 848 * Set LNA 849 */ 850 851 tuner_dbg("adjusting LNA parameters\n"); 852 if (type != V4L2_TUNER_ANALOG_TV) { 853 /* LNA TOP: lowest */ 854 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38); 855 if (rc < 0) 856 return rc; 857 858 /* 0: normal mode */ 859 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04); 860 if (rc < 0) 861 return rc; 862 863 /* 0: PRE_DECT off */ 864 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); 865 if (rc < 0) 866 return rc; 867 868 /* agc clk 250hz */ 869 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30); 870 if (rc < 0) 871 return rc; 872 873 msleep(250); 874 875 /* write LNA TOP = 3 */ 876 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38); 877 if (rc < 0) 878 return rc; 879 880 /* 881 * write discharge mode 882 * FIXME: IMHO, the mask here is wrong, but it matches 883 * what's there at the original driver 884 */ 885 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); 886 if (rc < 0) 887 return rc; 888 889 /* LNA discharge current */ 890 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); 891 if (rc < 0) 892 return rc; 893 894 /* agc clk 60hz */ 895 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30); 896 if (rc < 0) 897 return rc; 898 } else { 899 /* PRE_DECT off */ 900 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); 901 if (rc < 0) 902 return rc; 903 904 /* write LNA TOP */ 905 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38); 906 if (rc < 0) 907 return rc; 908 909 /* 910 * write discharge mode 911 * FIXME: IMHO, the mask here is wrong, but it matches 912 * what's there at the original driver 913 */ 914 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); 915 if (rc < 0) 916 return rc; 917 918 /* LNA discharge current */ 919 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); 920 if (rc < 0) 921 return rc; 922 923 /* agc clk 1Khz, external det1 cap 1u */ 924 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30); 925 if (rc < 0) 926 return rc; 927 928 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04); 929 if (rc < 0) 930 return rc; 931 } 932 return 0; 933 } 934 935 static int r820t_set_tv_standard(struct r820t_priv *priv, 936 unsigned bw, 937 enum v4l2_tuner_type type, 938 v4l2_std_id std, u32 delsys) 939 940 { 941 int rc, i; 942 u32 if_khz, filt_cal_lo; 943 u8 data[5], val; 944 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through; 945 u8 lt_att, flt_ext_widest, polyfil_cur; 946 bool need_calibration; 947 948 tuner_dbg("selecting the delivery system\n"); 949 950 if (delsys == SYS_ISDBT) { 951 if_khz = 4063; 952 filt_cal_lo = 59000; 953 filt_gain = 0x10; /* +3db, 6mhz on */ 954 img_r = 0x00; /* image negative */ 955 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 956 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */ 957 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */ 958 loop_through = 0x00; /* r5[7], lt on */ 959 lt_att = 0x00; /* r31[7], lt att enable */ 960 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 961 polyfil_cur = 0x60; /* r25[6:5]:min */ 962 } else if (delsys == SYS_DVBC_ANNEX_A) { 963 if_khz = 5070; 964 filt_cal_lo = 73500; 965 filt_gain = 0x10; /* +3db, 6mhz on */ 966 img_r = 0x00; /* image negative */ 967 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 968 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ 969 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 970 loop_through = 0x00; /* r5[7], lt on */ 971 lt_att = 0x00; /* r31[7], lt att enable */ 972 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 973 polyfil_cur = 0x60; /* r25[6:5]:min */ 974 } else { 975 if (bw <= 6) { 976 if_khz = 3570; 977 filt_cal_lo = 56000; /* 52000->56000 */ 978 filt_gain = 0x10; /* +3db, 6mhz on */ 979 img_r = 0x00; /* image negative */ 980 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 981 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */ 982 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 983 loop_through = 0x00; /* r5[7], lt on */ 984 lt_att = 0x00; /* r31[7], lt att enable */ 985 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 986 polyfil_cur = 0x60; /* r25[6:5]:min */ 987 } else if (bw == 7) { 988 #if 0 989 /* 990 * There are two 7 MHz tables defined on the original 991 * driver, but just the second one seems to be visible 992 * by rtl2832. Keep this one here commented, as it 993 * might be needed in the future 994 */ 995 996 if_khz = 4070; 997 filt_cal_lo = 60000; 998 filt_gain = 0x10; /* +3db, 6mhz on */ 999 img_r = 0x00; /* image negative */ 1000 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1001 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */ 1002 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1003 loop_through = 0x00; /* r5[7], lt on */ 1004 lt_att = 0x00; /* r31[7], lt att enable */ 1005 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1006 polyfil_cur = 0x60; /* r25[6:5]:min */ 1007 #endif 1008 /* 7 MHz, second table */ 1009 if_khz = 4570; 1010 filt_cal_lo = 63000; 1011 filt_gain = 0x10; /* +3db, 6mhz on */ 1012 img_r = 0x00; /* image negative */ 1013 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1014 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */ 1015 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1016 loop_through = 0x00; /* r5[7], lt on */ 1017 lt_att = 0x00; /* r31[7], lt att enable */ 1018 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1019 polyfil_cur = 0x60; /* r25[6:5]:min */ 1020 } else { 1021 if_khz = 4570; 1022 filt_cal_lo = 68500; 1023 filt_gain = 0x10; /* +3db, 6mhz on */ 1024 img_r = 0x00; /* image negative */ 1025 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1026 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ 1027 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1028 loop_through = 0x00; /* r5[7], lt on */ 1029 lt_att = 0x00; /* r31[7], lt att enable */ 1030 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1031 polyfil_cur = 0x60; /* r25[6:5]:min */ 1032 } 1033 } 1034 1035 /* Initialize the shadow registers */ 1036 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1037 1038 /* Init Flag & Xtal_check Result */ 1039 if (priv->imr_done) 1040 val = 1 | priv->xtal_cap_sel << 1; 1041 else 1042 val = 0; 1043 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f); 1044 if (rc < 0) 1045 return rc; 1046 1047 /* version */ 1048 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f); 1049 if (rc < 0) 1050 return rc; 1051 1052 /* for LT Gain test */ 1053 if (type != V4L2_TUNER_ANALOG_TV) { 1054 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38); 1055 if (rc < 0) 1056 return rc; 1057 usleep_range(1000, 2000); 1058 } 1059 priv->int_freq = if_khz * 1000; 1060 1061 /* Check if standard changed. If so, filter calibration is needed */ 1062 if (type != priv->type) 1063 need_calibration = true; 1064 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std)) 1065 need_calibration = true; 1066 else if ((type == V4L2_TUNER_DIGITAL_TV) && 1067 ((delsys != priv->delsys) || bw != priv->bw)) 1068 need_calibration = true; 1069 else 1070 need_calibration = false; 1071 1072 if (need_calibration) { 1073 tuner_dbg("calibrating the tuner\n"); 1074 for (i = 0; i < 2; i++) { 1075 /* Set filt_cap */ 1076 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60); 1077 if (rc < 0) 1078 return rc; 1079 1080 /* set cali clk =on */ 1081 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04); 1082 if (rc < 0) 1083 return rc; 1084 1085 /* X'tal cap 0pF for PLL */ 1086 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03); 1087 if (rc < 0) 1088 return rc; 1089 1090 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000); 1091 if (rc < 0 || !priv->has_lock) 1092 return rc; 1093 1094 /* Start Trigger */ 1095 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10); 1096 if (rc < 0) 1097 return rc; 1098 1099 usleep_range(1000, 2000); 1100 1101 /* Stop Trigger */ 1102 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10); 1103 if (rc < 0) 1104 return rc; 1105 1106 /* set cali clk =off */ 1107 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04); 1108 if (rc < 0) 1109 return rc; 1110 1111 /* Check if calibration worked */ 1112 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1113 if (rc < 0) 1114 return rc; 1115 1116 priv->fil_cal_code = data[4] & 0x0f; 1117 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f) 1118 break; 1119 } 1120 /* narrowest */ 1121 if (priv->fil_cal_code == 0x0f) 1122 priv->fil_cal_code = 0; 1123 } 1124 1125 rc = r820t_write_reg_mask(priv, 0x0a, 1126 filt_q | priv->fil_cal_code, 0x1f); 1127 if (rc < 0) 1128 return rc; 1129 1130 /* Set BW, Filter_gain, & HP corner */ 1131 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef); 1132 if (rc < 0) 1133 return rc; 1134 1135 1136 /* Set Img_R */ 1137 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80); 1138 if (rc < 0) 1139 return rc; 1140 1141 /* Set filt_3dB, V6MHz */ 1142 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30); 1143 if (rc < 0) 1144 return rc; 1145 1146 /* channel filter extension */ 1147 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60); 1148 if (rc < 0) 1149 return rc; 1150 1151 /* Loop through */ 1152 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80); 1153 if (rc < 0) 1154 return rc; 1155 1156 /* Loop through attenuation */ 1157 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80); 1158 if (rc < 0) 1159 return rc; 1160 1161 /* filter extension widest */ 1162 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80); 1163 if (rc < 0) 1164 return rc; 1165 1166 /* RF poly filter current */ 1167 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60); 1168 if (rc < 0) 1169 return rc; 1170 1171 /* Store current standard. If it changes, re-calibrate the tuner */ 1172 priv->delsys = delsys; 1173 priv->type = type; 1174 priv->std = std; 1175 priv->bw = bw; 1176 1177 return 0; 1178 } 1179 1180 static int r820t_read_gain(struct r820t_priv *priv) 1181 { 1182 u8 data[4]; 1183 int rc; 1184 1185 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1186 if (rc < 0) 1187 return rc; 1188 1189 return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4); 1190 } 1191 1192 #if 0 1193 /* FIXME: This routine requires more testing */ 1194 static int r820t_set_gain_mode(struct r820t_priv *priv, 1195 bool set_manual_gain, 1196 int gain) 1197 { 1198 int rc; 1199 1200 if (set_manual_gain) { 1201 int i, total_gain = 0; 1202 uint8_t mix_index = 0, lna_index = 0; 1203 u8 data[4]; 1204 1205 /* LNA auto off */ 1206 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10); 1207 if (rc < 0) 1208 return rc; 1209 1210 /* Mixer auto off */ 1211 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); 1212 if (rc < 0) 1213 return rc; 1214 1215 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1216 if (rc < 0) 1217 return rc; 1218 1219 /* set fixed VGA gain for now (16.3 dB) */ 1220 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f); 1221 if (rc < 0) 1222 return rc; 1223 1224 for (i = 0; i < 15; i++) { 1225 if (total_gain >= gain) 1226 break; 1227 1228 total_gain += r820t_lna_gain_steps[++lna_index]; 1229 1230 if (total_gain >= gain) 1231 break; 1232 1233 total_gain += r820t_mixer_gain_steps[++mix_index]; 1234 } 1235 1236 /* set LNA gain */ 1237 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f); 1238 if (rc < 0) 1239 return rc; 1240 1241 /* set Mixer gain */ 1242 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f); 1243 if (rc < 0) 1244 return rc; 1245 } else { 1246 /* LNA */ 1247 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10); 1248 if (rc < 0) 1249 return rc; 1250 1251 /* Mixer */ 1252 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10); 1253 if (rc < 0) 1254 return rc; 1255 1256 /* set fixed VGA gain for now (26.5 dB) */ 1257 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); 1258 if (rc < 0) 1259 return rc; 1260 } 1261 1262 return 0; 1263 } 1264 #endif 1265 1266 static int generic_set_freq(struct dvb_frontend *fe, 1267 u32 freq /* in HZ */, 1268 unsigned bw, 1269 enum v4l2_tuner_type type, 1270 v4l2_std_id std, u32 delsys) 1271 { 1272 struct r820t_priv *priv = fe->tuner_priv; 1273 int rc = -EINVAL; 1274 u32 lo_freq; 1275 1276 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n", 1277 freq / 1000, bw); 1278 1279 rc = r820t_set_tv_standard(priv, bw, type, std, delsys); 1280 if (rc < 0) 1281 goto err; 1282 1283 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC)) 1284 lo_freq = freq - priv->int_freq; 1285 else 1286 lo_freq = freq + priv->int_freq; 1287 1288 rc = r820t_set_mux(priv, lo_freq); 1289 if (rc < 0) 1290 goto err; 1291 1292 rc = r820t_set_pll(priv, type, lo_freq); 1293 if (rc < 0 || !priv->has_lock) 1294 goto err; 1295 1296 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys); 1297 if (rc < 0) 1298 goto err; 1299 1300 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n", 1301 __func__, freq, r820t_read_gain(priv)); 1302 1303 err: 1304 1305 if (rc < 0) 1306 tuner_dbg("%s: failed=%d\n", __func__, rc); 1307 return rc; 1308 } 1309 1310 /* 1311 * r820t standby logic 1312 */ 1313 1314 static int r820t_standby(struct r820t_priv *priv) 1315 { 1316 int rc; 1317 1318 /* If device was not initialized yet, don't need to standby */ 1319 if (!priv->init_done) 1320 return 0; 1321 1322 rc = r820t_write_reg(priv, 0x06, 0xb1); 1323 if (rc < 0) 1324 return rc; 1325 rc = r820t_write_reg(priv, 0x05, 0x03); 1326 if (rc < 0) 1327 return rc; 1328 rc = r820t_write_reg(priv, 0x07, 0x3a); 1329 if (rc < 0) 1330 return rc; 1331 rc = r820t_write_reg(priv, 0x08, 0x40); 1332 if (rc < 0) 1333 return rc; 1334 rc = r820t_write_reg(priv, 0x09, 0xc0); 1335 if (rc < 0) 1336 return rc; 1337 rc = r820t_write_reg(priv, 0x0a, 0x36); 1338 if (rc < 0) 1339 return rc; 1340 rc = r820t_write_reg(priv, 0x0c, 0x35); 1341 if (rc < 0) 1342 return rc; 1343 rc = r820t_write_reg(priv, 0x0f, 0x68); 1344 if (rc < 0) 1345 return rc; 1346 rc = r820t_write_reg(priv, 0x11, 0x03); 1347 if (rc < 0) 1348 return rc; 1349 rc = r820t_write_reg(priv, 0x17, 0xf4); 1350 if (rc < 0) 1351 return rc; 1352 rc = r820t_write_reg(priv, 0x19, 0x0c); 1353 1354 /* Force initial calibration */ 1355 priv->type = -1; 1356 1357 return rc; 1358 } 1359 1360 /* 1361 * r820t device init logic 1362 */ 1363 1364 static int r820t_xtal_check(struct r820t_priv *priv) 1365 { 1366 int rc, i; 1367 u8 data[3], val; 1368 1369 /* Initialize the shadow registers */ 1370 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1371 1372 /* cap 30pF & Drive Low */ 1373 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b); 1374 if (rc < 0) 1375 return rc; 1376 1377 /* set pll autotune = 128kHz */ 1378 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); 1379 if (rc < 0) 1380 return rc; 1381 1382 /* set manual initial reg = 111111; */ 1383 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f); 1384 if (rc < 0) 1385 return rc; 1386 1387 /* set auto */ 1388 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40); 1389 if (rc < 0) 1390 return rc; 1391 1392 /* Try several xtal capacitor alternatives */ 1393 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) { 1394 rc = r820t_write_reg_mask(priv, 0x10, 1395 r820t_xtal_capacitor[i][0], 0x1b); 1396 if (rc < 0) 1397 return rc; 1398 1399 usleep_range(5000, 6000); 1400 1401 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1402 if (rc < 0) 1403 return rc; 1404 if (!(data[2] & 0x40)) 1405 continue; 1406 1407 val = data[2] & 0x3f; 1408 1409 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23)) 1410 break; 1411 1412 if (val != 0x3f) 1413 break; 1414 } 1415 1416 if (i == ARRAY_SIZE(r820t_xtal_capacitor)) 1417 return -EINVAL; 1418 1419 return r820t_xtal_capacitor[i][1]; 1420 } 1421 1422 static int r820t_imr_prepare(struct r820t_priv *priv) 1423 { 1424 int rc; 1425 1426 /* Initialize the shadow registers */ 1427 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1428 1429 /* lna off (air-in off) */ 1430 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20); 1431 if (rc < 0) 1432 return rc; 1433 1434 /* mixer gain mode = manual */ 1435 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); 1436 if (rc < 0) 1437 return rc; 1438 1439 /* filter corner = lowest */ 1440 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f); 1441 if (rc < 0) 1442 return rc; 1443 1444 /* filter bw=+2cap, hp=5M */ 1445 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f); 1446 if (rc < 0) 1447 return rc; 1448 1449 /* adc=on, vga code mode, gain = 26.5dB */ 1450 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); 1451 if (rc < 0) 1452 return rc; 1453 1454 /* ring clk = on */ 1455 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08); 1456 if (rc < 0) 1457 return rc; 1458 1459 /* ring power = on */ 1460 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10); 1461 if (rc < 0) 1462 return rc; 1463 1464 /* from ring = ring pll in */ 1465 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02); 1466 if (rc < 0) 1467 return rc; 1468 1469 /* sw_pdect = det3 */ 1470 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80); 1471 if (rc < 0) 1472 return rc; 1473 1474 /* Set filt_3dB */ 1475 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20); 1476 1477 return rc; 1478 } 1479 1480 static int r820t_multi_read(struct r820t_priv *priv) 1481 { 1482 int rc, i; 1483 u16 sum = 0; 1484 u8 data[2], min = 255, max = 0; 1485 1486 usleep_range(5000, 6000); 1487 1488 for (i = 0; i < 6; i++) { 1489 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1490 if (rc < 0) 1491 return rc; 1492 1493 sum += data[1]; 1494 1495 if (data[1] < min) 1496 min = data[1]; 1497 1498 if (data[1] > max) 1499 max = data[1]; 1500 } 1501 rc = sum - max - min; 1502 1503 return rc; 1504 } 1505 1506 static int r820t_imr_cross(struct r820t_priv *priv, 1507 struct r820t_sect_type iq_point[3], 1508 u8 *x_direct) 1509 { 1510 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */ 1511 struct r820t_sect_type tmp; 1512 int i, rc; 1513 u8 reg08, reg09; 1514 1515 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0; 1516 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0; 1517 1518 tmp.gain_x = 0; 1519 tmp.phase_y = 0; 1520 tmp.value = 255; 1521 1522 for (i = 0; i < 5; i++) { 1523 switch (i) { 1524 case 0: 1525 cross[i].gain_x = reg08; 1526 cross[i].phase_y = reg09; 1527 break; 1528 case 1: 1529 cross[i].gain_x = reg08; /* 0 */ 1530 cross[i].phase_y = reg09 + 1; /* Q-1 */ 1531 break; 1532 case 2: 1533 cross[i].gain_x = reg08; /* 0 */ 1534 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */ 1535 break; 1536 case 3: 1537 cross[i].gain_x = reg08 + 1; /* Q-1 */ 1538 cross[i].phase_y = reg09; 1539 break; 1540 default: 1541 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */ 1542 cross[i].phase_y = reg09; 1543 } 1544 1545 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x); 1546 if (rc < 0) 1547 return rc; 1548 1549 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y); 1550 if (rc < 0) 1551 return rc; 1552 1553 rc = r820t_multi_read(priv); 1554 if (rc < 0) 1555 return rc; 1556 1557 cross[i].value = rc; 1558 1559 if (cross[i].value < tmp.value) 1560 tmp = cross[i]; 1561 } 1562 1563 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */ 1564 *x_direct = 0; 1565 1566 iq_point[0] = cross[0]; 1567 iq_point[1] = cross[1]; 1568 iq_point[2] = cross[2]; 1569 } else { /* (0,0) or x-direction */ 1570 *x_direct = 1; 1571 1572 iq_point[0] = cross[0]; 1573 iq_point[1] = cross[3]; 1574 iq_point[2] = cross[4]; 1575 } 1576 return 0; 1577 } 1578 1579 static void r820t_compre_cor(struct r820t_sect_type iq[3]) 1580 { 1581 int i; 1582 1583 for (i = 3; i > 0; i--) { 1584 if (iq[0].value > iq[i - 1].value) 1585 swap(iq[0], iq[i - 1]); 1586 } 1587 } 1588 1589 static int r820t_compre_step(struct r820t_priv *priv, 1590 struct r820t_sect_type iq[3], u8 reg) 1591 { 1592 int rc; 1593 struct r820t_sect_type tmp; 1594 1595 /* 1596 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare 1597 * with min value: 1598 * new < min => update to min and continue 1599 * new > min => Exit 1600 */ 1601 1602 /* min value already saved in iq[0] */ 1603 tmp.phase_y = iq[0].phase_y; 1604 tmp.gain_x = iq[0].gain_x; 1605 1606 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) && 1607 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) { 1608 if (reg == 0x08) 1609 tmp.gain_x++; 1610 else 1611 tmp.phase_y++; 1612 1613 rc = r820t_write_reg(priv, 0x08, tmp.gain_x); 1614 if (rc < 0) 1615 return rc; 1616 1617 rc = r820t_write_reg(priv, 0x09, tmp.phase_y); 1618 if (rc < 0) 1619 return rc; 1620 1621 rc = r820t_multi_read(priv); 1622 if (rc < 0) 1623 return rc; 1624 tmp.value = rc; 1625 1626 if (tmp.value <= iq[0].value) { 1627 iq[0].gain_x = tmp.gain_x; 1628 iq[0].phase_y = tmp.phase_y; 1629 iq[0].value = tmp.value; 1630 } else { 1631 return 0; 1632 } 1633 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int r820t_iq_tree(struct r820t_priv *priv, 1640 struct r820t_sect_type iq[3], 1641 u8 fix_val, u8 var_val, u8 fix_reg) 1642 { 1643 int rc, i; 1644 u8 tmp, var_reg; 1645 1646 /* 1647 * record IMC results by input gain/phase location then adjust 1648 * gain or phase positive 1 step and negtive 1 step, 1649 * both record results 1650 */ 1651 1652 if (fix_reg == 0x08) 1653 var_reg = 0x09; 1654 else 1655 var_reg = 0x08; 1656 1657 for (i = 0; i < 3; i++) { 1658 rc = r820t_write_reg(priv, fix_reg, fix_val); 1659 if (rc < 0) 1660 return rc; 1661 1662 rc = r820t_write_reg(priv, var_reg, var_val); 1663 if (rc < 0) 1664 return rc; 1665 1666 rc = r820t_multi_read(priv); 1667 if (rc < 0) 1668 return rc; 1669 iq[i].value = rc; 1670 1671 if (fix_reg == 0x08) { 1672 iq[i].gain_x = fix_val; 1673 iq[i].phase_y = var_val; 1674 } else { 1675 iq[i].phase_y = fix_val; 1676 iq[i].gain_x = var_val; 1677 } 1678 1679 if (i == 0) { /* try right-side point */ 1680 var_val++; 1681 } else if (i == 1) { /* try left-side point */ 1682 /* if absolute location is 1, change I/Q direction */ 1683 if ((var_val & 0x1f) < 0x02) { 1684 tmp = 2 - (var_val & 0x1f); 1685 1686 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */ 1687 if (var_val & 0x20) { 1688 var_val &= 0xc0; 1689 var_val |= tmp; 1690 } else { 1691 var_val |= 0x20 | tmp; 1692 } 1693 } else { 1694 var_val -= 2; 1695 } 1696 } 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int r820t_section(struct r820t_priv *priv, 1703 struct r820t_sect_type *iq_point) 1704 { 1705 int rc; 1706 struct r820t_sect_type compare_iq[3], compare_bet[3]; 1707 1708 /* Try X-1 column and save min result to compare_bet[0] */ 1709 if (!(iq_point->gain_x & 0x1f)) 1710 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */ 1711 else 1712 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */ 1713 compare_iq[0].phase_y = iq_point->phase_y; 1714 1715 /* y-direction */ 1716 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1717 compare_iq[0].phase_y, 0x08); 1718 if (rc < 0) 1719 return rc; 1720 1721 r820t_compre_cor(compare_iq); 1722 1723 compare_bet[0] = compare_iq[0]; 1724 1725 /* Try X column and save min result to compare_bet[1] */ 1726 compare_iq[0].gain_x = iq_point->gain_x; 1727 compare_iq[0].phase_y = iq_point->phase_y; 1728 1729 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1730 compare_iq[0].phase_y, 0x08); 1731 if (rc < 0) 1732 return rc; 1733 1734 r820t_compre_cor(compare_iq); 1735 1736 compare_bet[1] = compare_iq[0]; 1737 1738 /* Try X+1 column and save min result to compare_bet[2] */ 1739 if ((iq_point->gain_x & 0x1f) == 0x00) 1740 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */ 1741 else 1742 compare_iq[0].gain_x = iq_point->gain_x + 1; 1743 compare_iq[0].phase_y = iq_point->phase_y; 1744 1745 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1746 compare_iq[0].phase_y, 0x08); 1747 if (rc < 0) 1748 return rc; 1749 1750 r820t_compre_cor(compare_iq); 1751 1752 compare_bet[2] = compare_iq[0]; 1753 1754 r820t_compre_cor(compare_bet); 1755 1756 *iq_point = compare_bet[0]; 1757 1758 return 0; 1759 } 1760 1761 static int r820t_vga_adjust(struct r820t_priv *priv) 1762 { 1763 int rc; 1764 u8 vga_count; 1765 1766 /* increase vga power to let image significant */ 1767 for (vga_count = 12; vga_count < 16; vga_count++) { 1768 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f); 1769 if (rc < 0) 1770 return rc; 1771 1772 usleep_range(10000, 11000); 1773 1774 rc = r820t_multi_read(priv); 1775 if (rc < 0) 1776 return rc; 1777 1778 if (rc > 40 * 4) 1779 break; 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) 1786 { 1787 struct r820t_sect_type compare_iq[3]; 1788 int rc; 1789 u8 x_direction = 0; /* 1:x, 0:y */ 1790 u8 dir_reg, other_reg; 1791 1792 r820t_vga_adjust(priv); 1793 1794 rc = r820t_imr_cross(priv, compare_iq, &x_direction); 1795 if (rc < 0) 1796 return rc; 1797 1798 if (x_direction == 1) { 1799 dir_reg = 0x08; 1800 other_reg = 0x09; 1801 } else { 1802 dir_reg = 0x09; 1803 other_reg = 0x08; 1804 } 1805 1806 /* compare and find min of 3 points. determine i/q direction */ 1807 r820t_compre_cor(compare_iq); 1808 1809 /* increase step to find min value of this direction */ 1810 rc = r820t_compre_step(priv, compare_iq, dir_reg); 1811 if (rc < 0) 1812 return rc; 1813 1814 /* the other direction */ 1815 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1816 compare_iq[0].phase_y, dir_reg); 1817 if (rc < 0) 1818 return rc; 1819 1820 /* compare and find min of 3 points. determine i/q direction */ 1821 r820t_compre_cor(compare_iq); 1822 1823 /* increase step to find min value on this direction */ 1824 rc = r820t_compre_step(priv, compare_iq, other_reg); 1825 if (rc < 0) 1826 return rc; 1827 1828 /* check 3 points again */ 1829 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1830 compare_iq[0].phase_y, other_reg); 1831 if (rc < 0) 1832 return rc; 1833 1834 r820t_compre_cor(compare_iq); 1835 1836 /* section-9 check */ 1837 rc = r820t_section(priv, compare_iq); 1838 1839 *iq_pont = compare_iq[0]; 1840 1841 /* reset gain/phase control setting */ 1842 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f); 1843 if (rc < 0) 1844 return rc; 1845 1846 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f); 1847 1848 return rc; 1849 } 1850 1851 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) 1852 { 1853 int rc; 1854 1855 r820t_vga_adjust(priv); 1856 1857 /* 1858 * search surrounding points from previous point 1859 * try (x-1), (x), (x+1) columns, and find min IMR result point 1860 */ 1861 rc = r820t_section(priv, iq_pont); 1862 if (rc < 0) 1863 return rc; 1864 1865 return 0; 1866 } 1867 1868 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag) 1869 { 1870 struct r820t_sect_type imr_point; 1871 int rc; 1872 u32 ring_vco, ring_freq, ring_ref; 1873 u8 n_ring, n; 1874 int reg18, reg19, reg1f; 1875 1876 if (priv->cfg->xtal > 24000000) 1877 ring_ref = priv->cfg->xtal / 2000; 1878 else 1879 ring_ref = priv->cfg->xtal / 1000; 1880 1881 n_ring = 15; 1882 for (n = 0; n < 16; n++) { 1883 if ((16 + n) * 8 * ring_ref >= 3100000) { 1884 n_ring = n; 1885 break; 1886 } 1887 } 1888 1889 reg18 = r820t_read_cache_reg(priv, 0x18); 1890 reg19 = r820t_read_cache_reg(priv, 0x19); 1891 reg1f = r820t_read_cache_reg(priv, 0x1f); 1892 1893 reg18 &= 0xf0; /* set ring[3:0] */ 1894 reg18 |= n_ring; 1895 1896 ring_vco = (16 + n_ring) * 8 * ring_ref; 1897 1898 reg18 &= 0xdf; /* clear ring_se23 */ 1899 reg19 &= 0xfc; /* clear ring_seldiv */ 1900 reg1f &= 0xfc; /* clear ring_att */ 1901 1902 switch (imr_mem) { 1903 case 0: 1904 ring_freq = ring_vco / 48; 1905 reg18 |= 0x20; /* ring_se23 = 1 */ 1906 reg19 |= 0x03; /* ring_seldiv = 3 */ 1907 reg1f |= 0x02; /* ring_att 10 */ 1908 break; 1909 case 1: 1910 ring_freq = ring_vco / 16; 1911 reg18 |= 0x00; /* ring_se23 = 0 */ 1912 reg19 |= 0x02; /* ring_seldiv = 2 */ 1913 reg1f |= 0x00; /* pw_ring 00 */ 1914 break; 1915 case 2: 1916 ring_freq = ring_vco / 8; 1917 reg18 |= 0x00; /* ring_se23 = 0 */ 1918 reg19 |= 0x01; /* ring_seldiv = 1 */ 1919 reg1f |= 0x03; /* pw_ring 11 */ 1920 break; 1921 case 3: 1922 ring_freq = ring_vco / 6; 1923 reg18 |= 0x20; /* ring_se23 = 1 */ 1924 reg19 |= 0x00; /* ring_seldiv = 0 */ 1925 reg1f |= 0x03; /* pw_ring 11 */ 1926 break; 1927 case 4: 1928 ring_freq = ring_vco / 4; 1929 reg18 |= 0x00; /* ring_se23 = 0 */ 1930 reg19 |= 0x00; /* ring_seldiv = 0 */ 1931 reg1f |= 0x01; /* pw_ring 01 */ 1932 break; 1933 default: 1934 ring_freq = ring_vco / 4; 1935 reg18 |= 0x00; /* ring_se23 = 0 */ 1936 reg19 |= 0x00; /* ring_seldiv = 0 */ 1937 reg1f |= 0x01; /* pw_ring 01 */ 1938 break; 1939 } 1940 1941 1942 /* write pw_ring, n_ring, ringdiv2 registers */ 1943 1944 /* n_ring, ring_se23 */ 1945 rc = r820t_write_reg(priv, 0x18, reg18); 1946 if (rc < 0) 1947 return rc; 1948 1949 /* ring_sediv */ 1950 rc = r820t_write_reg(priv, 0x19, reg19); 1951 if (rc < 0) 1952 return rc; 1953 1954 /* pw_ring */ 1955 rc = r820t_write_reg(priv, 0x1f, reg1f); 1956 if (rc < 0) 1957 return rc; 1958 1959 /* mux input freq ~ rf_in freq */ 1960 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000); 1961 if (rc < 0) 1962 return rc; 1963 1964 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV, 1965 (ring_freq - 5300) * 1000); 1966 if (!priv->has_lock) 1967 rc = -EINVAL; 1968 if (rc < 0) 1969 return rc; 1970 1971 if (im_flag) { 1972 rc = r820t_iq(priv, &imr_point); 1973 } else { 1974 imr_point.gain_x = priv->imr_data[3].gain_x; 1975 imr_point.phase_y = priv->imr_data[3].phase_y; 1976 imr_point.value = priv->imr_data[3].value; 1977 1978 rc = r820t_f_imr(priv, &imr_point); 1979 } 1980 if (rc < 0) 1981 return rc; 1982 1983 /* save IMR value */ 1984 switch (imr_mem) { 1985 case 0: 1986 priv->imr_data[0].gain_x = imr_point.gain_x; 1987 priv->imr_data[0].phase_y = imr_point.phase_y; 1988 priv->imr_data[0].value = imr_point.value; 1989 break; 1990 case 1: 1991 priv->imr_data[1].gain_x = imr_point.gain_x; 1992 priv->imr_data[1].phase_y = imr_point.phase_y; 1993 priv->imr_data[1].value = imr_point.value; 1994 break; 1995 case 2: 1996 priv->imr_data[2].gain_x = imr_point.gain_x; 1997 priv->imr_data[2].phase_y = imr_point.phase_y; 1998 priv->imr_data[2].value = imr_point.value; 1999 break; 2000 case 3: 2001 priv->imr_data[3].gain_x = imr_point.gain_x; 2002 priv->imr_data[3].phase_y = imr_point.phase_y; 2003 priv->imr_data[3].value = imr_point.value; 2004 break; 2005 case 4: 2006 priv->imr_data[4].gain_x = imr_point.gain_x; 2007 priv->imr_data[4].phase_y = imr_point.phase_y; 2008 priv->imr_data[4].value = imr_point.value; 2009 break; 2010 default: 2011 priv->imr_data[4].gain_x = imr_point.gain_x; 2012 priv->imr_data[4].phase_y = imr_point.phase_y; 2013 priv->imr_data[4].value = imr_point.value; 2014 break; 2015 } 2016 2017 return 0; 2018 } 2019 2020 static int r820t_imr_callibrate(struct r820t_priv *priv) 2021 { 2022 int rc, i; 2023 int xtal_cap = 0; 2024 2025 if (priv->init_done) 2026 return 0; 2027 2028 /* Detect Xtal capacitance */ 2029 if ((priv->cfg->rafael_chip == CHIP_R820T) || 2030 (priv->cfg->rafael_chip == CHIP_R828S) || 2031 (priv->cfg->rafael_chip == CHIP_R820C)) { 2032 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P; 2033 } else { 2034 /* Initialize registers */ 2035 rc = r820t_write(priv, 0x05, 2036 r820t_init_array, sizeof(r820t_init_array)); 2037 if (rc < 0) 2038 return rc; 2039 for (i = 0; i < 3; i++) { 2040 rc = r820t_xtal_check(priv); 2041 if (rc < 0) 2042 return rc; 2043 if (!i || rc > xtal_cap) 2044 xtal_cap = rc; 2045 } 2046 priv->xtal_cap_sel = xtal_cap; 2047 } 2048 2049 /* 2050 * Disables IMR callibration. That emulates the same behaviour 2051 * as what is done by rtl-sdr userspace library. Useful for testing 2052 */ 2053 if (no_imr_cal) { 2054 priv->init_done = true; 2055 2056 return 0; 2057 } 2058 2059 /* Initialize registers */ 2060 rc = r820t_write(priv, 0x05, 2061 r820t_init_array, sizeof(r820t_init_array)); 2062 if (rc < 0) 2063 return rc; 2064 2065 rc = r820t_imr_prepare(priv); 2066 if (rc < 0) 2067 return rc; 2068 2069 rc = r820t_imr(priv, 3, true); 2070 if (rc < 0) 2071 return rc; 2072 rc = r820t_imr(priv, 1, false); 2073 if (rc < 0) 2074 return rc; 2075 rc = r820t_imr(priv, 0, false); 2076 if (rc < 0) 2077 return rc; 2078 rc = r820t_imr(priv, 2, false); 2079 if (rc < 0) 2080 return rc; 2081 rc = r820t_imr(priv, 4, false); 2082 if (rc < 0) 2083 return rc; 2084 2085 priv->init_done = true; 2086 priv->imr_done = true; 2087 2088 return 0; 2089 } 2090 2091 #if 0 2092 /* Not used, for now */ 2093 static int r820t_gpio(struct r820t_priv *priv, bool enable) 2094 { 2095 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01); 2096 } 2097 #endif 2098 2099 /* 2100 * r820t frontend operations and tuner attach code 2101 * 2102 * All driver locks and i2c control are only in this part of the code 2103 */ 2104 2105 static int r820t_init(struct dvb_frontend *fe) 2106 { 2107 struct r820t_priv *priv = fe->tuner_priv; 2108 int rc; 2109 2110 tuner_dbg("%s:\n", __func__); 2111 2112 mutex_lock(&priv->lock); 2113 if (fe->ops.i2c_gate_ctrl) 2114 fe->ops.i2c_gate_ctrl(fe, 1); 2115 2116 rc = r820t_imr_callibrate(priv); 2117 if (rc < 0) 2118 goto err; 2119 2120 /* Initialize registers */ 2121 rc = r820t_write(priv, 0x05, 2122 r820t_init_array, sizeof(r820t_init_array)); 2123 2124 err: 2125 if (fe->ops.i2c_gate_ctrl) 2126 fe->ops.i2c_gate_ctrl(fe, 0); 2127 mutex_unlock(&priv->lock); 2128 2129 if (rc < 0) 2130 tuner_dbg("%s: failed=%d\n", __func__, rc); 2131 return rc; 2132 } 2133 2134 static int r820t_sleep(struct dvb_frontend *fe) 2135 { 2136 struct r820t_priv *priv = fe->tuner_priv; 2137 int rc; 2138 2139 tuner_dbg("%s:\n", __func__); 2140 2141 mutex_lock(&priv->lock); 2142 if (fe->ops.i2c_gate_ctrl) 2143 fe->ops.i2c_gate_ctrl(fe, 1); 2144 2145 rc = r820t_standby(priv); 2146 2147 if (fe->ops.i2c_gate_ctrl) 2148 fe->ops.i2c_gate_ctrl(fe, 0); 2149 mutex_unlock(&priv->lock); 2150 2151 tuner_dbg("%s: failed=%d\n", __func__, rc); 2152 return rc; 2153 } 2154 2155 static int r820t_set_analog_freq(struct dvb_frontend *fe, 2156 struct analog_parameters *p) 2157 { 2158 struct r820t_priv *priv = fe->tuner_priv; 2159 unsigned bw; 2160 int rc; 2161 2162 tuner_dbg("%s called\n", __func__); 2163 2164 /* if std is not defined, choose one */ 2165 if (!p->std) 2166 p->std = V4L2_STD_MN; 2167 2168 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC)) 2169 bw = 6; 2170 else 2171 bw = 8; 2172 2173 mutex_lock(&priv->lock); 2174 if (fe->ops.i2c_gate_ctrl) 2175 fe->ops.i2c_gate_ctrl(fe, 1); 2176 2177 rc = generic_set_freq(fe, 62500l * p->frequency, bw, 2178 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED); 2179 2180 if (fe->ops.i2c_gate_ctrl) 2181 fe->ops.i2c_gate_ctrl(fe, 0); 2182 mutex_unlock(&priv->lock); 2183 2184 return rc; 2185 } 2186 2187 static int r820t_set_params(struct dvb_frontend *fe) 2188 { 2189 struct r820t_priv *priv = fe->tuner_priv; 2190 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2191 int rc; 2192 unsigned bw; 2193 2194 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", 2195 __func__, c->delivery_system, c->frequency, c->bandwidth_hz); 2196 2197 mutex_lock(&priv->lock); 2198 if (fe->ops.i2c_gate_ctrl) 2199 fe->ops.i2c_gate_ctrl(fe, 1); 2200 2201 bw = (c->bandwidth_hz + 500000) / 1000000; 2202 if (!bw) 2203 bw = 8; 2204 2205 rc = generic_set_freq(fe, c->frequency, bw, 2206 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system); 2207 2208 if (fe->ops.i2c_gate_ctrl) 2209 fe->ops.i2c_gate_ctrl(fe, 0); 2210 mutex_unlock(&priv->lock); 2211 2212 if (rc) 2213 tuner_dbg("%s: failed=%d\n", __func__, rc); 2214 return rc; 2215 } 2216 2217 static int r820t_signal(struct dvb_frontend *fe, u16 *strength) 2218 { 2219 struct r820t_priv *priv = fe->tuner_priv; 2220 int rc = 0; 2221 2222 mutex_lock(&priv->lock); 2223 if (fe->ops.i2c_gate_ctrl) 2224 fe->ops.i2c_gate_ctrl(fe, 1); 2225 2226 if (priv->has_lock) { 2227 rc = r820t_read_gain(priv); 2228 if (rc < 0) 2229 goto err; 2230 2231 /* A higher gain at LNA means a lower signal strength */ 2232 *strength = (45 - rc) << 4 | 0xff; 2233 if (*strength == 0xff) 2234 *strength = 0; 2235 } else { 2236 *strength = 0; 2237 } 2238 2239 err: 2240 if (fe->ops.i2c_gate_ctrl) 2241 fe->ops.i2c_gate_ctrl(fe, 0); 2242 mutex_unlock(&priv->lock); 2243 2244 tuner_dbg("%s: %s, gain=%d strength=%d\n", 2245 __func__, 2246 priv->has_lock ? "PLL locked" : "no signal", 2247 rc, *strength); 2248 2249 return 0; 2250 } 2251 2252 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 2253 { 2254 struct r820t_priv *priv = fe->tuner_priv; 2255 2256 tuner_dbg("%s:\n", __func__); 2257 2258 *frequency = priv->int_freq; 2259 2260 return 0; 2261 } 2262 2263 static int r820t_release(struct dvb_frontend *fe) 2264 { 2265 struct r820t_priv *priv = fe->tuner_priv; 2266 2267 tuner_dbg("%s:\n", __func__); 2268 2269 mutex_lock(&r820t_list_mutex); 2270 2271 if (priv) 2272 hybrid_tuner_release_state(priv); 2273 2274 mutex_unlock(&r820t_list_mutex); 2275 2276 fe->tuner_priv = NULL; 2277 2278 return 0; 2279 } 2280 2281 static const struct dvb_tuner_ops r820t_tuner_ops = { 2282 .info = { 2283 .name = "Rafael Micro R820T", 2284 .frequency_min = 42000000, 2285 .frequency_max = 1002000000, 2286 }, 2287 .init = r820t_init, 2288 .release = r820t_release, 2289 .sleep = r820t_sleep, 2290 .set_params = r820t_set_params, 2291 .set_analog_params = r820t_set_analog_freq, 2292 .get_if_frequency = r820t_get_if_frequency, 2293 .get_rf_strength = r820t_signal, 2294 }; 2295 2296 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe, 2297 struct i2c_adapter *i2c, 2298 const struct r820t_config *cfg) 2299 { 2300 struct r820t_priv *priv; 2301 int rc = -ENODEV; 2302 u8 data[5]; 2303 int instance; 2304 2305 mutex_lock(&r820t_list_mutex); 2306 2307 instance = hybrid_tuner_request_state(struct r820t_priv, priv, 2308 hybrid_tuner_instance_list, 2309 i2c, cfg->i2c_addr, 2310 "r820t"); 2311 switch (instance) { 2312 case 0: 2313 /* memory allocation failure */ 2314 goto err_no_gate; 2315 case 1: 2316 /* new tuner instance */ 2317 priv->cfg = cfg; 2318 2319 mutex_init(&priv->lock); 2320 2321 fe->tuner_priv = priv; 2322 break; 2323 case 2: 2324 /* existing tuner instance */ 2325 fe->tuner_priv = priv; 2326 break; 2327 } 2328 2329 if (fe->ops.i2c_gate_ctrl) 2330 fe->ops.i2c_gate_ctrl(fe, 1); 2331 2332 /* check if the tuner is there */ 2333 rc = r820t_read(priv, 0x00, data, sizeof(data)); 2334 if (rc < 0) 2335 goto err; 2336 2337 rc = r820t_sleep(fe); 2338 if (rc < 0) 2339 goto err; 2340 2341 tuner_info("Rafael Micro r820t successfully identified\n"); 2342 2343 if (fe->ops.i2c_gate_ctrl) 2344 fe->ops.i2c_gate_ctrl(fe, 0); 2345 2346 mutex_unlock(&r820t_list_mutex); 2347 2348 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, 2349 sizeof(struct dvb_tuner_ops)); 2350 2351 return fe; 2352 err: 2353 if (fe->ops.i2c_gate_ctrl) 2354 fe->ops.i2c_gate_ctrl(fe, 0); 2355 2356 err_no_gate: 2357 mutex_unlock(&r820t_list_mutex); 2358 2359 tuner_info("%s: failed=%d\n", __func__, rc); 2360 r820t_release(fe); 2361 return NULL; 2362 } 2363 EXPORT_SYMBOL_GPL(r820t_attach); 2364 2365 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver"); 2366 MODULE_AUTHOR("Mauro Carvalho Chehab"); 2367 MODULE_LICENSE("GPL"); 2368