1 // SPDX-License-Identifier: GPL-2.0 2 // Rafael Micro R820T driver 3 // 4 // Copyright (C) 2013 Mauro Carvalho Chehab 5 // 6 // This driver was written from scratch, based on an existing driver 7 // that it is part of rtl-sdr git tree, released under GPLv2: 8 // https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug 9 // https://github.com/n1gp/gr-baz 10 // 11 // From what I understood from the threads, the original driver was converted 12 // to userspace from a Realtek tree. I couldn't find the original tree. 13 // However, the original driver look awkward on my eyes. So, I decided to 14 // write a new version from it from the scratch, while trying to reproduce 15 // everything found there. 16 // 17 // TODO: 18 // After locking, the original driver seems to have some routines to 19 // improve reception. This was not implemented here yet. 20 // 21 // RF Gain set/get is not implemented. 22 23 #include <linux/videodev2.h> 24 #include <linux/mutex.h> 25 #include <linux/slab.h> 26 #include <linux/bitrev.h> 27 28 #include "tuner-i2c.h" 29 #include "r820t.h" 30 31 /* 32 * FIXME: I think that there are only 32 registers, but better safe than 33 * sorry. After finishing the driver, we may review it. 34 */ 35 #define REG_SHADOW_START 5 36 #define NUM_REGS 27 37 #define NUM_IMR 5 38 #define IMR_TRIAL 9 39 40 #define VER_NUM 49 41 42 static int debug; 43 module_param(debug, int, 0644); 44 MODULE_PARM_DESC(debug, "enable verbose debug messages"); 45 46 static int no_imr_cal; 47 module_param(no_imr_cal, int, 0444); 48 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init"); 49 50 51 /* 52 * enums and structures 53 */ 54 55 enum xtal_cap_value { 56 XTAL_LOW_CAP_30P = 0, 57 XTAL_LOW_CAP_20P, 58 XTAL_LOW_CAP_10P, 59 XTAL_LOW_CAP_0P, 60 XTAL_HIGH_CAP_0P 61 }; 62 63 struct r820t_sect_type { 64 u8 phase_y; 65 u8 gain_x; 66 u16 value; 67 }; 68 69 struct r820t_priv { 70 struct list_head hybrid_tuner_instance_list; 71 const struct r820t_config *cfg; 72 struct tuner_i2c_props i2c_props; 73 struct mutex lock; 74 75 u8 regs[NUM_REGS]; 76 u8 buf[NUM_REGS + 1]; 77 enum xtal_cap_value xtal_cap_sel; 78 u16 pll; /* kHz */ 79 u32 int_freq; 80 u8 fil_cal_code; 81 bool imr_done; 82 bool has_lock; 83 bool init_done; 84 struct r820t_sect_type imr_data[NUM_IMR]; 85 86 /* Store current mode */ 87 u32 delsys; 88 enum v4l2_tuner_type type; 89 v4l2_std_id std; 90 u32 bw; /* in MHz */ 91 }; 92 93 struct r820t_freq_range { 94 u32 freq; 95 u8 open_d; 96 u8 rf_mux_ploy; 97 u8 tf_c; 98 u8 xtal_cap20p; 99 u8 xtal_cap10p; 100 u8 xtal_cap0p; 101 u8 imr_mem; /* Not used, currently */ 102 }; 103 104 #define VCO_POWER_REF 0x02 105 #define DIP_FREQ 32000000 106 107 /* 108 * Static constants 109 */ 110 111 static LIST_HEAD(hybrid_tuner_instance_list); 112 static DEFINE_MUTEX(r820t_list_mutex); 113 114 /* Those initial values start from REG_SHADOW_START */ 115 static const u8 r820t_init_array[NUM_REGS] = { 116 0x83, 0x32, 0x75, /* 05 to 07 */ 117 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */ 118 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */ 119 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */ 120 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */ 121 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */ 122 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */ 123 }; 124 125 /* Tuner frequency ranges */ 126 static const struct r820t_freq_range freq_ranges[] = { 127 { 128 .freq = 0, 129 .open_d = 0x08, /* low */ 130 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 131 .tf_c = 0xdf, /* R27[7:0] band2,band0 */ 132 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 133 .xtal_cap10p = 0x01, 134 .xtal_cap0p = 0x00, 135 .imr_mem = 0, 136 }, { 137 .freq = 50, /* Start freq, in MHz */ 138 .open_d = 0x08, /* low */ 139 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 140 .tf_c = 0xbe, /* R27[7:0] band4,band1 */ 141 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 142 .xtal_cap10p = 0x01, 143 .xtal_cap0p = 0x00, 144 .imr_mem = 0, 145 }, { 146 .freq = 55, /* Start freq, in MHz */ 147 .open_d = 0x08, /* low */ 148 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 149 .tf_c = 0x8b, /* R27[7:0] band7,band4 */ 150 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 151 .xtal_cap10p = 0x01, 152 .xtal_cap0p = 0x00, 153 .imr_mem = 0, 154 }, { 155 .freq = 60, /* Start freq, in MHz */ 156 .open_d = 0x08, /* low */ 157 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 158 .tf_c = 0x7b, /* R27[7:0] band8,band4 */ 159 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 160 .xtal_cap10p = 0x01, 161 .xtal_cap0p = 0x00, 162 .imr_mem = 0, 163 }, { 164 .freq = 65, /* Start freq, in MHz */ 165 .open_d = 0x08, /* low */ 166 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 167 .tf_c = 0x69, /* R27[7:0] band9,band6 */ 168 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 169 .xtal_cap10p = 0x01, 170 .xtal_cap0p = 0x00, 171 .imr_mem = 0, 172 }, { 173 .freq = 70, /* Start freq, in MHz */ 174 .open_d = 0x08, /* low */ 175 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 176 .tf_c = 0x58, /* R27[7:0] band10,band7 */ 177 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 178 .xtal_cap10p = 0x01, 179 .xtal_cap0p = 0x00, 180 .imr_mem = 0, 181 }, { 182 .freq = 75, /* Start freq, in MHz */ 183 .open_d = 0x00, /* high */ 184 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 185 .tf_c = 0x44, /* R27[7:0] band11,band11 */ 186 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 187 .xtal_cap10p = 0x01, 188 .xtal_cap0p = 0x00, 189 .imr_mem = 0, 190 }, { 191 .freq = 80, /* Start freq, in MHz */ 192 .open_d = 0x00, /* high */ 193 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 194 .tf_c = 0x44, /* R27[7:0] band11,band11 */ 195 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */ 196 .xtal_cap10p = 0x01, 197 .xtal_cap0p = 0x00, 198 .imr_mem = 0, 199 }, { 200 .freq = 90, /* Start freq, in MHz */ 201 .open_d = 0x00, /* high */ 202 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 203 .tf_c = 0x34, /* R27[7:0] band12,band11 */ 204 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 205 .xtal_cap10p = 0x01, 206 .xtal_cap0p = 0x00, 207 .imr_mem = 0, 208 }, { 209 .freq = 100, /* Start freq, in MHz */ 210 .open_d = 0x00, /* high */ 211 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 212 .tf_c = 0x34, /* R27[7:0] band12,band11 */ 213 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 214 .xtal_cap10p = 0x01, 215 .xtal_cap0p = 0x00, 216 .imr_mem = 0, 217 }, { 218 .freq = 110, /* Start freq, in MHz */ 219 .open_d = 0x00, /* high */ 220 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 221 .tf_c = 0x24, /* R27[7:0] band13,band11 */ 222 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 223 .xtal_cap10p = 0x01, 224 .xtal_cap0p = 0x00, 225 .imr_mem = 1, 226 }, { 227 .freq = 120, /* Start freq, in MHz */ 228 .open_d = 0x00, /* high */ 229 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 230 .tf_c = 0x24, /* R27[7:0] band13,band11 */ 231 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 232 .xtal_cap10p = 0x01, 233 .xtal_cap0p = 0x00, 234 .imr_mem = 1, 235 }, { 236 .freq = 140, /* Start freq, in MHz */ 237 .open_d = 0x00, /* high */ 238 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 239 .tf_c = 0x14, /* R27[7:0] band14,band11 */ 240 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */ 241 .xtal_cap10p = 0x01, 242 .xtal_cap0p = 0x00, 243 .imr_mem = 1, 244 }, { 245 .freq = 180, /* Start freq, in MHz */ 246 .open_d = 0x00, /* high */ 247 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 248 .tf_c = 0x13, /* R27[7:0] band14,band12 */ 249 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 250 .xtal_cap10p = 0x00, 251 .xtal_cap0p = 0x00, 252 .imr_mem = 1, 253 }, { 254 .freq = 220, /* Start freq, in MHz */ 255 .open_d = 0x00, /* high */ 256 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 257 .tf_c = 0x13, /* R27[7:0] band14,band12 */ 258 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 259 .xtal_cap10p = 0x00, 260 .xtal_cap0p = 0x00, 261 .imr_mem = 2, 262 }, { 263 .freq = 250, /* Start freq, in MHz */ 264 .open_d = 0x00, /* high */ 265 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 266 .tf_c = 0x11, /* R27[7:0] highest,highest */ 267 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 268 .xtal_cap10p = 0x00, 269 .xtal_cap0p = 0x00, 270 .imr_mem = 2, 271 }, { 272 .freq = 280, /* Start freq, in MHz */ 273 .open_d = 0x00, /* high */ 274 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 275 .tf_c = 0x00, /* R27[7:0] highest,highest */ 276 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 277 .xtal_cap10p = 0x00, 278 .xtal_cap0p = 0x00, 279 .imr_mem = 2, 280 }, { 281 .freq = 310, /* Start freq, in MHz */ 282 .open_d = 0x00, /* high */ 283 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 284 .tf_c = 0x00, /* R27[7:0] highest,highest */ 285 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 286 .xtal_cap10p = 0x00, 287 .xtal_cap0p = 0x00, 288 .imr_mem = 2, 289 }, { 290 .freq = 450, /* Start freq, in MHz */ 291 .open_d = 0x00, /* high */ 292 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 293 .tf_c = 0x00, /* R27[7:0] highest,highest */ 294 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 295 .xtal_cap10p = 0x00, 296 .xtal_cap0p = 0x00, 297 .imr_mem = 3, 298 }, { 299 .freq = 588, /* Start freq, in MHz */ 300 .open_d = 0x00, /* high */ 301 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 302 .tf_c = 0x00, /* R27[7:0] highest,highest */ 303 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 304 .xtal_cap10p = 0x00, 305 .xtal_cap0p = 0x00, 306 .imr_mem = 3, 307 }, { 308 .freq = 650, /* Start freq, in MHz */ 309 .open_d = 0x00, /* high */ 310 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 311 .tf_c = 0x00, /* R27[7:0] highest,highest */ 312 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */ 313 .xtal_cap10p = 0x00, 314 .xtal_cap0p = 0x00, 315 .imr_mem = 4, 316 } 317 }; 318 319 static int r820t_xtal_capacitor[][2] = { 320 { 0x0b, XTAL_LOW_CAP_30P }, 321 { 0x02, XTAL_LOW_CAP_20P }, 322 { 0x01, XTAL_LOW_CAP_10P }, 323 { 0x00, XTAL_LOW_CAP_0P }, 324 { 0x10, XTAL_HIGH_CAP_0P }, 325 }; 326 327 /* 328 * I2C read/write code and shadow registers logic 329 */ 330 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val, 331 int len) 332 { 333 int r = reg - REG_SHADOW_START; 334 335 if (r < 0) { 336 len += r; 337 r = 0; 338 } 339 if (len <= 0) 340 return; 341 if (len > NUM_REGS - r) 342 len = NUM_REGS - r; 343 344 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n", 345 __func__, r + REG_SHADOW_START, len, len, val); 346 347 memcpy(&priv->regs[r], val, len); 348 } 349 350 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val, 351 int len) 352 { 353 int rc, size, pos = 0; 354 355 /* Store the shadow registers */ 356 shadow_store(priv, reg, val, len); 357 358 do { 359 if (len > priv->cfg->max_i2c_msg_len - 1) 360 size = priv->cfg->max_i2c_msg_len - 1; 361 else 362 size = len; 363 364 /* Fill I2C buffer */ 365 priv->buf[0] = reg; 366 memcpy(&priv->buf[1], &val[pos], size); 367 368 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1); 369 if (rc != size + 1) { 370 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n", 371 __func__, rc, reg, size, size, &priv->buf[1]); 372 if (rc < 0) 373 return rc; 374 return -EREMOTEIO; 375 } 376 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n", 377 __func__, reg, size, size, &priv->buf[1]); 378 379 reg += size; 380 len -= size; 381 pos += size; 382 } while (len > 0); 383 384 return 0; 385 } 386 387 static inline int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val) 388 { 389 u8 tmp = val; /* work around GCC PR81715 with asan-stack=1 */ 390 391 return r820t_write(priv, reg, &tmp, 1); 392 } 393 394 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg) 395 { 396 reg -= REG_SHADOW_START; 397 398 if (reg >= 0 && reg < NUM_REGS) 399 return priv->regs[reg]; 400 else 401 return -EINVAL; 402 } 403 404 static inline int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val, 405 u8 bit_mask) 406 { 407 u8 tmp = val; 408 int rc = r820t_read_cache_reg(priv, reg); 409 410 if (rc < 0) 411 return rc; 412 413 tmp = (rc & ~bit_mask) | (tmp & bit_mask); 414 415 return r820t_write(priv, reg, &tmp, 1); 416 } 417 418 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len) 419 { 420 int rc, i; 421 u8 *p = &priv->buf[1]; 422 423 priv->buf[0] = reg; 424 425 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len); 426 if (rc != len) { 427 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n", 428 __func__, rc, reg, len, len, p); 429 if (rc < 0) 430 return rc; 431 return -EREMOTEIO; 432 } 433 434 /* Copy data to the output buffer */ 435 for (i = 0; i < len; i++) 436 val[i] = bitrev8(p[i]); 437 438 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n", 439 __func__, reg, len, len, val); 440 441 return 0; 442 } 443 444 /* 445 * r820t tuning logic 446 */ 447 448 static int r820t_set_mux(struct r820t_priv *priv, u32 freq) 449 { 450 const struct r820t_freq_range *range; 451 int i, rc; 452 u8 val, reg08, reg09; 453 454 /* Get the proper frequency range */ 455 freq = freq / 1000000; 456 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) { 457 if (freq < freq_ranges[i + 1].freq) 458 break; 459 } 460 range = &freq_ranges[i]; 461 462 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq); 463 464 /* Open Drain */ 465 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08); 466 if (rc < 0) 467 return rc; 468 469 /* RF_MUX,Polymux */ 470 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3); 471 if (rc < 0) 472 return rc; 473 474 /* TF BAND */ 475 rc = r820t_write_reg(priv, 0x1b, range->tf_c); 476 if (rc < 0) 477 return rc; 478 479 /* XTAL CAP & Drive */ 480 switch (priv->xtal_cap_sel) { 481 case XTAL_LOW_CAP_30P: 482 case XTAL_LOW_CAP_20P: 483 val = range->xtal_cap20p | 0x08; 484 break; 485 case XTAL_LOW_CAP_10P: 486 val = range->xtal_cap10p | 0x08; 487 break; 488 case XTAL_HIGH_CAP_0P: 489 val = range->xtal_cap0p | 0x00; 490 break; 491 default: 492 case XTAL_LOW_CAP_0P: 493 val = range->xtal_cap0p | 0x08; 494 break; 495 } 496 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b); 497 if (rc < 0) 498 return rc; 499 500 if (priv->imr_done) { 501 reg08 = priv->imr_data[range->imr_mem].gain_x; 502 reg09 = priv->imr_data[range->imr_mem].phase_y; 503 } else { 504 reg08 = 0; 505 reg09 = 0; 506 } 507 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f); 508 if (rc < 0) 509 return rc; 510 511 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f); 512 513 return rc; 514 } 515 516 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type, 517 u32 freq) 518 { 519 u32 vco_freq; 520 int rc, i; 521 unsigned sleep_time = 10000; 522 u32 vco_fra; /* VCO contribution by SDM (kHz) */ 523 u32 vco_min = 1770000; 524 u32 vco_max = vco_min * 2; 525 u32 pll_ref; 526 u16 n_sdm = 2; 527 u16 sdm = 0; 528 u8 mix_div = 2; 529 u8 div_buf = 0; 530 u8 div_num = 0; 531 u8 refdiv2 = 0; 532 u8 ni, si, nint, vco_fine_tune, val; 533 u8 data[5]; 534 535 /* Frequency in kHz */ 536 freq = freq / 1000; 537 pll_ref = priv->cfg->xtal / 1000; 538 539 #if 0 540 /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */ 541 if ((priv->cfg->rafael_chip == CHIP_R620D) || 542 (priv->cfg->rafael_chip == CHIP_R828D) || 543 (priv->cfg->rafael_chip == CHIP_R828)) { 544 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */ 545 if (type != V4L2_TUNER_DIGITAL_TV) { 546 pll_ref /= 2; 547 refdiv2 = 0x10; 548 sleep_time = 20000; 549 } 550 } else { 551 if (priv->cfg->xtal > 24000000) { 552 pll_ref /= 2; 553 refdiv2 = 0x10; 554 } 555 } 556 #endif 557 558 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10); 559 if (rc < 0) 560 return rc; 561 562 /* set pll autotune = 128kHz */ 563 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); 564 if (rc < 0) 565 return rc; 566 567 /* set VCO current = 100 */ 568 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0); 569 if (rc < 0) 570 return rc; 571 572 /* Calculate divider */ 573 while (mix_div <= 64) { 574 if (((freq * mix_div) >= vco_min) && 575 ((freq * mix_div) < vco_max)) { 576 div_buf = mix_div; 577 while (div_buf > 2) { 578 div_buf = div_buf >> 1; 579 div_num++; 580 } 581 break; 582 } 583 mix_div = mix_div << 1; 584 } 585 586 rc = r820t_read(priv, 0x00, data, sizeof(data)); 587 if (rc < 0) 588 return rc; 589 590 vco_fine_tune = (data[4] & 0x30) >> 4; 591 592 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n", 593 mix_div, div_num, vco_fine_tune); 594 595 /* 596 * XXX: R828D/16MHz seems to have always vco_fine_tune=1. 597 * Due to that, this calculation goes wrong. 598 */ 599 if (priv->cfg->rafael_chip != CHIP_R828D) { 600 if (vco_fine_tune > VCO_POWER_REF) 601 div_num = div_num - 1; 602 else if (vco_fine_tune < VCO_POWER_REF) 603 div_num = div_num + 1; 604 } 605 606 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0); 607 if (rc < 0) 608 return rc; 609 610 vco_freq = freq * mix_div; 611 nint = vco_freq / (2 * pll_ref); 612 vco_fra = vco_freq - 2 * pll_ref * nint; 613 614 /* boundary spur prevention */ 615 if (vco_fra < pll_ref / 64) { 616 vco_fra = 0; 617 } else if (vco_fra > pll_ref * 127 / 64) { 618 vco_fra = 0; 619 nint++; 620 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) { 621 vco_fra = pll_ref * 127 / 128; 622 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) { 623 vco_fra = pll_ref * 129 / 128; 624 } 625 626 ni = (nint - 13) / 4; 627 si = nint - 4 * ni - 13; 628 629 rc = r820t_write_reg(priv, 0x14, ni + (si << 6)); 630 if (rc < 0) 631 return rc; 632 633 /* pw_sdm */ 634 if (!vco_fra) 635 val = 0x08; 636 else 637 val = 0x00; 638 639 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08); 640 if (rc < 0) 641 return rc; 642 643 /* sdm calculator */ 644 while (vco_fra > 1) { 645 if (vco_fra > (2 * pll_ref / n_sdm)) { 646 sdm = sdm + 32768 / (n_sdm / 2); 647 vco_fra = vco_fra - 2 * pll_ref / n_sdm; 648 if (n_sdm >= 0x8000) 649 break; 650 } 651 n_sdm = n_sdm << 1; 652 } 653 654 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n", 655 freq, pll_ref, refdiv2 ? " / 2" : "", sdm); 656 657 rc = r820t_write_reg(priv, 0x16, sdm >> 8); 658 if (rc < 0) 659 return rc; 660 rc = r820t_write_reg(priv, 0x15, sdm & 0xff); 661 if (rc < 0) 662 return rc; 663 664 for (i = 0; i < 2; i++) { 665 usleep_range(sleep_time, sleep_time + 1000); 666 667 /* Check if PLL has locked */ 668 rc = r820t_read(priv, 0x00, data, 3); 669 if (rc < 0) 670 return rc; 671 if (data[2] & 0x40) 672 break; 673 674 if (!i) { 675 /* Didn't lock. Increase VCO current */ 676 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0); 677 if (rc < 0) 678 return rc; 679 } 680 } 681 682 if (!(data[2] & 0x40)) { 683 priv->has_lock = false; 684 return 0; 685 } 686 687 priv->has_lock = true; 688 tuner_dbg("tuner has lock at frequency %d kHz\n", freq); 689 690 /* set pll autotune = 8kHz */ 691 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08); 692 693 return rc; 694 } 695 696 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq, 697 enum v4l2_tuner_type type, 698 v4l2_std_id std, 699 u32 delsys) 700 { 701 int rc; 702 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l; 703 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur; 704 705 tuner_dbg("adjusting tuner parameters for the standard\n"); 706 707 switch (delsys) { 708 case SYS_DVBT: 709 if ((freq == 506000000) || (freq == 666000000) || 710 (freq == 818000000)) { 711 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */ 712 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 713 cp_cur = 0x28; /* 101, 0.2 */ 714 div_buf_cur = 0x20; /* 10, 200u */ 715 } else { 716 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 717 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 718 cp_cur = 0x38; /* 111, auto */ 719 div_buf_cur = 0x30; /* 11, 150u */ 720 } 721 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 722 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 723 air_cable1_in = 0x00; 724 cable2_in = 0x00; 725 pre_dect = 0x40; 726 lna_discharge = 14; 727 filter_cur = 0x40; /* 10, low */ 728 break; 729 case SYS_DVBT2: 730 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 731 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 732 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 733 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 734 air_cable1_in = 0x00; 735 cable2_in = 0x00; 736 pre_dect = 0x40; 737 lna_discharge = 14; 738 cp_cur = 0x38; /* 111, auto */ 739 div_buf_cur = 0x30; /* 11, 150u */ 740 filter_cur = 0x40; /* 10, low */ 741 break; 742 case SYS_ISDBT: 743 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 744 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 745 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */ 746 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 747 air_cable1_in = 0x00; 748 cable2_in = 0x00; 749 pre_dect = 0x40; 750 lna_discharge = 14; 751 cp_cur = 0x38; /* 111, auto */ 752 div_buf_cur = 0x30; /* 11, 150u */ 753 filter_cur = 0x40; /* 10, low */ 754 break; 755 case SYS_DVBC_ANNEX_A: 756 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 757 lna_top = 0xe5; 758 lna_vth_l = 0x62; 759 mixer_vth_l = 0x75; 760 air_cable1_in = 0x60; 761 cable2_in = 0x00; 762 pre_dect = 0x40; 763 lna_discharge = 14; 764 cp_cur = 0x38; /* 111, auto */ 765 div_buf_cur = 0x30; /* 11, 150u */ 766 filter_cur = 0x40; /* 10, low */ 767 break; 768 default: /* DVB-T 8M */ 769 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */ 770 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */ 771 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */ 772 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */ 773 air_cable1_in = 0x00; 774 cable2_in = 0x00; 775 pre_dect = 0x40; 776 lna_discharge = 14; 777 cp_cur = 0x38; /* 111, auto */ 778 div_buf_cur = 0x30; /* 11, 150u */ 779 filter_cur = 0x40; /* 10, low */ 780 break; 781 } 782 783 if (priv->cfg->use_diplexer && 784 ((priv->cfg->rafael_chip == CHIP_R820T) || 785 (priv->cfg->rafael_chip == CHIP_R828S) || 786 (priv->cfg->rafael_chip == CHIP_R820C))) { 787 if (freq > DIP_FREQ) 788 air_cable1_in = 0x00; 789 else 790 air_cable1_in = 0x60; 791 cable2_in = 0x00; 792 } 793 794 795 if (priv->cfg->use_predetect) { 796 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40); 797 if (rc < 0) 798 return rc; 799 } 800 801 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7); 802 if (rc < 0) 803 return rc; 804 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8); 805 if (rc < 0) 806 return rc; 807 rc = r820t_write_reg(priv, 0x0d, lna_vth_l); 808 if (rc < 0) 809 return rc; 810 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l); 811 if (rc < 0) 812 return rc; 813 814 /* Air-IN only for Astrometa */ 815 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60); 816 if (rc < 0) 817 return rc; 818 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08); 819 if (rc < 0) 820 return rc; 821 822 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38); 823 if (rc < 0) 824 return rc; 825 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30); 826 if (rc < 0) 827 return rc; 828 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60); 829 if (rc < 0) 830 return rc; 831 /* 832 * Original driver initializes regs 0x05 and 0x06 with the 833 * same value again on this point. Probably, it is just an 834 * error there 835 */ 836 837 /* 838 * Set LNA 839 */ 840 841 tuner_dbg("adjusting LNA parameters\n"); 842 if (type != V4L2_TUNER_ANALOG_TV) { 843 /* LNA TOP: lowest */ 844 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38); 845 if (rc < 0) 846 return rc; 847 848 /* 0: normal mode */ 849 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04); 850 if (rc < 0) 851 return rc; 852 853 /* 0: PRE_DECT off */ 854 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); 855 if (rc < 0) 856 return rc; 857 858 /* agc clk 250hz */ 859 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30); 860 if (rc < 0) 861 return rc; 862 863 msleep(250); 864 865 /* write LNA TOP = 3 */ 866 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38); 867 if (rc < 0) 868 return rc; 869 870 /* 871 * write discharge mode 872 * FIXME: IMHO, the mask here is wrong, but it matches 873 * what's there at the original driver 874 */ 875 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); 876 if (rc < 0) 877 return rc; 878 879 /* LNA discharge current */ 880 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); 881 if (rc < 0) 882 return rc; 883 884 /* agc clk 60hz */ 885 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30); 886 if (rc < 0) 887 return rc; 888 } else { 889 /* PRE_DECT off */ 890 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40); 891 if (rc < 0) 892 return rc; 893 894 /* write LNA TOP */ 895 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38); 896 if (rc < 0) 897 return rc; 898 899 /* 900 * write discharge mode 901 * FIXME: IMHO, the mask here is wrong, but it matches 902 * what's there at the original driver 903 */ 904 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04); 905 if (rc < 0) 906 return rc; 907 908 /* LNA discharge current */ 909 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f); 910 if (rc < 0) 911 return rc; 912 913 /* agc clk 1Khz, external det1 cap 1u */ 914 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30); 915 if (rc < 0) 916 return rc; 917 918 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04); 919 if (rc < 0) 920 return rc; 921 } 922 return 0; 923 } 924 925 static int r820t_set_tv_standard(struct r820t_priv *priv, 926 unsigned bw, 927 enum v4l2_tuner_type type, 928 v4l2_std_id std, u32 delsys) 929 930 { 931 int rc, i; 932 u32 if_khz, filt_cal_lo; 933 u8 data[5], val; 934 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through; 935 u8 lt_att, flt_ext_widest, polyfil_cur; 936 bool need_calibration; 937 938 tuner_dbg("selecting the delivery system\n"); 939 940 if (delsys == SYS_ISDBT) { 941 if_khz = 4063; 942 filt_cal_lo = 59000; 943 filt_gain = 0x10; /* +3db, 6mhz on */ 944 img_r = 0x00; /* image negative */ 945 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 946 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */ 947 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */ 948 loop_through = 0x00; /* r5[7], lt on */ 949 lt_att = 0x00; /* r31[7], lt att enable */ 950 flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */ 951 polyfil_cur = 0x60; /* r25[6:5]:min */ 952 } else if (delsys == SYS_DVBC_ANNEX_A) { 953 if_khz = 5070; 954 filt_cal_lo = 73500; 955 filt_gain = 0x10; /* +3db, 6mhz on */ 956 img_r = 0x00; /* image negative */ 957 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 958 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ 959 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 960 loop_through = 0x00; /* r5[7], lt on */ 961 lt_att = 0x00; /* r31[7], lt att enable */ 962 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 963 polyfil_cur = 0x60; /* r25[6:5]:min */ 964 } else if (delsys == SYS_DVBC_ANNEX_C) { 965 if_khz = 4063; 966 filt_cal_lo = 55000; 967 filt_gain = 0x10; /* +3db, 6mhz on */ 968 img_r = 0x00; /* image negative */ 969 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 970 hp_cor = 0x6a; /* 1.7m disable, +0cap, 1.0mhz */ 971 ext_enable = 0x40; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 972 loop_through = 0x00; /* r5[7], lt on */ 973 lt_att = 0x00; /* r31[7], lt att enable */ 974 flt_ext_widest = 0x80; /* r15[7]: flt_ext_wide on */ 975 polyfil_cur = 0x60; /* r25[6:5]:min */ 976 } else { 977 if (bw <= 6) { 978 if_khz = 3570; 979 filt_cal_lo = 56000; /* 52000->56000 */ 980 filt_gain = 0x10; /* +3db, 6mhz on */ 981 img_r = 0x00; /* image negative */ 982 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 983 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */ 984 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 985 loop_through = 0x00; /* r5[7], lt on */ 986 lt_att = 0x00; /* r31[7], lt att enable */ 987 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 988 polyfil_cur = 0x60; /* r25[6:5]:min */ 989 } else if (bw == 7) { 990 #if 0 991 /* 992 * There are two 7 MHz tables defined on the original 993 * driver, but just the second one seems to be visible 994 * by rtl2832. Keep this one here commented, as it 995 * might be needed in the future 996 */ 997 998 if_khz = 4070; 999 filt_cal_lo = 60000; 1000 filt_gain = 0x10; /* +3db, 6mhz on */ 1001 img_r = 0x00; /* image negative */ 1002 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1003 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */ 1004 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1005 loop_through = 0x00; /* r5[7], lt on */ 1006 lt_att = 0x00; /* r31[7], lt att enable */ 1007 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1008 polyfil_cur = 0x60; /* r25[6:5]:min */ 1009 #endif 1010 /* 7 MHz, second table */ 1011 if_khz = 4570; 1012 filt_cal_lo = 63000; 1013 filt_gain = 0x10; /* +3db, 6mhz on */ 1014 img_r = 0x00; /* image negative */ 1015 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1016 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */ 1017 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1018 loop_through = 0x00; /* r5[7], lt on */ 1019 lt_att = 0x00; /* r31[7], lt att enable */ 1020 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1021 polyfil_cur = 0x60; /* r25[6:5]:min */ 1022 } else { 1023 if_khz = 4570; 1024 filt_cal_lo = 68500; 1025 filt_gain = 0x10; /* +3db, 6mhz on */ 1026 img_r = 0x00; /* image negative */ 1027 filt_q = 0x10; /* r10[4]:low q(1'b1) */ 1028 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */ 1029 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */ 1030 loop_through = 0x00; /* r5[7], lt on */ 1031 lt_att = 0x00; /* r31[7], lt att enable */ 1032 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */ 1033 polyfil_cur = 0x60; /* r25[6:5]:min */ 1034 } 1035 } 1036 1037 /* Initialize the shadow registers */ 1038 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1039 1040 /* Init Flag & Xtal_check Result */ 1041 if (priv->imr_done) 1042 val = 1 | priv->xtal_cap_sel << 1; 1043 else 1044 val = 0; 1045 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f); 1046 if (rc < 0) 1047 return rc; 1048 1049 /* version */ 1050 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f); 1051 if (rc < 0) 1052 return rc; 1053 1054 /* for LT Gain test */ 1055 if (type != V4L2_TUNER_ANALOG_TV) { 1056 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38); 1057 if (rc < 0) 1058 return rc; 1059 usleep_range(1000, 2000); 1060 } 1061 priv->int_freq = if_khz * 1000; 1062 1063 /* Check if standard changed. If so, filter calibration is needed */ 1064 if (type != priv->type) 1065 need_calibration = true; 1066 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std)) 1067 need_calibration = true; 1068 else if ((type == V4L2_TUNER_DIGITAL_TV) && 1069 ((delsys != priv->delsys) || bw != priv->bw)) 1070 need_calibration = true; 1071 else 1072 need_calibration = false; 1073 1074 if (need_calibration) { 1075 tuner_dbg("calibrating the tuner\n"); 1076 for (i = 0; i < 2; i++) { 1077 /* Set filt_cap */ 1078 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60); 1079 if (rc < 0) 1080 return rc; 1081 1082 /* set cali clk =on */ 1083 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04); 1084 if (rc < 0) 1085 return rc; 1086 1087 /* X'tal cap 0pF for PLL */ 1088 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03); 1089 if (rc < 0) 1090 return rc; 1091 1092 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000); 1093 if (rc < 0 || !priv->has_lock) 1094 return rc; 1095 1096 /* Start Trigger */ 1097 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10); 1098 if (rc < 0) 1099 return rc; 1100 1101 usleep_range(1000, 2000); 1102 1103 /* Stop Trigger */ 1104 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10); 1105 if (rc < 0) 1106 return rc; 1107 1108 /* set cali clk =off */ 1109 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04); 1110 if (rc < 0) 1111 return rc; 1112 1113 /* Check if calibration worked */ 1114 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1115 if (rc < 0) 1116 return rc; 1117 1118 priv->fil_cal_code = data[4] & 0x0f; 1119 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f) 1120 break; 1121 } 1122 /* narrowest */ 1123 if (priv->fil_cal_code == 0x0f) 1124 priv->fil_cal_code = 0; 1125 } 1126 1127 rc = r820t_write_reg_mask(priv, 0x0a, 1128 filt_q | priv->fil_cal_code, 0x1f); 1129 if (rc < 0) 1130 return rc; 1131 1132 /* Set BW, Filter_gain, & HP corner */ 1133 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef); 1134 if (rc < 0) 1135 return rc; 1136 1137 1138 /* Set Img_R */ 1139 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80); 1140 if (rc < 0) 1141 return rc; 1142 1143 /* Set filt_3dB, V6MHz */ 1144 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30); 1145 if (rc < 0) 1146 return rc; 1147 1148 /* channel filter extension */ 1149 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60); 1150 if (rc < 0) 1151 return rc; 1152 1153 /* Loop through */ 1154 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80); 1155 if (rc < 0) 1156 return rc; 1157 1158 /* Loop through attenuation */ 1159 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80); 1160 if (rc < 0) 1161 return rc; 1162 1163 /* filter extension widest */ 1164 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80); 1165 if (rc < 0) 1166 return rc; 1167 1168 /* RF poly filter current */ 1169 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60); 1170 if (rc < 0) 1171 return rc; 1172 1173 /* Store current standard. If it changes, re-calibrate the tuner */ 1174 priv->delsys = delsys; 1175 priv->type = type; 1176 priv->std = std; 1177 priv->bw = bw; 1178 1179 return 0; 1180 } 1181 1182 static int r820t_read_gain(struct r820t_priv *priv) 1183 { 1184 u8 data[4]; 1185 int rc; 1186 1187 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1188 if (rc < 0) 1189 return rc; 1190 1191 return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4); 1192 } 1193 1194 #if 0 1195 /* FIXME: This routine requires more testing */ 1196 1197 /* 1198 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm 1199 * input power, for raw results see: 1200 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/ 1201 */ 1202 1203 static const int r820t_lna_gain_steps[] = { 1204 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13 1205 }; 1206 1207 static const int r820t_mixer_gain_steps[] = { 1208 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8 1209 }; 1210 1211 static int r820t_set_gain_mode(struct r820t_priv *priv, 1212 bool set_manual_gain, 1213 int gain) 1214 { 1215 int rc; 1216 1217 if (set_manual_gain) { 1218 int i, total_gain = 0; 1219 uint8_t mix_index = 0, lna_index = 0; 1220 u8 data[4]; 1221 1222 /* LNA auto off */ 1223 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10); 1224 if (rc < 0) 1225 return rc; 1226 1227 /* Mixer auto off */ 1228 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); 1229 if (rc < 0) 1230 return rc; 1231 1232 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1233 if (rc < 0) 1234 return rc; 1235 1236 /* set fixed VGA gain for now (16.3 dB) */ 1237 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f); 1238 if (rc < 0) 1239 return rc; 1240 1241 for (i = 0; i < 15; i++) { 1242 if (total_gain >= gain) 1243 break; 1244 1245 total_gain += r820t_lna_gain_steps[++lna_index]; 1246 1247 if (total_gain >= gain) 1248 break; 1249 1250 total_gain += r820t_mixer_gain_steps[++mix_index]; 1251 } 1252 1253 /* set LNA gain */ 1254 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f); 1255 if (rc < 0) 1256 return rc; 1257 1258 /* set Mixer gain */ 1259 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f); 1260 if (rc < 0) 1261 return rc; 1262 } else { 1263 /* LNA */ 1264 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10); 1265 if (rc < 0) 1266 return rc; 1267 1268 /* Mixer */ 1269 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10); 1270 if (rc < 0) 1271 return rc; 1272 1273 /* set fixed VGA gain for now (26.5 dB) */ 1274 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); 1275 if (rc < 0) 1276 return rc; 1277 } 1278 1279 return 0; 1280 } 1281 #endif 1282 1283 static int generic_set_freq(struct dvb_frontend *fe, 1284 u32 freq /* in HZ */, 1285 unsigned bw, 1286 enum v4l2_tuner_type type, 1287 v4l2_std_id std, u32 delsys) 1288 { 1289 struct r820t_priv *priv = fe->tuner_priv; 1290 int rc; 1291 u32 lo_freq; 1292 1293 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n", 1294 freq / 1000, bw); 1295 1296 rc = r820t_set_tv_standard(priv, bw, type, std, delsys); 1297 if (rc < 0) 1298 goto err; 1299 1300 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC)) 1301 lo_freq = freq - priv->int_freq; 1302 else 1303 lo_freq = freq + priv->int_freq; 1304 1305 rc = r820t_set_mux(priv, lo_freq); 1306 if (rc < 0) 1307 goto err; 1308 1309 rc = r820t_set_pll(priv, type, lo_freq); 1310 if (rc < 0 || !priv->has_lock) 1311 goto err; 1312 1313 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys); 1314 if (rc < 0) 1315 goto err; 1316 1317 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n", 1318 __func__, freq, r820t_read_gain(priv)); 1319 1320 err: 1321 1322 if (rc < 0) 1323 tuner_dbg("%s: failed=%d\n", __func__, rc); 1324 return rc; 1325 } 1326 1327 /* 1328 * r820t standby logic 1329 */ 1330 1331 static int r820t_standby(struct r820t_priv *priv) 1332 { 1333 int rc; 1334 1335 /* If device was not initialized yet, don't need to standby */ 1336 if (!priv->init_done) 1337 return 0; 1338 1339 rc = r820t_write_reg(priv, 0x06, 0xb1); 1340 if (rc < 0) 1341 return rc; 1342 rc = r820t_write_reg(priv, 0x05, 0x03); 1343 if (rc < 0) 1344 return rc; 1345 rc = r820t_write_reg(priv, 0x07, 0x3a); 1346 if (rc < 0) 1347 return rc; 1348 rc = r820t_write_reg(priv, 0x08, 0x40); 1349 if (rc < 0) 1350 return rc; 1351 rc = r820t_write_reg(priv, 0x09, 0xc0); 1352 if (rc < 0) 1353 return rc; 1354 rc = r820t_write_reg(priv, 0x0a, 0x36); 1355 if (rc < 0) 1356 return rc; 1357 rc = r820t_write_reg(priv, 0x0c, 0x35); 1358 if (rc < 0) 1359 return rc; 1360 rc = r820t_write_reg(priv, 0x0f, 0x68); 1361 if (rc < 0) 1362 return rc; 1363 rc = r820t_write_reg(priv, 0x11, 0x03); 1364 if (rc < 0) 1365 return rc; 1366 rc = r820t_write_reg(priv, 0x17, 0xf4); 1367 if (rc < 0) 1368 return rc; 1369 rc = r820t_write_reg(priv, 0x19, 0x0c); 1370 1371 /* Force initial calibration */ 1372 priv->type = -1; 1373 1374 return rc; 1375 } 1376 1377 /* 1378 * r820t device init logic 1379 */ 1380 1381 static int r820t_xtal_check(struct r820t_priv *priv) 1382 { 1383 int rc, i; 1384 u8 data[3], val; 1385 1386 /* Initialize the shadow registers */ 1387 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1388 1389 /* cap 30pF & Drive Low */ 1390 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b); 1391 if (rc < 0) 1392 return rc; 1393 1394 /* set pll autotune = 128kHz */ 1395 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c); 1396 if (rc < 0) 1397 return rc; 1398 1399 /* set manual initial reg = 111111; */ 1400 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f); 1401 if (rc < 0) 1402 return rc; 1403 1404 /* set auto */ 1405 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40); 1406 if (rc < 0) 1407 return rc; 1408 1409 /* Try several xtal capacitor alternatives */ 1410 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) { 1411 rc = r820t_write_reg_mask(priv, 0x10, 1412 r820t_xtal_capacitor[i][0], 0x1b); 1413 if (rc < 0) 1414 return rc; 1415 1416 usleep_range(5000, 6000); 1417 1418 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1419 if (rc < 0) 1420 return rc; 1421 if (!(data[2] & 0x40)) 1422 continue; 1423 1424 val = data[2] & 0x3f; 1425 1426 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23)) 1427 break; 1428 1429 if (val != 0x3f) 1430 break; 1431 } 1432 1433 if (i == ARRAY_SIZE(r820t_xtal_capacitor)) 1434 return -EINVAL; 1435 1436 return r820t_xtal_capacitor[i][1]; 1437 } 1438 1439 static int r820t_imr_prepare(struct r820t_priv *priv) 1440 { 1441 int rc; 1442 1443 /* Initialize the shadow registers */ 1444 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array)); 1445 1446 /* lna off (air-in off) */ 1447 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20); 1448 if (rc < 0) 1449 return rc; 1450 1451 /* mixer gain mode = manual */ 1452 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10); 1453 if (rc < 0) 1454 return rc; 1455 1456 /* filter corner = lowest */ 1457 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f); 1458 if (rc < 0) 1459 return rc; 1460 1461 /* filter bw=+2cap, hp=5M */ 1462 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f); 1463 if (rc < 0) 1464 return rc; 1465 1466 /* adc=on, vga code mode, gain = 26.5dB */ 1467 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f); 1468 if (rc < 0) 1469 return rc; 1470 1471 /* ring clk = on */ 1472 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08); 1473 if (rc < 0) 1474 return rc; 1475 1476 /* ring power = on */ 1477 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10); 1478 if (rc < 0) 1479 return rc; 1480 1481 /* from ring = ring pll in */ 1482 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02); 1483 if (rc < 0) 1484 return rc; 1485 1486 /* sw_pdect = det3 */ 1487 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80); 1488 if (rc < 0) 1489 return rc; 1490 1491 /* Set filt_3dB */ 1492 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20); 1493 1494 return rc; 1495 } 1496 1497 static int r820t_multi_read(struct r820t_priv *priv) 1498 { 1499 int rc, i; 1500 u16 sum = 0; 1501 u8 data[2], min = 255, max = 0; 1502 1503 usleep_range(5000, 6000); 1504 1505 for (i = 0; i < 6; i++) { 1506 rc = r820t_read(priv, 0x00, data, sizeof(data)); 1507 if (rc < 0) 1508 return rc; 1509 1510 sum += data[1]; 1511 1512 if (data[1] < min) 1513 min = data[1]; 1514 1515 if (data[1] > max) 1516 max = data[1]; 1517 } 1518 rc = sum - max - min; 1519 1520 return rc; 1521 } 1522 1523 static int r820t_imr_cross(struct r820t_priv *priv, 1524 struct r820t_sect_type iq_point[3], 1525 u8 *x_direct) 1526 { 1527 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */ 1528 struct r820t_sect_type tmp; 1529 int i, rc; 1530 u8 reg08, reg09; 1531 1532 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0; 1533 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0; 1534 1535 tmp.gain_x = 0; 1536 tmp.phase_y = 0; 1537 tmp.value = 255; 1538 1539 for (i = 0; i < 5; i++) { 1540 switch (i) { 1541 case 0: 1542 cross[i].gain_x = reg08; 1543 cross[i].phase_y = reg09; 1544 break; 1545 case 1: 1546 cross[i].gain_x = reg08; /* 0 */ 1547 cross[i].phase_y = reg09 + 1; /* Q-1 */ 1548 break; 1549 case 2: 1550 cross[i].gain_x = reg08; /* 0 */ 1551 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */ 1552 break; 1553 case 3: 1554 cross[i].gain_x = reg08 + 1; /* Q-1 */ 1555 cross[i].phase_y = reg09; 1556 break; 1557 default: 1558 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */ 1559 cross[i].phase_y = reg09; 1560 } 1561 1562 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x); 1563 if (rc < 0) 1564 return rc; 1565 1566 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y); 1567 if (rc < 0) 1568 return rc; 1569 1570 rc = r820t_multi_read(priv); 1571 if (rc < 0) 1572 return rc; 1573 1574 cross[i].value = rc; 1575 1576 if (cross[i].value < tmp.value) 1577 tmp = cross[i]; 1578 } 1579 1580 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */ 1581 *x_direct = 0; 1582 1583 iq_point[0] = cross[0]; 1584 iq_point[1] = cross[1]; 1585 iq_point[2] = cross[2]; 1586 } else { /* (0,0) or x-direction */ 1587 *x_direct = 1; 1588 1589 iq_point[0] = cross[0]; 1590 iq_point[1] = cross[3]; 1591 iq_point[2] = cross[4]; 1592 } 1593 return 0; 1594 } 1595 1596 static void r820t_compre_cor(struct r820t_sect_type iq[3]) 1597 { 1598 int i; 1599 1600 for (i = 3; i > 0; i--) { 1601 if (iq[0].value > iq[i - 1].value) 1602 swap(iq[0], iq[i - 1]); 1603 } 1604 } 1605 1606 static int r820t_compre_step(struct r820t_priv *priv, 1607 struct r820t_sect_type iq[3], u8 reg) 1608 { 1609 int rc; 1610 struct r820t_sect_type tmp; 1611 1612 /* 1613 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare 1614 * with min value: 1615 * new < min => update to min and continue 1616 * new > min => Exit 1617 */ 1618 1619 /* min value already saved in iq[0] */ 1620 tmp.phase_y = iq[0].phase_y; 1621 tmp.gain_x = iq[0].gain_x; 1622 1623 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) && 1624 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) { 1625 if (reg == 0x08) 1626 tmp.gain_x++; 1627 else 1628 tmp.phase_y++; 1629 1630 rc = r820t_write_reg(priv, 0x08, tmp.gain_x); 1631 if (rc < 0) 1632 return rc; 1633 1634 rc = r820t_write_reg(priv, 0x09, tmp.phase_y); 1635 if (rc < 0) 1636 return rc; 1637 1638 rc = r820t_multi_read(priv); 1639 if (rc < 0) 1640 return rc; 1641 tmp.value = rc; 1642 1643 if (tmp.value <= iq[0].value) { 1644 iq[0].gain_x = tmp.gain_x; 1645 iq[0].phase_y = tmp.phase_y; 1646 iq[0].value = tmp.value; 1647 } else { 1648 return 0; 1649 } 1650 1651 } 1652 1653 return 0; 1654 } 1655 1656 static int r820t_iq_tree(struct r820t_priv *priv, 1657 struct r820t_sect_type iq[3], 1658 u8 fix_val, u8 var_val, u8 fix_reg) 1659 { 1660 int rc, i; 1661 u8 tmp, var_reg; 1662 1663 /* 1664 * record IMC results by input gain/phase location then adjust 1665 * gain or phase positive 1 step and negtive 1 step, 1666 * both record results 1667 */ 1668 1669 if (fix_reg == 0x08) 1670 var_reg = 0x09; 1671 else 1672 var_reg = 0x08; 1673 1674 for (i = 0; i < 3; i++) { 1675 rc = r820t_write_reg(priv, fix_reg, fix_val); 1676 if (rc < 0) 1677 return rc; 1678 1679 rc = r820t_write_reg(priv, var_reg, var_val); 1680 if (rc < 0) 1681 return rc; 1682 1683 rc = r820t_multi_read(priv); 1684 if (rc < 0) 1685 return rc; 1686 iq[i].value = rc; 1687 1688 if (fix_reg == 0x08) { 1689 iq[i].gain_x = fix_val; 1690 iq[i].phase_y = var_val; 1691 } else { 1692 iq[i].phase_y = fix_val; 1693 iq[i].gain_x = var_val; 1694 } 1695 1696 if (i == 0) { /* try right-side point */ 1697 var_val++; 1698 } else if (i == 1) { /* try left-side point */ 1699 /* if absolute location is 1, change I/Q direction */ 1700 if ((var_val & 0x1f) < 0x02) { 1701 tmp = 2 - (var_val & 0x1f); 1702 1703 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */ 1704 if (var_val & 0x20) { 1705 var_val &= 0xc0; 1706 var_val |= tmp; 1707 } else { 1708 var_val |= 0x20 | tmp; 1709 } 1710 } else { 1711 var_val -= 2; 1712 } 1713 } 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int r820t_section(struct r820t_priv *priv, 1720 struct r820t_sect_type *iq_point) 1721 { 1722 int rc; 1723 struct r820t_sect_type compare_iq[3], compare_bet[3]; 1724 1725 /* Try X-1 column and save min result to compare_bet[0] */ 1726 if (!(iq_point->gain_x & 0x1f)) 1727 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */ 1728 else 1729 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */ 1730 compare_iq[0].phase_y = iq_point->phase_y; 1731 1732 /* y-direction */ 1733 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1734 compare_iq[0].phase_y, 0x08); 1735 if (rc < 0) 1736 return rc; 1737 1738 r820t_compre_cor(compare_iq); 1739 1740 compare_bet[0] = compare_iq[0]; 1741 1742 /* Try X column and save min result to compare_bet[1] */ 1743 compare_iq[0].gain_x = iq_point->gain_x; 1744 compare_iq[0].phase_y = iq_point->phase_y; 1745 1746 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1747 compare_iq[0].phase_y, 0x08); 1748 if (rc < 0) 1749 return rc; 1750 1751 r820t_compre_cor(compare_iq); 1752 1753 compare_bet[1] = compare_iq[0]; 1754 1755 /* Try X+1 column and save min result to compare_bet[2] */ 1756 if ((iq_point->gain_x & 0x1f) == 0x00) 1757 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */ 1758 else 1759 compare_iq[0].gain_x = iq_point->gain_x + 1; 1760 compare_iq[0].phase_y = iq_point->phase_y; 1761 1762 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1763 compare_iq[0].phase_y, 0x08); 1764 if (rc < 0) 1765 return rc; 1766 1767 r820t_compre_cor(compare_iq); 1768 1769 compare_bet[2] = compare_iq[0]; 1770 1771 r820t_compre_cor(compare_bet); 1772 1773 *iq_point = compare_bet[0]; 1774 1775 return 0; 1776 } 1777 1778 static int r820t_vga_adjust(struct r820t_priv *priv) 1779 { 1780 int rc; 1781 u8 vga_count; 1782 1783 /* increase vga power to let image significant */ 1784 for (vga_count = 12; vga_count < 16; vga_count++) { 1785 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f); 1786 if (rc < 0) 1787 return rc; 1788 1789 usleep_range(10000, 11000); 1790 1791 rc = r820t_multi_read(priv); 1792 if (rc < 0) 1793 return rc; 1794 1795 if (rc > 40 * 4) 1796 break; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) 1803 { 1804 struct r820t_sect_type compare_iq[3]; 1805 int rc; 1806 u8 x_direction = 0; /* 1:x, 0:y */ 1807 u8 dir_reg, other_reg; 1808 1809 r820t_vga_adjust(priv); 1810 1811 rc = r820t_imr_cross(priv, compare_iq, &x_direction); 1812 if (rc < 0) 1813 return rc; 1814 1815 if (x_direction == 1) { 1816 dir_reg = 0x08; 1817 other_reg = 0x09; 1818 } else { 1819 dir_reg = 0x09; 1820 other_reg = 0x08; 1821 } 1822 1823 /* compare and find min of 3 points. determine i/q direction */ 1824 r820t_compre_cor(compare_iq); 1825 1826 /* increase step to find min value of this direction */ 1827 rc = r820t_compre_step(priv, compare_iq, dir_reg); 1828 if (rc < 0) 1829 return rc; 1830 1831 /* the other direction */ 1832 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1833 compare_iq[0].phase_y, dir_reg); 1834 if (rc < 0) 1835 return rc; 1836 1837 /* compare and find min of 3 points. determine i/q direction */ 1838 r820t_compre_cor(compare_iq); 1839 1840 /* increase step to find min value on this direction */ 1841 rc = r820t_compre_step(priv, compare_iq, other_reg); 1842 if (rc < 0) 1843 return rc; 1844 1845 /* check 3 points again */ 1846 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x, 1847 compare_iq[0].phase_y, other_reg); 1848 if (rc < 0) 1849 return rc; 1850 1851 r820t_compre_cor(compare_iq); 1852 1853 /* section-9 check */ 1854 rc = r820t_section(priv, compare_iq); 1855 1856 *iq_pont = compare_iq[0]; 1857 1858 /* reset gain/phase control setting */ 1859 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f); 1860 if (rc < 0) 1861 return rc; 1862 1863 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f); 1864 1865 return rc; 1866 } 1867 1868 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont) 1869 { 1870 int rc; 1871 1872 r820t_vga_adjust(priv); 1873 1874 /* 1875 * search surrounding points from previous point 1876 * try (x-1), (x), (x+1) columns, and find min IMR result point 1877 */ 1878 rc = r820t_section(priv, iq_pont); 1879 if (rc < 0) 1880 return rc; 1881 1882 return 0; 1883 } 1884 1885 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag) 1886 { 1887 struct r820t_sect_type imr_point; 1888 int rc; 1889 u32 ring_vco, ring_freq, ring_ref; 1890 u8 n_ring, n; 1891 int reg18, reg19, reg1f; 1892 1893 if (priv->cfg->xtal > 24000000) 1894 ring_ref = priv->cfg->xtal / 2000; 1895 else 1896 ring_ref = priv->cfg->xtal / 1000; 1897 1898 n_ring = 15; 1899 for (n = 0; n < 16; n++) { 1900 if ((16 + n) * 8 * ring_ref >= 3100000) { 1901 n_ring = n; 1902 break; 1903 } 1904 } 1905 1906 reg18 = r820t_read_cache_reg(priv, 0x18); 1907 reg19 = r820t_read_cache_reg(priv, 0x19); 1908 reg1f = r820t_read_cache_reg(priv, 0x1f); 1909 1910 reg18 &= 0xf0; /* set ring[3:0] */ 1911 reg18 |= n_ring; 1912 1913 ring_vco = (16 + n_ring) * 8 * ring_ref; 1914 1915 reg18 &= 0xdf; /* clear ring_se23 */ 1916 reg19 &= 0xfc; /* clear ring_seldiv */ 1917 reg1f &= 0xfc; /* clear ring_att */ 1918 1919 switch (imr_mem) { 1920 case 0: 1921 ring_freq = ring_vco / 48; 1922 reg18 |= 0x20; /* ring_se23 = 1 */ 1923 reg19 |= 0x03; /* ring_seldiv = 3 */ 1924 reg1f |= 0x02; /* ring_att 10 */ 1925 break; 1926 case 1: 1927 ring_freq = ring_vco / 16; 1928 reg18 |= 0x00; /* ring_se23 = 0 */ 1929 reg19 |= 0x02; /* ring_seldiv = 2 */ 1930 reg1f |= 0x00; /* pw_ring 00 */ 1931 break; 1932 case 2: 1933 ring_freq = ring_vco / 8; 1934 reg18 |= 0x00; /* ring_se23 = 0 */ 1935 reg19 |= 0x01; /* ring_seldiv = 1 */ 1936 reg1f |= 0x03; /* pw_ring 11 */ 1937 break; 1938 case 3: 1939 ring_freq = ring_vco / 6; 1940 reg18 |= 0x20; /* ring_se23 = 1 */ 1941 reg19 |= 0x00; /* ring_seldiv = 0 */ 1942 reg1f |= 0x03; /* pw_ring 11 */ 1943 break; 1944 case 4: 1945 ring_freq = ring_vco / 4; 1946 reg18 |= 0x00; /* ring_se23 = 0 */ 1947 reg19 |= 0x00; /* ring_seldiv = 0 */ 1948 reg1f |= 0x01; /* pw_ring 01 */ 1949 break; 1950 default: 1951 ring_freq = ring_vco / 4; 1952 reg18 |= 0x00; /* ring_se23 = 0 */ 1953 reg19 |= 0x00; /* ring_seldiv = 0 */ 1954 reg1f |= 0x01; /* pw_ring 01 */ 1955 break; 1956 } 1957 1958 1959 /* write pw_ring, n_ring, ringdiv2 registers */ 1960 1961 /* n_ring, ring_se23 */ 1962 rc = r820t_write_reg(priv, 0x18, reg18); 1963 if (rc < 0) 1964 return rc; 1965 1966 /* ring_sediv */ 1967 rc = r820t_write_reg(priv, 0x19, reg19); 1968 if (rc < 0) 1969 return rc; 1970 1971 /* pw_ring */ 1972 rc = r820t_write_reg(priv, 0x1f, reg1f); 1973 if (rc < 0) 1974 return rc; 1975 1976 /* mux input freq ~ rf_in freq */ 1977 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000); 1978 if (rc < 0) 1979 return rc; 1980 1981 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV, 1982 (ring_freq - 5300) * 1000); 1983 if (!priv->has_lock) 1984 rc = -EINVAL; 1985 if (rc < 0) 1986 return rc; 1987 1988 if (im_flag) { 1989 rc = r820t_iq(priv, &imr_point); 1990 } else { 1991 imr_point.gain_x = priv->imr_data[3].gain_x; 1992 imr_point.phase_y = priv->imr_data[3].phase_y; 1993 imr_point.value = priv->imr_data[3].value; 1994 1995 rc = r820t_f_imr(priv, &imr_point); 1996 } 1997 if (rc < 0) 1998 return rc; 1999 2000 /* save IMR value */ 2001 switch (imr_mem) { 2002 case 0: 2003 priv->imr_data[0].gain_x = imr_point.gain_x; 2004 priv->imr_data[0].phase_y = imr_point.phase_y; 2005 priv->imr_data[0].value = imr_point.value; 2006 break; 2007 case 1: 2008 priv->imr_data[1].gain_x = imr_point.gain_x; 2009 priv->imr_data[1].phase_y = imr_point.phase_y; 2010 priv->imr_data[1].value = imr_point.value; 2011 break; 2012 case 2: 2013 priv->imr_data[2].gain_x = imr_point.gain_x; 2014 priv->imr_data[2].phase_y = imr_point.phase_y; 2015 priv->imr_data[2].value = imr_point.value; 2016 break; 2017 case 3: 2018 priv->imr_data[3].gain_x = imr_point.gain_x; 2019 priv->imr_data[3].phase_y = imr_point.phase_y; 2020 priv->imr_data[3].value = imr_point.value; 2021 break; 2022 case 4: 2023 priv->imr_data[4].gain_x = imr_point.gain_x; 2024 priv->imr_data[4].phase_y = imr_point.phase_y; 2025 priv->imr_data[4].value = imr_point.value; 2026 break; 2027 default: 2028 priv->imr_data[4].gain_x = imr_point.gain_x; 2029 priv->imr_data[4].phase_y = imr_point.phase_y; 2030 priv->imr_data[4].value = imr_point.value; 2031 break; 2032 } 2033 2034 return 0; 2035 } 2036 2037 static int r820t_imr_callibrate(struct r820t_priv *priv) 2038 { 2039 int rc, i; 2040 int xtal_cap = 0; 2041 2042 if (priv->init_done) 2043 return 0; 2044 2045 /* Detect Xtal capacitance */ 2046 if ((priv->cfg->rafael_chip == CHIP_R820T) || 2047 (priv->cfg->rafael_chip == CHIP_R828S) || 2048 (priv->cfg->rafael_chip == CHIP_R820C)) { 2049 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P; 2050 } else { 2051 /* Initialize registers */ 2052 rc = r820t_write(priv, 0x05, 2053 r820t_init_array, sizeof(r820t_init_array)); 2054 if (rc < 0) 2055 return rc; 2056 for (i = 0; i < 3; i++) { 2057 rc = r820t_xtal_check(priv); 2058 if (rc < 0) 2059 return rc; 2060 if (!i || rc > xtal_cap) 2061 xtal_cap = rc; 2062 } 2063 priv->xtal_cap_sel = xtal_cap; 2064 } 2065 2066 /* 2067 * Disables IMR callibration. That emulates the same behaviour 2068 * as what is done by rtl-sdr userspace library. Useful for testing 2069 */ 2070 if (no_imr_cal) { 2071 priv->init_done = true; 2072 2073 return 0; 2074 } 2075 2076 /* Initialize registers */ 2077 rc = r820t_write(priv, 0x05, 2078 r820t_init_array, sizeof(r820t_init_array)); 2079 if (rc < 0) 2080 return rc; 2081 2082 rc = r820t_imr_prepare(priv); 2083 if (rc < 0) 2084 return rc; 2085 2086 rc = r820t_imr(priv, 3, true); 2087 if (rc < 0) 2088 return rc; 2089 rc = r820t_imr(priv, 1, false); 2090 if (rc < 0) 2091 return rc; 2092 rc = r820t_imr(priv, 0, false); 2093 if (rc < 0) 2094 return rc; 2095 rc = r820t_imr(priv, 2, false); 2096 if (rc < 0) 2097 return rc; 2098 rc = r820t_imr(priv, 4, false); 2099 if (rc < 0) 2100 return rc; 2101 2102 priv->init_done = true; 2103 priv->imr_done = true; 2104 2105 return 0; 2106 } 2107 2108 #if 0 2109 /* Not used, for now */ 2110 static int r820t_gpio(struct r820t_priv *priv, bool enable) 2111 { 2112 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01); 2113 } 2114 #endif 2115 2116 /* 2117 * r820t frontend operations and tuner attach code 2118 * 2119 * All driver locks and i2c control are only in this part of the code 2120 */ 2121 2122 static int r820t_init(struct dvb_frontend *fe) 2123 { 2124 struct r820t_priv *priv = fe->tuner_priv; 2125 int rc; 2126 2127 tuner_dbg("%s:\n", __func__); 2128 2129 mutex_lock(&priv->lock); 2130 if (fe->ops.i2c_gate_ctrl) 2131 fe->ops.i2c_gate_ctrl(fe, 1); 2132 2133 rc = r820t_imr_callibrate(priv); 2134 if (rc < 0) 2135 goto err; 2136 2137 /* Initialize registers */ 2138 rc = r820t_write(priv, 0x05, 2139 r820t_init_array, sizeof(r820t_init_array)); 2140 2141 err: 2142 if (fe->ops.i2c_gate_ctrl) 2143 fe->ops.i2c_gate_ctrl(fe, 0); 2144 mutex_unlock(&priv->lock); 2145 2146 if (rc < 0) 2147 tuner_dbg("%s: failed=%d\n", __func__, rc); 2148 return rc; 2149 } 2150 2151 static int r820t_sleep(struct dvb_frontend *fe) 2152 { 2153 struct r820t_priv *priv = fe->tuner_priv; 2154 int rc; 2155 2156 tuner_dbg("%s:\n", __func__); 2157 2158 mutex_lock(&priv->lock); 2159 if (fe->ops.i2c_gate_ctrl) 2160 fe->ops.i2c_gate_ctrl(fe, 1); 2161 2162 rc = r820t_standby(priv); 2163 2164 if (fe->ops.i2c_gate_ctrl) 2165 fe->ops.i2c_gate_ctrl(fe, 0); 2166 mutex_unlock(&priv->lock); 2167 2168 tuner_dbg("%s: failed=%d\n", __func__, rc); 2169 return rc; 2170 } 2171 2172 static int r820t_set_analog_freq(struct dvb_frontend *fe, 2173 struct analog_parameters *p) 2174 { 2175 struct r820t_priv *priv = fe->tuner_priv; 2176 unsigned bw; 2177 int rc; 2178 2179 tuner_dbg("%s called\n", __func__); 2180 2181 /* if std is not defined, choose one */ 2182 if (!p->std) 2183 p->std = V4L2_STD_MN; 2184 2185 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC)) 2186 bw = 6; 2187 else 2188 bw = 8; 2189 2190 mutex_lock(&priv->lock); 2191 if (fe->ops.i2c_gate_ctrl) 2192 fe->ops.i2c_gate_ctrl(fe, 1); 2193 2194 rc = generic_set_freq(fe, 62500l * p->frequency, bw, 2195 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED); 2196 2197 if (fe->ops.i2c_gate_ctrl) 2198 fe->ops.i2c_gate_ctrl(fe, 0); 2199 mutex_unlock(&priv->lock); 2200 2201 return rc; 2202 } 2203 2204 static int r820t_set_params(struct dvb_frontend *fe) 2205 { 2206 struct r820t_priv *priv = fe->tuner_priv; 2207 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 2208 int rc; 2209 unsigned bw; 2210 2211 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", 2212 __func__, c->delivery_system, c->frequency, c->bandwidth_hz); 2213 2214 mutex_lock(&priv->lock); 2215 if (fe->ops.i2c_gate_ctrl) 2216 fe->ops.i2c_gate_ctrl(fe, 1); 2217 2218 bw = (c->bandwidth_hz + 500000) / 1000000; 2219 if (!bw) 2220 bw = 8; 2221 2222 rc = generic_set_freq(fe, c->frequency, bw, 2223 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system); 2224 2225 if (fe->ops.i2c_gate_ctrl) 2226 fe->ops.i2c_gate_ctrl(fe, 0); 2227 mutex_unlock(&priv->lock); 2228 2229 if (rc) 2230 tuner_dbg("%s: failed=%d\n", __func__, rc); 2231 return rc; 2232 } 2233 2234 static int r820t_signal(struct dvb_frontend *fe, u16 *strength) 2235 { 2236 struct r820t_priv *priv = fe->tuner_priv; 2237 int rc = 0; 2238 2239 mutex_lock(&priv->lock); 2240 if (fe->ops.i2c_gate_ctrl) 2241 fe->ops.i2c_gate_ctrl(fe, 1); 2242 2243 if (priv->has_lock) { 2244 rc = r820t_read_gain(priv); 2245 if (rc < 0) 2246 goto err; 2247 2248 /* A higher gain at LNA means a lower signal strength */ 2249 *strength = (45 - rc) << 4 | 0xff; 2250 if (*strength == 0xff) 2251 *strength = 0; 2252 } else { 2253 *strength = 0; 2254 } 2255 2256 err: 2257 if (fe->ops.i2c_gate_ctrl) 2258 fe->ops.i2c_gate_ctrl(fe, 0); 2259 mutex_unlock(&priv->lock); 2260 2261 tuner_dbg("%s: %s, gain=%d strength=%d\n", 2262 __func__, 2263 priv->has_lock ? "PLL locked" : "no signal", 2264 rc, *strength); 2265 2266 return 0; 2267 } 2268 2269 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 2270 { 2271 struct r820t_priv *priv = fe->tuner_priv; 2272 2273 tuner_dbg("%s:\n", __func__); 2274 2275 *frequency = priv->int_freq; 2276 2277 return 0; 2278 } 2279 2280 static void r820t_release(struct dvb_frontend *fe) 2281 { 2282 struct r820t_priv *priv = fe->tuner_priv; 2283 2284 tuner_dbg("%s:\n", __func__); 2285 2286 mutex_lock(&r820t_list_mutex); 2287 2288 if (priv) 2289 hybrid_tuner_release_state(priv); 2290 2291 mutex_unlock(&r820t_list_mutex); 2292 2293 fe->tuner_priv = NULL; 2294 } 2295 2296 static const struct dvb_tuner_ops r820t_tuner_ops = { 2297 .info = { 2298 .name = "Rafael Micro R820T", 2299 .frequency_min = 42000000, 2300 .frequency_max = 1002000000, 2301 }, 2302 .init = r820t_init, 2303 .release = r820t_release, 2304 .sleep = r820t_sleep, 2305 .set_params = r820t_set_params, 2306 .set_analog_params = r820t_set_analog_freq, 2307 .get_if_frequency = r820t_get_if_frequency, 2308 .get_rf_strength = r820t_signal, 2309 }; 2310 2311 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe, 2312 struct i2c_adapter *i2c, 2313 const struct r820t_config *cfg) 2314 { 2315 struct r820t_priv *priv; 2316 int rc = -ENODEV; 2317 u8 data[5]; 2318 int instance; 2319 2320 mutex_lock(&r820t_list_mutex); 2321 2322 instance = hybrid_tuner_request_state(struct r820t_priv, priv, 2323 hybrid_tuner_instance_list, 2324 i2c, cfg->i2c_addr, 2325 "r820t"); 2326 switch (instance) { 2327 case 0: 2328 /* memory allocation failure */ 2329 goto err_no_gate; 2330 case 1: 2331 /* new tuner instance */ 2332 priv->cfg = cfg; 2333 2334 mutex_init(&priv->lock); 2335 2336 fe->tuner_priv = priv; 2337 break; 2338 case 2: 2339 /* existing tuner instance */ 2340 fe->tuner_priv = priv; 2341 break; 2342 } 2343 2344 if (fe->ops.i2c_gate_ctrl) 2345 fe->ops.i2c_gate_ctrl(fe, 1); 2346 2347 /* check if the tuner is there */ 2348 rc = r820t_read(priv, 0x00, data, sizeof(data)); 2349 if (rc < 0) 2350 goto err; 2351 2352 rc = r820t_sleep(fe); 2353 if (rc < 0) 2354 goto err; 2355 2356 tuner_info("Rafael Micro r820t successfully identified\n"); 2357 2358 if (fe->ops.i2c_gate_ctrl) 2359 fe->ops.i2c_gate_ctrl(fe, 0); 2360 2361 mutex_unlock(&r820t_list_mutex); 2362 2363 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops, 2364 sizeof(struct dvb_tuner_ops)); 2365 2366 return fe; 2367 err: 2368 if (fe->ops.i2c_gate_ctrl) 2369 fe->ops.i2c_gate_ctrl(fe, 0); 2370 2371 err_no_gate: 2372 mutex_unlock(&r820t_list_mutex); 2373 2374 tuner_info("%s: failed=%d\n", __func__, rc); 2375 r820t_release(fe); 2376 return NULL; 2377 } 2378 EXPORT_SYMBOL_GPL(r820t_attach); 2379 2380 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver"); 2381 MODULE_AUTHOR("Mauro Carvalho Chehab"); 2382 MODULE_LICENSE("GPL v2"); 2383