1 /* 2 * Sharp QM1D1C0042 8PSK tuner driver 3 * 4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 /* 18 * NOTICE: 19 * As the disclosed information on the chip is very limited, 20 * this driver lacks some features, including chip config like IF freq. 21 * It assumes that users of this driver (such as a PCI bridge of 22 * DTV receiver cards) know the relevant info and 23 * configure the chip via I2C if necessary. 24 * 25 * Currently, PT3 driver is the only one that uses this driver, 26 * and contains init/config code in its firmware. 27 * Thus some part of the code might be dependent on PT3 specific config. 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/math64.h> 32 #include "qm1d1c0042.h" 33 34 #define QM1D1C0042_NUM_REGS 0x20 35 #define QM1D1C0042_NUM_REG_ROWS 2 36 37 static const u8 38 reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { { 39 0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33, 40 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 41 0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86, 42 0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00 43 }, { 44 0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33, 45 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 46 0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6, 47 0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00 48 } 49 }; 50 51 static int reg_index; 52 53 static const struct qm1d1c0042_config default_cfg = { 54 .xtal_freq = 16000, 55 .lpf = 1, 56 .fast_srch = 0, 57 .lpf_wait = 20, 58 .fast_srch_wait = 4, 59 .normal_srch_wait = 15, 60 }; 61 62 struct qm1d1c0042_state { 63 struct qm1d1c0042_config cfg; 64 struct i2c_client *i2c; 65 u8 regs[QM1D1C0042_NUM_REGS]; 66 }; 67 68 static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c) 69 { 70 return container_of(c, struct qm1d1c0042_state, cfg); 71 } 72 73 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) 74 { 75 u8 wbuf[2] = { reg, val }; 76 int ret; 77 78 ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf)); 79 if (ret >= 0 && ret < sizeof(wbuf)) 80 ret = -EIO; 81 return (ret == sizeof(wbuf)) ? 0 : ret; 82 } 83 84 static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val) 85 { 86 struct i2c_msg msgs[2] = { 87 { 88 .addr = state->i2c->addr, 89 .flags = 0, 90 .buf = ®, 91 .len = 1, 92 }, 93 { 94 .addr = state->i2c->addr, 95 .flags = I2C_M_RD, 96 .buf = val, 97 .len = 1, 98 }, 99 }; 100 int ret; 101 102 ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs)); 103 if (ret >= 0 && ret < ARRAY_SIZE(msgs)) 104 ret = -EIO; 105 return (ret == ARRAY_SIZE(msgs)) ? 0 : ret; 106 } 107 108 109 static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast) 110 { 111 if (fast) 112 state->regs[0x03] |= 0x01; /* set fast search mode */ 113 else 114 state->regs[0x03] &= ~0x01 & 0xff; 115 116 return reg_write(state, 0x03, state->regs[0x03]); 117 } 118 119 static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state) 120 { 121 int ret; 122 123 state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */ 124 state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */ 125 state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */ 126 ret = reg_write(state, 0x01, state->regs[0x01]); 127 if (ret == 0) 128 ret = reg_write(state, 0x05, state->regs[0x05]); 129 130 if (ret < 0) 131 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", 132 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id); 133 return ret; 134 } 135 136 /* tuner_ops */ 137 138 static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg) 139 { 140 struct qm1d1c0042_state *state; 141 struct qm1d1c0042_config *cfg; 142 143 state = fe->tuner_priv; 144 cfg = priv_cfg; 145 146 if (cfg->fe) 147 state->cfg.fe = cfg->fe; 148 149 if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT) 150 dev_warn(&state->i2c->dev, 151 "(%s) changing xtal_freq not supported. ", __func__); 152 state->cfg.xtal_freq = default_cfg.xtal_freq; 153 154 state->cfg.lpf = cfg->lpf; 155 state->cfg.fast_srch = cfg->fast_srch; 156 157 if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT) 158 state->cfg.lpf_wait = cfg->lpf_wait; 159 else 160 state->cfg.lpf_wait = default_cfg.lpf_wait; 161 162 if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT) 163 state->cfg.fast_srch_wait = cfg->fast_srch_wait; 164 else 165 state->cfg.fast_srch_wait = default_cfg.fast_srch_wait; 166 167 if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT) 168 state->cfg.normal_srch_wait = cfg->normal_srch_wait; 169 else 170 state->cfg.normal_srch_wait = default_cfg.normal_srch_wait; 171 return 0; 172 } 173 174 /* divisor, vco_band parameters */ 175 /* {maxfreq, param1(band?), param2(div?) */ 176 static const u32 conv_table[9][3] = { 177 { 2151000, 1, 7 }, 178 { 1950000, 1, 6 }, 179 { 1800000, 1, 5 }, 180 { 1600000, 1, 4 }, 181 { 1450000, 1, 3 }, 182 { 1250000, 1, 2 }, 183 { 1200000, 0, 7 }, 184 { 975000, 0, 6 }, 185 { 950000, 0, 0 } 186 }; 187 188 static int qm1d1c0042_set_params(struct dvb_frontend *fe) 189 { 190 struct qm1d1c0042_state *state; 191 u32 freq; 192 int i, ret; 193 u8 val, mask; 194 u32 a, sd; 195 s32 b; 196 197 state = fe->tuner_priv; 198 freq = fe->dtv_property_cache.frequency; 199 200 state->regs[0x08] &= 0xf0; 201 state->regs[0x08] |= 0x09; 202 203 state->regs[0x13] &= 0x9f; 204 state->regs[0x13] |= 0x20; 205 206 /* div2/vco_band */ 207 val = state->regs[0x02] & 0x0f; 208 for (i = 0; i < 8; i++) 209 if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) { 210 val |= conv_table[i][1] << 7; 211 val |= conv_table[i][2] << 4; 212 break; 213 } 214 ret = reg_write(state, 0x02, val); 215 if (ret < 0) 216 return ret; 217 218 a = (freq + state->cfg.xtal_freq / 2) / state->cfg.xtal_freq; 219 220 state->regs[0x06] &= 0x40; 221 state->regs[0x06] |= (a - 12) / 4; 222 ret = reg_write(state, 0x06, state->regs[0x06]); 223 if (ret < 0) 224 return ret; 225 226 state->regs[0x07] &= 0xf0; 227 state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f; 228 ret = reg_write(state, 0x07, state->regs[0x07]); 229 if (ret < 0) 230 return ret; 231 232 /* LPF */ 233 val = state->regs[0x08]; 234 if (state->cfg.lpf) { 235 /* LPF_CLK, LPF_FC */ 236 val &= 0xf0; 237 val |= 0x02; 238 } 239 ret = reg_write(state, 0x08, val); 240 if (ret < 0) 241 return ret; 242 243 /* 244 * b = (freq / state->cfg.xtal_freq - a) << 20; 245 * sd = b (b >= 0) 246 * 1<<22 + b (b < 0) 247 */ 248 b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq) 249 - (((s64) a) << 20); 250 251 if (b >= 0) 252 sd = b; 253 else 254 sd = (1 << 22) + b; 255 256 state->regs[0x09] &= 0xc0; 257 state->regs[0x09] |= (sd >> 16) & 0x3f; 258 state->regs[0x0a] = (sd >> 8) & 0xff; 259 state->regs[0x0b] = sd & 0xff; 260 ret = reg_write(state, 0x09, state->regs[0x09]); 261 if (ret == 0) 262 ret = reg_write(state, 0x0a, state->regs[0x0a]); 263 if (ret == 0) 264 ret = reg_write(state, 0x0b, state->regs[0x0b]); 265 if (ret != 0) 266 return ret; 267 268 if (!state->cfg.lpf) { 269 /* CSEL_Offset */ 270 ret = reg_write(state, 0x13, state->regs[0x13]); 271 if (ret < 0) 272 return ret; 273 } 274 275 /* VCO_TM, LPF_TM */ 276 mask = state->cfg.lpf ? 0x3f : 0x7f; 277 val = state->regs[0x0c] & mask; 278 ret = reg_write(state, 0x0c, val); 279 if (ret < 0) 280 return ret; 281 usleep_range(2000, 3000); 282 val = state->regs[0x0c] | ~mask; 283 ret = reg_write(state, 0x0c, val); 284 if (ret < 0) 285 return ret; 286 287 if (state->cfg.lpf) 288 msleep(state->cfg.lpf_wait); 289 else if (state->regs[0x03] & 0x01) 290 msleep(state->cfg.fast_srch_wait); 291 else 292 msleep(state->cfg.normal_srch_wait); 293 294 if (state->cfg.lpf) { 295 /* LPF_FC */ 296 ret = reg_write(state, 0x08, 0x09); 297 if (ret < 0) 298 return ret; 299 300 /* CSEL_Offset */ 301 ret = reg_write(state, 0x13, state->regs[0x13]); 302 if (ret < 0) 303 return ret; 304 } 305 return 0; 306 } 307 308 static int qm1d1c0042_sleep(struct dvb_frontend *fe) 309 { 310 struct qm1d1c0042_state *state; 311 int ret; 312 313 state = fe->tuner_priv; 314 state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */ 315 state->regs[0x01] |= 1 << 0; /* STDBY */ 316 state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */ 317 ret = reg_write(state, 0x05, state->regs[0x05]); 318 if (ret == 0) 319 ret = reg_write(state, 0x01, state->regs[0x01]); 320 if (ret < 0) 321 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", 322 __func__, fe->dvb->num, fe->id); 323 return ret; 324 } 325 326 static int qm1d1c0042_init(struct dvb_frontend *fe) 327 { 328 struct qm1d1c0042_state *state; 329 u8 val; 330 int i, ret; 331 332 state = fe->tuner_priv; 333 334 reg_write(state, 0x01, 0x0c); 335 reg_write(state, 0x01, 0x0c); 336 337 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */ 338 if (ret < 0) 339 goto failed; 340 usleep_range(2000, 3000); 341 342 ret = reg_write(state, 0x01, 0x1c); /* soft reset off */ 343 if (ret < 0) 344 goto failed; 345 346 /* check ID and choose initial registers corresponding ID */ 347 ret = reg_read(state, 0x00, &val); 348 if (ret < 0) 349 goto failed; 350 for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS; 351 reg_index++) { 352 if (val == reg_initval[reg_index][0x00]) 353 break; 354 } 355 if (reg_index >= QM1D1C0042_NUM_REG_ROWS) 356 goto failed; 357 memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS); 358 usleep_range(2000, 3000); 359 360 state->regs[0x0c] |= 0x40; 361 ret = reg_write(state, 0x0c, state->regs[0x0c]); 362 if (ret < 0) 363 goto failed; 364 msleep(state->cfg.lpf_wait); 365 366 /* set all writable registers */ 367 for (i = 1; i <= 0x0c ; i++) { 368 ret = reg_write(state, i, state->regs[i]); 369 if (ret < 0) 370 goto failed; 371 } 372 for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) { 373 ret = reg_write(state, i, state->regs[i]); 374 if (ret < 0) 375 goto failed; 376 } 377 378 ret = qm1d1c0042_wakeup(state); 379 if (ret < 0) 380 goto failed; 381 382 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch); 383 if (ret < 0) 384 goto failed; 385 386 return ret; 387 388 failed: 389 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", 390 __func__, fe->dvb->num, fe->id); 391 return ret; 392 } 393 394 /* I2C driver functions */ 395 396 static const struct dvb_tuner_ops qm1d1c0042_ops = { 397 .info = { 398 .name = "Sharp QM1D1C0042", 399 400 .frequency_min = 950000, 401 .frequency_max = 2150000, 402 }, 403 404 .init = qm1d1c0042_init, 405 .sleep = qm1d1c0042_sleep, 406 .set_config = qm1d1c0042_set_config, 407 .set_params = qm1d1c0042_set_params, 408 }; 409 410 411 static int qm1d1c0042_probe(struct i2c_client *client, 412 const struct i2c_device_id *id) 413 { 414 struct qm1d1c0042_state *state; 415 struct qm1d1c0042_config *cfg; 416 struct dvb_frontend *fe; 417 418 state = kzalloc(sizeof(*state), GFP_KERNEL); 419 if (!state) 420 return -ENOMEM; 421 state->i2c = client; 422 423 cfg = client->dev.platform_data; 424 fe = cfg->fe; 425 fe->tuner_priv = state; 426 qm1d1c0042_set_config(fe, cfg); 427 memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops)); 428 429 i2c_set_clientdata(client, &state->cfg); 430 dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n"); 431 return 0; 432 } 433 434 static int qm1d1c0042_remove(struct i2c_client *client) 435 { 436 struct qm1d1c0042_state *state; 437 438 state = cfg_to_state(i2c_get_clientdata(client)); 439 state->cfg.fe->tuner_priv = NULL; 440 kfree(state); 441 return 0; 442 } 443 444 445 static const struct i2c_device_id qm1d1c0042_id[] = { 446 {"qm1d1c0042", 0}, 447 {} 448 }; 449 MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id); 450 451 static struct i2c_driver qm1d1c0042_driver = { 452 .driver = { 453 .name = "qm1d1c0042", 454 }, 455 .probe = qm1d1c0042_probe, 456 .remove = qm1d1c0042_remove, 457 .id_table = qm1d1c0042_id, 458 }; 459 460 module_i2c_driver(qm1d1c0042_driver); 461 462 MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner"); 463 MODULE_AUTHOR("Akihiro TSUKADA"); 464 MODULE_LICENSE("GPL"); 465