1 /* 2 * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner 3 * 4 * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/i2c.h> 18 #include <linux/types.h> 19 #include <linux/videodev2.h> 20 #include "tuner-i2c.h" 21 #include "mxl5007t.h" 22 23 static DEFINE_MUTEX(mxl5007t_list_mutex); 24 static LIST_HEAD(hybrid_tuner_instance_list); 25 26 static int mxl5007t_debug; 27 module_param_named(debug, mxl5007t_debug, int, 0644); 28 MODULE_PARM_DESC(debug, "set debug level"); 29 30 /* ------------------------------------------------------------------------- */ 31 32 #define mxl_printk(kern, fmt, arg...) \ 33 printk(kern "%s: " fmt "\n", __func__, ##arg) 34 35 #define mxl_err(fmt, arg...) \ 36 mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg) 37 38 #define mxl_warn(fmt, arg...) \ 39 mxl_printk(KERN_WARNING, fmt, ##arg) 40 41 #define mxl_info(fmt, arg...) \ 42 mxl_printk(KERN_INFO, fmt, ##arg) 43 44 #define mxl_debug(fmt, arg...) \ 45 ({ \ 46 if (mxl5007t_debug) \ 47 mxl_printk(KERN_DEBUG, fmt, ##arg); \ 48 }) 49 50 #define mxl_fail(ret) \ 51 ({ \ 52 int __ret; \ 53 __ret = (ret < 0); \ 54 if (__ret) \ 55 mxl_printk(KERN_ERR, "error %d on line %d", \ 56 ret, __LINE__); \ 57 __ret; \ 58 }) 59 60 /* ------------------------------------------------------------------------- */ 61 62 #define MHz 1000000 63 64 enum mxl5007t_mode { 65 MxL_MODE_ISDBT = 0, 66 MxL_MODE_DVBT = 1, 67 MxL_MODE_ATSC = 2, 68 MxL_MODE_CABLE = 0x10, 69 }; 70 71 enum mxl5007t_chip_version { 72 MxL_UNKNOWN_ID = 0x00, 73 MxL_5007_V1_F1 = 0x11, 74 MxL_5007_V1_F2 = 0x12, 75 MxL_5007_V4 = 0x14, 76 MxL_5007_V2_100_F1 = 0x21, 77 MxL_5007_V2_100_F2 = 0x22, 78 MxL_5007_V2_200_F1 = 0x23, 79 MxL_5007_V2_200_F2 = 0x24, 80 }; 81 82 struct reg_pair_t { 83 u8 reg; 84 u8 val; 85 }; 86 87 /* ------------------------------------------------------------------------- */ 88 89 static struct reg_pair_t init_tab[] = { 90 { 0x02, 0x06 }, 91 { 0x03, 0x48 }, 92 { 0x05, 0x04 }, 93 { 0x06, 0x10 }, 94 { 0x2e, 0x15 }, /* OVERRIDE */ 95 { 0x30, 0x10 }, /* OVERRIDE */ 96 { 0x45, 0x58 }, /* OVERRIDE */ 97 { 0x48, 0x19 }, /* OVERRIDE */ 98 { 0x52, 0x03 }, /* OVERRIDE */ 99 { 0x53, 0x44 }, /* OVERRIDE */ 100 { 0x6a, 0x4b }, /* OVERRIDE */ 101 { 0x76, 0x00 }, /* OVERRIDE */ 102 { 0x78, 0x18 }, /* OVERRIDE */ 103 { 0x7a, 0x17 }, /* OVERRIDE */ 104 { 0x85, 0x06 }, /* OVERRIDE */ 105 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */ 106 { 0, 0 } 107 }; 108 109 static struct reg_pair_t init_tab_cable[] = { 110 { 0x02, 0x06 }, 111 { 0x03, 0x48 }, 112 { 0x05, 0x04 }, 113 { 0x06, 0x10 }, 114 { 0x09, 0x3f }, 115 { 0x0a, 0x3f }, 116 { 0x0b, 0x3f }, 117 { 0x2e, 0x15 }, /* OVERRIDE */ 118 { 0x30, 0x10 }, /* OVERRIDE */ 119 { 0x45, 0x58 }, /* OVERRIDE */ 120 { 0x48, 0x19 }, /* OVERRIDE */ 121 { 0x52, 0x03 }, /* OVERRIDE */ 122 { 0x53, 0x44 }, /* OVERRIDE */ 123 { 0x6a, 0x4b }, /* OVERRIDE */ 124 { 0x76, 0x00 }, /* OVERRIDE */ 125 { 0x78, 0x18 }, /* OVERRIDE */ 126 { 0x7a, 0x17 }, /* OVERRIDE */ 127 { 0x85, 0x06 }, /* OVERRIDE */ 128 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */ 129 { 0, 0 } 130 }; 131 132 /* ------------------------------------------------------------------------- */ 133 134 static struct reg_pair_t reg_pair_rftune[] = { 135 { 0x0f, 0x00 }, /* abort tune */ 136 { 0x0c, 0x15 }, 137 { 0x0d, 0x40 }, 138 { 0x0e, 0x0e }, 139 { 0x1f, 0x87 }, /* OVERRIDE */ 140 { 0x20, 0x1f }, /* OVERRIDE */ 141 { 0x21, 0x87 }, /* OVERRIDE */ 142 { 0x22, 0x1f }, /* OVERRIDE */ 143 { 0x80, 0x01 }, /* freq dependent */ 144 { 0x0f, 0x01 }, /* start tune */ 145 { 0, 0 } 146 }; 147 148 /* ------------------------------------------------------------------------- */ 149 150 struct mxl5007t_state { 151 struct list_head hybrid_tuner_instance_list; 152 struct tuner_i2c_props i2c_props; 153 154 struct mutex lock; 155 156 struct mxl5007t_config *config; 157 158 enum mxl5007t_chip_version chip_id; 159 160 struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)]; 161 struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)]; 162 struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)]; 163 164 enum mxl5007t_if_freq if_freq; 165 166 u32 frequency; 167 u32 bandwidth; 168 }; 169 170 /* ------------------------------------------------------------------------- */ 171 172 /* called by _init and _rftun to manipulate the register arrays */ 173 174 static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val) 175 { 176 unsigned int i = 0; 177 178 while (reg_pair[i].reg || reg_pair[i].val) { 179 if (reg_pair[i].reg == reg) { 180 reg_pair[i].val &= ~mask; 181 reg_pair[i].val |= val; 182 } 183 i++; 184 185 } 186 return; 187 } 188 189 static void copy_reg_bits(struct reg_pair_t *reg_pair1, 190 struct reg_pair_t *reg_pair2) 191 { 192 unsigned int i, j; 193 194 i = j = 0; 195 196 while (reg_pair1[i].reg || reg_pair1[i].val) { 197 while (reg_pair2[j].reg || reg_pair2[j].val) { 198 if (reg_pair1[i].reg != reg_pair2[j].reg) { 199 j++; 200 continue; 201 } 202 reg_pair2[j].val = reg_pair1[i].val; 203 break; 204 } 205 i++; 206 } 207 return; 208 } 209 210 /* ------------------------------------------------------------------------- */ 211 212 static void mxl5007t_set_mode_bits(struct mxl5007t_state *state, 213 enum mxl5007t_mode mode, 214 s32 if_diff_out_level) 215 { 216 switch (mode) { 217 case MxL_MODE_ATSC: 218 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12); 219 break; 220 case MxL_MODE_DVBT: 221 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11); 222 break; 223 case MxL_MODE_ISDBT: 224 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10); 225 break; 226 case MxL_MODE_CABLE: 227 set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1); 228 set_reg_bits(state->tab_init_cable, 0x0a, 0xff, 229 8 - if_diff_out_level); 230 set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17); 231 break; 232 default: 233 mxl_fail(-EINVAL); 234 } 235 return; 236 } 237 238 static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, 239 enum mxl5007t_if_freq if_freq, 240 int invert_if) 241 { 242 u8 val; 243 244 switch (if_freq) { 245 case MxL_IF_4_MHZ: 246 val = 0x00; 247 break; 248 case MxL_IF_4_5_MHZ: 249 val = 0x02; 250 break; 251 case MxL_IF_4_57_MHZ: 252 val = 0x03; 253 break; 254 case MxL_IF_5_MHZ: 255 val = 0x04; 256 break; 257 case MxL_IF_5_38_MHZ: 258 val = 0x05; 259 break; 260 case MxL_IF_6_MHZ: 261 val = 0x06; 262 break; 263 case MxL_IF_6_28_MHZ: 264 val = 0x07; 265 break; 266 case MxL_IF_9_1915_MHZ: 267 val = 0x08; 268 break; 269 case MxL_IF_35_25_MHZ: 270 val = 0x09; 271 break; 272 case MxL_IF_36_15_MHZ: 273 val = 0x0a; 274 break; 275 case MxL_IF_44_MHZ: 276 val = 0x0b; 277 break; 278 default: 279 mxl_fail(-EINVAL); 280 return; 281 } 282 set_reg_bits(state->tab_init, 0x02, 0x0f, val); 283 284 /* set inverted IF or normal IF */ 285 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00); 286 287 state->if_freq = if_freq; 288 289 return; 290 } 291 292 static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, 293 enum mxl5007t_xtal_freq xtal_freq) 294 { 295 switch (xtal_freq) { 296 case MxL_XTAL_16_MHZ: 297 /* select xtal freq & ref freq */ 298 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00); 299 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00); 300 break; 301 case MxL_XTAL_20_MHZ: 302 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10); 303 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01); 304 break; 305 case MxL_XTAL_20_25_MHZ: 306 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20); 307 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02); 308 break; 309 case MxL_XTAL_20_48_MHZ: 310 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30); 311 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03); 312 break; 313 case MxL_XTAL_24_MHZ: 314 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40); 315 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04); 316 break; 317 case MxL_XTAL_25_MHZ: 318 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50); 319 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05); 320 break; 321 case MxL_XTAL_25_14_MHZ: 322 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60); 323 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06); 324 break; 325 case MxL_XTAL_27_MHZ: 326 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70); 327 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07); 328 break; 329 case MxL_XTAL_28_8_MHZ: 330 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80); 331 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08); 332 break; 333 case MxL_XTAL_32_MHZ: 334 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90); 335 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09); 336 break; 337 case MxL_XTAL_40_MHZ: 338 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0); 339 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a); 340 break; 341 case MxL_XTAL_44_MHZ: 342 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0); 343 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b); 344 break; 345 case MxL_XTAL_48_MHZ: 346 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0); 347 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c); 348 break; 349 case MxL_XTAL_49_3811_MHZ: 350 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0); 351 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d); 352 break; 353 default: 354 mxl_fail(-EINVAL); 355 return; 356 } 357 358 return; 359 } 360 361 static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state, 362 enum mxl5007t_mode mode) 363 { 364 struct mxl5007t_config *cfg = state->config; 365 366 memcpy(&state->tab_init, &init_tab, sizeof(init_tab)); 367 memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable)); 368 369 mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level); 370 mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); 371 mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); 372 373 set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3); 374 set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp); 375 376 if (mode >= MxL_MODE_CABLE) { 377 copy_reg_bits(state->tab_init, state->tab_init_cable); 378 return state->tab_init_cable; 379 } else 380 return state->tab_init; 381 } 382 383 /* ------------------------------------------------------------------------- */ 384 385 enum mxl5007t_bw_mhz { 386 MxL_BW_6MHz = 6, 387 MxL_BW_7MHz = 7, 388 MxL_BW_8MHz = 8, 389 }; 390 391 static void mxl5007t_set_bw_bits(struct mxl5007t_state *state, 392 enum mxl5007t_bw_mhz bw) 393 { 394 u8 val; 395 396 switch (bw) { 397 case MxL_BW_6MHz: 398 val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A, 399 * and DIG_MODEINDEX_CSF */ 400 break; 401 case MxL_BW_7MHz: 402 val = 0x2a; 403 break; 404 case MxL_BW_8MHz: 405 val = 0x3f; 406 break; 407 default: 408 mxl_fail(-EINVAL); 409 return; 410 } 411 set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val); 412 413 return; 414 } 415 416 static struct 417 reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state, 418 u32 rf_freq, enum mxl5007t_bw_mhz bw) 419 { 420 u32 dig_rf_freq = 0; 421 u32 temp; 422 u32 frac_divider = 1000000; 423 unsigned int i; 424 425 memcpy(&state->tab_rftune, ®_pair_rftune, sizeof(reg_pair_rftune)); 426 427 mxl5007t_set_bw_bits(state, bw); 428 429 /* Convert RF frequency into 16 bits => 430 * 10 bit integer (MHz) + 6 bit fraction */ 431 dig_rf_freq = rf_freq / MHz; 432 433 temp = rf_freq % MHz; 434 435 for (i = 0; i < 6; i++) { 436 dig_rf_freq <<= 1; 437 frac_divider /= 2; 438 if (temp > frac_divider) { 439 temp -= frac_divider; 440 dig_rf_freq++; 441 } 442 } 443 444 /* add to have shift center point by 7.8124 kHz */ 445 if (temp > 7812) 446 dig_rf_freq++; 447 448 set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq); 449 set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8)); 450 451 if (rf_freq >= 333000000) 452 set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40); 453 454 return state->tab_rftune; 455 } 456 457 /* ------------------------------------------------------------------------- */ 458 459 static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val) 460 { 461 u8 buf[] = { reg, val }; 462 struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0, 463 .buf = buf, .len = 2 }; 464 int ret; 465 466 ret = i2c_transfer(state->i2c_props.adap, &msg, 1); 467 if (ret != 1) { 468 mxl_err("failed!"); 469 return -EREMOTEIO; 470 } 471 return 0; 472 } 473 474 static int mxl5007t_write_regs(struct mxl5007t_state *state, 475 struct reg_pair_t *reg_pair) 476 { 477 unsigned int i = 0; 478 int ret = 0; 479 480 while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) { 481 ret = mxl5007t_write_reg(state, 482 reg_pair[i].reg, reg_pair[i].val); 483 i++; 484 } 485 return ret; 486 } 487 488 static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) 489 { 490 u8 buf[2] = { 0xfb, reg }; 491 struct i2c_msg msg[] = { 492 { .addr = state->i2c_props.addr, .flags = 0, 493 .buf = buf, .len = 2 }, 494 { .addr = state->i2c_props.addr, .flags = I2C_M_RD, 495 .buf = val, .len = 1 }, 496 }; 497 int ret; 498 499 ret = i2c_transfer(state->i2c_props.adap, msg, 2); 500 if (ret != 2) { 501 mxl_err("failed!"); 502 return -EREMOTEIO; 503 } 504 return 0; 505 } 506 507 static int mxl5007t_soft_reset(struct mxl5007t_state *state) 508 { 509 u8 d = 0xff; 510 struct i2c_msg msg = { 511 .addr = state->i2c_props.addr, .flags = 0, 512 .buf = &d, .len = 1 513 }; 514 int ret = i2c_transfer(state->i2c_props.adap, &msg, 1); 515 516 if (ret != 1) { 517 mxl_err("failed!"); 518 return -EREMOTEIO; 519 } 520 return 0; 521 } 522 523 static int mxl5007t_tuner_init(struct mxl5007t_state *state, 524 enum mxl5007t_mode mode) 525 { 526 struct reg_pair_t *init_regs; 527 int ret; 528 529 /* calculate initialization reg array */ 530 init_regs = mxl5007t_calc_init_regs(state, mode); 531 532 ret = mxl5007t_write_regs(state, init_regs); 533 if (mxl_fail(ret)) 534 goto fail; 535 mdelay(1); 536 fail: 537 return ret; 538 } 539 540 static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz, 541 enum mxl5007t_bw_mhz bw) 542 { 543 struct reg_pair_t *rf_tune_regs; 544 int ret; 545 546 /* calculate channel change reg array */ 547 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw); 548 549 ret = mxl5007t_write_regs(state, rf_tune_regs); 550 if (mxl_fail(ret)) 551 goto fail; 552 msleep(3); 553 fail: 554 return ret; 555 } 556 557 /* ------------------------------------------------------------------------- */ 558 559 static int mxl5007t_synth_lock_status(struct mxl5007t_state *state, 560 int *rf_locked, int *ref_locked) 561 { 562 u8 d; 563 int ret; 564 565 *rf_locked = 0; 566 *ref_locked = 0; 567 568 ret = mxl5007t_read_reg(state, 0xd8, &d); 569 if (mxl_fail(ret)) 570 goto fail; 571 572 if ((d & 0x0c) == 0x0c) 573 *rf_locked = 1; 574 575 if ((d & 0x03) == 0x03) 576 *ref_locked = 1; 577 fail: 578 return ret; 579 } 580 581 /* ------------------------------------------------------------------------- */ 582 583 static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status) 584 { 585 struct mxl5007t_state *state = fe->tuner_priv; 586 int rf_locked, ref_locked, ret; 587 588 *status = 0; 589 590 if (fe->ops.i2c_gate_ctrl) 591 fe->ops.i2c_gate_ctrl(fe, 1); 592 593 ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked); 594 if (mxl_fail(ret)) 595 goto fail; 596 mxl_debug("%s%s", rf_locked ? "rf locked " : "", 597 ref_locked ? "ref locked" : ""); 598 599 if ((rf_locked) || (ref_locked)) 600 *status |= TUNER_STATUS_LOCKED; 601 fail: 602 if (fe->ops.i2c_gate_ctrl) 603 fe->ops.i2c_gate_ctrl(fe, 0); 604 605 return ret; 606 } 607 608 /* ------------------------------------------------------------------------- */ 609 610 static int mxl5007t_set_params(struct dvb_frontend *fe) 611 { 612 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 613 u32 delsys = c->delivery_system; 614 struct mxl5007t_state *state = fe->tuner_priv; 615 enum mxl5007t_bw_mhz bw; 616 enum mxl5007t_mode mode; 617 int ret; 618 u32 freq = c->frequency; 619 620 switch (delsys) { 621 case SYS_ATSC: 622 mode = MxL_MODE_ATSC; 623 bw = MxL_BW_6MHz; 624 break; 625 case SYS_DVBC_ANNEX_B: 626 mode = MxL_MODE_CABLE; 627 bw = MxL_BW_6MHz; 628 break; 629 case SYS_DVBT: 630 case SYS_DVBT2: 631 mode = MxL_MODE_DVBT; 632 switch (c->bandwidth_hz) { 633 case 6000000: 634 bw = MxL_BW_6MHz; 635 break; 636 case 7000000: 637 bw = MxL_BW_7MHz; 638 break; 639 case 8000000: 640 bw = MxL_BW_8MHz; 641 break; 642 default: 643 return -EINVAL; 644 } 645 break; 646 default: 647 mxl_err("modulation type not supported!"); 648 return -EINVAL; 649 } 650 651 if (fe->ops.i2c_gate_ctrl) 652 fe->ops.i2c_gate_ctrl(fe, 1); 653 654 mutex_lock(&state->lock); 655 656 ret = mxl5007t_tuner_init(state, mode); 657 if (mxl_fail(ret)) 658 goto fail; 659 660 ret = mxl5007t_tuner_rf_tune(state, freq, bw); 661 if (mxl_fail(ret)) 662 goto fail; 663 664 state->frequency = freq; 665 state->bandwidth = c->bandwidth_hz; 666 fail: 667 mutex_unlock(&state->lock); 668 669 if (fe->ops.i2c_gate_ctrl) 670 fe->ops.i2c_gate_ctrl(fe, 0); 671 672 return ret; 673 } 674 675 /* ------------------------------------------------------------------------- */ 676 677 static int mxl5007t_init(struct dvb_frontend *fe) 678 { 679 struct mxl5007t_state *state = fe->tuner_priv; 680 int ret; 681 682 if (fe->ops.i2c_gate_ctrl) 683 fe->ops.i2c_gate_ctrl(fe, 1); 684 685 /* wake from standby */ 686 ret = mxl5007t_write_reg(state, 0x01, 0x01); 687 mxl_fail(ret); 688 689 if (fe->ops.i2c_gate_ctrl) 690 fe->ops.i2c_gate_ctrl(fe, 0); 691 692 return ret; 693 } 694 695 static int mxl5007t_sleep(struct dvb_frontend *fe) 696 { 697 struct mxl5007t_state *state = fe->tuner_priv; 698 int ret; 699 700 if (fe->ops.i2c_gate_ctrl) 701 fe->ops.i2c_gate_ctrl(fe, 1); 702 703 /* enter standby mode */ 704 ret = mxl5007t_write_reg(state, 0x01, 0x00); 705 mxl_fail(ret); 706 ret = mxl5007t_write_reg(state, 0x0f, 0x00); 707 mxl_fail(ret); 708 709 if (fe->ops.i2c_gate_ctrl) 710 fe->ops.i2c_gate_ctrl(fe, 0); 711 712 return ret; 713 } 714 715 /* ------------------------------------------------------------------------- */ 716 717 static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency) 718 { 719 struct mxl5007t_state *state = fe->tuner_priv; 720 *frequency = state->frequency; 721 return 0; 722 } 723 724 static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 725 { 726 struct mxl5007t_state *state = fe->tuner_priv; 727 *bandwidth = state->bandwidth; 728 return 0; 729 } 730 731 static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 732 { 733 struct mxl5007t_state *state = fe->tuner_priv; 734 735 *frequency = 0; 736 737 switch (state->if_freq) { 738 case MxL_IF_4_MHZ: 739 *frequency = 4000000; 740 break; 741 case MxL_IF_4_5_MHZ: 742 *frequency = 4500000; 743 break; 744 case MxL_IF_4_57_MHZ: 745 *frequency = 4570000; 746 break; 747 case MxL_IF_5_MHZ: 748 *frequency = 5000000; 749 break; 750 case MxL_IF_5_38_MHZ: 751 *frequency = 5380000; 752 break; 753 case MxL_IF_6_MHZ: 754 *frequency = 6000000; 755 break; 756 case MxL_IF_6_28_MHZ: 757 *frequency = 6280000; 758 break; 759 case MxL_IF_9_1915_MHZ: 760 *frequency = 9191500; 761 break; 762 case MxL_IF_35_25_MHZ: 763 *frequency = 35250000; 764 break; 765 case MxL_IF_36_15_MHZ: 766 *frequency = 36150000; 767 break; 768 case MxL_IF_44_MHZ: 769 *frequency = 44000000; 770 break; 771 } 772 return 0; 773 } 774 775 static void mxl5007t_release(struct dvb_frontend *fe) 776 { 777 struct mxl5007t_state *state = fe->tuner_priv; 778 779 mutex_lock(&mxl5007t_list_mutex); 780 781 if (state) 782 hybrid_tuner_release_state(state); 783 784 mutex_unlock(&mxl5007t_list_mutex); 785 786 fe->tuner_priv = NULL; 787 } 788 789 /* ------------------------------------------------------------------------- */ 790 791 static const struct dvb_tuner_ops mxl5007t_tuner_ops = { 792 .info = { 793 .name = "MaxLinear MxL5007T", 794 }, 795 .init = mxl5007t_init, 796 .sleep = mxl5007t_sleep, 797 .set_params = mxl5007t_set_params, 798 .get_status = mxl5007t_get_status, 799 .get_frequency = mxl5007t_get_frequency, 800 .get_bandwidth = mxl5007t_get_bandwidth, 801 .release = mxl5007t_release, 802 .get_if_frequency = mxl5007t_get_if_frequency, 803 }; 804 805 static int mxl5007t_get_chip_id(struct mxl5007t_state *state) 806 { 807 char *name; 808 int ret; 809 u8 id; 810 811 ret = mxl5007t_read_reg(state, 0xd9, &id); 812 if (mxl_fail(ret)) 813 goto fail; 814 815 switch (id) { 816 case MxL_5007_V1_F1: 817 name = "MxL5007.v1.f1"; 818 break; 819 case MxL_5007_V1_F2: 820 name = "MxL5007.v1.f2"; 821 break; 822 case MxL_5007_V2_100_F1: 823 name = "MxL5007.v2.100.f1"; 824 break; 825 case MxL_5007_V2_100_F2: 826 name = "MxL5007.v2.100.f2"; 827 break; 828 case MxL_5007_V2_200_F1: 829 name = "MxL5007.v2.200.f1"; 830 break; 831 case MxL_5007_V2_200_F2: 832 name = "MxL5007.v2.200.f2"; 833 break; 834 case MxL_5007_V4: 835 name = "MxL5007T.v4"; 836 break; 837 default: 838 name = "MxL5007T"; 839 printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id); 840 id = MxL_UNKNOWN_ID; 841 } 842 state->chip_id = id; 843 mxl_info("%s detected @ %d-%04x", name, 844 i2c_adapter_id(state->i2c_props.adap), 845 state->i2c_props.addr); 846 return 0; 847 fail: 848 mxl_warn("unable to identify device @ %d-%04x", 849 i2c_adapter_id(state->i2c_props.adap), 850 state->i2c_props.addr); 851 852 state->chip_id = MxL_UNKNOWN_ID; 853 return ret; 854 } 855 856 struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe, 857 struct i2c_adapter *i2c, u8 addr, 858 struct mxl5007t_config *cfg) 859 { 860 struct mxl5007t_state *state = NULL; 861 int instance, ret; 862 863 mutex_lock(&mxl5007t_list_mutex); 864 instance = hybrid_tuner_request_state(struct mxl5007t_state, state, 865 hybrid_tuner_instance_list, 866 i2c, addr, "mxl5007t"); 867 switch (instance) { 868 case 0: 869 goto fail; 870 case 1: 871 /* new tuner instance */ 872 state->config = cfg; 873 874 mutex_init(&state->lock); 875 876 if (fe->ops.i2c_gate_ctrl) 877 fe->ops.i2c_gate_ctrl(fe, 1); 878 879 ret = mxl5007t_get_chip_id(state); 880 881 if (fe->ops.i2c_gate_ctrl) 882 fe->ops.i2c_gate_ctrl(fe, 0); 883 884 /* check return value of mxl5007t_get_chip_id */ 885 if (mxl_fail(ret)) 886 goto fail; 887 break; 888 default: 889 /* existing tuner instance */ 890 break; 891 } 892 893 if (fe->ops.i2c_gate_ctrl) 894 fe->ops.i2c_gate_ctrl(fe, 1); 895 896 ret = mxl5007t_soft_reset(state); 897 898 if (fe->ops.i2c_gate_ctrl) 899 fe->ops.i2c_gate_ctrl(fe, 0); 900 901 if (mxl_fail(ret)) 902 goto fail; 903 904 if (fe->ops.i2c_gate_ctrl) 905 fe->ops.i2c_gate_ctrl(fe, 1); 906 907 ret = mxl5007t_write_reg(state, 0x04, 908 state->config->loop_thru_enable); 909 910 if (fe->ops.i2c_gate_ctrl) 911 fe->ops.i2c_gate_ctrl(fe, 0); 912 913 if (mxl_fail(ret)) 914 goto fail; 915 916 fe->tuner_priv = state; 917 918 mutex_unlock(&mxl5007t_list_mutex); 919 920 memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops, 921 sizeof(struct dvb_tuner_ops)); 922 923 return fe; 924 fail: 925 mutex_unlock(&mxl5007t_list_mutex); 926 927 mxl5007t_release(fe); 928 return NULL; 929 } 930 EXPORT_SYMBOL_GPL(mxl5007t_attach); 931 MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver"); 932 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); 933 MODULE_LICENSE("GPL"); 934 MODULE_VERSION("0.2"); 935