1 /* 2 * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner 3 * 4 * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include <linux/i2c.h> 22 #include <linux/types.h> 23 #include <linux/videodev2.h> 24 #include "tuner-i2c.h" 25 #include "mxl5007t.h" 26 27 static DEFINE_MUTEX(mxl5007t_list_mutex); 28 static LIST_HEAD(hybrid_tuner_instance_list); 29 30 static int mxl5007t_debug; 31 module_param_named(debug, mxl5007t_debug, int, 0644); 32 MODULE_PARM_DESC(debug, "set debug level"); 33 34 /* ------------------------------------------------------------------------- */ 35 36 #define mxl_printk(kern, fmt, arg...) \ 37 printk(kern "%s: " fmt "\n", __func__, ##arg) 38 39 #define mxl_err(fmt, arg...) \ 40 mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg) 41 42 #define mxl_warn(fmt, arg...) \ 43 mxl_printk(KERN_WARNING, fmt, ##arg) 44 45 #define mxl_info(fmt, arg...) \ 46 mxl_printk(KERN_INFO, fmt, ##arg) 47 48 #define mxl_debug(fmt, arg...) \ 49 ({ \ 50 if (mxl5007t_debug) \ 51 mxl_printk(KERN_DEBUG, fmt, ##arg); \ 52 }) 53 54 #define mxl_fail(ret) \ 55 ({ \ 56 int __ret; \ 57 __ret = (ret < 0); \ 58 if (__ret) \ 59 mxl_printk(KERN_ERR, "error %d on line %d", \ 60 ret, __LINE__); \ 61 __ret; \ 62 }) 63 64 /* ------------------------------------------------------------------------- */ 65 66 #define MHz 1000000 67 68 enum mxl5007t_mode { 69 MxL_MODE_ISDBT = 0, 70 MxL_MODE_DVBT = 1, 71 MxL_MODE_ATSC = 2, 72 MxL_MODE_CABLE = 0x10, 73 }; 74 75 enum mxl5007t_chip_version { 76 MxL_UNKNOWN_ID = 0x00, 77 MxL_5007_V1_F1 = 0x11, 78 MxL_5007_V1_F2 = 0x12, 79 MxL_5007_V4 = 0x14, 80 MxL_5007_V2_100_F1 = 0x21, 81 MxL_5007_V2_100_F2 = 0x22, 82 MxL_5007_V2_200_F1 = 0x23, 83 MxL_5007_V2_200_F2 = 0x24, 84 }; 85 86 struct reg_pair_t { 87 u8 reg; 88 u8 val; 89 }; 90 91 /* ------------------------------------------------------------------------- */ 92 93 static struct reg_pair_t init_tab[] = { 94 { 0x02, 0x06 }, 95 { 0x03, 0x48 }, 96 { 0x05, 0x04 }, 97 { 0x06, 0x10 }, 98 { 0x2e, 0x15 }, /* OVERRIDE */ 99 { 0x30, 0x10 }, /* OVERRIDE */ 100 { 0x45, 0x58 }, /* OVERRIDE */ 101 { 0x48, 0x19 }, /* OVERRIDE */ 102 { 0x52, 0x03 }, /* OVERRIDE */ 103 { 0x53, 0x44 }, /* OVERRIDE */ 104 { 0x6a, 0x4b }, /* OVERRIDE */ 105 { 0x76, 0x00 }, /* OVERRIDE */ 106 { 0x78, 0x18 }, /* OVERRIDE */ 107 { 0x7a, 0x17 }, /* OVERRIDE */ 108 { 0x85, 0x06 }, /* OVERRIDE */ 109 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */ 110 { 0, 0 } 111 }; 112 113 static struct reg_pair_t init_tab_cable[] = { 114 { 0x02, 0x06 }, 115 { 0x03, 0x48 }, 116 { 0x05, 0x04 }, 117 { 0x06, 0x10 }, 118 { 0x09, 0x3f }, 119 { 0x0a, 0x3f }, 120 { 0x0b, 0x3f }, 121 { 0x2e, 0x15 }, /* OVERRIDE */ 122 { 0x30, 0x10 }, /* OVERRIDE */ 123 { 0x45, 0x58 }, /* OVERRIDE */ 124 { 0x48, 0x19 }, /* OVERRIDE */ 125 { 0x52, 0x03 }, /* OVERRIDE */ 126 { 0x53, 0x44 }, /* OVERRIDE */ 127 { 0x6a, 0x4b }, /* OVERRIDE */ 128 { 0x76, 0x00 }, /* OVERRIDE */ 129 { 0x78, 0x18 }, /* OVERRIDE */ 130 { 0x7a, 0x17 }, /* OVERRIDE */ 131 { 0x85, 0x06 }, /* OVERRIDE */ 132 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */ 133 { 0, 0 } 134 }; 135 136 /* ------------------------------------------------------------------------- */ 137 138 static struct reg_pair_t reg_pair_rftune[] = { 139 { 0x0f, 0x00 }, /* abort tune */ 140 { 0x0c, 0x15 }, 141 { 0x0d, 0x40 }, 142 { 0x0e, 0x0e }, 143 { 0x1f, 0x87 }, /* OVERRIDE */ 144 { 0x20, 0x1f }, /* OVERRIDE */ 145 { 0x21, 0x87 }, /* OVERRIDE */ 146 { 0x22, 0x1f }, /* OVERRIDE */ 147 { 0x80, 0x01 }, /* freq dependent */ 148 { 0x0f, 0x01 }, /* start tune */ 149 { 0, 0 } 150 }; 151 152 /* ------------------------------------------------------------------------- */ 153 154 struct mxl5007t_state { 155 struct list_head hybrid_tuner_instance_list; 156 struct tuner_i2c_props i2c_props; 157 158 struct mutex lock; 159 160 struct mxl5007t_config *config; 161 162 enum mxl5007t_chip_version chip_id; 163 164 struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)]; 165 struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)]; 166 struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)]; 167 168 enum mxl5007t_if_freq if_freq; 169 170 u32 frequency; 171 u32 bandwidth; 172 }; 173 174 /* ------------------------------------------------------------------------- */ 175 176 /* called by _init and _rftun to manipulate the register arrays */ 177 178 static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val) 179 { 180 unsigned int i = 0; 181 182 while (reg_pair[i].reg || reg_pair[i].val) { 183 if (reg_pair[i].reg == reg) { 184 reg_pair[i].val &= ~mask; 185 reg_pair[i].val |= val; 186 } 187 i++; 188 189 } 190 return; 191 } 192 193 static void copy_reg_bits(struct reg_pair_t *reg_pair1, 194 struct reg_pair_t *reg_pair2) 195 { 196 unsigned int i, j; 197 198 i = j = 0; 199 200 while (reg_pair1[i].reg || reg_pair1[i].val) { 201 while (reg_pair2[j].reg || reg_pair2[j].val) { 202 if (reg_pair1[i].reg != reg_pair2[j].reg) { 203 j++; 204 continue; 205 } 206 reg_pair2[j].val = reg_pair1[i].val; 207 break; 208 } 209 i++; 210 } 211 return; 212 } 213 214 /* ------------------------------------------------------------------------- */ 215 216 static void mxl5007t_set_mode_bits(struct mxl5007t_state *state, 217 enum mxl5007t_mode mode, 218 s32 if_diff_out_level) 219 { 220 switch (mode) { 221 case MxL_MODE_ATSC: 222 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12); 223 break; 224 case MxL_MODE_DVBT: 225 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11); 226 break; 227 case MxL_MODE_ISDBT: 228 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10); 229 break; 230 case MxL_MODE_CABLE: 231 set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1); 232 set_reg_bits(state->tab_init_cable, 0x0a, 0xff, 233 8 - if_diff_out_level); 234 set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17); 235 break; 236 default: 237 mxl_fail(-EINVAL); 238 } 239 return; 240 } 241 242 static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, 243 enum mxl5007t_if_freq if_freq, 244 int invert_if) 245 { 246 u8 val; 247 248 switch (if_freq) { 249 case MxL_IF_4_MHZ: 250 val = 0x00; 251 break; 252 case MxL_IF_4_5_MHZ: 253 val = 0x02; 254 break; 255 case MxL_IF_4_57_MHZ: 256 val = 0x03; 257 break; 258 case MxL_IF_5_MHZ: 259 val = 0x04; 260 break; 261 case MxL_IF_5_38_MHZ: 262 val = 0x05; 263 break; 264 case MxL_IF_6_MHZ: 265 val = 0x06; 266 break; 267 case MxL_IF_6_28_MHZ: 268 val = 0x07; 269 break; 270 case MxL_IF_9_1915_MHZ: 271 val = 0x08; 272 break; 273 case MxL_IF_35_25_MHZ: 274 val = 0x09; 275 break; 276 case MxL_IF_36_15_MHZ: 277 val = 0x0a; 278 break; 279 case MxL_IF_44_MHZ: 280 val = 0x0b; 281 break; 282 default: 283 mxl_fail(-EINVAL); 284 return; 285 } 286 set_reg_bits(state->tab_init, 0x02, 0x0f, val); 287 288 /* set inverted IF or normal IF */ 289 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00); 290 291 state->if_freq = if_freq; 292 293 return; 294 } 295 296 static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, 297 enum mxl5007t_xtal_freq xtal_freq) 298 { 299 switch (xtal_freq) { 300 case MxL_XTAL_16_MHZ: 301 /* select xtal freq & ref freq */ 302 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00); 303 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00); 304 break; 305 case MxL_XTAL_20_MHZ: 306 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10); 307 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01); 308 break; 309 case MxL_XTAL_20_25_MHZ: 310 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20); 311 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02); 312 break; 313 case MxL_XTAL_20_48_MHZ: 314 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30); 315 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03); 316 break; 317 case MxL_XTAL_24_MHZ: 318 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40); 319 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04); 320 break; 321 case MxL_XTAL_25_MHZ: 322 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50); 323 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05); 324 break; 325 case MxL_XTAL_25_14_MHZ: 326 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60); 327 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06); 328 break; 329 case MxL_XTAL_27_MHZ: 330 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70); 331 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07); 332 break; 333 case MxL_XTAL_28_8_MHZ: 334 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80); 335 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08); 336 break; 337 case MxL_XTAL_32_MHZ: 338 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90); 339 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09); 340 break; 341 case MxL_XTAL_40_MHZ: 342 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0); 343 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a); 344 break; 345 case MxL_XTAL_44_MHZ: 346 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0); 347 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b); 348 break; 349 case MxL_XTAL_48_MHZ: 350 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0); 351 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c); 352 break; 353 case MxL_XTAL_49_3811_MHZ: 354 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0); 355 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d); 356 break; 357 default: 358 mxl_fail(-EINVAL); 359 return; 360 } 361 362 return; 363 } 364 365 static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state, 366 enum mxl5007t_mode mode) 367 { 368 struct mxl5007t_config *cfg = state->config; 369 370 memcpy(&state->tab_init, &init_tab, sizeof(init_tab)); 371 memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable)); 372 373 mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level); 374 mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); 375 mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); 376 377 set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3); 378 set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp); 379 380 if (mode >= MxL_MODE_CABLE) { 381 copy_reg_bits(state->tab_init, state->tab_init_cable); 382 return state->tab_init_cable; 383 } else 384 return state->tab_init; 385 } 386 387 /* ------------------------------------------------------------------------- */ 388 389 enum mxl5007t_bw_mhz { 390 MxL_BW_6MHz = 6, 391 MxL_BW_7MHz = 7, 392 MxL_BW_8MHz = 8, 393 }; 394 395 static void mxl5007t_set_bw_bits(struct mxl5007t_state *state, 396 enum mxl5007t_bw_mhz bw) 397 { 398 u8 val; 399 400 switch (bw) { 401 case MxL_BW_6MHz: 402 val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A, 403 * and DIG_MODEINDEX_CSF */ 404 break; 405 case MxL_BW_7MHz: 406 val = 0x2a; 407 break; 408 case MxL_BW_8MHz: 409 val = 0x3f; 410 break; 411 default: 412 mxl_fail(-EINVAL); 413 return; 414 } 415 set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val); 416 417 return; 418 } 419 420 static struct 421 reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state, 422 u32 rf_freq, enum mxl5007t_bw_mhz bw) 423 { 424 u32 dig_rf_freq = 0; 425 u32 temp; 426 u32 frac_divider = 1000000; 427 unsigned int i; 428 429 memcpy(&state->tab_rftune, ®_pair_rftune, sizeof(reg_pair_rftune)); 430 431 mxl5007t_set_bw_bits(state, bw); 432 433 /* Convert RF frequency into 16 bits => 434 * 10 bit integer (MHz) + 6 bit fraction */ 435 dig_rf_freq = rf_freq / MHz; 436 437 temp = rf_freq % MHz; 438 439 for (i = 0; i < 6; i++) { 440 dig_rf_freq <<= 1; 441 frac_divider /= 2; 442 if (temp > frac_divider) { 443 temp -= frac_divider; 444 dig_rf_freq++; 445 } 446 } 447 448 /* add to have shift center point by 7.8124 kHz */ 449 if (temp > 7812) 450 dig_rf_freq++; 451 452 set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq); 453 set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8)); 454 455 if (rf_freq >= 333000000) 456 set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40); 457 458 return state->tab_rftune; 459 } 460 461 /* ------------------------------------------------------------------------- */ 462 463 static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val) 464 { 465 u8 buf[] = { reg, val }; 466 struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0, 467 .buf = buf, .len = 2 }; 468 int ret; 469 470 ret = i2c_transfer(state->i2c_props.adap, &msg, 1); 471 if (ret != 1) { 472 mxl_err("failed!"); 473 return -EREMOTEIO; 474 } 475 return 0; 476 } 477 478 static int mxl5007t_write_regs(struct mxl5007t_state *state, 479 struct reg_pair_t *reg_pair) 480 { 481 unsigned int i = 0; 482 int ret = 0; 483 484 while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) { 485 ret = mxl5007t_write_reg(state, 486 reg_pair[i].reg, reg_pair[i].val); 487 i++; 488 } 489 return ret; 490 } 491 492 static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) 493 { 494 u8 buf[2] = { 0xfb, reg }; 495 struct i2c_msg msg[] = { 496 { .addr = state->i2c_props.addr, .flags = 0, 497 .buf = buf, .len = 2 }, 498 { .addr = state->i2c_props.addr, .flags = I2C_M_RD, 499 .buf = val, .len = 1 }, 500 }; 501 int ret; 502 503 ret = i2c_transfer(state->i2c_props.adap, msg, 2); 504 if (ret != 2) { 505 mxl_err("failed!"); 506 return -EREMOTEIO; 507 } 508 return 0; 509 } 510 511 static int mxl5007t_soft_reset(struct mxl5007t_state *state) 512 { 513 u8 d = 0xff; 514 struct i2c_msg msg = { 515 .addr = state->i2c_props.addr, .flags = 0, 516 .buf = &d, .len = 1 517 }; 518 int ret = i2c_transfer(state->i2c_props.adap, &msg, 1); 519 520 if (ret != 1) { 521 mxl_err("failed!"); 522 return -EREMOTEIO; 523 } 524 return 0; 525 } 526 527 static int mxl5007t_tuner_init(struct mxl5007t_state *state, 528 enum mxl5007t_mode mode) 529 { 530 struct reg_pair_t *init_regs; 531 int ret; 532 533 /* calculate initialization reg array */ 534 init_regs = mxl5007t_calc_init_regs(state, mode); 535 536 ret = mxl5007t_write_regs(state, init_regs); 537 if (mxl_fail(ret)) 538 goto fail; 539 mdelay(1); 540 fail: 541 return ret; 542 } 543 544 static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz, 545 enum mxl5007t_bw_mhz bw) 546 { 547 struct reg_pair_t *rf_tune_regs; 548 int ret; 549 550 /* calculate channel change reg array */ 551 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw); 552 553 ret = mxl5007t_write_regs(state, rf_tune_regs); 554 if (mxl_fail(ret)) 555 goto fail; 556 msleep(3); 557 fail: 558 return ret; 559 } 560 561 /* ------------------------------------------------------------------------- */ 562 563 static int mxl5007t_synth_lock_status(struct mxl5007t_state *state, 564 int *rf_locked, int *ref_locked) 565 { 566 u8 d; 567 int ret; 568 569 *rf_locked = 0; 570 *ref_locked = 0; 571 572 ret = mxl5007t_read_reg(state, 0xd8, &d); 573 if (mxl_fail(ret)) 574 goto fail; 575 576 if ((d & 0x0c) == 0x0c) 577 *rf_locked = 1; 578 579 if ((d & 0x03) == 0x03) 580 *ref_locked = 1; 581 fail: 582 return ret; 583 } 584 585 /* ------------------------------------------------------------------------- */ 586 587 static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status) 588 { 589 struct mxl5007t_state *state = fe->tuner_priv; 590 int rf_locked, ref_locked, ret; 591 592 *status = 0; 593 594 if (fe->ops.i2c_gate_ctrl) 595 fe->ops.i2c_gate_ctrl(fe, 1); 596 597 ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked); 598 if (mxl_fail(ret)) 599 goto fail; 600 mxl_debug("%s%s", rf_locked ? "rf locked " : "", 601 ref_locked ? "ref locked" : ""); 602 603 if ((rf_locked) || (ref_locked)) 604 *status |= TUNER_STATUS_LOCKED; 605 fail: 606 if (fe->ops.i2c_gate_ctrl) 607 fe->ops.i2c_gate_ctrl(fe, 0); 608 609 return ret; 610 } 611 612 /* ------------------------------------------------------------------------- */ 613 614 static int mxl5007t_set_params(struct dvb_frontend *fe) 615 { 616 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 617 u32 delsys = c->delivery_system; 618 struct mxl5007t_state *state = fe->tuner_priv; 619 enum mxl5007t_bw_mhz bw; 620 enum mxl5007t_mode mode; 621 int ret; 622 u32 freq = c->frequency; 623 624 switch (delsys) { 625 case SYS_ATSC: 626 mode = MxL_MODE_ATSC; 627 bw = MxL_BW_6MHz; 628 break; 629 case SYS_DVBC_ANNEX_B: 630 mode = MxL_MODE_CABLE; 631 bw = MxL_BW_6MHz; 632 break; 633 case SYS_DVBT: 634 case SYS_DVBT2: 635 mode = MxL_MODE_DVBT; 636 switch (c->bandwidth_hz) { 637 case 6000000: 638 bw = MxL_BW_6MHz; 639 break; 640 case 7000000: 641 bw = MxL_BW_7MHz; 642 break; 643 case 8000000: 644 bw = MxL_BW_8MHz; 645 break; 646 default: 647 return -EINVAL; 648 } 649 break; 650 default: 651 mxl_err("modulation type not supported!"); 652 return -EINVAL; 653 } 654 655 if (fe->ops.i2c_gate_ctrl) 656 fe->ops.i2c_gate_ctrl(fe, 1); 657 658 mutex_lock(&state->lock); 659 660 ret = mxl5007t_tuner_init(state, mode); 661 if (mxl_fail(ret)) 662 goto fail; 663 664 ret = mxl5007t_tuner_rf_tune(state, freq, bw); 665 if (mxl_fail(ret)) 666 goto fail; 667 668 state->frequency = freq; 669 state->bandwidth = c->bandwidth_hz; 670 fail: 671 mutex_unlock(&state->lock); 672 673 if (fe->ops.i2c_gate_ctrl) 674 fe->ops.i2c_gate_ctrl(fe, 0); 675 676 return ret; 677 } 678 679 /* ------------------------------------------------------------------------- */ 680 681 static int mxl5007t_init(struct dvb_frontend *fe) 682 { 683 struct mxl5007t_state *state = fe->tuner_priv; 684 int ret; 685 686 if (fe->ops.i2c_gate_ctrl) 687 fe->ops.i2c_gate_ctrl(fe, 1); 688 689 /* wake from standby */ 690 ret = mxl5007t_write_reg(state, 0x01, 0x01); 691 mxl_fail(ret); 692 693 if (fe->ops.i2c_gate_ctrl) 694 fe->ops.i2c_gate_ctrl(fe, 0); 695 696 return ret; 697 } 698 699 static int mxl5007t_sleep(struct dvb_frontend *fe) 700 { 701 struct mxl5007t_state *state = fe->tuner_priv; 702 int ret; 703 704 if (fe->ops.i2c_gate_ctrl) 705 fe->ops.i2c_gate_ctrl(fe, 1); 706 707 /* enter standby mode */ 708 ret = mxl5007t_write_reg(state, 0x01, 0x00); 709 mxl_fail(ret); 710 ret = mxl5007t_write_reg(state, 0x0f, 0x00); 711 mxl_fail(ret); 712 713 if (fe->ops.i2c_gate_ctrl) 714 fe->ops.i2c_gate_ctrl(fe, 0); 715 716 return ret; 717 } 718 719 /* ------------------------------------------------------------------------- */ 720 721 static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency) 722 { 723 struct mxl5007t_state *state = fe->tuner_priv; 724 *frequency = state->frequency; 725 return 0; 726 } 727 728 static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 729 { 730 struct mxl5007t_state *state = fe->tuner_priv; 731 *bandwidth = state->bandwidth; 732 return 0; 733 } 734 735 static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 736 { 737 struct mxl5007t_state *state = fe->tuner_priv; 738 739 *frequency = 0; 740 741 switch (state->if_freq) { 742 case MxL_IF_4_MHZ: 743 *frequency = 4000000; 744 break; 745 case MxL_IF_4_5_MHZ: 746 *frequency = 4500000; 747 break; 748 case MxL_IF_4_57_MHZ: 749 *frequency = 4570000; 750 break; 751 case MxL_IF_5_MHZ: 752 *frequency = 5000000; 753 break; 754 case MxL_IF_5_38_MHZ: 755 *frequency = 5380000; 756 break; 757 case MxL_IF_6_MHZ: 758 *frequency = 6000000; 759 break; 760 case MxL_IF_6_28_MHZ: 761 *frequency = 6280000; 762 break; 763 case MxL_IF_9_1915_MHZ: 764 *frequency = 9191500; 765 break; 766 case MxL_IF_35_25_MHZ: 767 *frequency = 35250000; 768 break; 769 case MxL_IF_36_15_MHZ: 770 *frequency = 36150000; 771 break; 772 case MxL_IF_44_MHZ: 773 *frequency = 44000000; 774 break; 775 } 776 return 0; 777 } 778 779 static int mxl5007t_release(struct dvb_frontend *fe) 780 { 781 struct mxl5007t_state *state = fe->tuner_priv; 782 783 mutex_lock(&mxl5007t_list_mutex); 784 785 if (state) 786 hybrid_tuner_release_state(state); 787 788 mutex_unlock(&mxl5007t_list_mutex); 789 790 fe->tuner_priv = NULL; 791 792 return 0; 793 } 794 795 /* ------------------------------------------------------------------------- */ 796 797 static struct dvb_tuner_ops mxl5007t_tuner_ops = { 798 .info = { 799 .name = "MaxLinear MxL5007T", 800 }, 801 .init = mxl5007t_init, 802 .sleep = mxl5007t_sleep, 803 .set_params = mxl5007t_set_params, 804 .get_status = mxl5007t_get_status, 805 .get_frequency = mxl5007t_get_frequency, 806 .get_bandwidth = mxl5007t_get_bandwidth, 807 .release = mxl5007t_release, 808 .get_if_frequency = mxl5007t_get_if_frequency, 809 }; 810 811 static int mxl5007t_get_chip_id(struct mxl5007t_state *state) 812 { 813 char *name; 814 int ret; 815 u8 id; 816 817 ret = mxl5007t_read_reg(state, 0xd9, &id); 818 if (mxl_fail(ret)) 819 goto fail; 820 821 switch (id) { 822 case MxL_5007_V1_F1: 823 name = "MxL5007.v1.f1"; 824 break; 825 case MxL_5007_V1_F2: 826 name = "MxL5007.v1.f2"; 827 break; 828 case MxL_5007_V2_100_F1: 829 name = "MxL5007.v2.100.f1"; 830 break; 831 case MxL_5007_V2_100_F2: 832 name = "MxL5007.v2.100.f2"; 833 break; 834 case MxL_5007_V2_200_F1: 835 name = "MxL5007.v2.200.f1"; 836 break; 837 case MxL_5007_V2_200_F2: 838 name = "MxL5007.v2.200.f2"; 839 break; 840 case MxL_5007_V4: 841 name = "MxL5007T.v4"; 842 break; 843 default: 844 name = "MxL5007T"; 845 printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id); 846 id = MxL_UNKNOWN_ID; 847 } 848 state->chip_id = id; 849 mxl_info("%s detected @ %d-%04x", name, 850 i2c_adapter_id(state->i2c_props.adap), 851 state->i2c_props.addr); 852 return 0; 853 fail: 854 mxl_warn("unable to identify device @ %d-%04x", 855 i2c_adapter_id(state->i2c_props.adap), 856 state->i2c_props.addr); 857 858 state->chip_id = MxL_UNKNOWN_ID; 859 return ret; 860 } 861 862 struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe, 863 struct i2c_adapter *i2c, u8 addr, 864 struct mxl5007t_config *cfg) 865 { 866 struct mxl5007t_state *state = NULL; 867 int instance, ret; 868 869 mutex_lock(&mxl5007t_list_mutex); 870 instance = hybrid_tuner_request_state(struct mxl5007t_state, state, 871 hybrid_tuner_instance_list, 872 i2c, addr, "mxl5007t"); 873 switch (instance) { 874 case 0: 875 goto fail; 876 case 1: 877 /* new tuner instance */ 878 state->config = cfg; 879 880 mutex_init(&state->lock); 881 882 if (fe->ops.i2c_gate_ctrl) 883 fe->ops.i2c_gate_ctrl(fe, 1); 884 885 ret = mxl5007t_get_chip_id(state); 886 887 if (fe->ops.i2c_gate_ctrl) 888 fe->ops.i2c_gate_ctrl(fe, 0); 889 890 /* check return value of mxl5007t_get_chip_id */ 891 if (mxl_fail(ret)) 892 goto fail; 893 break; 894 default: 895 /* existing tuner instance */ 896 break; 897 } 898 899 if (fe->ops.i2c_gate_ctrl) 900 fe->ops.i2c_gate_ctrl(fe, 1); 901 902 ret = mxl5007t_soft_reset(state); 903 904 if (fe->ops.i2c_gate_ctrl) 905 fe->ops.i2c_gate_ctrl(fe, 0); 906 907 if (mxl_fail(ret)) 908 goto fail; 909 910 if (fe->ops.i2c_gate_ctrl) 911 fe->ops.i2c_gate_ctrl(fe, 1); 912 913 ret = mxl5007t_write_reg(state, 0x04, 914 state->config->loop_thru_enable); 915 916 if (fe->ops.i2c_gate_ctrl) 917 fe->ops.i2c_gate_ctrl(fe, 0); 918 919 if (mxl_fail(ret)) 920 goto fail; 921 922 fe->tuner_priv = state; 923 924 mutex_unlock(&mxl5007t_list_mutex); 925 926 memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops, 927 sizeof(struct dvb_tuner_ops)); 928 929 return fe; 930 fail: 931 mutex_unlock(&mxl5007t_list_mutex); 932 933 mxl5007t_release(fe); 934 return NULL; 935 } 936 EXPORT_SYMBOL_GPL(mxl5007t_attach); 937 MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver"); 938 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); 939 MODULE_LICENSE("GPL"); 940 MODULE_VERSION("0.2"); 941