1 /* 2 * Fitipower FC0012 tuner driver 3 * 4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include "fc0012.h" 22 #include "fc0012-priv.h" 23 24 static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) 25 { 26 u8 buf[2] = {reg, val}; 27 struct i2c_msg msg = { 28 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 29 }; 30 31 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { 32 dev_err(&priv->i2c->dev, 33 "%s: I2C write reg failed, reg: %02x, val: %02x\n", 34 KBUILD_MODNAME, reg, val); 35 return -EREMOTEIO; 36 } 37 return 0; 38 } 39 40 static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) 41 { 42 struct i2c_msg msg[2] = { 43 { .addr = priv->cfg->i2c_address, .flags = 0, 44 .buf = ®, .len = 1 }, 45 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, 46 .buf = val, .len = 1 }, 47 }; 48 49 if (i2c_transfer(priv->i2c, msg, 2) != 2) { 50 dev_err(&priv->i2c->dev, 51 "%s: I2C read reg failed, reg: %02x\n", 52 KBUILD_MODNAME, reg); 53 return -EREMOTEIO; 54 } 55 return 0; 56 } 57 58 static void fc0012_release(struct dvb_frontend *fe) 59 { 60 kfree(fe->tuner_priv); 61 fe->tuner_priv = NULL; 62 } 63 64 static int fc0012_init(struct dvb_frontend *fe) 65 { 66 struct fc0012_priv *priv = fe->tuner_priv; 67 int i, ret = 0; 68 unsigned char reg[] = { 69 0x00, /* dummy reg. 0 */ 70 0x05, /* reg. 0x01 */ 71 0x10, /* reg. 0x02 */ 72 0x00, /* reg. 0x03 */ 73 0x00, /* reg. 0x04 */ 74 0x0f, /* reg. 0x05: may also be 0x0a */ 75 0x00, /* reg. 0x06: divider 2, VCO slow */ 76 0x00, /* reg. 0x07: may also be 0x0f */ 77 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, 78 Loop Bw 1/8 */ 79 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */ 80 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ 81 0x82, /* reg. 0x0b: Output Clock is same as clock frequency, 82 may also be 0x83 */ 83 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ 84 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */ 85 0x00, /* reg. 0x0e */ 86 0x00, /* reg. 0x0f */ 87 0x00, /* reg. 0x10: may also be 0x0d */ 88 0x00, /* reg. 0x11 */ 89 0x1f, /* reg. 0x12: Set to maximum gain */ 90 0x08, /* reg. 0x13: Set to Middle Gain: 0x08, 91 Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */ 92 0x00, /* reg. 0x14 */ 93 0x04, /* reg. 0x15: Enable LNA COMPS */ 94 }; 95 96 switch (priv->cfg->xtal_freq) { 97 case FC_XTAL_27_MHZ: 98 case FC_XTAL_28_8_MHZ: 99 reg[0x07] |= 0x20; 100 break; 101 case FC_XTAL_36_MHZ: 102 default: 103 break; 104 } 105 106 if (priv->cfg->dual_master) 107 reg[0x0c] |= 0x02; 108 109 if (priv->cfg->loop_through) 110 reg[0x09] |= 0x01; 111 112 if (fe->ops.i2c_gate_ctrl) 113 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 114 115 for (i = 1; i < sizeof(reg); i++) { 116 ret = fc0012_writereg(priv, i, reg[i]); 117 if (ret) 118 break; 119 } 120 121 if (fe->ops.i2c_gate_ctrl) 122 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 123 124 if (ret) 125 dev_err(&priv->i2c->dev, "%s: fc0012_writereg failed: %d\n", 126 KBUILD_MODNAME, ret); 127 128 return ret; 129 } 130 131 static int fc0012_set_params(struct dvb_frontend *fe) 132 { 133 struct fc0012_priv *priv = fe->tuner_priv; 134 int i, ret = 0; 135 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 136 u32 freq = p->frequency / 1000; 137 u32 delsys = p->delivery_system; 138 unsigned char reg[7], am, pm, multi, tmp; 139 unsigned long f_vco; 140 unsigned short xtal_freq_khz_2, xin, xdiv; 141 bool vco_select = false; 142 143 if (fe->callback) { 144 ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER, 145 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1)); 146 if (ret) 147 goto exit; 148 } 149 150 switch (priv->cfg->xtal_freq) { 151 case FC_XTAL_27_MHZ: 152 xtal_freq_khz_2 = 27000 / 2; 153 break; 154 case FC_XTAL_36_MHZ: 155 xtal_freq_khz_2 = 36000 / 2; 156 break; 157 case FC_XTAL_28_8_MHZ: 158 default: 159 xtal_freq_khz_2 = 28800 / 2; 160 break; 161 } 162 163 /* select frequency divider and the frequency of VCO */ 164 if (freq < 37084) { /* freq * 96 < 3560000 */ 165 multi = 96; 166 reg[5] = 0x82; 167 reg[6] = 0x00; 168 } else if (freq < 55625) { /* freq * 64 < 3560000 */ 169 multi = 64; 170 reg[5] = 0x82; 171 reg[6] = 0x02; 172 } else if (freq < 74167) { /* freq * 48 < 3560000 */ 173 multi = 48; 174 reg[5] = 0x42; 175 reg[6] = 0x00; 176 } else if (freq < 111250) { /* freq * 32 < 3560000 */ 177 multi = 32; 178 reg[5] = 0x42; 179 reg[6] = 0x02; 180 } else if (freq < 148334) { /* freq * 24 < 3560000 */ 181 multi = 24; 182 reg[5] = 0x22; 183 reg[6] = 0x00; 184 } else if (freq < 222500) { /* freq * 16 < 3560000 */ 185 multi = 16; 186 reg[5] = 0x22; 187 reg[6] = 0x02; 188 } else if (freq < 296667) { /* freq * 12 < 3560000 */ 189 multi = 12; 190 reg[5] = 0x12; 191 reg[6] = 0x00; 192 } else if (freq < 445000) { /* freq * 8 < 3560000 */ 193 multi = 8; 194 reg[5] = 0x12; 195 reg[6] = 0x02; 196 } else if (freq < 593334) { /* freq * 6 < 3560000 */ 197 multi = 6; 198 reg[5] = 0x0a; 199 reg[6] = 0x00; 200 } else { 201 multi = 4; 202 reg[5] = 0x0a; 203 reg[6] = 0x02; 204 } 205 206 f_vco = freq * multi; 207 208 if (f_vco >= 3060000) { 209 reg[6] |= 0x08; 210 vco_select = true; 211 } 212 213 if (freq >= 45000) { 214 /* From divided value (XDIV) determined the FA and FP value */ 215 xdiv = (unsigned short)(f_vco / xtal_freq_khz_2); 216 if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2)) 217 xdiv++; 218 219 pm = (unsigned char)(xdiv / 8); 220 am = (unsigned char)(xdiv - (8 * pm)); 221 222 if (am < 2) { 223 reg[1] = am + 8; 224 reg[2] = pm - 1; 225 } else { 226 reg[1] = am; 227 reg[2] = pm; 228 } 229 } else { 230 /* fix for frequency less than 45 MHz */ 231 reg[1] = 0x06; 232 reg[2] = 0x11; 233 } 234 235 /* fix clock out */ 236 reg[6] |= 0x20; 237 238 /* From VCO frequency determines the XIN ( fractional part of Delta 239 Sigma PLL) and divided value (XDIV) */ 240 xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2); 241 xin = (xin << 15) / xtal_freq_khz_2; 242 if (xin >= 16384) 243 xin += 32768; 244 245 reg[3] = xin >> 8; /* xin with 9 bit resolution */ 246 reg[4] = xin & 0xff; 247 248 if (delsys == SYS_DVBT) { 249 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ 250 switch (p->bandwidth_hz) { 251 case 6000000: 252 reg[6] |= 0x80; 253 break; 254 case 7000000: 255 reg[6] |= 0x40; 256 break; 257 case 8000000: 258 default: 259 break; 260 } 261 } else { 262 dev_err(&priv->i2c->dev, "%s: modulation type not supported!\n", 263 KBUILD_MODNAME); 264 return -EINVAL; 265 } 266 267 /* modified for Realtek demod */ 268 reg[5] |= 0x07; 269 270 if (fe->ops.i2c_gate_ctrl) 271 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 272 273 for (i = 1; i <= 6; i++) { 274 ret = fc0012_writereg(priv, i, reg[i]); 275 if (ret) 276 goto exit; 277 } 278 279 /* VCO Calibration */ 280 ret = fc0012_writereg(priv, 0x0e, 0x80); 281 if (!ret) 282 ret = fc0012_writereg(priv, 0x0e, 0x00); 283 284 /* VCO Re-Calibration if needed */ 285 if (!ret) 286 ret = fc0012_writereg(priv, 0x0e, 0x00); 287 288 if (!ret) { 289 msleep(10); 290 ret = fc0012_readreg(priv, 0x0e, &tmp); 291 } 292 if (ret) 293 goto exit; 294 295 /* vco selection */ 296 tmp &= 0x3f; 297 298 if (vco_select) { 299 if (tmp > 0x3c) { 300 reg[6] &= ~0x08; 301 ret = fc0012_writereg(priv, 0x06, reg[6]); 302 if (!ret) 303 ret = fc0012_writereg(priv, 0x0e, 0x80); 304 if (!ret) 305 ret = fc0012_writereg(priv, 0x0e, 0x00); 306 } 307 } else { 308 if (tmp < 0x02) { 309 reg[6] |= 0x08; 310 ret = fc0012_writereg(priv, 0x06, reg[6]); 311 if (!ret) 312 ret = fc0012_writereg(priv, 0x0e, 0x80); 313 if (!ret) 314 ret = fc0012_writereg(priv, 0x0e, 0x00); 315 } 316 } 317 318 priv->frequency = p->frequency; 319 priv->bandwidth = p->bandwidth_hz; 320 321 exit: 322 if (fe->ops.i2c_gate_ctrl) 323 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 324 if (ret) 325 dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n", 326 KBUILD_MODNAME, __func__, ret); 327 return ret; 328 } 329 330 static int fc0012_get_frequency(struct dvb_frontend *fe, u32 *frequency) 331 { 332 struct fc0012_priv *priv = fe->tuner_priv; 333 *frequency = priv->frequency; 334 return 0; 335 } 336 337 static int fc0012_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 338 { 339 *frequency = 0; /* Zero-IF */ 340 return 0; 341 } 342 343 static int fc0012_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 344 { 345 struct fc0012_priv *priv = fe->tuner_priv; 346 *bandwidth = priv->bandwidth; 347 return 0; 348 } 349 350 #define INPUT_ADC_LEVEL -8 351 352 static int fc0012_get_rf_strength(struct dvb_frontend *fe, u16 *strength) 353 { 354 struct fc0012_priv *priv = fe->tuner_priv; 355 int ret; 356 unsigned char tmp; 357 int int_temp, lna_gain, int_lna, tot_agc_gain, power; 358 const int fc0012_lna_gain_table[] = { 359 /* low gain */ 360 -63, -58, -99, -73, 361 -63, -65, -54, -60, 362 /* middle gain */ 363 71, 70, 68, 67, 364 65, 63, 61, 58, 365 /* high gain */ 366 197, 191, 188, 186, 367 184, 182, 181, 179, 368 }; 369 370 if (fe->ops.i2c_gate_ctrl) 371 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 372 373 ret = fc0012_writereg(priv, 0x12, 0x00); 374 if (ret) 375 goto err; 376 377 ret = fc0012_readreg(priv, 0x12, &tmp); 378 if (ret) 379 goto err; 380 int_temp = tmp; 381 382 ret = fc0012_readreg(priv, 0x13, &tmp); 383 if (ret) 384 goto err; 385 lna_gain = tmp & 0x1f; 386 387 if (fe->ops.i2c_gate_ctrl) 388 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 389 390 if (lna_gain < ARRAY_SIZE(fc0012_lna_gain_table)) { 391 int_lna = fc0012_lna_gain_table[lna_gain]; 392 tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 + 393 (int_temp & 0x1f)) * 2; 394 power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10; 395 396 if (power >= 45) 397 *strength = 255; /* 100% */ 398 else if (power < -95) 399 *strength = 0; 400 else 401 *strength = (power + 95) * 255 / 140; 402 403 *strength |= *strength << 8; 404 } else { 405 ret = -1; 406 } 407 408 goto exit; 409 410 err: 411 if (fe->ops.i2c_gate_ctrl) 412 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 413 exit: 414 if (ret) 415 dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n", 416 KBUILD_MODNAME, __func__, ret); 417 return ret; 418 } 419 420 static const struct dvb_tuner_ops fc0012_tuner_ops = { 421 .info = { 422 .name = "Fitipower FC0012", 423 424 .frequency_min = 37000000, /* estimate */ 425 .frequency_max = 862000000, /* estimate */ 426 .frequency_step = 0, 427 }, 428 429 .release = fc0012_release, 430 431 .init = fc0012_init, 432 433 .set_params = fc0012_set_params, 434 435 .get_frequency = fc0012_get_frequency, 436 .get_if_frequency = fc0012_get_if_frequency, 437 .get_bandwidth = fc0012_get_bandwidth, 438 439 .get_rf_strength = fc0012_get_rf_strength, 440 }; 441 442 struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe, 443 struct i2c_adapter *i2c, const struct fc0012_config *cfg) 444 { 445 struct fc0012_priv *priv; 446 int ret; 447 u8 chip_id; 448 449 if (fe->ops.i2c_gate_ctrl) 450 fe->ops.i2c_gate_ctrl(fe, 1); 451 452 priv = kzalloc(sizeof(struct fc0012_priv), GFP_KERNEL); 453 if (!priv) { 454 ret = -ENOMEM; 455 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); 456 goto err; 457 } 458 459 priv->cfg = cfg; 460 priv->i2c = i2c; 461 462 /* check if the tuner is there */ 463 ret = fc0012_readreg(priv, 0x00, &chip_id); 464 if (ret < 0) 465 goto err; 466 467 dev_dbg(&i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); 468 469 switch (chip_id) { 470 case 0xa1: 471 break; 472 default: 473 ret = -ENODEV; 474 goto err; 475 } 476 477 dev_info(&i2c->dev, "%s: Fitipower FC0012 successfully identified\n", 478 KBUILD_MODNAME); 479 480 if (priv->cfg->loop_through) { 481 ret = fc0012_writereg(priv, 0x09, 0x6f); 482 if (ret < 0) 483 goto err; 484 } 485 486 /* 487 * TODO: Clock out en or div? 488 * For dual tuner configuration clearing bit [0] is required. 489 */ 490 if (priv->cfg->clock_out) { 491 ret = fc0012_writereg(priv, 0x0b, 0x82); 492 if (ret < 0) 493 goto err; 494 } 495 496 fe->tuner_priv = priv; 497 memcpy(&fe->ops.tuner_ops, &fc0012_tuner_ops, 498 sizeof(struct dvb_tuner_ops)); 499 500 err: 501 if (fe->ops.i2c_gate_ctrl) 502 fe->ops.i2c_gate_ctrl(fe, 0); 503 504 if (ret) { 505 dev_dbg(&i2c->dev, "%s: failed: %d\n", __func__, ret); 506 kfree(priv); 507 return NULL; 508 } 509 510 return fe; 511 } 512 EXPORT_SYMBOL(fc0012_attach); 513 514 MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver"); 515 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>"); 516 MODULE_LICENSE("GPL"); 517 MODULE_VERSION("0.6"); 518