1 /* 2 * Fitipower FC0012 tuner driver 3 * 4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #include "fc0012.h" 22 #include "fc0012-priv.h" 23 24 static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) 25 { 26 u8 buf[2] = {reg, val}; 27 struct i2c_msg msg = { 28 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 29 }; 30 31 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { 32 err("I2C write reg failed, reg: %02x, val: %02x", reg, val); 33 return -EREMOTEIO; 34 } 35 return 0; 36 } 37 38 static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) 39 { 40 struct i2c_msg msg[2] = { 41 { .addr = priv->addr, .flags = 0, .buf = ®, .len = 1 }, 42 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, 43 }; 44 45 if (i2c_transfer(priv->i2c, msg, 2) != 2) { 46 err("I2C read reg failed, reg: %02x", reg); 47 return -EREMOTEIO; 48 } 49 return 0; 50 } 51 52 static int fc0012_release(struct dvb_frontend *fe) 53 { 54 kfree(fe->tuner_priv); 55 fe->tuner_priv = NULL; 56 return 0; 57 } 58 59 static int fc0012_init(struct dvb_frontend *fe) 60 { 61 struct fc0012_priv *priv = fe->tuner_priv; 62 int i, ret = 0; 63 unsigned char reg[] = { 64 0x00, /* dummy reg. 0 */ 65 0x05, /* reg. 0x01 */ 66 0x10, /* reg. 0x02 */ 67 0x00, /* reg. 0x03 */ 68 0x00, /* reg. 0x04 */ 69 0x0f, /* reg. 0x05: may also be 0x0a */ 70 0x00, /* reg. 0x06: divider 2, VCO slow */ 71 0x00, /* reg. 0x07: may also be 0x0f */ 72 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, 73 Loop Bw 1/8 */ 74 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */ 75 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ 76 0x82, /* reg. 0x0b: Output Clock is same as clock frequency, 77 may also be 0x83 */ 78 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ 79 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */ 80 0x00, /* reg. 0x0e */ 81 0x00, /* reg. 0x0f */ 82 0x00, /* reg. 0x10: may also be 0x0d */ 83 0x00, /* reg. 0x11 */ 84 0x1f, /* reg. 0x12: Set to maximum gain */ 85 0x08, /* reg. 0x13: Set to Middle Gain: 0x08, 86 Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */ 87 0x00, /* reg. 0x14 */ 88 0x04, /* reg. 0x15: Enable LNA COMPS */ 89 }; 90 91 switch (priv->xtal_freq) { 92 case FC_XTAL_27_MHZ: 93 case FC_XTAL_28_8_MHZ: 94 reg[0x07] |= 0x20; 95 break; 96 case FC_XTAL_36_MHZ: 97 default: 98 break; 99 } 100 101 if (priv->dual_master) 102 reg[0x0c] |= 0x02; 103 104 if (fe->ops.i2c_gate_ctrl) 105 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 106 107 for (i = 1; i < sizeof(reg); i++) { 108 ret = fc0012_writereg(priv, i, reg[i]); 109 if (ret) 110 break; 111 } 112 113 if (fe->ops.i2c_gate_ctrl) 114 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 115 116 if (ret) 117 err("fc0012_writereg failed: %d", ret); 118 119 return ret; 120 } 121 122 static int fc0012_sleep(struct dvb_frontend *fe) 123 { 124 /* nothing to do here */ 125 return 0; 126 } 127 128 static int fc0012_set_params(struct dvb_frontend *fe) 129 { 130 struct fc0012_priv *priv = fe->tuner_priv; 131 int i, ret = 0; 132 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 133 u32 freq = p->frequency / 1000; 134 u32 delsys = p->delivery_system; 135 unsigned char reg[7], am, pm, multi, tmp; 136 unsigned long f_vco; 137 unsigned short xtal_freq_khz_2, xin, xdiv; 138 int vco_select = false; 139 140 if (fe->callback) { 141 ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER, 142 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1)); 143 if (ret) 144 goto exit; 145 } 146 147 switch (priv->xtal_freq) { 148 case FC_XTAL_27_MHZ: 149 xtal_freq_khz_2 = 27000 / 2; 150 break; 151 case FC_XTAL_36_MHZ: 152 xtal_freq_khz_2 = 36000 / 2; 153 break; 154 case FC_XTAL_28_8_MHZ: 155 default: 156 xtal_freq_khz_2 = 28800 / 2; 157 break; 158 } 159 160 /* select frequency divider and the frequency of VCO */ 161 if (freq < 37084) { /* freq * 96 < 3560000 */ 162 multi = 96; 163 reg[5] = 0x82; 164 reg[6] = 0x00; 165 } else if (freq < 55625) { /* freq * 64 < 3560000 */ 166 multi = 64; 167 reg[5] = 0x82; 168 reg[6] = 0x02; 169 } else if (freq < 74167) { /* freq * 48 < 3560000 */ 170 multi = 48; 171 reg[5] = 0x42; 172 reg[6] = 0x00; 173 } else if (freq < 111250) { /* freq * 32 < 3560000 */ 174 multi = 32; 175 reg[5] = 0x42; 176 reg[6] = 0x02; 177 } else if (freq < 148334) { /* freq * 24 < 3560000 */ 178 multi = 24; 179 reg[5] = 0x22; 180 reg[6] = 0x00; 181 } else if (freq < 222500) { /* freq * 16 < 3560000 */ 182 multi = 16; 183 reg[5] = 0x22; 184 reg[6] = 0x02; 185 } else if (freq < 296667) { /* freq * 12 < 3560000 */ 186 multi = 12; 187 reg[5] = 0x12; 188 reg[6] = 0x00; 189 } else if (freq < 445000) { /* freq * 8 < 3560000 */ 190 multi = 8; 191 reg[5] = 0x12; 192 reg[6] = 0x02; 193 } else if (freq < 593334) { /* freq * 6 < 3560000 */ 194 multi = 6; 195 reg[5] = 0x0a; 196 reg[6] = 0x00; 197 } else { 198 multi = 4; 199 reg[5] = 0x0a; 200 reg[6] = 0x02; 201 } 202 203 f_vco = freq * multi; 204 205 if (f_vco >= 3060000) { 206 reg[6] |= 0x08; 207 vco_select = true; 208 } 209 210 if (freq >= 45000) { 211 /* From divided value (XDIV) determined the FA and FP value */ 212 xdiv = (unsigned short)(f_vco / xtal_freq_khz_2); 213 if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2)) 214 xdiv++; 215 216 pm = (unsigned char)(xdiv / 8); 217 am = (unsigned char)(xdiv - (8 * pm)); 218 219 if (am < 2) { 220 reg[1] = am + 8; 221 reg[2] = pm - 1; 222 } else { 223 reg[1] = am; 224 reg[2] = pm; 225 } 226 } else { 227 /* fix for frequency less than 45 MHz */ 228 reg[1] = 0x06; 229 reg[2] = 0x11; 230 } 231 232 /* fix clock out */ 233 reg[6] |= 0x20; 234 235 /* From VCO frequency determines the XIN ( fractional part of Delta 236 Sigma PLL) and divided value (XDIV) */ 237 xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2); 238 xin = (xin << 15) / xtal_freq_khz_2; 239 if (xin >= 16384) 240 xin += 32768; 241 242 reg[3] = xin >> 8; /* xin with 9 bit resolution */ 243 reg[4] = xin & 0xff; 244 245 if (delsys == SYS_DVBT) { 246 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ 247 switch (p->bandwidth_hz) { 248 case 6000000: 249 reg[6] |= 0x80; 250 break; 251 case 7000000: 252 reg[6] |= 0x40; 253 break; 254 case 8000000: 255 default: 256 break; 257 } 258 } else { 259 err("%s: modulation type not supported!", __func__); 260 return -EINVAL; 261 } 262 263 /* modified for Realtek demod */ 264 reg[5] |= 0x07; 265 266 if (fe->ops.i2c_gate_ctrl) 267 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 268 269 for (i = 1; i <= 6; i++) { 270 ret = fc0012_writereg(priv, i, reg[i]); 271 if (ret) 272 goto exit; 273 } 274 275 /* VCO Calibration */ 276 ret = fc0012_writereg(priv, 0x0e, 0x80); 277 if (!ret) 278 ret = fc0012_writereg(priv, 0x0e, 0x00); 279 280 /* VCO Re-Calibration if needed */ 281 if (!ret) 282 ret = fc0012_writereg(priv, 0x0e, 0x00); 283 284 if (!ret) { 285 msleep(10); 286 ret = fc0012_readreg(priv, 0x0e, &tmp); 287 } 288 if (ret) 289 goto exit; 290 291 /* vco selection */ 292 tmp &= 0x3f; 293 294 if (vco_select) { 295 if (tmp > 0x3c) { 296 reg[6] &= ~0x08; 297 ret = fc0012_writereg(priv, 0x06, reg[6]); 298 if (!ret) 299 ret = fc0012_writereg(priv, 0x0e, 0x80); 300 if (!ret) 301 ret = fc0012_writereg(priv, 0x0e, 0x00); 302 } 303 } else { 304 if (tmp < 0x02) { 305 reg[6] |= 0x08; 306 ret = fc0012_writereg(priv, 0x06, reg[6]); 307 if (!ret) 308 ret = fc0012_writereg(priv, 0x0e, 0x80); 309 if (!ret) 310 ret = fc0012_writereg(priv, 0x0e, 0x00); 311 } 312 } 313 314 priv->frequency = p->frequency; 315 priv->bandwidth = p->bandwidth_hz; 316 317 exit: 318 if (fe->ops.i2c_gate_ctrl) 319 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 320 if (ret) 321 warn("%s: failed: %d", __func__, ret); 322 return ret; 323 } 324 325 static int fc0012_get_frequency(struct dvb_frontend *fe, u32 *frequency) 326 { 327 struct fc0012_priv *priv = fe->tuner_priv; 328 *frequency = priv->frequency; 329 return 0; 330 } 331 332 static int fc0012_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 333 { 334 /* CHECK: always ? */ 335 *frequency = 0; 336 return 0; 337 } 338 339 static int fc0012_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 340 { 341 struct fc0012_priv *priv = fe->tuner_priv; 342 *bandwidth = priv->bandwidth; 343 return 0; 344 } 345 346 #define INPUT_ADC_LEVEL -8 347 348 static int fc0012_get_rf_strength(struct dvb_frontend *fe, u16 *strength) 349 { 350 struct fc0012_priv *priv = fe->tuner_priv; 351 int ret; 352 unsigned char tmp; 353 int int_temp, lna_gain, int_lna, tot_agc_gain, power; 354 const int fc0012_lna_gain_table[] = { 355 /* low gain */ 356 -63, -58, -99, -73, 357 -63, -65, -54, -60, 358 /* middle gain */ 359 71, 70, 68, 67, 360 65, 63, 61, 58, 361 /* high gain */ 362 197, 191, 188, 186, 363 184, 182, 181, 179, 364 }; 365 366 if (fe->ops.i2c_gate_ctrl) 367 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 368 369 ret = fc0012_writereg(priv, 0x12, 0x00); 370 if (ret) 371 goto err; 372 373 ret = fc0012_readreg(priv, 0x12, &tmp); 374 if (ret) 375 goto err; 376 int_temp = tmp; 377 378 ret = fc0012_readreg(priv, 0x13, &tmp); 379 if (ret) 380 goto err; 381 lna_gain = tmp & 0x1f; 382 383 if (fe->ops.i2c_gate_ctrl) 384 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 385 386 if (lna_gain < ARRAY_SIZE(fc0012_lna_gain_table)) { 387 int_lna = fc0012_lna_gain_table[lna_gain]; 388 tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 + 389 (int_temp & 0x1f)) * 2; 390 power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10; 391 392 if (power >= 45) 393 *strength = 255; /* 100% */ 394 else if (power < -95) 395 *strength = 0; 396 else 397 *strength = (power + 95) * 255 / 140; 398 399 *strength |= *strength << 8; 400 } else { 401 ret = -1; 402 } 403 404 goto exit; 405 406 err: 407 if (fe->ops.i2c_gate_ctrl) 408 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 409 exit: 410 if (ret) 411 warn("%s: failed: %d", __func__, ret); 412 return ret; 413 } 414 415 static const struct dvb_tuner_ops fc0012_tuner_ops = { 416 .info = { 417 .name = "Fitipower FC0012", 418 419 .frequency_min = 37000000, /* estimate */ 420 .frequency_max = 862000000, /* estimate */ 421 .frequency_step = 0, 422 }, 423 424 .release = fc0012_release, 425 426 .init = fc0012_init, 427 .sleep = fc0012_sleep, 428 429 .set_params = fc0012_set_params, 430 431 .get_frequency = fc0012_get_frequency, 432 .get_if_frequency = fc0012_get_if_frequency, 433 .get_bandwidth = fc0012_get_bandwidth, 434 435 .get_rf_strength = fc0012_get_rf_strength, 436 }; 437 438 struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe, 439 struct i2c_adapter *i2c, u8 i2c_address, int dual_master, 440 enum fc001x_xtal_freq xtal_freq) 441 { 442 struct fc0012_priv *priv = NULL; 443 444 priv = kzalloc(sizeof(struct fc0012_priv), GFP_KERNEL); 445 if (priv == NULL) 446 return NULL; 447 448 priv->i2c = i2c; 449 priv->dual_master = dual_master; 450 priv->addr = i2c_address; 451 priv->xtal_freq = xtal_freq; 452 453 info("Fitipower FC0012 successfully attached."); 454 455 fe->tuner_priv = priv; 456 457 memcpy(&fe->ops.tuner_ops, &fc0012_tuner_ops, 458 sizeof(struct dvb_tuner_ops)); 459 460 return fe; 461 } 462 EXPORT_SYMBOL(fc0012_attach); 463 464 MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver"); 465 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>"); 466 MODULE_LICENSE("GPL"); 467 MODULE_VERSION("0.6"); 468