1 /* 2 * Fitipower FC0012 tuner driver 3 * 4 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "fc0012.h" 18 #include "fc0012-priv.h" 19 20 static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) 21 { 22 u8 buf[2] = {reg, val}; 23 struct i2c_msg msg = { 24 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 25 }; 26 27 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { 28 dev_err(&priv->i2c->dev, 29 "%s: I2C write reg failed, reg: %02x, val: %02x\n", 30 KBUILD_MODNAME, reg, val); 31 return -EREMOTEIO; 32 } 33 return 0; 34 } 35 36 static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) 37 { 38 struct i2c_msg msg[2] = { 39 { .addr = priv->cfg->i2c_address, .flags = 0, 40 .buf = ®, .len = 1 }, 41 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, 42 .buf = val, .len = 1 }, 43 }; 44 45 if (i2c_transfer(priv->i2c, msg, 2) != 2) { 46 dev_err(&priv->i2c->dev, 47 "%s: I2C read reg failed, reg: %02x\n", 48 KBUILD_MODNAME, reg); 49 return -EREMOTEIO; 50 } 51 return 0; 52 } 53 54 static void fc0012_release(struct dvb_frontend *fe) 55 { 56 kfree(fe->tuner_priv); 57 fe->tuner_priv = NULL; 58 } 59 60 static int fc0012_init(struct dvb_frontend *fe) 61 { 62 struct fc0012_priv *priv = fe->tuner_priv; 63 int i, ret = 0; 64 unsigned char reg[] = { 65 0x00, /* dummy reg. 0 */ 66 0x05, /* reg. 0x01 */ 67 0x10, /* reg. 0x02 */ 68 0x00, /* reg. 0x03 */ 69 0x00, /* reg. 0x04 */ 70 0x0f, /* reg. 0x05: may also be 0x0a */ 71 0x00, /* reg. 0x06: divider 2, VCO slow */ 72 0x00, /* reg. 0x07: may also be 0x0f */ 73 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, 74 Loop Bw 1/8 */ 75 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */ 76 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ 77 0x82, /* reg. 0x0b: Output Clock is same as clock frequency, 78 may also be 0x83 */ 79 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ 80 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */ 81 0x00, /* reg. 0x0e */ 82 0x00, /* reg. 0x0f */ 83 0x00, /* reg. 0x10: may also be 0x0d */ 84 0x00, /* reg. 0x11 */ 85 0x1f, /* reg. 0x12: Set to maximum gain */ 86 0x08, /* reg. 0x13: Set to Middle Gain: 0x08, 87 Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */ 88 0x00, /* reg. 0x14 */ 89 0x04, /* reg. 0x15: Enable LNA COMPS */ 90 }; 91 92 switch (priv->cfg->xtal_freq) { 93 case FC_XTAL_27_MHZ: 94 case FC_XTAL_28_8_MHZ: 95 reg[0x07] |= 0x20; 96 break; 97 case FC_XTAL_36_MHZ: 98 default: 99 break; 100 } 101 102 if (priv->cfg->dual_master) 103 reg[0x0c] |= 0x02; 104 105 if (priv->cfg->loop_through) 106 reg[0x09] |= 0x01; 107 108 if (fe->ops.i2c_gate_ctrl) 109 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 110 111 for (i = 1; i < sizeof(reg); i++) { 112 ret = fc0012_writereg(priv, i, reg[i]); 113 if (ret) 114 break; 115 } 116 117 if (fe->ops.i2c_gate_ctrl) 118 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 119 120 if (ret) 121 dev_err(&priv->i2c->dev, "%s: fc0012_writereg failed: %d\n", 122 KBUILD_MODNAME, ret); 123 124 return ret; 125 } 126 127 static int fc0012_set_params(struct dvb_frontend *fe) 128 { 129 struct fc0012_priv *priv = fe->tuner_priv; 130 int i, ret = 0; 131 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 132 u32 freq = p->frequency / 1000; 133 u32 delsys = p->delivery_system; 134 unsigned char reg[7], am, pm, multi, tmp; 135 unsigned long f_vco; 136 unsigned short xtal_freq_khz_2, xin, xdiv; 137 bool vco_select = false; 138 139 if (fe->callback) { 140 ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER, 141 FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1)); 142 if (ret) 143 goto exit; 144 } 145 146 switch (priv->cfg->xtal_freq) { 147 case FC_XTAL_27_MHZ: 148 xtal_freq_khz_2 = 27000 / 2; 149 break; 150 case FC_XTAL_36_MHZ: 151 xtal_freq_khz_2 = 36000 / 2; 152 break; 153 case FC_XTAL_28_8_MHZ: 154 default: 155 xtal_freq_khz_2 = 28800 / 2; 156 break; 157 } 158 159 /* select frequency divider and the frequency of VCO */ 160 if (freq < 37084) { /* freq * 96 < 3560000 */ 161 multi = 96; 162 reg[5] = 0x82; 163 reg[6] = 0x00; 164 } else if (freq < 55625) { /* freq * 64 < 3560000 */ 165 multi = 64; 166 reg[5] = 0x82; 167 reg[6] = 0x02; 168 } else if (freq < 74167) { /* freq * 48 < 3560000 */ 169 multi = 48; 170 reg[5] = 0x42; 171 reg[6] = 0x00; 172 } else if (freq < 111250) { /* freq * 32 < 3560000 */ 173 multi = 32; 174 reg[5] = 0x42; 175 reg[6] = 0x02; 176 } else if (freq < 148334) { /* freq * 24 < 3560000 */ 177 multi = 24; 178 reg[5] = 0x22; 179 reg[6] = 0x00; 180 } else if (freq < 222500) { /* freq * 16 < 3560000 */ 181 multi = 16; 182 reg[5] = 0x22; 183 reg[6] = 0x02; 184 } else if (freq < 296667) { /* freq * 12 < 3560000 */ 185 multi = 12; 186 reg[5] = 0x12; 187 reg[6] = 0x00; 188 } else if (freq < 445000) { /* freq * 8 < 3560000 */ 189 multi = 8; 190 reg[5] = 0x12; 191 reg[6] = 0x02; 192 } else if (freq < 593334) { /* freq * 6 < 3560000 */ 193 multi = 6; 194 reg[5] = 0x0a; 195 reg[6] = 0x00; 196 } else { 197 multi = 4; 198 reg[5] = 0x0a; 199 reg[6] = 0x02; 200 } 201 202 f_vco = freq * multi; 203 204 if (f_vco >= 3060000) { 205 reg[6] |= 0x08; 206 vco_select = true; 207 } 208 209 if (freq >= 45000) { 210 /* From divided value (XDIV) determined the FA and FP value */ 211 xdiv = (unsigned short)(f_vco / xtal_freq_khz_2); 212 if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2)) 213 xdiv++; 214 215 pm = (unsigned char)(xdiv / 8); 216 am = (unsigned char)(xdiv - (8 * pm)); 217 218 if (am < 2) { 219 reg[1] = am + 8; 220 reg[2] = pm - 1; 221 } else { 222 reg[1] = am; 223 reg[2] = pm; 224 } 225 } else { 226 /* fix for frequency less than 45 MHz */ 227 reg[1] = 0x06; 228 reg[2] = 0x11; 229 } 230 231 /* fix clock out */ 232 reg[6] |= 0x20; 233 234 /* From VCO frequency determines the XIN ( fractional part of Delta 235 Sigma PLL) and divided value (XDIV) */ 236 xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2); 237 xin = (xin << 15) / xtal_freq_khz_2; 238 if (xin >= 16384) 239 xin += 32768; 240 241 reg[3] = xin >> 8; /* xin with 9 bit resolution */ 242 reg[4] = xin & 0xff; 243 244 if (delsys == SYS_DVBT) { 245 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ 246 switch (p->bandwidth_hz) { 247 case 6000000: 248 reg[6] |= 0x80; 249 break; 250 case 7000000: 251 reg[6] |= 0x40; 252 break; 253 case 8000000: 254 default: 255 break; 256 } 257 } else { 258 dev_err(&priv->i2c->dev, "%s: modulation type not supported!\n", 259 KBUILD_MODNAME); 260 return -EINVAL; 261 } 262 263 /* modified for Realtek demod */ 264 reg[5] |= 0x07; 265 266 if (fe->ops.i2c_gate_ctrl) 267 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 268 269 for (i = 1; i <= 6; i++) { 270 ret = fc0012_writereg(priv, i, reg[i]); 271 if (ret) 272 goto exit; 273 } 274 275 /* VCO Calibration */ 276 ret = fc0012_writereg(priv, 0x0e, 0x80); 277 if (!ret) 278 ret = fc0012_writereg(priv, 0x0e, 0x00); 279 280 /* VCO Re-Calibration if needed */ 281 if (!ret) 282 ret = fc0012_writereg(priv, 0x0e, 0x00); 283 284 if (!ret) { 285 msleep(10); 286 ret = fc0012_readreg(priv, 0x0e, &tmp); 287 } 288 if (ret) 289 goto exit; 290 291 /* vco selection */ 292 tmp &= 0x3f; 293 294 if (vco_select) { 295 if (tmp > 0x3c) { 296 reg[6] &= ~0x08; 297 ret = fc0012_writereg(priv, 0x06, reg[6]); 298 if (!ret) 299 ret = fc0012_writereg(priv, 0x0e, 0x80); 300 if (!ret) 301 ret = fc0012_writereg(priv, 0x0e, 0x00); 302 } 303 } else { 304 if (tmp < 0x02) { 305 reg[6] |= 0x08; 306 ret = fc0012_writereg(priv, 0x06, reg[6]); 307 if (!ret) 308 ret = fc0012_writereg(priv, 0x0e, 0x80); 309 if (!ret) 310 ret = fc0012_writereg(priv, 0x0e, 0x00); 311 } 312 } 313 314 priv->frequency = p->frequency; 315 priv->bandwidth = p->bandwidth_hz; 316 317 exit: 318 if (fe->ops.i2c_gate_ctrl) 319 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 320 if (ret) 321 dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n", 322 KBUILD_MODNAME, __func__, ret); 323 return ret; 324 } 325 326 static int fc0012_get_frequency(struct dvb_frontend *fe, u32 *frequency) 327 { 328 struct fc0012_priv *priv = fe->tuner_priv; 329 *frequency = priv->frequency; 330 return 0; 331 } 332 333 static int fc0012_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 334 { 335 *frequency = 0; /* Zero-IF */ 336 return 0; 337 } 338 339 static int fc0012_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 340 { 341 struct fc0012_priv *priv = fe->tuner_priv; 342 *bandwidth = priv->bandwidth; 343 return 0; 344 } 345 346 #define INPUT_ADC_LEVEL -8 347 348 static int fc0012_get_rf_strength(struct dvb_frontend *fe, u16 *strength) 349 { 350 struct fc0012_priv *priv = fe->tuner_priv; 351 int ret; 352 unsigned char tmp; 353 int int_temp, lna_gain, int_lna, tot_agc_gain, power; 354 static const int fc0012_lna_gain_table[] = { 355 /* low gain */ 356 -63, -58, -99, -73, 357 -63, -65, -54, -60, 358 /* middle gain */ 359 71, 70, 68, 67, 360 65, 63, 61, 58, 361 /* high gain */ 362 197, 191, 188, 186, 363 184, 182, 181, 179, 364 }; 365 366 if (fe->ops.i2c_gate_ctrl) 367 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 368 369 ret = fc0012_writereg(priv, 0x12, 0x00); 370 if (ret) 371 goto err; 372 373 ret = fc0012_readreg(priv, 0x12, &tmp); 374 if (ret) 375 goto err; 376 int_temp = tmp; 377 378 ret = fc0012_readreg(priv, 0x13, &tmp); 379 if (ret) 380 goto err; 381 lna_gain = tmp & 0x1f; 382 383 if (fe->ops.i2c_gate_ctrl) 384 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 385 386 if (lna_gain < ARRAY_SIZE(fc0012_lna_gain_table)) { 387 int_lna = fc0012_lna_gain_table[lna_gain]; 388 tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 + 389 (int_temp & 0x1f)) * 2; 390 power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10; 391 392 if (power >= 45) 393 *strength = 255; /* 100% */ 394 else if (power < -95) 395 *strength = 0; 396 else 397 *strength = (power + 95) * 255 / 140; 398 399 *strength |= *strength << 8; 400 } else { 401 ret = -1; 402 } 403 404 goto exit; 405 406 err: 407 if (fe->ops.i2c_gate_ctrl) 408 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 409 exit: 410 if (ret) 411 dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n", 412 KBUILD_MODNAME, __func__, ret); 413 return ret; 414 } 415 416 static const struct dvb_tuner_ops fc0012_tuner_ops = { 417 .info = { 418 .name = "Fitipower FC0012", 419 420 .frequency_min = 37000000, /* estimate */ 421 .frequency_max = 862000000, /* estimate */ 422 .frequency_step = 0, 423 }, 424 425 .release = fc0012_release, 426 427 .init = fc0012_init, 428 429 .set_params = fc0012_set_params, 430 431 .get_frequency = fc0012_get_frequency, 432 .get_if_frequency = fc0012_get_if_frequency, 433 .get_bandwidth = fc0012_get_bandwidth, 434 435 .get_rf_strength = fc0012_get_rf_strength, 436 }; 437 438 struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe, 439 struct i2c_adapter *i2c, const struct fc0012_config *cfg) 440 { 441 struct fc0012_priv *priv; 442 int ret; 443 u8 chip_id; 444 445 if (fe->ops.i2c_gate_ctrl) 446 fe->ops.i2c_gate_ctrl(fe, 1); 447 448 priv = kzalloc(sizeof(struct fc0012_priv), GFP_KERNEL); 449 if (!priv) { 450 ret = -ENOMEM; 451 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); 452 goto err; 453 } 454 455 priv->cfg = cfg; 456 priv->i2c = i2c; 457 458 /* check if the tuner is there */ 459 ret = fc0012_readreg(priv, 0x00, &chip_id); 460 if (ret < 0) 461 goto err; 462 463 dev_dbg(&i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); 464 465 switch (chip_id) { 466 case 0xa1: 467 break; 468 default: 469 ret = -ENODEV; 470 goto err; 471 } 472 473 dev_info(&i2c->dev, "%s: Fitipower FC0012 successfully identified\n", 474 KBUILD_MODNAME); 475 476 if (priv->cfg->loop_through) { 477 ret = fc0012_writereg(priv, 0x09, 0x6f); 478 if (ret < 0) 479 goto err; 480 } 481 482 /* 483 * TODO: Clock out en or div? 484 * For dual tuner configuration clearing bit [0] is required. 485 */ 486 if (priv->cfg->clock_out) { 487 ret = fc0012_writereg(priv, 0x0b, 0x82); 488 if (ret < 0) 489 goto err; 490 } 491 492 fe->tuner_priv = priv; 493 memcpy(&fe->ops.tuner_ops, &fc0012_tuner_ops, 494 sizeof(struct dvb_tuner_ops)); 495 496 err: 497 if (fe->ops.i2c_gate_ctrl) 498 fe->ops.i2c_gate_ctrl(fe, 0); 499 500 if (ret) { 501 dev_dbg(&i2c->dev, "%s: failed: %d\n", __func__, ret); 502 kfree(priv); 503 return NULL; 504 } 505 506 return fe; 507 } 508 EXPORT_SYMBOL(fc0012_attach); 509 510 MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver"); 511 MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>"); 512 MODULE_LICENSE("GPL"); 513 MODULE_VERSION("0.6"); 514