1 /* 2 * Elonics E4000 silicon tuner driver 3 * 4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #include "e4000_priv.h" 22 23 /* write multiple registers */ 24 static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) 25 { 26 int ret; 27 u8 buf[1 + len]; 28 struct i2c_msg msg[1] = { 29 { 30 .addr = priv->cfg->i2c_addr, 31 .flags = 0, 32 .len = sizeof(buf), 33 .buf = buf, 34 } 35 }; 36 37 buf[0] = reg; 38 memcpy(&buf[1], val, len); 39 40 ret = i2c_transfer(priv->i2c, msg, 1); 41 if (ret == 1) { 42 ret = 0; 43 } else { 44 dev_warn(&priv->i2c->dev, 45 "%s: i2c wr failed=%d reg=%02x len=%d\n", 46 KBUILD_MODNAME, ret, reg, len); 47 ret = -EREMOTEIO; 48 } 49 return ret; 50 } 51 52 /* read multiple registers */ 53 static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len) 54 { 55 int ret; 56 u8 buf[len]; 57 struct i2c_msg msg[2] = { 58 { 59 .addr = priv->cfg->i2c_addr, 60 .flags = 0, 61 .len = 1, 62 .buf = ®, 63 }, { 64 .addr = priv->cfg->i2c_addr, 65 .flags = I2C_M_RD, 66 .len = sizeof(buf), 67 .buf = buf, 68 } 69 }; 70 71 ret = i2c_transfer(priv->i2c, msg, 2); 72 if (ret == 2) { 73 memcpy(val, buf, len); 74 ret = 0; 75 } else { 76 dev_warn(&priv->i2c->dev, 77 "%s: i2c rd failed=%d reg=%02x len=%d\n", 78 KBUILD_MODNAME, ret, reg, len); 79 ret = -EREMOTEIO; 80 } 81 82 return ret; 83 } 84 85 /* write single register */ 86 static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val) 87 { 88 return e4000_wr_regs(priv, reg, &val, 1); 89 } 90 91 /* read single register */ 92 static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val) 93 { 94 return e4000_rd_regs(priv, reg, val, 1); 95 } 96 97 static int e4000_init(struct dvb_frontend *fe) 98 { 99 struct e4000_priv *priv = fe->tuner_priv; 100 int ret; 101 102 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 103 104 if (fe->ops.i2c_gate_ctrl) 105 fe->ops.i2c_gate_ctrl(fe, 1); 106 107 /* dummy I2C to ensure I2C wakes up */ 108 ret = e4000_wr_reg(priv, 0x02, 0x40); 109 110 /* reset */ 111 ret = e4000_wr_reg(priv, 0x00, 0x01); 112 if (ret < 0) 113 goto err; 114 115 /* disable output clock */ 116 ret = e4000_wr_reg(priv, 0x06, 0x00); 117 if (ret < 0) 118 goto err; 119 120 ret = e4000_wr_reg(priv, 0x7a, 0x96); 121 if (ret < 0) 122 goto err; 123 124 /* configure gains */ 125 ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2); 126 if (ret < 0) 127 goto err; 128 129 ret = e4000_wr_reg(priv, 0x82, 0x00); 130 if (ret < 0) 131 goto err; 132 133 ret = e4000_wr_reg(priv, 0x24, 0x05); 134 if (ret < 0) 135 goto err; 136 137 ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2); 138 if (ret < 0) 139 goto err; 140 141 ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2); 142 if (ret < 0) 143 goto err; 144 145 /* DC offset control */ 146 ret = e4000_wr_reg(priv, 0x2d, 0x1f); 147 if (ret < 0) 148 goto err; 149 150 ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2); 151 if (ret < 0) 152 goto err; 153 154 /* gain control */ 155 ret = e4000_wr_reg(priv, 0x1a, 0x17); 156 if (ret < 0) 157 goto err; 158 159 ret = e4000_wr_reg(priv, 0x1f, 0x1a); 160 if (ret < 0) 161 goto err; 162 163 if (fe->ops.i2c_gate_ctrl) 164 fe->ops.i2c_gate_ctrl(fe, 0); 165 166 return 0; 167 err: 168 if (fe->ops.i2c_gate_ctrl) 169 fe->ops.i2c_gate_ctrl(fe, 0); 170 171 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 172 return ret; 173 } 174 175 static int e4000_sleep(struct dvb_frontend *fe) 176 { 177 struct e4000_priv *priv = fe->tuner_priv; 178 int ret; 179 180 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 181 182 if (fe->ops.i2c_gate_ctrl) 183 fe->ops.i2c_gate_ctrl(fe, 1); 184 185 ret = e4000_wr_reg(priv, 0x00, 0x00); 186 if (ret < 0) 187 goto err; 188 189 if (fe->ops.i2c_gate_ctrl) 190 fe->ops.i2c_gate_ctrl(fe, 0); 191 192 return 0; 193 err: 194 if (fe->ops.i2c_gate_ctrl) 195 fe->ops.i2c_gate_ctrl(fe, 0); 196 197 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 198 return ret; 199 } 200 201 static int e4000_set_params(struct dvb_frontend *fe) 202 { 203 struct e4000_priv *priv = fe->tuner_priv; 204 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 205 int ret, i, sigma_delta; 206 unsigned int f_vco; 207 u8 buf[5], i_data[4], q_data[4]; 208 209 dev_dbg(&priv->i2c->dev, 210 "%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n", 211 __func__, c->delivery_system, c->frequency, 212 c->bandwidth_hz); 213 214 if (fe->ops.i2c_gate_ctrl) 215 fe->ops.i2c_gate_ctrl(fe, 1); 216 217 /* gain control manual */ 218 ret = e4000_wr_reg(priv, 0x1a, 0x00); 219 if (ret < 0) 220 goto err; 221 222 /* PLL */ 223 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) { 224 if (c->frequency <= e4000_pll_lut[i].freq) 225 break; 226 } 227 228 if (i == ARRAY_SIZE(e4000_pll_lut)) 229 goto err; 230 231 /* 232 * Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz 233 * or more. 234 */ 235 f_vco = c->frequency * e4000_pll_lut[i].mul; 236 sigma_delta = 0x10000UL * (f_vco % priv->cfg->clock) / priv->cfg->clock; 237 buf[0] = f_vco / priv->cfg->clock; 238 buf[1] = (sigma_delta >> 0) & 0xff; 239 buf[2] = (sigma_delta >> 8) & 0xff; 240 buf[3] = 0x00; 241 buf[4] = e4000_pll_lut[i].div; 242 243 dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n", 244 __func__, f_vco, buf[0], sigma_delta); 245 246 ret = e4000_wr_regs(priv, 0x09, buf, 5); 247 if (ret < 0) 248 goto err; 249 250 /* LNA filter (RF filter) */ 251 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) { 252 if (c->frequency <= e400_lna_filter_lut[i].freq) 253 break; 254 } 255 256 if (i == ARRAY_SIZE(e400_lna_filter_lut)) 257 goto err; 258 259 ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val); 260 if (ret < 0) 261 goto err; 262 263 /* IF filters */ 264 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) { 265 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq) 266 break; 267 } 268 269 if (i == ARRAY_SIZE(e4000_if_filter_lut)) 270 goto err; 271 272 buf[0] = e4000_if_filter_lut[i].reg11_val; 273 buf[1] = e4000_if_filter_lut[i].reg12_val; 274 275 ret = e4000_wr_regs(priv, 0x11, buf, 2); 276 if (ret < 0) 277 goto err; 278 279 /* frequency band */ 280 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) { 281 if (c->frequency <= e4000_band_lut[i].freq) 282 break; 283 } 284 285 if (i == ARRAY_SIZE(e4000_band_lut)) 286 goto err; 287 288 ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val); 289 if (ret < 0) 290 goto err; 291 292 ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val); 293 if (ret < 0) 294 goto err; 295 296 /* DC offset */ 297 for (i = 0; i < 4; i++) { 298 if (i == 0) 299 ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3); 300 else if (i == 1) 301 ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2); 302 else if (i == 2) 303 ret = e4000_wr_regs(priv, 0x15, "\x01", 1); 304 else 305 ret = e4000_wr_regs(priv, 0x16, "\x7e", 1); 306 307 if (ret < 0) 308 goto err; 309 310 ret = e4000_wr_reg(priv, 0x29, 0x01); 311 if (ret < 0) 312 goto err; 313 314 ret = e4000_rd_regs(priv, 0x2a, buf, 3); 315 if (ret < 0) 316 goto err; 317 318 i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f); 319 q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f); 320 } 321 322 swap(q_data[2], q_data[3]); 323 swap(i_data[2], i_data[3]); 324 325 ret = e4000_wr_regs(priv, 0x50, q_data, 4); 326 if (ret < 0) 327 goto err; 328 329 ret = e4000_wr_regs(priv, 0x60, i_data, 4); 330 if (ret < 0) 331 goto err; 332 333 /* gain control auto */ 334 ret = e4000_wr_reg(priv, 0x1a, 0x17); 335 if (ret < 0) 336 goto err; 337 338 if (fe->ops.i2c_gate_ctrl) 339 fe->ops.i2c_gate_ctrl(fe, 0); 340 341 return 0; 342 err: 343 if (fe->ops.i2c_gate_ctrl) 344 fe->ops.i2c_gate_ctrl(fe, 0); 345 346 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 347 return ret; 348 } 349 350 static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 351 { 352 struct e4000_priv *priv = fe->tuner_priv; 353 354 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 355 356 *frequency = 0; /* Zero-IF */ 357 358 return 0; 359 } 360 361 static int e4000_release(struct dvb_frontend *fe) 362 { 363 struct e4000_priv *priv = fe->tuner_priv; 364 365 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 366 367 kfree(fe->tuner_priv); 368 369 return 0; 370 } 371 372 static const struct dvb_tuner_ops e4000_tuner_ops = { 373 .info = { 374 .name = "Elonics E4000", 375 .frequency_min = 174000000, 376 .frequency_max = 862000000, 377 }, 378 379 .release = e4000_release, 380 381 .init = e4000_init, 382 .sleep = e4000_sleep, 383 .set_params = e4000_set_params, 384 385 .get_if_frequency = e4000_get_if_frequency, 386 }; 387 388 struct dvb_frontend *e4000_attach(struct dvb_frontend *fe, 389 struct i2c_adapter *i2c, const struct e4000_config *cfg) 390 { 391 struct e4000_priv *priv; 392 int ret; 393 u8 chip_id; 394 395 if (fe->ops.i2c_gate_ctrl) 396 fe->ops.i2c_gate_ctrl(fe, 1); 397 398 priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL); 399 if (!priv) { 400 ret = -ENOMEM; 401 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); 402 goto err; 403 } 404 405 priv->cfg = cfg; 406 priv->i2c = i2c; 407 408 /* check if the tuner is there */ 409 ret = e4000_rd_reg(priv, 0x02, &chip_id); 410 if (ret < 0) 411 goto err; 412 413 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); 414 415 if (chip_id != 0x40) 416 goto err; 417 418 /* put sleep as chip seems to be in normal mode by default */ 419 ret = e4000_wr_reg(priv, 0x00, 0x00); 420 if (ret < 0) 421 goto err; 422 423 dev_info(&priv->i2c->dev, 424 "%s: Elonics E4000 successfully identified\n", 425 KBUILD_MODNAME); 426 427 fe->tuner_priv = priv; 428 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops, 429 sizeof(struct dvb_tuner_ops)); 430 431 if (fe->ops.i2c_gate_ctrl) 432 fe->ops.i2c_gate_ctrl(fe, 0); 433 434 return fe; 435 err: 436 if (fe->ops.i2c_gate_ctrl) 437 fe->ops.i2c_gate_ctrl(fe, 0); 438 439 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); 440 kfree(priv); 441 return NULL; 442 } 443 EXPORT_SYMBOL(e4000_attach); 444 445 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver"); 446 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 447 MODULE_LICENSE("GPL"); 448