1 /* 2 * GS1662 device registration. 3 * 4 * Copyright (C) 2015-2016 Nexvision 5 * Author: Charles-Antoine Couret <charles-antoine.couret@nexvision.fr> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/spi/spi.h> 16 #include <linux/platform_device.h> 17 #include <linux/ctype.h> 18 #include <linux/err.h> 19 #include <linux/device.h> 20 #include <linux/module.h> 21 22 #include <linux/videodev2.h> 23 #include <media/v4l2-common.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-device.h> 26 #include <media/v4l2-subdev.h> 27 #include <media/v4l2-dv-timings.h> 28 #include <linux/v4l2-dv-timings.h> 29 30 #define REG_STATUS 0x04 31 #define REG_FORCE_FMT 0x06 32 #define REG_LINES_PER_FRAME 0x12 33 #define REG_WORDS_PER_LINE 0x13 34 #define REG_WORDS_PER_ACT_LINE 0x14 35 #define REG_ACT_LINES_PER_FRAME 0x15 36 37 #define MASK_H_LOCK 0x001 38 #define MASK_V_LOCK 0x002 39 #define MASK_STD_LOCK 0x004 40 #define MASK_FORCE_STD 0x020 41 #define MASK_STD_STATUS 0x3E0 42 43 #define GS_WIDTH_MIN 720 44 #define GS_WIDTH_MAX 2048 45 #define GS_HEIGHT_MIN 487 46 #define GS_HEIGHT_MAX 1080 47 #define GS_PIXELCLOCK_MIN 10519200 48 #define GS_PIXELCLOCK_MAX 74250000 49 50 struct gs { 51 struct spi_device *pdev; 52 struct v4l2_subdev sd; 53 struct v4l2_dv_timings current_timings; 54 int enabled; 55 }; 56 57 struct gs_reg_fmt { 58 u16 reg_value; 59 struct v4l2_dv_timings format; 60 }; 61 62 struct gs_reg_fmt_custom { 63 u16 reg_value; 64 __u32 width; 65 __u32 height; 66 __u64 pixelclock; 67 __u32 interlaced; 68 }; 69 70 static const struct spi_device_id gs_id[] = { 71 { "gs1662", 0 }, 72 { } 73 }; 74 MODULE_DEVICE_TABLE(spi, gs_id); 75 76 static const struct v4l2_dv_timings fmt_cap[] = { 77 V4L2_DV_BT_SDI_720X487I60, 78 V4L2_DV_BT_CEA_720X576P50, 79 V4L2_DV_BT_CEA_1280X720P24, 80 V4L2_DV_BT_CEA_1280X720P25, 81 V4L2_DV_BT_CEA_1280X720P30, 82 V4L2_DV_BT_CEA_1280X720P50, 83 V4L2_DV_BT_CEA_1280X720P60, 84 V4L2_DV_BT_CEA_1920X1080P24, 85 V4L2_DV_BT_CEA_1920X1080P25, 86 V4L2_DV_BT_CEA_1920X1080P30, 87 V4L2_DV_BT_CEA_1920X1080I50, 88 V4L2_DV_BT_CEA_1920X1080I60, 89 }; 90 91 static const struct gs_reg_fmt reg_fmt[] = { 92 { 0x00, V4L2_DV_BT_CEA_1280X720P60 }, 93 { 0x01, V4L2_DV_BT_CEA_1280X720P60 }, 94 { 0x02, V4L2_DV_BT_CEA_1280X720P30 }, 95 { 0x03, V4L2_DV_BT_CEA_1280X720P30 }, 96 { 0x04, V4L2_DV_BT_CEA_1280X720P50 }, 97 { 0x05, V4L2_DV_BT_CEA_1280X720P50 }, 98 { 0x06, V4L2_DV_BT_CEA_1280X720P25 }, 99 { 0x07, V4L2_DV_BT_CEA_1280X720P25 }, 100 { 0x08, V4L2_DV_BT_CEA_1280X720P24 }, 101 { 0x09, V4L2_DV_BT_CEA_1280X720P24 }, 102 { 0x0A, V4L2_DV_BT_CEA_1920X1080I60 }, 103 { 0x0B, V4L2_DV_BT_CEA_1920X1080P30 }, 104 105 /* Default value: keep this field before 0xC */ 106 { 0x14, V4L2_DV_BT_CEA_1920X1080I50 }, 107 { 0x0C, V4L2_DV_BT_CEA_1920X1080I50 }, 108 { 0x0D, V4L2_DV_BT_CEA_1920X1080P25 }, 109 { 0x0E, V4L2_DV_BT_CEA_1920X1080P25 }, 110 { 0x10, V4L2_DV_BT_CEA_1920X1080P24 }, 111 { 0x12, V4L2_DV_BT_CEA_1920X1080P24 }, 112 { 0x16, V4L2_DV_BT_SDI_720X487I60 }, 113 { 0x19, V4L2_DV_BT_SDI_720X487I60 }, 114 { 0x18, V4L2_DV_BT_CEA_720X576P50 }, 115 { 0x1A, V4L2_DV_BT_CEA_720X576P50 }, 116 117 /* Implement following timings before enable it. 118 * Because of we don't have access to these theoretical timings yet. 119 * Workaround: use functions to get and set registers for these formats. 120 */ 121 #if 0 122 { 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ 123 { 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */ 124 { 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ 125 { 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */ 126 { 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ 127 { 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ 128 { 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */ 129 #endif 130 }; 131 132 static const struct v4l2_dv_timings_cap gs_timings_cap = { 133 .type = V4L2_DV_BT_656_1120, 134 /* keep this initialization for compatibility with GCC < 4.4.6 */ 135 .reserved = { 0 }, 136 V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN, 137 GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN, 138 GS_PIXELCLOCK_MAX, 139 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI, 140 V4L2_DV_BT_CAP_PROGRESSIVE 141 | V4L2_DV_BT_CAP_INTERLACED) 142 }; 143 144 static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value) 145 { 146 int ret; 147 u16 buf_addr = (0x8000 | (0x0FFF & addr)); 148 u16 buf_value = 0; 149 struct spi_message msg; 150 struct spi_transfer tx[] = { 151 { 152 .tx_buf = &buf_addr, 153 .len = 2, 154 .delay_usecs = 1, 155 }, { 156 .rx_buf = &buf_value, 157 .len = 2, 158 .delay_usecs = 1, 159 }, 160 }; 161 162 spi_message_init(&msg); 163 spi_message_add_tail(&tx[0], &msg); 164 spi_message_add_tail(&tx[1], &msg); 165 ret = spi_sync(spi, &msg); 166 167 *value = buf_value; 168 169 return ret; 170 } 171 172 static int gs_write_register(struct spi_device *spi, u16 addr, u16 value) 173 { 174 int ret; 175 u16 buf_addr = addr; 176 u16 buf_value = value; 177 struct spi_message msg; 178 struct spi_transfer tx[] = { 179 { 180 .tx_buf = &buf_addr, 181 .len = 2, 182 .delay_usecs = 1, 183 }, { 184 .tx_buf = &buf_value, 185 .len = 2, 186 .delay_usecs = 1, 187 }, 188 }; 189 190 spi_message_init(&msg); 191 spi_message_add_tail(&tx[0], &msg); 192 spi_message_add_tail(&tx[1], &msg); 193 ret = spi_sync(spi, &msg); 194 195 return ret; 196 } 197 198 #ifdef CONFIG_VIDEO_ADV_DEBUG 199 static int gs_g_register(struct v4l2_subdev *sd, 200 struct v4l2_dbg_register *reg) 201 { 202 struct spi_device *spi = v4l2_get_subdevdata(sd); 203 u16 val; 204 int ret; 205 206 ret = gs_read_register(spi, reg->reg & 0xFFFF, &val); 207 reg->val = val; 208 reg->size = 2; 209 return ret; 210 } 211 212 static int gs_s_register(struct v4l2_subdev *sd, 213 const struct v4l2_dbg_register *reg) 214 { 215 struct spi_device *spi = v4l2_get_subdevdata(sd); 216 217 return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF); 218 } 219 #endif 220 221 static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) 222 { 223 int std = (status & MASK_STD_STATUS) >> 5; 224 int i; 225 226 for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { 227 if (reg_fmt[i].reg_value == std) { 228 *timings = reg_fmt[i].format; 229 return 0; 230 } 231 } 232 233 return -ERANGE; 234 } 235 236 static u16 get_register_timings(struct v4l2_dv_timings *timings) 237 { 238 int i; 239 240 for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { 241 if (v4l2_match_dv_timings(timings, ®_fmt[i].format, 0, 242 false)) 243 return reg_fmt[i].reg_value | MASK_FORCE_STD; 244 } 245 246 return 0x0; 247 } 248 249 static inline struct gs *to_gs(struct v4l2_subdev *sd) 250 { 251 return container_of(sd, struct gs, sd); 252 } 253 254 static int gs_s_dv_timings(struct v4l2_subdev *sd, 255 struct v4l2_dv_timings *timings) 256 { 257 struct gs *gs = to_gs(sd); 258 int reg_value; 259 260 reg_value = get_register_timings(timings); 261 if (reg_value == 0x0) 262 return -EINVAL; 263 264 gs->current_timings = *timings; 265 return 0; 266 } 267 268 static int gs_g_dv_timings(struct v4l2_subdev *sd, 269 struct v4l2_dv_timings *timings) 270 { 271 struct gs *gs = to_gs(sd); 272 273 *timings = gs->current_timings; 274 return 0; 275 } 276 277 static int gs_query_dv_timings(struct v4l2_subdev *sd, 278 struct v4l2_dv_timings *timings) 279 { 280 struct gs *gs = to_gs(sd); 281 struct v4l2_dv_timings fmt; 282 u16 reg_value, i; 283 int ret; 284 285 if (gs->enabled) 286 return -EBUSY; 287 288 /* 289 * Check if the component detect a line, a frame or something else 290 * which looks like a video signal activity. 291 */ 292 for (i = 0; i < 4; i++) { 293 gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, ®_value); 294 if (reg_value) 295 break; 296 } 297 298 /* If no register reports a video signal */ 299 if (i >= 4) 300 return -ENOLINK; 301 302 gs_read_register(gs->pdev, REG_STATUS, ®_value); 303 if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK)) 304 return -ENOLCK; 305 if (!(reg_value & MASK_STD_LOCK)) 306 return -ERANGE; 307 308 ret = gs_status_format(reg_value, &fmt); 309 310 if (ret < 0) 311 return ret; 312 313 *timings = fmt; 314 return 0; 315 } 316 317 static int gs_enum_dv_timings(struct v4l2_subdev *sd, 318 struct v4l2_enum_dv_timings *timings) 319 { 320 if (timings->index >= ARRAY_SIZE(fmt_cap)) 321 return -EINVAL; 322 323 if (timings->pad != 0) 324 return -EINVAL; 325 326 timings->timings = fmt_cap[timings->index]; 327 return 0; 328 } 329 330 static int gs_s_stream(struct v4l2_subdev *sd, int enable) 331 { 332 struct gs *gs = to_gs(sd); 333 int reg_value; 334 335 if (gs->enabled == enable) 336 return 0; 337 338 gs->enabled = enable; 339 340 if (enable) { 341 /* To force the specific format */ 342 reg_value = get_register_timings(&gs->current_timings); 343 return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value); 344 } 345 346 /* To renable auto-detection mode */ 347 return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0); 348 } 349 350 static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status) 351 { 352 struct gs *gs = to_gs(sd); 353 u16 reg_value, i; 354 int ret; 355 356 /* 357 * Check if the component detect a line, a frame or something else 358 * which looks like a video signal activity. 359 */ 360 for (i = 0; i < 4; i++) { 361 ret = gs_read_register(gs->pdev, 362 REG_LINES_PER_FRAME + i, ®_value); 363 if (reg_value) 364 break; 365 if (ret) { 366 *status = V4L2_IN_ST_NO_POWER; 367 return ret; 368 } 369 } 370 371 /* If no register reports a video signal */ 372 if (i >= 4) 373 *status |= V4L2_IN_ST_NO_SIGNAL; 374 375 ret = gs_read_register(gs->pdev, REG_STATUS, ®_value); 376 if (!(reg_value & MASK_H_LOCK)) 377 *status |= V4L2_IN_ST_NO_H_LOCK; 378 if (!(reg_value & MASK_V_LOCK)) 379 *status |= V4L2_IN_ST_NO_V_LOCK; 380 if (!(reg_value & MASK_STD_LOCK)) 381 *status |= V4L2_IN_ST_NO_STD_LOCK; 382 383 return ret; 384 } 385 386 static int gs_dv_timings_cap(struct v4l2_subdev *sd, 387 struct v4l2_dv_timings_cap *cap) 388 { 389 if (cap->pad != 0) 390 return -EINVAL; 391 392 *cap = gs_timings_cap; 393 return 0; 394 } 395 396 /* V4L2 core operation handlers */ 397 static const struct v4l2_subdev_core_ops gs_core_ops = { 398 #ifdef CONFIG_VIDEO_ADV_DEBUG 399 .g_register = gs_g_register, 400 .s_register = gs_s_register, 401 #endif 402 }; 403 404 static const struct v4l2_subdev_video_ops gs_video_ops = { 405 .s_dv_timings = gs_s_dv_timings, 406 .g_dv_timings = gs_g_dv_timings, 407 .s_stream = gs_s_stream, 408 .g_input_status = gs_g_input_status, 409 .query_dv_timings = gs_query_dv_timings, 410 }; 411 412 static const struct v4l2_subdev_pad_ops gs_pad_ops = { 413 .enum_dv_timings = gs_enum_dv_timings, 414 .dv_timings_cap = gs_dv_timings_cap, 415 }; 416 417 /* V4L2 top level operation handlers */ 418 static const struct v4l2_subdev_ops gs_ops = { 419 .core = &gs_core_ops, 420 .video = &gs_video_ops, 421 .pad = &gs_pad_ops, 422 }; 423 424 static int gs_probe(struct spi_device *spi) 425 { 426 int ret; 427 struct gs *gs; 428 struct v4l2_subdev *sd; 429 430 gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL); 431 if (!gs) 432 return -ENOMEM; 433 434 gs->pdev = spi; 435 sd = &gs->sd; 436 437 spi->mode = SPI_MODE_0; 438 spi->irq = -1; 439 spi->max_speed_hz = 10000000; 440 spi->bits_per_word = 16; 441 ret = spi_setup(spi); 442 v4l2_spi_subdev_init(sd, spi, &gs_ops); 443 444 gs->current_timings = reg_fmt[0].format; 445 gs->enabled = 0; 446 447 /* Set H_CONFIG to SMPTE timings */ 448 gs_write_register(spi, 0x0, 0x300); 449 450 return ret; 451 } 452 453 static int gs_remove(struct spi_device *spi) 454 { 455 struct v4l2_subdev *sd = spi_get_drvdata(spi); 456 457 v4l2_device_unregister_subdev(sd); 458 459 return 0; 460 } 461 462 static struct spi_driver gs_driver = { 463 .driver = { 464 .name = "gs1662", 465 }, 466 467 .probe = gs_probe, 468 .remove = gs_remove, 469 .id_table = gs_id, 470 }; 471 472 module_spi_driver(gs_driver); 473 474 MODULE_LICENSE("GPL"); 475 MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>"); 476 MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver"); 477