1 /* 2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond 3 * SuperI/O chips. 4 * 5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but 6 * could probably support others (Winbond WEC102X, NatSemi, etc) 7 * with minor modifications. 8 * 9 * Original Author: David Härdeman <david@hardeman.nu> 10 * Copyright (C) 2012 Sean Young <sean@mess.org> 11 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu> 12 * 13 * Dedicated to my daughter Matilda, without whose loving attention this 14 * driver would have been finished in half the time and with a fraction 15 * of the bugs. 16 * 17 * Written using: 18 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel 19 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) 20 * o DSDT dumps 21 * 22 * Supported features: 23 * o IR Receive 24 * o IR Transmit 25 * o Wake-On-CIR functionality 26 * o Carrier detection 27 * 28 * This program is free software; you can redistribute it and/or modify 29 * it under the terms of the GNU General Public License as published by 30 * the Free Software Foundation; either version 2 of the License, or 31 * (at your option) any later version. 32 * 33 * This program is distributed in the hope that it will be useful, 34 * but WITHOUT ANY WARRANTY; without even the implied warranty of 35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 36 * GNU General Public License for more details. 37 * 38 * You should have received a copy of the GNU General Public License 39 * along with this program; if not, write to the Free Software 40 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 41 */ 42 43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 44 45 #include <linux/module.h> 46 #include <linux/pnp.h> 47 #include <linux/interrupt.h> 48 #include <linux/timer.h> 49 #include <linux/leds.h> 50 #include <linux/spinlock.h> 51 #include <linux/pci_ids.h> 52 #include <linux/io.h> 53 #include <linux/bitrev.h> 54 #include <linux/slab.h> 55 #include <linux/wait.h> 56 #include <linux/sched.h> 57 #include <media/rc-core.h> 58 59 #define DRVNAME "winbond-cir" 60 61 /* CEIR Wake-Up Registers, relative to data->wbase */ 62 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ 63 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ 64 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ 65 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ 66 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ 67 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ 68 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ 69 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ 70 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ 71 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ 72 73 /* CEIR Enhanced Functionality Registers, relative to data->ebase */ 74 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ 75 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ 76 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ 77 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ 78 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ 79 80 /* SP3 Banked Registers, relative to data->sbase */ 81 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ 82 /* Bank 0 */ 83 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ 84 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ 85 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ 86 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ 87 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ 88 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ 89 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ 90 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ 91 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ 92 /* Bank 2 */ 93 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ 94 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ 95 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ 96 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ 97 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ 98 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ 99 /* Bank 3 */ 100 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ 101 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ 102 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ 103 /* Bank 4 */ 104 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ 105 /* Bank 5 */ 106 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ 107 /* Bank 6 */ 108 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ 109 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ 110 /* Bank 7 */ 111 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ 112 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ 113 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ 114 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ 115 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ 116 117 /* 118 * Magic values follow 119 */ 120 121 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 122 #define WBCIR_IRQ_NONE 0x00 123 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 124 #define WBCIR_IRQ_RX 0x01 125 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 126 #define WBCIR_IRQ_TX_LOW 0x02 127 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 128 #define WBCIR_IRQ_ERR 0x04 129 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 130 #define WBCIR_IRQ_TX_EMPTY 0x20 131 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ 132 #define WBCIR_LED_ENABLE 0x80 133 /* RX data available bit for WBCIR_REG_SP3_LSR */ 134 #define WBCIR_RX_AVAIL 0x01 135 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ 136 #define WBCIR_RX_OVERRUN 0x02 137 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ 138 #define WBCIR_TX_EOT 0x04 139 /* RX disable bit for WBCIR_REG_SP3_ASCR */ 140 #define WBCIR_RX_DISABLE 0x20 141 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ 142 #define WBCIR_TX_UNDERRUN 0x40 143 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ 144 #define WBCIR_EXT_ENABLE 0x01 145 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ 146 #define WBCIR_REGSEL_COMPARE 0x10 147 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ 148 #define WBCIR_REGSEL_MASK 0x20 149 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ 150 #define WBCIR_REG_ADDR0 0x00 151 /* Enable carrier counter */ 152 #define WBCIR_CNTR_EN 0x01 153 /* Reset carrier counter */ 154 #define WBCIR_CNTR_R 0x02 155 /* Invert TX */ 156 #define WBCIR_IRTX_INV 0x04 157 158 /* Valid banks for the SP3 UART */ 159 enum wbcir_bank { 160 WBCIR_BANK_0 = 0x00, 161 WBCIR_BANK_1 = 0x80, 162 WBCIR_BANK_2 = 0xE0, 163 WBCIR_BANK_3 = 0xE4, 164 WBCIR_BANK_4 = 0xE8, 165 WBCIR_BANK_5 = 0xEC, 166 WBCIR_BANK_6 = 0xF0, 167 WBCIR_BANK_7 = 0xF4, 168 }; 169 170 /* Supported power-on IR Protocols */ 171 enum wbcir_protocol { 172 IR_PROTOCOL_RC5 = 0x0, 173 IR_PROTOCOL_NEC = 0x1, 174 IR_PROTOCOL_RC6 = 0x2, 175 }; 176 177 /* Possible states for IR reception */ 178 enum wbcir_rxstate { 179 WBCIR_RXSTATE_INACTIVE = 0, 180 WBCIR_RXSTATE_ACTIVE, 181 WBCIR_RXSTATE_ERROR 182 }; 183 184 /* Possible states for IR transmission */ 185 enum wbcir_txstate { 186 WBCIR_TXSTATE_INACTIVE = 0, 187 WBCIR_TXSTATE_ACTIVE, 188 WBCIR_TXSTATE_ERROR 189 }; 190 191 /* Misc */ 192 #define WBCIR_NAME "Winbond CIR" 193 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ 194 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ 195 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */ 196 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ 197 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ 198 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ 199 200 /* Per-device data */ 201 struct wbcir_data { 202 spinlock_t spinlock; 203 struct rc_dev *dev; 204 struct led_classdev led; 205 206 unsigned long wbase; /* Wake-Up Baseaddr */ 207 unsigned long ebase; /* Enhanced Func. Baseaddr */ 208 unsigned long sbase; /* Serial Port Baseaddr */ 209 unsigned int irq; /* Serial Port IRQ */ 210 u8 irqmask; 211 212 /* RX state */ 213 enum wbcir_rxstate rxstate; 214 struct led_trigger *rxtrigger; 215 int carrier_report_enabled; 216 u32 pulse_duration; 217 218 /* TX state */ 219 enum wbcir_txstate txstate; 220 struct led_trigger *txtrigger; 221 u32 txlen; 222 u32 txoff; 223 u32 *txbuf; 224 u8 txmask; 225 u32 txcarrier; 226 }; 227 228 static enum wbcir_protocol protocol = IR_PROTOCOL_RC6; 229 module_param(protocol, uint, 0444); 230 MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command " 231 "(0 = RC5, 1 = NEC, 2 = RC6A, default)"); 232 233 static bool invert; /* default = 0 */ 234 module_param(invert, bool, 0444); 235 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); 236 237 static bool txandrx; /* default = 0 */ 238 module_param(txandrx, bool, 0444); 239 MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); 240 241 static unsigned int wake_sc = 0x800F040C; 242 module_param(wake_sc, uint, 0644); 243 MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command"); 244 245 static unsigned int wake_rc6mode = 6; 246 module_param(wake_rc6mode, uint, 0644); 247 MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command " 248 "(0 = 0, 6 = 6A, default)"); 249 250 251 252 /***************************************************************************** 253 * 254 * UTILITY FUNCTIONS 255 * 256 *****************************************************************************/ 257 258 /* Caller needs to hold wbcir_lock */ 259 static void 260 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) 261 { 262 u8 val; 263 264 val = inb(addr); 265 val = ((val & ~mask) | (bits & mask)); 266 outb(val, addr); 267 } 268 269 /* Selects the register bank for the serial port */ 270 static inline void 271 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) 272 { 273 outb(bank, data->sbase + WBCIR_REG_SP3_BSR); 274 } 275 276 static inline void 277 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) 278 { 279 if (data->irqmask == irqmask) 280 return; 281 282 wbcir_select_bank(data, WBCIR_BANK_0); 283 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); 284 data->irqmask = irqmask; 285 } 286 287 static enum led_brightness 288 wbcir_led_brightness_get(struct led_classdev *led_cdev) 289 { 290 struct wbcir_data *data = container_of(led_cdev, 291 struct wbcir_data, 292 led); 293 294 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) 295 return LED_FULL; 296 else 297 return LED_OFF; 298 } 299 300 static void 301 wbcir_led_brightness_set(struct led_classdev *led_cdev, 302 enum led_brightness brightness) 303 { 304 struct wbcir_data *data = container_of(led_cdev, 305 struct wbcir_data, 306 led); 307 308 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, 309 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, 310 WBCIR_LED_ENABLE); 311 } 312 313 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ 314 static u8 315 wbcir_to_rc6cells(u8 val) 316 { 317 u8 coded = 0x00; 318 int i; 319 320 val &= 0x0F; 321 for (i = 0; i < 4; i++) { 322 if (val & 0x01) 323 coded |= 0x02 << (i * 2); 324 else 325 coded |= 0x01 << (i * 2); 326 val >>= 1; 327 } 328 329 return coded; 330 } 331 332 /***************************************************************************** 333 * 334 * INTERRUPT FUNCTIONS 335 * 336 *****************************************************************************/ 337 338 static void 339 wbcir_carrier_report(struct wbcir_data *data) 340 { 341 unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) | 342 inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8; 343 344 if (counter > 0 && counter < 0xffff) { 345 DEFINE_IR_RAW_EVENT(ev); 346 347 ev.carrier_report = 1; 348 ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u, 349 data->pulse_duration); 350 351 ir_raw_event_store(data->dev, &ev); 352 } 353 354 /* reset and restart the counter */ 355 data->pulse_duration = 0; 356 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, 357 WBCIR_CNTR_EN | WBCIR_CNTR_R); 358 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN, 359 WBCIR_CNTR_EN | WBCIR_CNTR_R); 360 } 361 362 static void 363 wbcir_idle_rx(struct rc_dev *dev, bool idle) 364 { 365 struct wbcir_data *data = dev->priv; 366 367 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) { 368 data->rxstate = WBCIR_RXSTATE_ACTIVE; 369 led_trigger_event(data->rxtrigger, LED_FULL); 370 } 371 372 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) { 373 data->rxstate = WBCIR_RXSTATE_INACTIVE; 374 led_trigger_event(data->rxtrigger, LED_OFF); 375 376 if (data->carrier_report_enabled) 377 wbcir_carrier_report(data); 378 379 /* Tell hardware to go idle by setting RXINACTIVE */ 380 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); 381 } 382 } 383 384 static void 385 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) 386 { 387 u8 irdata; 388 DEFINE_IR_RAW_EVENT(rawir); 389 unsigned duration; 390 391 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ 392 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { 393 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); 394 if (data->rxstate == WBCIR_RXSTATE_ERROR) 395 continue; 396 397 duration = ((irdata & 0x7F) + 1) * 2; 398 rawir.pulse = irdata & 0x80 ? false : true; 399 rawir.duration = US_TO_NS(duration); 400 401 if (rawir.pulse) 402 data->pulse_duration += duration; 403 404 ir_raw_event_store_with_filter(data->dev, &rawir); 405 } 406 407 ir_raw_event_handle(data->dev); 408 } 409 410 static void 411 wbcir_irq_tx(struct wbcir_data *data) 412 { 413 unsigned int space; 414 unsigned int used; 415 u8 bytes[16]; 416 u8 byte; 417 418 if (!data->txbuf) 419 return; 420 421 switch (data->txstate) { 422 case WBCIR_TXSTATE_INACTIVE: 423 /* TX FIFO empty */ 424 space = 16; 425 led_trigger_event(data->txtrigger, LED_FULL); 426 break; 427 case WBCIR_TXSTATE_ACTIVE: 428 /* TX FIFO low (3 bytes or less) */ 429 space = 13; 430 break; 431 case WBCIR_TXSTATE_ERROR: 432 space = 0; 433 break; 434 default: 435 return; 436 } 437 438 /* 439 * TX data is run-length coded in bytes: YXXXXXXX 440 * Y = space (1) or pulse (0) 441 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) 442 */ 443 for (used = 0; used < space && data->txoff != data->txlen; used++) { 444 if (data->txbuf[data->txoff] == 0) { 445 data->txoff++; 446 continue; 447 } 448 byte = min((u32)0x80, data->txbuf[data->txoff]); 449 data->txbuf[data->txoff] -= byte; 450 byte--; 451 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ 452 bytes[used] = byte; 453 } 454 455 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen) 456 data->txoff++; 457 458 if (used == 0) { 459 /* Finished */ 460 if (data->txstate == WBCIR_TXSTATE_ERROR) 461 /* Clear TX underrun bit */ 462 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); 463 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); 464 led_trigger_event(data->txtrigger, LED_OFF); 465 kfree(data->txbuf); 466 data->txbuf = NULL; 467 data->txstate = WBCIR_TXSTATE_INACTIVE; 468 } else if (data->txoff == data->txlen) { 469 /* At the end of transmission, tell the hw before last byte */ 470 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); 471 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); 472 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); 473 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | 474 WBCIR_IRQ_TX_EMPTY); 475 } else { 476 /* More data to follow... */ 477 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); 478 if (data->txstate == WBCIR_TXSTATE_INACTIVE) { 479 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | 480 WBCIR_IRQ_TX_LOW); 481 data->txstate = WBCIR_TXSTATE_ACTIVE; 482 } 483 } 484 } 485 486 static irqreturn_t 487 wbcir_irq_handler(int irqno, void *cookie) 488 { 489 struct pnp_dev *device = cookie; 490 struct wbcir_data *data = pnp_get_drvdata(device); 491 unsigned long flags; 492 u8 status; 493 494 spin_lock_irqsave(&data->spinlock, flags); 495 wbcir_select_bank(data, WBCIR_BANK_0); 496 status = inb(data->sbase + WBCIR_REG_SP3_EIR); 497 status &= data->irqmask; 498 499 if (!status) { 500 spin_unlock_irqrestore(&data->spinlock, flags); 501 return IRQ_NONE; 502 } 503 504 if (status & WBCIR_IRQ_ERR) { 505 /* RX overflow? (read clears bit) */ 506 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { 507 data->rxstate = WBCIR_RXSTATE_ERROR; 508 ir_raw_event_reset(data->dev); 509 } 510 511 /* TX underflow? */ 512 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) 513 data->txstate = WBCIR_TXSTATE_ERROR; 514 } 515 516 if (status & WBCIR_IRQ_RX) 517 wbcir_irq_rx(data, device); 518 519 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) 520 wbcir_irq_tx(data); 521 522 spin_unlock_irqrestore(&data->spinlock, flags); 523 return IRQ_HANDLED; 524 } 525 526 /***************************************************************************** 527 * 528 * RC-CORE INTERFACE FUNCTIONS 529 * 530 *****************************************************************************/ 531 532 static int 533 wbcir_set_carrier_report(struct rc_dev *dev, int enable) 534 { 535 struct wbcir_data *data = dev->priv; 536 unsigned long flags; 537 538 spin_lock_irqsave(&data->spinlock, flags); 539 540 if (data->carrier_report_enabled == enable) { 541 spin_unlock_irqrestore(&data->spinlock, flags); 542 return 0; 543 } 544 545 data->pulse_duration = 0; 546 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, 547 WBCIR_CNTR_EN | WBCIR_CNTR_R); 548 549 if (enable && data->dev->idle) 550 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, 551 WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R); 552 553 data->carrier_report_enabled = enable; 554 spin_unlock_irqrestore(&data->spinlock, flags); 555 556 return 0; 557 } 558 559 static int 560 wbcir_txcarrier(struct rc_dev *dev, u32 carrier) 561 { 562 struct wbcir_data *data = dev->priv; 563 unsigned long flags; 564 u8 val; 565 u32 freq; 566 567 freq = DIV_ROUND_CLOSEST(carrier, 1000); 568 if (freq < 30 || freq > 60) 569 return -EINVAL; 570 571 switch (freq) { 572 case 58: 573 case 59: 574 case 60: 575 val = freq - 58; 576 freq *= 1000; 577 break; 578 case 57: 579 val = freq - 27; 580 freq = 56900; 581 break; 582 default: 583 val = freq - 27; 584 freq *= 1000; 585 break; 586 } 587 588 spin_lock_irqsave(&data->spinlock, flags); 589 if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 590 spin_unlock_irqrestore(&data->spinlock, flags); 591 return -EBUSY; 592 } 593 594 if (data->txcarrier != freq) { 595 wbcir_select_bank(data, WBCIR_BANK_7); 596 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); 597 data->txcarrier = freq; 598 } 599 600 spin_unlock_irqrestore(&data->spinlock, flags); 601 return 0; 602 } 603 604 static int 605 wbcir_txmask(struct rc_dev *dev, u32 mask) 606 { 607 struct wbcir_data *data = dev->priv; 608 unsigned long flags; 609 u8 val; 610 611 /* Four outputs, only one output can be enabled at a time */ 612 switch (mask) { 613 case 0x1: 614 val = 0x0; 615 break; 616 case 0x2: 617 val = 0x1; 618 break; 619 case 0x4: 620 val = 0x2; 621 break; 622 case 0x8: 623 val = 0x3; 624 break; 625 default: 626 return -EINVAL; 627 } 628 629 spin_lock_irqsave(&data->spinlock, flags); 630 if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 631 spin_unlock_irqrestore(&data->spinlock, flags); 632 return -EBUSY; 633 } 634 635 if (data->txmask != mask) { 636 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); 637 data->txmask = mask; 638 } 639 640 spin_unlock_irqrestore(&data->spinlock, flags); 641 return 0; 642 } 643 644 static int 645 wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) 646 { 647 struct wbcir_data *data = dev->priv; 648 unsigned *buf; 649 unsigned i; 650 unsigned long flags; 651 652 buf = kmalloc(count * sizeof(*b), GFP_KERNEL); 653 if (!buf) 654 return -ENOMEM; 655 656 /* Convert values to multiples of 10us */ 657 for (i = 0; i < count; i++) 658 buf[i] = DIV_ROUND_CLOSEST(b[i], 10); 659 660 /* Not sure if this is possible, but better safe than sorry */ 661 spin_lock_irqsave(&data->spinlock, flags); 662 if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 663 spin_unlock_irqrestore(&data->spinlock, flags); 664 kfree(buf); 665 return -EBUSY; 666 } 667 668 /* Fill the TX fifo once, the irq handler will do the rest */ 669 data->txbuf = buf; 670 data->txlen = count; 671 data->txoff = 0; 672 wbcir_irq_tx(data); 673 674 /* We're done */ 675 spin_unlock_irqrestore(&data->spinlock, flags); 676 return count; 677 } 678 679 /***************************************************************************** 680 * 681 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS 682 * 683 *****************************************************************************/ 684 685 static void 686 wbcir_shutdown(struct pnp_dev *device) 687 { 688 struct device *dev = &device->dev; 689 struct wbcir_data *data = pnp_get_drvdata(device); 690 bool do_wake = true; 691 u8 match[11]; 692 u8 mask[11]; 693 u8 rc6_csl = 0; 694 int i; 695 696 memset(match, 0, sizeof(match)); 697 memset(mask, 0, sizeof(mask)); 698 699 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) { 700 do_wake = false; 701 goto finish; 702 } 703 704 switch (protocol) { 705 case IR_PROTOCOL_RC5: 706 if (wake_sc > 0xFFF) { 707 do_wake = false; 708 dev_err(dev, "RC5 - Invalid wake scancode\n"); 709 break; 710 } 711 712 /* Mask = 13 bits, ex toggle */ 713 mask[0] = 0xFF; 714 mask[1] = 0x17; 715 716 match[0] = (wake_sc & 0x003F); /* 6 command bits */ 717 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */ 718 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */ 719 if (!(wake_sc & 0x0040)) /* 2nd start bit */ 720 match[1] |= 0x10; 721 722 break; 723 724 case IR_PROTOCOL_NEC: 725 if (wake_sc > 0xFFFFFF) { 726 do_wake = false; 727 dev_err(dev, "NEC - Invalid wake scancode\n"); 728 break; 729 } 730 731 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF; 732 733 match[1] = bitrev8((wake_sc & 0xFF)); 734 match[0] = ~match[1]; 735 736 match[3] = bitrev8((wake_sc & 0xFF00) >> 8); 737 if (wake_sc > 0xFFFF) 738 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16); 739 else 740 match[2] = ~match[3]; 741 742 break; 743 744 case IR_PROTOCOL_RC6: 745 746 if (wake_rc6mode == 0) { 747 if (wake_sc > 0xFFFF) { 748 do_wake = false; 749 dev_err(dev, "RC6 - Invalid wake scancode\n"); 750 break; 751 } 752 753 /* Command */ 754 match[0] = wbcir_to_rc6cells(wake_sc >> 0); 755 mask[0] = 0xFF; 756 match[1] = wbcir_to_rc6cells(wake_sc >> 4); 757 mask[1] = 0xFF; 758 759 /* Address */ 760 match[2] = wbcir_to_rc6cells(wake_sc >> 8); 761 mask[2] = 0xFF; 762 match[3] = wbcir_to_rc6cells(wake_sc >> 12); 763 mask[3] = 0xFF; 764 765 /* Header */ 766 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ 767 mask[4] = 0xF0; 768 match[5] = 0x09; /* start bit = 1, mode2 = 0 */ 769 mask[5] = 0x0F; 770 771 rc6_csl = 44; 772 773 } else if (wake_rc6mode == 6) { 774 i = 0; 775 776 /* Command */ 777 match[i] = wbcir_to_rc6cells(wake_sc >> 0); 778 mask[i++] = 0xFF; 779 match[i] = wbcir_to_rc6cells(wake_sc >> 4); 780 mask[i++] = 0xFF; 781 782 /* Address + Toggle */ 783 match[i] = wbcir_to_rc6cells(wake_sc >> 8); 784 mask[i++] = 0xFF; 785 match[i] = wbcir_to_rc6cells(wake_sc >> 12); 786 mask[i++] = 0x3F; 787 788 /* Customer bits 7 - 0 */ 789 match[i] = wbcir_to_rc6cells(wake_sc >> 16); 790 mask[i++] = 0xFF; 791 match[i] = wbcir_to_rc6cells(wake_sc >> 20); 792 mask[i++] = 0xFF; 793 794 if (wake_sc & 0x80000000) { 795 /* Customer range bit and bits 15 - 8 */ 796 match[i] = wbcir_to_rc6cells(wake_sc >> 24); 797 mask[i++] = 0xFF; 798 match[i] = wbcir_to_rc6cells(wake_sc >> 28); 799 mask[i++] = 0xFF; 800 rc6_csl = 76; 801 } else if (wake_sc <= 0x007FFFFF) { 802 rc6_csl = 60; 803 } else { 804 do_wake = false; 805 dev_err(dev, "RC6 - Invalid wake scancode\n"); 806 break; 807 } 808 809 /* Header */ 810 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ 811 mask[i++] = 0xFF; 812 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ 813 mask[i++] = 0x0F; 814 815 } else { 816 do_wake = false; 817 dev_err(dev, "RC6 - Invalid wake mode\n"); 818 } 819 820 break; 821 822 default: 823 do_wake = false; 824 break; 825 } 826 827 finish: 828 if (do_wake) { 829 /* Set compare and compare mask */ 830 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, 831 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, 832 0x3F); 833 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); 834 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, 835 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, 836 0x3F); 837 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); 838 839 /* RC6 Compare String Len */ 840 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); 841 842 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 843 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 844 845 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ 846 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); 847 848 /* Set CEIR_EN */ 849 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01); 850 851 } else { 852 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ 853 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 854 855 /* Clear CEIR_EN */ 856 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); 857 } 858 859 /* 860 * ACPI will set the HW disable bit for SP3 which means that the 861 * output signals are left in an undefined state which may cause 862 * spurious interrupts which we need to ignore until the hardware 863 * is reinitialized. 864 */ 865 wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 866 disable_irq(data->irq); 867 868 /* Disable LED */ 869 led_trigger_event(data->rxtrigger, LED_OFF); 870 led_trigger_event(data->txtrigger, LED_OFF); 871 } 872 873 static int 874 wbcir_suspend(struct pnp_dev *device, pm_message_t state) 875 { 876 wbcir_shutdown(device); 877 return 0; 878 } 879 880 static void 881 wbcir_init_hw(struct wbcir_data *data) 882 { 883 u8 tmp; 884 885 /* Disable interrupts */ 886 wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 887 888 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */ 889 tmp = protocol << 4; 890 if (invert) 891 tmp |= 0x08; 892 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL); 893 894 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 895 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 896 897 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ 898 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 899 900 /* Set RC5 cell time to correspond to 36 kHz */ 901 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); 902 903 /* Set IRTX_INV */ 904 if (invert) 905 outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL); 906 else 907 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); 908 909 /* 910 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, 911 * set SP3_IRRX_SW to binary 01, helpfully not documented 912 */ 913 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); 914 data->txmask = 0x1; 915 916 /* Enable extended mode */ 917 wbcir_select_bank(data, WBCIR_BANK_2); 918 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); 919 920 /* 921 * Configure baud generator, IR data will be sampled at 922 * a bitrate of: (24Mhz * prescaler) / (divisor * 16). 923 * 924 * The ECIR registers include a flag to change the 925 * 24Mhz clock freq to 48Mhz. 926 * 927 * It's not documented in the specs, but fifo levels 928 * other than 16 seems to be unsupported. 929 */ 930 931 /* prescaler 1.0, tx/rx fifo lvl 16 */ 932 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); 933 934 /* Set baud divisor to sample every 2 ns */ 935 outb(0x03, data->sbase + WBCIR_REG_SP3_BGDL); 936 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); 937 938 /* Set CEIR mode */ 939 wbcir_select_bank(data, WBCIR_BANK_0); 940 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); 941 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ 942 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ 943 944 /* 945 * Disable RX demod, enable run-length enc/dec, set freq span and 946 * enable over-sampling 947 */ 948 wbcir_select_bank(data, WBCIR_BANK_7); 949 outb(0xd0, data->sbase + WBCIR_REG_SP3_RCCFG); 950 951 /* Disable timer */ 952 wbcir_select_bank(data, WBCIR_BANK_4); 953 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); 954 955 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ 956 wbcir_select_bank(data, WBCIR_BANK_5); 957 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); 958 959 /* Disable CRC */ 960 wbcir_select_bank(data, WBCIR_BANK_6); 961 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); 962 963 /* Set RX demodulation freq, not really used */ 964 wbcir_select_bank(data, WBCIR_BANK_7); 965 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); 966 967 /* Set TX modulation, 36kHz, 7us pulse width */ 968 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); 969 data->txcarrier = 36000; 970 971 /* Set invert and pin direction */ 972 if (invert) 973 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); 974 else 975 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); 976 977 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ 978 wbcir_select_bank(data, WBCIR_BANK_0); 979 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); 980 981 /* Clear AUX status bits */ 982 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); 983 984 /* Clear RX state */ 985 data->rxstate = WBCIR_RXSTATE_INACTIVE; 986 ir_raw_event_reset(data->dev); 987 ir_raw_event_set_idle(data->dev, true); 988 989 /* Clear TX state */ 990 if (data->txstate == WBCIR_TXSTATE_ACTIVE) { 991 kfree(data->txbuf); 992 data->txbuf = NULL; 993 data->txstate = WBCIR_TXSTATE_INACTIVE; 994 } 995 996 /* Enable interrupts */ 997 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); 998 } 999 1000 static int 1001 wbcir_resume(struct pnp_dev *device) 1002 { 1003 struct wbcir_data *data = pnp_get_drvdata(device); 1004 1005 wbcir_init_hw(data); 1006 enable_irq(data->irq); 1007 1008 return 0; 1009 } 1010 1011 static int 1012 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) 1013 { 1014 struct device *dev = &device->dev; 1015 struct wbcir_data *data; 1016 int err; 1017 1018 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && 1019 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && 1020 pnp_port_len(device, 2) == SP_IOMEM_LEN)) { 1021 dev_err(dev, "Invalid resources\n"); 1022 return -ENODEV; 1023 } 1024 1025 data = kzalloc(sizeof(*data), GFP_KERNEL); 1026 if (!data) { 1027 err = -ENOMEM; 1028 goto exit; 1029 } 1030 1031 pnp_set_drvdata(device, data); 1032 1033 spin_lock_init(&data->spinlock); 1034 data->ebase = pnp_port_start(device, 0); 1035 data->wbase = pnp_port_start(device, 1); 1036 data->sbase = pnp_port_start(device, 2); 1037 data->irq = pnp_irq(device, 0); 1038 1039 if (data->wbase == 0 || data->ebase == 0 || 1040 data->sbase == 0 || data->irq == 0) { 1041 err = -ENODEV; 1042 dev_err(dev, "Invalid resources\n"); 1043 goto exit_free_data; 1044 } 1045 1046 dev_dbg(&device->dev, "Found device " 1047 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", 1048 data->wbase, data->ebase, data->sbase, data->irq); 1049 1050 led_trigger_register_simple("cir-tx", &data->txtrigger); 1051 if (!data->txtrigger) { 1052 err = -ENOMEM; 1053 goto exit_free_data; 1054 } 1055 1056 led_trigger_register_simple("cir-rx", &data->rxtrigger); 1057 if (!data->rxtrigger) { 1058 err = -ENOMEM; 1059 goto exit_unregister_txtrigger; 1060 } 1061 1062 data->led.name = "cir::activity"; 1063 data->led.default_trigger = "cir-rx"; 1064 data->led.brightness_set = wbcir_led_brightness_set; 1065 data->led.brightness_get = wbcir_led_brightness_get; 1066 err = led_classdev_register(&device->dev, &data->led); 1067 if (err) 1068 goto exit_unregister_rxtrigger; 1069 1070 data->dev = rc_allocate_device(); 1071 if (!data->dev) { 1072 err = -ENOMEM; 1073 goto exit_unregister_led; 1074 } 1075 1076 data->dev->driver_type = RC_DRIVER_IR_RAW; 1077 data->dev->driver_name = DRVNAME; 1078 data->dev->input_name = WBCIR_NAME; 1079 data->dev->input_phys = "wbcir/cir0"; 1080 data->dev->input_id.bustype = BUS_HOST; 1081 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; 1082 data->dev->input_id.product = WBCIR_ID_FAMILY; 1083 data->dev->input_id.version = WBCIR_ID_CHIP; 1084 data->dev->map_name = RC_MAP_RC6_MCE; 1085 data->dev->s_idle = wbcir_idle_rx; 1086 data->dev->s_carrier_report = wbcir_set_carrier_report; 1087 data->dev->s_tx_mask = wbcir_txmask; 1088 data->dev->s_tx_carrier = wbcir_txcarrier; 1089 data->dev->tx_ir = wbcir_tx; 1090 data->dev->priv = data; 1091 data->dev->dev.parent = &device->dev; 1092 data->dev->timeout = MS_TO_NS(100); 1093 data->dev->rx_resolution = US_TO_NS(2); 1094 data->dev->allowed_protos = RC_BIT_ALL; 1095 1096 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { 1097 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 1098 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); 1099 err = -EBUSY; 1100 goto exit_free_rc; 1101 } 1102 1103 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { 1104 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 1105 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); 1106 err = -EBUSY; 1107 goto exit_release_wbase; 1108 } 1109 1110 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { 1111 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 1112 data->sbase, data->sbase + SP_IOMEM_LEN - 1); 1113 err = -EBUSY; 1114 goto exit_release_ebase; 1115 } 1116 1117 err = request_irq(data->irq, wbcir_irq_handler, 1118 IRQF_DISABLED, DRVNAME, device); 1119 if (err) { 1120 dev_err(dev, "Failed to claim IRQ %u\n", data->irq); 1121 err = -EBUSY; 1122 goto exit_release_sbase; 1123 } 1124 1125 err = rc_register_device(data->dev); 1126 if (err) 1127 goto exit_free_irq; 1128 1129 device_init_wakeup(&device->dev, 1); 1130 1131 wbcir_init_hw(data); 1132 1133 return 0; 1134 1135 exit_free_irq: 1136 free_irq(data->irq, device); 1137 exit_release_sbase: 1138 release_region(data->sbase, SP_IOMEM_LEN); 1139 exit_release_ebase: 1140 release_region(data->ebase, EHFUNC_IOMEM_LEN); 1141 exit_release_wbase: 1142 release_region(data->wbase, WAKEUP_IOMEM_LEN); 1143 exit_free_rc: 1144 rc_free_device(data->dev); 1145 exit_unregister_led: 1146 led_classdev_unregister(&data->led); 1147 exit_unregister_rxtrigger: 1148 led_trigger_unregister_simple(data->rxtrigger); 1149 exit_unregister_txtrigger: 1150 led_trigger_unregister_simple(data->txtrigger); 1151 exit_free_data: 1152 kfree(data); 1153 pnp_set_drvdata(device, NULL); 1154 exit: 1155 return err; 1156 } 1157 1158 static void 1159 wbcir_remove(struct pnp_dev *device) 1160 { 1161 struct wbcir_data *data = pnp_get_drvdata(device); 1162 1163 /* Disable interrupts */ 1164 wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 1165 free_irq(data->irq, device); 1166 1167 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 1168 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 1169 1170 /* Clear CEIR_EN */ 1171 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); 1172 1173 /* Clear BUFF_EN, END_EN, MATCH_EN */ 1174 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 1175 1176 rc_unregister_device(data->dev); 1177 1178 led_trigger_unregister_simple(data->rxtrigger); 1179 led_trigger_unregister_simple(data->txtrigger); 1180 led_classdev_unregister(&data->led); 1181 1182 /* This is ok since &data->led isn't actually used */ 1183 wbcir_led_brightness_set(&data->led, LED_OFF); 1184 1185 release_region(data->wbase, WAKEUP_IOMEM_LEN); 1186 release_region(data->ebase, EHFUNC_IOMEM_LEN); 1187 release_region(data->sbase, SP_IOMEM_LEN); 1188 1189 kfree(data); 1190 1191 pnp_set_drvdata(device, NULL); 1192 } 1193 1194 static const struct pnp_device_id wbcir_ids[] = { 1195 { "WEC1022", 0 }, 1196 { "", 0 } 1197 }; 1198 MODULE_DEVICE_TABLE(pnp, wbcir_ids); 1199 1200 static struct pnp_driver wbcir_driver = { 1201 .name = WBCIR_NAME, 1202 .id_table = wbcir_ids, 1203 .probe = wbcir_probe, 1204 .remove = wbcir_remove, 1205 .suspend = wbcir_suspend, 1206 .resume = wbcir_resume, 1207 .shutdown = wbcir_shutdown 1208 }; 1209 1210 static int __init 1211 wbcir_init(void) 1212 { 1213 int ret; 1214 1215 switch (protocol) { 1216 case IR_PROTOCOL_RC5: 1217 case IR_PROTOCOL_NEC: 1218 case IR_PROTOCOL_RC6: 1219 break; 1220 default: 1221 pr_err("Invalid power-on protocol\n"); 1222 } 1223 1224 ret = pnp_register_driver(&wbcir_driver); 1225 if (ret) 1226 pr_err("Unable to register driver\n"); 1227 1228 return ret; 1229 } 1230 1231 static void __exit 1232 wbcir_exit(void) 1233 { 1234 pnp_unregister_driver(&wbcir_driver); 1235 } 1236 1237 module_init(wbcir_init); 1238 module_exit(wbcir_exit); 1239 1240 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); 1241 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); 1242 MODULE_LICENSE("GPL"); 1243