1 /* 2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond 3 * SuperI/O chips. 4 * 5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but 6 * could probably support others (Winbond WEC102X, NatSemi, etc) 7 * with minor modifications. 8 * 9 * Original Author: David Härdeman <david@hardeman.nu> 10 * Copyright (C) 2012 Sean Young <sean@mess.org> 11 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu> 12 * 13 * Dedicated to my daughter Matilda, without whose loving attention this 14 * driver would have been finished in half the time and with a fraction 15 * of the bugs. 16 * 17 * Written using: 18 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel 19 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) 20 * o DSDT dumps 21 * 22 * Supported features: 23 * o IR Receive 24 * o IR Transmit 25 * o Wake-On-CIR functionality 26 * o Carrier detection 27 * 28 * This program is free software; you can redistribute it and/or modify 29 * it under the terms of the GNU General Public License as published by 30 * the Free Software Foundation; either version 2 of the License, or 31 * (at your option) any later version. 32 * 33 * This program is distributed in the hope that it will be useful, 34 * but WITHOUT ANY WARRANTY; without even the implied warranty of 35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 36 * GNU General Public License for more details. 37 */ 38 39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 40 41 #include <linux/module.h> 42 #include <linux/pnp.h> 43 #include <linux/interrupt.h> 44 #include <linux/timer.h> 45 #include <linux/leds.h> 46 #include <linux/spinlock.h> 47 #include <linux/pci_ids.h> 48 #include <linux/io.h> 49 #include <linux/bitrev.h> 50 #include <linux/slab.h> 51 #include <linux/wait.h> 52 #include <linux/sched.h> 53 #include <media/rc-core.h> 54 55 #define DRVNAME "winbond-cir" 56 57 /* CEIR Wake-Up Registers, relative to data->wbase */ 58 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ 59 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ 60 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ 61 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ 62 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ 63 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ 64 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ 65 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ 66 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ 67 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ 68 69 /* CEIR Enhanced Functionality Registers, relative to data->ebase */ 70 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ 71 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ 72 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ 73 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ 74 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ 75 76 /* SP3 Banked Registers, relative to data->sbase */ 77 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ 78 /* Bank 0 */ 79 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ 80 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ 81 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ 82 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ 83 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ 84 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ 85 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ 86 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ 87 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ 88 /* Bank 2 */ 89 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ 90 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ 91 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ 92 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ 93 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ 94 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ 95 /* Bank 3 */ 96 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ 97 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ 98 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ 99 /* Bank 4 */ 100 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ 101 /* Bank 5 */ 102 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ 103 /* Bank 6 */ 104 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ 105 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ 106 /* Bank 7 */ 107 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ 108 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ 109 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ 110 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ 111 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ 112 113 /* 114 * Magic values follow 115 */ 116 117 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 118 #define WBCIR_IRQ_NONE 0x00 119 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 120 #define WBCIR_IRQ_RX 0x01 121 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 122 #define WBCIR_IRQ_TX_LOW 0x02 123 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 124 #define WBCIR_IRQ_ERR 0x04 125 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 126 #define WBCIR_IRQ_TX_EMPTY 0x20 127 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ 128 #define WBCIR_LED_ENABLE 0x80 129 /* RX data available bit for WBCIR_REG_SP3_LSR */ 130 #define WBCIR_RX_AVAIL 0x01 131 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ 132 #define WBCIR_RX_OVERRUN 0x02 133 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ 134 #define WBCIR_TX_EOT 0x04 135 /* RX disable bit for WBCIR_REG_SP3_ASCR */ 136 #define WBCIR_RX_DISABLE 0x20 137 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ 138 #define WBCIR_TX_UNDERRUN 0x40 139 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ 140 #define WBCIR_EXT_ENABLE 0x01 141 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ 142 #define WBCIR_REGSEL_COMPARE 0x10 143 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ 144 #define WBCIR_REGSEL_MASK 0x20 145 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ 146 #define WBCIR_REG_ADDR0 0x00 147 /* Enable carrier counter */ 148 #define WBCIR_CNTR_EN 0x01 149 /* Reset carrier counter */ 150 #define WBCIR_CNTR_R 0x02 151 /* Invert TX */ 152 #define WBCIR_IRTX_INV 0x04 153 /* Receiver oversampling */ 154 #define WBCIR_RX_T_OV 0x40 155 156 /* Valid banks for the SP3 UART */ 157 enum wbcir_bank { 158 WBCIR_BANK_0 = 0x00, 159 WBCIR_BANK_1 = 0x80, 160 WBCIR_BANK_2 = 0xE0, 161 WBCIR_BANK_3 = 0xE4, 162 WBCIR_BANK_4 = 0xE8, 163 WBCIR_BANK_5 = 0xEC, 164 WBCIR_BANK_6 = 0xF0, 165 WBCIR_BANK_7 = 0xF4, 166 }; 167 168 /* Supported power-on IR Protocols */ 169 enum wbcir_protocol { 170 IR_PROTOCOL_RC5 = 0x0, 171 IR_PROTOCOL_NEC = 0x1, 172 IR_PROTOCOL_RC6 = 0x2, 173 }; 174 175 /* Possible states for IR reception */ 176 enum wbcir_rxstate { 177 WBCIR_RXSTATE_INACTIVE = 0, 178 WBCIR_RXSTATE_ACTIVE, 179 WBCIR_RXSTATE_ERROR 180 }; 181 182 /* Possible states for IR transmission */ 183 enum wbcir_txstate { 184 WBCIR_TXSTATE_INACTIVE = 0, 185 WBCIR_TXSTATE_ACTIVE, 186 WBCIR_TXSTATE_ERROR 187 }; 188 189 /* Misc */ 190 #define WBCIR_NAME "Winbond CIR" 191 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ 192 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ 193 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ 194 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ 195 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ 196 197 /* Per-device data */ 198 struct wbcir_data { 199 spinlock_t spinlock; 200 struct rc_dev *dev; 201 struct led_classdev led; 202 203 unsigned long wbase; /* Wake-Up Baseaddr */ 204 unsigned long ebase; /* Enhanced Func. Baseaddr */ 205 unsigned long sbase; /* Serial Port Baseaddr */ 206 unsigned int irq; /* Serial Port IRQ */ 207 u8 irqmask; 208 209 /* RX state */ 210 enum wbcir_rxstate rxstate; 211 int carrier_report_enabled; 212 u32 pulse_duration; 213 214 /* TX state */ 215 enum wbcir_txstate txstate; 216 u32 txlen; 217 u32 txoff; 218 u32 *txbuf; 219 u8 txmask; 220 u32 txcarrier; 221 }; 222 223 static bool invert; /* default = 0 */ 224 module_param(invert, bool, 0444); 225 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); 226 227 static bool txandrx; /* default = 0 */ 228 module_param(txandrx, bool, 0444); 229 MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); 230 231 232 /***************************************************************************** 233 * 234 * UTILITY FUNCTIONS 235 * 236 *****************************************************************************/ 237 238 /* Caller needs to hold wbcir_lock */ 239 static void 240 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) 241 { 242 u8 val; 243 244 val = inb(addr); 245 val = ((val & ~mask) | (bits & mask)); 246 outb(val, addr); 247 } 248 249 /* Selects the register bank for the serial port */ 250 static inline void 251 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) 252 { 253 outb(bank, data->sbase + WBCIR_REG_SP3_BSR); 254 } 255 256 static inline void 257 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) 258 { 259 if (data->irqmask == irqmask) 260 return; 261 262 wbcir_select_bank(data, WBCIR_BANK_0); 263 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); 264 data->irqmask = irqmask; 265 } 266 267 static enum led_brightness 268 wbcir_led_brightness_get(struct led_classdev *led_cdev) 269 { 270 struct wbcir_data *data = container_of(led_cdev, 271 struct wbcir_data, 272 led); 273 274 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) 275 return LED_FULL; 276 else 277 return LED_OFF; 278 } 279 280 static void 281 wbcir_led_brightness_set(struct led_classdev *led_cdev, 282 enum led_brightness brightness) 283 { 284 struct wbcir_data *data = container_of(led_cdev, 285 struct wbcir_data, 286 led); 287 288 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, 289 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, 290 WBCIR_LED_ENABLE); 291 } 292 293 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ 294 static u8 295 wbcir_to_rc6cells(u8 val) 296 { 297 u8 coded = 0x00; 298 int i; 299 300 val &= 0x0F; 301 for (i = 0; i < 4; i++) { 302 if (val & 0x01) 303 coded |= 0x02 << (i * 2); 304 else 305 coded |= 0x01 << (i * 2); 306 val >>= 1; 307 } 308 309 return coded; 310 } 311 312 /***************************************************************************** 313 * 314 * INTERRUPT FUNCTIONS 315 * 316 *****************************************************************************/ 317 318 static void 319 wbcir_carrier_report(struct wbcir_data *data) 320 { 321 unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) | 322 inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8; 323 324 if (counter > 0 && counter < 0xffff) { 325 DEFINE_IR_RAW_EVENT(ev); 326 327 ev.carrier_report = 1; 328 ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u, 329 data->pulse_duration); 330 331 ir_raw_event_store(data->dev, &ev); 332 } 333 334 /* reset and restart the counter */ 335 data->pulse_duration = 0; 336 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, 337 WBCIR_CNTR_EN | WBCIR_CNTR_R); 338 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN, 339 WBCIR_CNTR_EN | WBCIR_CNTR_R); 340 } 341 342 static void 343 wbcir_idle_rx(struct rc_dev *dev, bool idle) 344 { 345 struct wbcir_data *data = dev->priv; 346 347 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) 348 data->rxstate = WBCIR_RXSTATE_ACTIVE; 349 350 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) { 351 data->rxstate = WBCIR_RXSTATE_INACTIVE; 352 353 if (data->carrier_report_enabled) 354 wbcir_carrier_report(data); 355 356 /* Tell hardware to go idle by setting RXINACTIVE */ 357 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); 358 } 359 } 360 361 static void 362 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) 363 { 364 u8 irdata; 365 DEFINE_IR_RAW_EVENT(rawir); 366 unsigned duration; 367 368 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ 369 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { 370 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); 371 if (data->rxstate == WBCIR_RXSTATE_ERROR) 372 continue; 373 374 duration = ((irdata & 0x7F) + 1) * 375 (data->carrier_report_enabled ? 2 : 10); 376 rawir.pulse = irdata & 0x80 ? false : true; 377 rawir.duration = US_TO_NS(duration); 378 379 if (rawir.pulse) 380 data->pulse_duration += duration; 381 382 ir_raw_event_store_with_filter(data->dev, &rawir); 383 } 384 385 ir_raw_event_handle(data->dev); 386 } 387 388 static void 389 wbcir_irq_tx(struct wbcir_data *data) 390 { 391 unsigned int space; 392 unsigned int used; 393 u8 bytes[16]; 394 u8 byte; 395 396 if (!data->txbuf) 397 return; 398 399 switch (data->txstate) { 400 case WBCIR_TXSTATE_INACTIVE: 401 /* TX FIFO empty */ 402 space = 16; 403 break; 404 case WBCIR_TXSTATE_ACTIVE: 405 /* TX FIFO low (3 bytes or less) */ 406 space = 13; 407 break; 408 case WBCIR_TXSTATE_ERROR: 409 space = 0; 410 break; 411 default: 412 return; 413 } 414 415 /* 416 * TX data is run-length coded in bytes: YXXXXXXX 417 * Y = space (1) or pulse (0) 418 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) 419 */ 420 for (used = 0; used < space && data->txoff != data->txlen; used++) { 421 if (data->txbuf[data->txoff] == 0) { 422 data->txoff++; 423 continue; 424 } 425 byte = min((u32)0x80, data->txbuf[data->txoff]); 426 data->txbuf[data->txoff] -= byte; 427 byte--; 428 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ 429 bytes[used] = byte; 430 } 431 432 while (data->txoff != data->txlen && data->txbuf[data->txoff] == 0) 433 data->txoff++; 434 435 if (used == 0) { 436 /* Finished */ 437 if (data->txstate == WBCIR_TXSTATE_ERROR) 438 /* Clear TX underrun bit */ 439 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); 440 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); 441 kfree(data->txbuf); 442 data->txbuf = NULL; 443 data->txstate = WBCIR_TXSTATE_INACTIVE; 444 } else if (data->txoff == data->txlen) { 445 /* At the end of transmission, tell the hw before last byte */ 446 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); 447 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); 448 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); 449 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | 450 WBCIR_IRQ_TX_EMPTY); 451 } else { 452 /* More data to follow... */ 453 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); 454 if (data->txstate == WBCIR_TXSTATE_INACTIVE) { 455 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | 456 WBCIR_IRQ_TX_LOW); 457 data->txstate = WBCIR_TXSTATE_ACTIVE; 458 } 459 } 460 } 461 462 static irqreturn_t 463 wbcir_irq_handler(int irqno, void *cookie) 464 { 465 struct pnp_dev *device = cookie; 466 struct wbcir_data *data = pnp_get_drvdata(device); 467 unsigned long flags; 468 u8 status; 469 470 spin_lock_irqsave(&data->spinlock, flags); 471 wbcir_select_bank(data, WBCIR_BANK_0); 472 status = inb(data->sbase + WBCIR_REG_SP3_EIR); 473 status &= data->irqmask; 474 475 if (!status) { 476 spin_unlock_irqrestore(&data->spinlock, flags); 477 return IRQ_NONE; 478 } 479 480 if (status & WBCIR_IRQ_ERR) { 481 /* RX overflow? (read clears bit) */ 482 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { 483 data->rxstate = WBCIR_RXSTATE_ERROR; 484 ir_raw_event_reset(data->dev); 485 } 486 487 /* TX underflow? */ 488 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) 489 data->txstate = WBCIR_TXSTATE_ERROR; 490 } 491 492 if (status & WBCIR_IRQ_RX) 493 wbcir_irq_rx(data, device); 494 495 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) 496 wbcir_irq_tx(data); 497 498 spin_unlock_irqrestore(&data->spinlock, flags); 499 return IRQ_HANDLED; 500 } 501 502 /***************************************************************************** 503 * 504 * RC-CORE INTERFACE FUNCTIONS 505 * 506 *****************************************************************************/ 507 508 static int 509 wbcir_set_carrier_report(struct rc_dev *dev, int enable) 510 { 511 struct wbcir_data *data = dev->priv; 512 unsigned long flags; 513 514 spin_lock_irqsave(&data->spinlock, flags); 515 516 if (data->carrier_report_enabled == enable) { 517 spin_unlock_irqrestore(&data->spinlock, flags); 518 return 0; 519 } 520 521 data->pulse_duration = 0; 522 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, 523 WBCIR_CNTR_EN | WBCIR_CNTR_R); 524 525 if (enable && data->dev->idle) 526 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, 527 WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R); 528 529 /* Set a higher sampling resolution if carrier reports are enabled */ 530 wbcir_select_bank(data, WBCIR_BANK_2); 531 data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10); 532 outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL); 533 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); 534 535 /* Enable oversampling if carrier reports are enabled */ 536 wbcir_select_bank(data, WBCIR_BANK_7); 537 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG, 538 enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV); 539 540 data->carrier_report_enabled = enable; 541 spin_unlock_irqrestore(&data->spinlock, flags); 542 543 return 0; 544 } 545 546 static int 547 wbcir_txcarrier(struct rc_dev *dev, u32 carrier) 548 { 549 struct wbcir_data *data = dev->priv; 550 unsigned long flags; 551 u8 val; 552 u32 freq; 553 554 freq = DIV_ROUND_CLOSEST(carrier, 1000); 555 if (freq < 30 || freq > 60) 556 return -EINVAL; 557 558 switch (freq) { 559 case 58: 560 case 59: 561 case 60: 562 val = freq - 58; 563 freq *= 1000; 564 break; 565 case 57: 566 val = freq - 27; 567 freq = 56900; 568 break; 569 default: 570 val = freq - 27; 571 freq *= 1000; 572 break; 573 } 574 575 spin_lock_irqsave(&data->spinlock, flags); 576 if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 577 spin_unlock_irqrestore(&data->spinlock, flags); 578 return -EBUSY; 579 } 580 581 if (data->txcarrier != freq) { 582 wbcir_select_bank(data, WBCIR_BANK_7); 583 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); 584 data->txcarrier = freq; 585 } 586 587 spin_unlock_irqrestore(&data->spinlock, flags); 588 return 0; 589 } 590 591 static int 592 wbcir_txmask(struct rc_dev *dev, u32 mask) 593 { 594 struct wbcir_data *data = dev->priv; 595 unsigned long flags; 596 u8 val; 597 598 /* return the number of transmitters */ 599 if (mask > 15) 600 return 4; 601 602 /* Four outputs, only one output can be enabled at a time */ 603 switch (mask) { 604 case 0x1: 605 val = 0x0; 606 break; 607 case 0x2: 608 val = 0x1; 609 break; 610 case 0x4: 611 val = 0x2; 612 break; 613 case 0x8: 614 val = 0x3; 615 break; 616 default: 617 return -EINVAL; 618 } 619 620 spin_lock_irqsave(&data->spinlock, flags); 621 if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 622 spin_unlock_irqrestore(&data->spinlock, flags); 623 return -EBUSY; 624 } 625 626 if (data->txmask != mask) { 627 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); 628 data->txmask = mask; 629 } 630 631 spin_unlock_irqrestore(&data->spinlock, flags); 632 return 0; 633 } 634 635 static int 636 wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) 637 { 638 struct wbcir_data *data = dev->priv; 639 unsigned *buf; 640 unsigned i; 641 unsigned long flags; 642 643 buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL); 644 if (!buf) 645 return -ENOMEM; 646 647 /* Convert values to multiples of 10us */ 648 for (i = 0; i < count; i++) 649 buf[i] = DIV_ROUND_CLOSEST(b[i], 10); 650 651 /* Not sure if this is possible, but better safe than sorry */ 652 spin_lock_irqsave(&data->spinlock, flags); 653 if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 654 spin_unlock_irqrestore(&data->spinlock, flags); 655 kfree(buf); 656 return -EBUSY; 657 } 658 659 /* Fill the TX fifo once, the irq handler will do the rest */ 660 data->txbuf = buf; 661 data->txlen = count; 662 data->txoff = 0; 663 wbcir_irq_tx(data); 664 665 /* We're done */ 666 spin_unlock_irqrestore(&data->spinlock, flags); 667 return count; 668 } 669 670 /***************************************************************************** 671 * 672 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS 673 * 674 *****************************************************************************/ 675 676 static void 677 wbcir_shutdown(struct pnp_dev *device) 678 { 679 struct device *dev = &device->dev; 680 struct wbcir_data *data = pnp_get_drvdata(device); 681 struct rc_dev *rc = data->dev; 682 bool do_wake = true; 683 u8 match[11]; 684 u8 mask[11]; 685 u8 rc6_csl = 0; 686 u8 proto; 687 u32 wake_sc = rc->scancode_wakeup_filter.data; 688 u32 mask_sc = rc->scancode_wakeup_filter.mask; 689 int i; 690 691 memset(match, 0, sizeof(match)); 692 memset(mask, 0, sizeof(mask)); 693 694 if (!mask_sc || !device_may_wakeup(dev)) { 695 do_wake = false; 696 goto finish; 697 } 698 699 switch (rc->wakeup_protocol) { 700 case RC_PROTO_RC5: 701 /* Mask = 13 bits, ex toggle */ 702 mask[0] = (mask_sc & 0x003f); 703 mask[0] |= (mask_sc & 0x0300) >> 2; 704 mask[1] = (mask_sc & 0x1c00) >> 10; 705 if (mask_sc & 0x0040) /* 2nd start bit */ 706 match[1] |= 0x10; 707 708 match[0] = (wake_sc & 0x003F); /* 6 command bits */ 709 match[0] |= (wake_sc & 0x0300) >> 2; /* 2 address bits */ 710 match[1] = (wake_sc & 0x1c00) >> 10; /* 3 address bits */ 711 if (!(wake_sc & 0x0040)) /* 2nd start bit */ 712 match[1] |= 0x10; 713 714 proto = IR_PROTOCOL_RC5; 715 break; 716 717 case RC_PROTO_NEC: 718 mask[1] = bitrev8(mask_sc); 719 mask[0] = mask[1]; 720 mask[3] = bitrev8(mask_sc >> 8); 721 mask[2] = mask[3]; 722 723 match[1] = bitrev8(wake_sc); 724 match[0] = ~match[1]; 725 match[3] = bitrev8(wake_sc >> 8); 726 match[2] = ~match[3]; 727 728 proto = IR_PROTOCOL_NEC; 729 break; 730 731 case RC_PROTO_NECX: 732 mask[1] = bitrev8(mask_sc); 733 mask[0] = mask[1]; 734 mask[2] = bitrev8(mask_sc >> 8); 735 mask[3] = bitrev8(mask_sc >> 16); 736 737 match[1] = bitrev8(wake_sc); 738 match[0] = ~match[1]; 739 match[2] = bitrev8(wake_sc >> 8); 740 match[3] = bitrev8(wake_sc >> 16); 741 742 proto = IR_PROTOCOL_NEC; 743 break; 744 745 case RC_PROTO_NEC32: 746 mask[0] = bitrev8(mask_sc); 747 mask[1] = bitrev8(mask_sc >> 8); 748 mask[2] = bitrev8(mask_sc >> 16); 749 mask[3] = bitrev8(mask_sc >> 24); 750 751 match[0] = bitrev8(wake_sc); 752 match[1] = bitrev8(wake_sc >> 8); 753 match[2] = bitrev8(wake_sc >> 16); 754 match[3] = bitrev8(wake_sc >> 24); 755 756 proto = IR_PROTOCOL_NEC; 757 break; 758 759 case RC_PROTO_RC6_0: 760 /* Command */ 761 match[0] = wbcir_to_rc6cells(wake_sc >> 0); 762 mask[0] = wbcir_to_rc6cells(mask_sc >> 0); 763 match[1] = wbcir_to_rc6cells(wake_sc >> 4); 764 mask[1] = wbcir_to_rc6cells(mask_sc >> 4); 765 766 /* Address */ 767 match[2] = wbcir_to_rc6cells(wake_sc >> 8); 768 mask[2] = wbcir_to_rc6cells(mask_sc >> 8); 769 match[3] = wbcir_to_rc6cells(wake_sc >> 12); 770 mask[3] = wbcir_to_rc6cells(mask_sc >> 12); 771 772 /* Header */ 773 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ 774 mask[4] = 0xF0; 775 match[5] = 0x09; /* start bit = 1, mode2 = 0 */ 776 mask[5] = 0x0F; 777 778 rc6_csl = 44; 779 proto = IR_PROTOCOL_RC6; 780 break; 781 782 case RC_PROTO_RC6_6A_24: 783 case RC_PROTO_RC6_6A_32: 784 case RC_PROTO_RC6_MCE: 785 i = 0; 786 787 /* Command */ 788 match[i] = wbcir_to_rc6cells(wake_sc >> 0); 789 mask[i++] = wbcir_to_rc6cells(mask_sc >> 0); 790 match[i] = wbcir_to_rc6cells(wake_sc >> 4); 791 mask[i++] = wbcir_to_rc6cells(mask_sc >> 4); 792 793 /* Address + Toggle */ 794 match[i] = wbcir_to_rc6cells(wake_sc >> 8); 795 mask[i++] = wbcir_to_rc6cells(mask_sc >> 8); 796 match[i] = wbcir_to_rc6cells(wake_sc >> 12); 797 mask[i++] = wbcir_to_rc6cells(mask_sc >> 12); 798 799 /* Customer bits 7 - 0 */ 800 match[i] = wbcir_to_rc6cells(wake_sc >> 16); 801 mask[i++] = wbcir_to_rc6cells(mask_sc >> 16); 802 803 if (rc->wakeup_protocol == RC_PROTO_RC6_6A_20) { 804 rc6_csl = 52; 805 } else { 806 match[i] = wbcir_to_rc6cells(wake_sc >> 20); 807 mask[i++] = wbcir_to_rc6cells(mask_sc >> 20); 808 809 if (rc->wakeup_protocol == RC_PROTO_RC6_6A_24) { 810 rc6_csl = 60; 811 } else { 812 /* Customer range bit and bits 15 - 8 */ 813 match[i] = wbcir_to_rc6cells(wake_sc >> 24); 814 mask[i++] = wbcir_to_rc6cells(mask_sc >> 24); 815 match[i] = wbcir_to_rc6cells(wake_sc >> 28); 816 mask[i++] = wbcir_to_rc6cells(mask_sc >> 28); 817 rc6_csl = 76; 818 } 819 } 820 821 /* Header */ 822 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ 823 mask[i++] = 0xFF; 824 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ 825 mask[i++] = 0x0F; 826 proto = IR_PROTOCOL_RC6; 827 break; 828 default: 829 do_wake = false; 830 break; 831 } 832 833 finish: 834 if (do_wake) { 835 /* Set compare and compare mask */ 836 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, 837 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, 838 0x3F); 839 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); 840 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, 841 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, 842 0x3F); 843 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); 844 845 /* RC6 Compare String Len */ 846 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); 847 848 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 849 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 850 851 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ 852 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); 853 854 /* Set CEIR_EN */ 855 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 856 (proto << 4) | 0x01, 0x31); 857 858 } else { 859 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ 860 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 861 862 /* Clear CEIR_EN */ 863 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); 864 } 865 866 /* 867 * ACPI will set the HW disable bit for SP3 which means that the 868 * output signals are left in an undefined state which may cause 869 * spurious interrupts which we need to ignore until the hardware 870 * is reinitialized. 871 */ 872 wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 873 disable_irq(data->irq); 874 } 875 876 /* 877 * Wakeup handling is done on shutdown. 878 */ 879 static int 880 wbcir_set_wakeup_filter(struct rc_dev *rc, struct rc_scancode_filter *filter) 881 { 882 return 0; 883 } 884 885 static int 886 wbcir_suspend(struct pnp_dev *device, pm_message_t state) 887 { 888 struct wbcir_data *data = pnp_get_drvdata(device); 889 led_classdev_suspend(&data->led); 890 wbcir_shutdown(device); 891 return 0; 892 } 893 894 static void 895 wbcir_init_hw(struct wbcir_data *data) 896 { 897 /* Disable interrupts */ 898 wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 899 900 /* Set RX_INV, Clear CEIR_EN (needed for the led) */ 901 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, invert ? 8 : 0, 0x09); 902 903 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 904 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 905 906 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ 907 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 908 909 /* Set RC5 cell time to correspond to 36 kHz */ 910 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); 911 912 /* Set IRTX_INV */ 913 if (invert) 914 outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL); 915 else 916 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); 917 918 /* 919 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, 920 * set SP3_IRRX_SW to binary 01, helpfully not documented 921 */ 922 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); 923 data->txmask = 0x1; 924 925 /* Enable extended mode */ 926 wbcir_select_bank(data, WBCIR_BANK_2); 927 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); 928 929 /* 930 * Configure baud generator, IR data will be sampled at 931 * a bitrate of: (24Mhz * prescaler) / (divisor * 16). 932 * 933 * The ECIR registers include a flag to change the 934 * 24Mhz clock freq to 48Mhz. 935 * 936 * It's not documented in the specs, but fifo levels 937 * other than 16 seems to be unsupported. 938 */ 939 940 /* prescaler 1.0, tx/rx fifo lvl 16 */ 941 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); 942 943 /* Set baud divisor to sample every 10 us */ 944 outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL); 945 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); 946 947 /* Set CEIR mode */ 948 wbcir_select_bank(data, WBCIR_BANK_0); 949 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); 950 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ 951 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ 952 953 /* Disable RX demod, enable run-length enc/dec, set freq span */ 954 wbcir_select_bank(data, WBCIR_BANK_7); 955 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG); 956 957 /* Disable timer */ 958 wbcir_select_bank(data, WBCIR_BANK_4); 959 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); 960 961 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ 962 wbcir_select_bank(data, WBCIR_BANK_5); 963 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); 964 965 /* Disable CRC */ 966 wbcir_select_bank(data, WBCIR_BANK_6); 967 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); 968 969 /* Set RX demodulation freq, not really used */ 970 wbcir_select_bank(data, WBCIR_BANK_7); 971 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); 972 973 /* Set TX modulation, 36kHz, 7us pulse width */ 974 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); 975 data->txcarrier = 36000; 976 977 /* Set invert and pin direction */ 978 if (invert) 979 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); 980 else 981 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); 982 983 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ 984 wbcir_select_bank(data, WBCIR_BANK_0); 985 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); 986 987 /* Clear AUX status bits */ 988 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); 989 990 /* Clear RX state */ 991 data->rxstate = WBCIR_RXSTATE_INACTIVE; 992 ir_raw_event_reset(data->dev); 993 ir_raw_event_set_idle(data->dev, true); 994 995 /* Clear TX state */ 996 if (data->txstate == WBCIR_TXSTATE_ACTIVE) { 997 kfree(data->txbuf); 998 data->txbuf = NULL; 999 data->txstate = WBCIR_TXSTATE_INACTIVE; 1000 } 1001 1002 /* Enable interrupts */ 1003 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); 1004 } 1005 1006 static int 1007 wbcir_resume(struct pnp_dev *device) 1008 { 1009 struct wbcir_data *data = pnp_get_drvdata(device); 1010 1011 wbcir_init_hw(data); 1012 enable_irq(data->irq); 1013 led_classdev_resume(&data->led); 1014 1015 return 0; 1016 } 1017 1018 static int 1019 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) 1020 { 1021 struct device *dev = &device->dev; 1022 struct wbcir_data *data; 1023 int err; 1024 1025 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && 1026 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && 1027 pnp_port_len(device, 2) == SP_IOMEM_LEN)) { 1028 dev_err(dev, "Invalid resources\n"); 1029 return -ENODEV; 1030 } 1031 1032 data = kzalloc(sizeof(*data), GFP_KERNEL); 1033 if (!data) { 1034 err = -ENOMEM; 1035 goto exit; 1036 } 1037 1038 pnp_set_drvdata(device, data); 1039 1040 spin_lock_init(&data->spinlock); 1041 data->ebase = pnp_port_start(device, 0); 1042 data->wbase = pnp_port_start(device, 1); 1043 data->sbase = pnp_port_start(device, 2); 1044 data->irq = pnp_irq(device, 0); 1045 1046 if (data->wbase == 0 || data->ebase == 0 || 1047 data->sbase == 0 || data->irq == 0) { 1048 err = -ENODEV; 1049 dev_err(dev, "Invalid resources\n"); 1050 goto exit_free_data; 1051 } 1052 1053 dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", 1054 data->wbase, data->ebase, data->sbase, data->irq); 1055 1056 data->led.name = "cir::activity"; 1057 data->led.default_trigger = "rc-feedback"; 1058 data->led.brightness_set = wbcir_led_brightness_set; 1059 data->led.brightness_get = wbcir_led_brightness_get; 1060 err = led_classdev_register(&device->dev, &data->led); 1061 if (err) 1062 goto exit_free_data; 1063 1064 data->dev = rc_allocate_device(RC_DRIVER_IR_RAW); 1065 if (!data->dev) { 1066 err = -ENOMEM; 1067 goto exit_unregister_led; 1068 } 1069 1070 data->dev->driver_name = DRVNAME; 1071 data->dev->device_name = WBCIR_NAME; 1072 data->dev->input_phys = "wbcir/cir0"; 1073 data->dev->input_id.bustype = BUS_HOST; 1074 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; 1075 data->dev->input_id.product = WBCIR_ID_FAMILY; 1076 data->dev->input_id.version = WBCIR_ID_CHIP; 1077 data->dev->map_name = RC_MAP_RC6_MCE; 1078 data->dev->s_idle = wbcir_idle_rx; 1079 data->dev->s_carrier_report = wbcir_set_carrier_report; 1080 data->dev->s_tx_mask = wbcir_txmask; 1081 data->dev->s_tx_carrier = wbcir_txcarrier; 1082 data->dev->tx_ir = wbcir_tx; 1083 data->dev->priv = data; 1084 data->dev->dev.parent = &device->dev; 1085 data->dev->min_timeout = 1; 1086 data->dev->timeout = IR_DEFAULT_TIMEOUT; 1087 data->dev->max_timeout = 10 * IR_DEFAULT_TIMEOUT; 1088 data->dev->rx_resolution = US_TO_NS(2); 1089 data->dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 1090 data->dev->allowed_wakeup_protocols = RC_PROTO_BIT_NEC | 1091 RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | RC_PROTO_BIT_RC5 | 1092 RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 | 1093 RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 | 1094 RC_PROTO_BIT_RC6_MCE; 1095 data->dev->wakeup_protocol = RC_PROTO_RC6_MCE; 1096 data->dev->scancode_wakeup_filter.data = 0x800f040c; 1097 data->dev->scancode_wakeup_filter.mask = 0xffff7fff; 1098 data->dev->s_wakeup_filter = wbcir_set_wakeup_filter; 1099 1100 err = rc_register_device(data->dev); 1101 if (err) 1102 goto exit_free_rc; 1103 1104 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { 1105 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 1106 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); 1107 err = -EBUSY; 1108 goto exit_unregister_device; 1109 } 1110 1111 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { 1112 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 1113 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); 1114 err = -EBUSY; 1115 goto exit_release_wbase; 1116 } 1117 1118 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { 1119 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 1120 data->sbase, data->sbase + SP_IOMEM_LEN - 1); 1121 err = -EBUSY; 1122 goto exit_release_ebase; 1123 } 1124 1125 err = request_irq(data->irq, wbcir_irq_handler, 1126 0, DRVNAME, device); 1127 if (err) { 1128 dev_err(dev, "Failed to claim IRQ %u\n", data->irq); 1129 err = -EBUSY; 1130 goto exit_release_sbase; 1131 } 1132 1133 device_init_wakeup(&device->dev, 1); 1134 1135 wbcir_init_hw(data); 1136 1137 return 0; 1138 1139 exit_release_sbase: 1140 release_region(data->sbase, SP_IOMEM_LEN); 1141 exit_release_ebase: 1142 release_region(data->ebase, EHFUNC_IOMEM_LEN); 1143 exit_release_wbase: 1144 release_region(data->wbase, WAKEUP_IOMEM_LEN); 1145 exit_unregister_device: 1146 rc_unregister_device(data->dev); 1147 data->dev = NULL; 1148 exit_free_rc: 1149 rc_free_device(data->dev); 1150 exit_unregister_led: 1151 led_classdev_unregister(&data->led); 1152 exit_free_data: 1153 kfree(data); 1154 pnp_set_drvdata(device, NULL); 1155 exit: 1156 return err; 1157 } 1158 1159 static void 1160 wbcir_remove(struct pnp_dev *device) 1161 { 1162 struct wbcir_data *data = pnp_get_drvdata(device); 1163 1164 /* Disable interrupts */ 1165 wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 1166 free_irq(data->irq, device); 1167 1168 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 1169 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 1170 1171 /* Clear CEIR_EN */ 1172 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); 1173 1174 /* Clear BUFF_EN, END_EN, MATCH_EN */ 1175 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 1176 1177 rc_unregister_device(data->dev); 1178 1179 led_classdev_unregister(&data->led); 1180 1181 /* This is ok since &data->led isn't actually used */ 1182 wbcir_led_brightness_set(&data->led, LED_OFF); 1183 1184 release_region(data->wbase, WAKEUP_IOMEM_LEN); 1185 release_region(data->ebase, EHFUNC_IOMEM_LEN); 1186 release_region(data->sbase, SP_IOMEM_LEN); 1187 1188 kfree(data); 1189 1190 pnp_set_drvdata(device, NULL); 1191 } 1192 1193 static const struct pnp_device_id wbcir_ids[] = { 1194 { "WEC1022", 0 }, 1195 { "", 0 } 1196 }; 1197 MODULE_DEVICE_TABLE(pnp, wbcir_ids); 1198 1199 static struct pnp_driver wbcir_driver = { 1200 .name = DRVNAME, 1201 .id_table = wbcir_ids, 1202 .probe = wbcir_probe, 1203 .remove = wbcir_remove, 1204 .suspend = wbcir_suspend, 1205 .resume = wbcir_resume, 1206 .shutdown = wbcir_shutdown 1207 }; 1208 1209 static int __init 1210 wbcir_init(void) 1211 { 1212 int ret; 1213 1214 ret = pnp_register_driver(&wbcir_driver); 1215 if (ret) 1216 pr_err("Unable to register driver\n"); 1217 1218 return ret; 1219 } 1220 1221 static void __exit 1222 wbcir_exit(void) 1223 { 1224 pnp_unregister_driver(&wbcir_driver); 1225 } 1226 1227 module_init(wbcir_init); 1228 module_exit(wbcir_exit); 1229 1230 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); 1231 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); 1232 MODULE_LICENSE("GPL"); 1233