15b2e303fSDavid Härdeman /* 25b2e303fSDavid Härdeman * winbond-cir.c - Driver for the Consumer IR functionality of Winbond 35b2e303fSDavid Härdeman * SuperI/O chips. 45b2e303fSDavid Härdeman * 55b2e303fSDavid Härdeman * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but 65b2e303fSDavid Härdeman * could probably support others (Winbond WEC102X, NatSemi, etc) 75b2e303fSDavid Härdeman * with minor modifications. 85b2e303fSDavid Härdeman * 9b87f2eddSDavid Härdeman * Original Author: David Härdeman <david@hardeman.nu> 1037b0b4e9SSean Young * Copyright (C) 2012 Sean Young <sean@mess.org> 11b87f2eddSDavid Härdeman * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu> 125b2e303fSDavid Härdeman * 135b2e303fSDavid Härdeman * Dedicated to my daughter Matilda, without whose loving attention this 145b2e303fSDavid Härdeman * driver would have been finished in half the time and with a fraction 155b2e303fSDavid Härdeman * of the bugs. 165b2e303fSDavid Härdeman * 175b2e303fSDavid Härdeman * Written using: 185b2e303fSDavid Härdeman * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel 195b2e303fSDavid Härdeman * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) 205b2e303fSDavid Härdeman * o DSDT dumps 215b2e303fSDavid Härdeman * 225b2e303fSDavid Härdeman * Supported features: 23c829f267SDavid Härdeman * o IR Receive 24c829f267SDavid Härdeman * o IR Transmit 255b2e303fSDavid Härdeman * o Wake-On-CIR functionality 2637b0b4e9SSean Young * o Carrier detection 275b2e303fSDavid Härdeman * 285b2e303fSDavid Härdeman * This program is free software; you can redistribute it and/or modify 295b2e303fSDavid Härdeman * it under the terms of the GNU General Public License as published by 305b2e303fSDavid Härdeman * the Free Software Foundation; either version 2 of the License, or 315b2e303fSDavid Härdeman * (at your option) any later version. 325b2e303fSDavid Härdeman * 335b2e303fSDavid Härdeman * This program is distributed in the hope that it will be useful, 345b2e303fSDavid Härdeman * but WITHOUT ANY WARRANTY; without even the implied warranty of 355b2e303fSDavid Härdeman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 365b2e303fSDavid Härdeman * GNU General Public License for more details. 375b2e303fSDavid Härdeman */ 385b2e303fSDavid Härdeman 39d8a10ac9SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 40d8a10ac9SJoe Perches 415b2e303fSDavid Härdeman #include <linux/module.h> 425b2e303fSDavid Härdeman #include <linux/pnp.h> 435b2e303fSDavid Härdeman #include <linux/interrupt.h> 445b2e303fSDavid Härdeman #include <linux/timer.h> 455b2e303fSDavid Härdeman #include <linux/leds.h> 465b2e303fSDavid Härdeman #include <linux/spinlock.h> 475b2e303fSDavid Härdeman #include <linux/pci_ids.h> 485b2e303fSDavid Härdeman #include <linux/io.h> 495b2e303fSDavid Härdeman #include <linux/bitrev.h> 505b2e303fSDavid Härdeman #include <linux/slab.h> 51c829f267SDavid Härdeman #include <linux/wait.h> 52c829f267SDavid Härdeman #include <linux/sched.h> 536bda9644SMauro Carvalho Chehab #include <media/rc-core.h> 545b2e303fSDavid Härdeman 555b2e303fSDavid Härdeman #define DRVNAME "winbond-cir" 565b2e303fSDavid Härdeman 575b2e303fSDavid Härdeman /* CEIR Wake-Up Registers, relative to data->wbase */ 585b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ 595b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ 605b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ 615b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ 625b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ 635b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ 645b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ 655b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ 665b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ 675b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ 685b2e303fSDavid Härdeman 695b2e303fSDavid Härdeman /* CEIR Enhanced Functionality Registers, relative to data->ebase */ 705b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ 715b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ 725b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ 735b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ 745b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ 755b2e303fSDavid Härdeman 765b2e303fSDavid Härdeman /* SP3 Banked Registers, relative to data->sbase */ 775b2e303fSDavid Härdeman #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ 785b2e303fSDavid Härdeman /* Bank 0 */ 795b2e303fSDavid Härdeman #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ 805b2e303fSDavid Härdeman #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ 815b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ 825b2e303fSDavid Härdeman #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ 835b2e303fSDavid Härdeman #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ 845b2e303fSDavid Härdeman #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ 855b2e303fSDavid Härdeman #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ 865b2e303fSDavid Härdeman #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ 875b2e303fSDavid Härdeman #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ 885b2e303fSDavid Härdeman /* Bank 2 */ 895b2e303fSDavid Härdeman #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ 905b2e303fSDavid Härdeman #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ 915b2e303fSDavid Härdeman #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ 925b2e303fSDavid Härdeman #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ 935b2e303fSDavid Härdeman #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ 945b2e303fSDavid Härdeman #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ 955b2e303fSDavid Härdeman /* Bank 3 */ 965b2e303fSDavid Härdeman #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ 975b2e303fSDavid Härdeman #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ 985b2e303fSDavid Härdeman #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ 995b2e303fSDavid Härdeman /* Bank 4 */ 1005b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ 1015b2e303fSDavid Härdeman /* Bank 5 */ 1025b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ 1035b2e303fSDavid Härdeman /* Bank 6 */ 1045b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ 1055b2e303fSDavid Härdeman #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ 1065b2e303fSDavid Härdeman /* Bank 7 */ 1075b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ 1085b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ 1095b2e303fSDavid Härdeman #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ 1105b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ 1115b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ 1125b2e303fSDavid Härdeman 1135b2e303fSDavid Härdeman /* 1145b2e303fSDavid Härdeman * Magic values follow 1155b2e303fSDavid Härdeman */ 1165b2e303fSDavid Härdeman 1175b2e303fSDavid Härdeman /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 1185b2e303fSDavid Härdeman #define WBCIR_IRQ_NONE 0x00 1195b2e303fSDavid Härdeman /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 1205b2e303fSDavid Härdeman #define WBCIR_IRQ_RX 0x01 121c829f267SDavid Härdeman /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 122c829f267SDavid Härdeman #define WBCIR_IRQ_TX_LOW 0x02 1235b2e303fSDavid Härdeman /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 1245b2e303fSDavid Härdeman #define WBCIR_IRQ_ERR 0x04 125c829f267SDavid Härdeman /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ 126c829f267SDavid Härdeman #define WBCIR_IRQ_TX_EMPTY 0x20 1275b2e303fSDavid Härdeman /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ 1285b2e303fSDavid Härdeman #define WBCIR_LED_ENABLE 0x80 1295b2e303fSDavid Härdeman /* RX data available bit for WBCIR_REG_SP3_LSR */ 1305b2e303fSDavid Härdeman #define WBCIR_RX_AVAIL 0x01 131c829f267SDavid Härdeman /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ 132c829f267SDavid Härdeman #define WBCIR_RX_OVERRUN 0x02 133c829f267SDavid Härdeman /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ 134c829f267SDavid Härdeman #define WBCIR_TX_EOT 0x04 1355b2e303fSDavid Härdeman /* RX disable bit for WBCIR_REG_SP3_ASCR */ 1365b2e303fSDavid Härdeman #define WBCIR_RX_DISABLE 0x20 137c829f267SDavid Härdeman /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ 138c829f267SDavid Härdeman #define WBCIR_TX_UNDERRUN 0x40 1395b2e303fSDavid Härdeman /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ 1405b2e303fSDavid Härdeman #define WBCIR_EXT_ENABLE 0x01 1415b2e303fSDavid Härdeman /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ 1425b2e303fSDavid Härdeman #define WBCIR_REGSEL_COMPARE 0x10 1435b2e303fSDavid Härdeman /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ 1445b2e303fSDavid Härdeman #define WBCIR_REGSEL_MASK 0x20 1455b2e303fSDavid Härdeman /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ 1465b2e303fSDavid Härdeman #define WBCIR_REG_ADDR0 0x00 14737b0b4e9SSean Young /* Enable carrier counter */ 14837b0b4e9SSean Young #define WBCIR_CNTR_EN 0x01 14937b0b4e9SSean Young /* Reset carrier counter */ 15037b0b4e9SSean Young #define WBCIR_CNTR_R 0x02 15137b0b4e9SSean Young /* Invert TX */ 15237b0b4e9SSean Young #define WBCIR_IRTX_INV 0x04 1536f2627c2SSean Young /* Receiver oversampling */ 1546f2627c2SSean Young #define WBCIR_RX_T_OV 0x40 1555b2e303fSDavid Härdeman 1565b2e303fSDavid Härdeman /* Valid banks for the SP3 UART */ 1575b2e303fSDavid Härdeman enum wbcir_bank { 1585b2e303fSDavid Härdeman WBCIR_BANK_0 = 0x00, 1595b2e303fSDavid Härdeman WBCIR_BANK_1 = 0x80, 1605b2e303fSDavid Härdeman WBCIR_BANK_2 = 0xE0, 1615b2e303fSDavid Härdeman WBCIR_BANK_3 = 0xE4, 1625b2e303fSDavid Härdeman WBCIR_BANK_4 = 0xE8, 1635b2e303fSDavid Härdeman WBCIR_BANK_5 = 0xEC, 1645b2e303fSDavid Härdeman WBCIR_BANK_6 = 0xF0, 1655b2e303fSDavid Härdeman WBCIR_BANK_7 = 0xF4, 1665b2e303fSDavid Härdeman }; 1675b2e303fSDavid Härdeman 1685b2e303fSDavid Härdeman /* Supported power-on IR Protocols */ 1695b2e303fSDavid Härdeman enum wbcir_protocol { 1705b2e303fSDavid Härdeman IR_PROTOCOL_RC5 = 0x0, 1715b2e303fSDavid Härdeman IR_PROTOCOL_NEC = 0x1, 1725b2e303fSDavid Härdeman IR_PROTOCOL_RC6 = 0x2, 1735b2e303fSDavid Härdeman }; 1745b2e303fSDavid Härdeman 175c829f267SDavid Härdeman /* Possible states for IR reception */ 176c829f267SDavid Härdeman enum wbcir_rxstate { 177c829f267SDavid Härdeman WBCIR_RXSTATE_INACTIVE = 0, 178c829f267SDavid Härdeman WBCIR_RXSTATE_ACTIVE, 179c829f267SDavid Härdeman WBCIR_RXSTATE_ERROR 180c829f267SDavid Härdeman }; 181c829f267SDavid Härdeman 182c829f267SDavid Härdeman /* Possible states for IR transmission */ 183c829f267SDavid Härdeman enum wbcir_txstate { 184c829f267SDavid Härdeman WBCIR_TXSTATE_INACTIVE = 0, 185c829f267SDavid Härdeman WBCIR_TXSTATE_ACTIVE, 186c829f267SDavid Härdeman WBCIR_TXSTATE_ERROR 187c829f267SDavid Härdeman }; 188c829f267SDavid Härdeman 1895b2e303fSDavid Härdeman /* Misc */ 190a66cd0b6SSean Young #define WBCIR_NAME "Winbond CIR" 1915b2e303fSDavid Härdeman #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ 1925b2e303fSDavid Härdeman #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ 1935b2e303fSDavid Härdeman #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ 1945b2e303fSDavid Härdeman #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ 1955b2e303fSDavid Härdeman #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ 1965b2e303fSDavid Härdeman 1975b2e303fSDavid Härdeman /* Per-device data */ 1985b2e303fSDavid Härdeman struct wbcir_data { 1995b2e303fSDavid Härdeman spinlock_t spinlock; 200c829f267SDavid Härdeman struct rc_dev *dev; 201c829f267SDavid Härdeman struct led_classdev led; 2025b2e303fSDavid Härdeman 2035b2e303fSDavid Härdeman unsigned long wbase; /* Wake-Up Baseaddr */ 2045b2e303fSDavid Härdeman unsigned long ebase; /* Enhanced Func. Baseaddr */ 2055b2e303fSDavid Härdeman unsigned long sbase; /* Serial Port Baseaddr */ 2065b2e303fSDavid Härdeman unsigned int irq; /* Serial Port IRQ */ 207c829f267SDavid Härdeman u8 irqmask; 2085b2e303fSDavid Härdeman 209c829f267SDavid Härdeman /* RX state */ 210c829f267SDavid Härdeman enum wbcir_rxstate rxstate; 21137b0b4e9SSean Young int carrier_report_enabled; 21237b0b4e9SSean Young u32 pulse_duration; 2135b2e303fSDavid Härdeman 214c829f267SDavid Härdeman /* TX state */ 215c829f267SDavid Härdeman enum wbcir_txstate txstate; 216c829f267SDavid Härdeman u32 txlen; 217c829f267SDavid Härdeman u32 txoff; 218c829f267SDavid Härdeman u32 *txbuf; 219c829f267SDavid Härdeman u8 txmask; 220c829f267SDavid Härdeman u32 txcarrier; 2215b2e303fSDavid Härdeman }; 2225b2e303fSDavid Härdeman 22390ab5ee9SRusty Russell static bool invert; /* default = 0 */ 2245b2e303fSDavid Härdeman module_param(invert, bool, 0444); 2255b2e303fSDavid Härdeman MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); 2265b2e303fSDavid Härdeman 22790ab5ee9SRusty Russell static bool txandrx; /* default = 0 */ 228c829f267SDavid Härdeman module_param(txandrx, bool, 0444); 22957f4422fSAnton Blanchard MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); 230c829f267SDavid Härdeman 2315b2e303fSDavid Härdeman 2325b2e303fSDavid Härdeman /***************************************************************************** 2335b2e303fSDavid Härdeman * 2345b2e303fSDavid Härdeman * UTILITY FUNCTIONS 2355b2e303fSDavid Härdeman * 2365b2e303fSDavid Härdeman *****************************************************************************/ 2375b2e303fSDavid Härdeman 2385b2e303fSDavid Härdeman /* Caller needs to hold wbcir_lock */ 2395b2e303fSDavid Härdeman static void 2405b2e303fSDavid Härdeman wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) 2415b2e303fSDavid Härdeman { 2425b2e303fSDavid Härdeman u8 val; 2435b2e303fSDavid Härdeman 2445b2e303fSDavid Härdeman val = inb(addr); 2455b2e303fSDavid Härdeman val = ((val & ~mask) | (bits & mask)); 2465b2e303fSDavid Härdeman outb(val, addr); 2475b2e303fSDavid Härdeman } 2485b2e303fSDavid Härdeman 2495b2e303fSDavid Härdeman /* Selects the register bank for the serial port */ 2505b2e303fSDavid Härdeman static inline void 2515b2e303fSDavid Härdeman wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) 2525b2e303fSDavid Härdeman { 2535b2e303fSDavid Härdeman outb(bank, data->sbase + WBCIR_REG_SP3_BSR); 2545b2e303fSDavid Härdeman } 2555b2e303fSDavid Härdeman 256c829f267SDavid Härdeman static inline void 257c829f267SDavid Härdeman wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) 258c829f267SDavid Härdeman { 259c829f267SDavid Härdeman if (data->irqmask == irqmask) 260c829f267SDavid Härdeman return; 261c829f267SDavid Härdeman 262c829f267SDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0); 263c829f267SDavid Härdeman outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); 264c829f267SDavid Härdeman data->irqmask = irqmask; 265c829f267SDavid Härdeman } 266c829f267SDavid Härdeman 2675b2e303fSDavid Härdeman static enum led_brightness 2685b2e303fSDavid Härdeman wbcir_led_brightness_get(struct led_classdev *led_cdev) 2695b2e303fSDavid Härdeman { 2705b2e303fSDavid Härdeman struct wbcir_data *data = container_of(led_cdev, 2715b2e303fSDavid Härdeman struct wbcir_data, 2725b2e303fSDavid Härdeman led); 2735b2e303fSDavid Härdeman 2745b2e303fSDavid Härdeman if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) 2755b2e303fSDavid Härdeman return LED_FULL; 2765b2e303fSDavid Härdeman else 2775b2e303fSDavid Härdeman return LED_OFF; 2785b2e303fSDavid Härdeman } 2795b2e303fSDavid Härdeman 2805b2e303fSDavid Härdeman static void 2815b2e303fSDavid Härdeman wbcir_led_brightness_set(struct led_classdev *led_cdev, 2825b2e303fSDavid Härdeman enum led_brightness brightness) 2835b2e303fSDavid Härdeman { 2845b2e303fSDavid Härdeman struct wbcir_data *data = container_of(led_cdev, 2855b2e303fSDavid Härdeman struct wbcir_data, 2865b2e303fSDavid Härdeman led); 2875b2e303fSDavid Härdeman 2885b2e303fSDavid Härdeman wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, 2895b2e303fSDavid Härdeman brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, 2905b2e303fSDavid Härdeman WBCIR_LED_ENABLE); 2915b2e303fSDavid Härdeman } 2925b2e303fSDavid Härdeman 2935b2e303fSDavid Härdeman /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ 2945b2e303fSDavid Härdeman static u8 2955b2e303fSDavid Härdeman wbcir_to_rc6cells(u8 val) 2965b2e303fSDavid Härdeman { 2975b2e303fSDavid Härdeman u8 coded = 0x00; 2985b2e303fSDavid Härdeman int i; 2995b2e303fSDavid Härdeman 3005b2e303fSDavid Härdeman val &= 0x0F; 3015b2e303fSDavid Härdeman for (i = 0; i < 4; i++) { 3025b2e303fSDavid Härdeman if (val & 0x01) 3035b2e303fSDavid Härdeman coded |= 0x02 << (i * 2); 3045b2e303fSDavid Härdeman else 3055b2e303fSDavid Härdeman coded |= 0x01 << (i * 2); 3065b2e303fSDavid Härdeman val >>= 1; 3075b2e303fSDavid Härdeman } 3085b2e303fSDavid Härdeman 3095b2e303fSDavid Härdeman return coded; 3105b2e303fSDavid Härdeman } 3115b2e303fSDavid Härdeman 3125b2e303fSDavid Härdeman /***************************************************************************** 3135b2e303fSDavid Härdeman * 3145b2e303fSDavid Härdeman * INTERRUPT FUNCTIONS 3155b2e303fSDavid Härdeman * 3165b2e303fSDavid Härdeman *****************************************************************************/ 3175b2e303fSDavid Härdeman 318c829f267SDavid Härdeman static void 31937b0b4e9SSean Young wbcir_carrier_report(struct wbcir_data *data) 32037b0b4e9SSean Young { 32137b0b4e9SSean Young unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) | 32237b0b4e9SSean Young inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8; 32337b0b4e9SSean Young 32437b0b4e9SSean Young if (counter > 0 && counter < 0xffff) { 32537b0b4e9SSean Young DEFINE_IR_RAW_EVENT(ev); 32637b0b4e9SSean Young 32737b0b4e9SSean Young ev.carrier_report = 1; 32837b0b4e9SSean Young ev.carrier = DIV_ROUND_CLOSEST(counter * 1000000u, 32937b0b4e9SSean Young data->pulse_duration); 33037b0b4e9SSean Young 33137b0b4e9SSean Young ir_raw_event_store(data->dev, &ev); 33237b0b4e9SSean Young } 33337b0b4e9SSean Young 33437b0b4e9SSean Young /* reset and restart the counter */ 33537b0b4e9SSean Young data->pulse_duration = 0; 33637b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, 33737b0b4e9SSean Young WBCIR_CNTR_EN | WBCIR_CNTR_R); 33837b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN, 33937b0b4e9SSean Young WBCIR_CNTR_EN | WBCIR_CNTR_R); 34037b0b4e9SSean Young } 34137b0b4e9SSean Young 34237b0b4e9SSean Young static void 343488ebc48SDavid Härdeman wbcir_idle_rx(struct rc_dev *dev, bool idle) 3445b2e303fSDavid Härdeman { 345488ebc48SDavid Härdeman struct wbcir_data *data = dev->priv; 3465b2e303fSDavid Härdeman 3471ac7fdeeSSean Young if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) 348c829f267SDavid Härdeman data->rxstate = WBCIR_RXSTATE_ACTIVE; 3495b2e303fSDavid Härdeman 350e5eda7faSSean Young if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) { 351e5eda7faSSean Young data->rxstate = WBCIR_RXSTATE_INACTIVE; 35237b0b4e9SSean Young 35337b0b4e9SSean Young if (data->carrier_report_enabled) 35437b0b4e9SSean Young wbcir_carrier_report(data); 35537b0b4e9SSean Young 356488ebc48SDavid Härdeman /* Tell hardware to go idle by setting RXINACTIVE */ 357488ebc48SDavid Härdeman outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); 358488ebc48SDavid Härdeman } 359e5eda7faSSean Young } 360488ebc48SDavid Härdeman 361488ebc48SDavid Härdeman static void 362488ebc48SDavid Härdeman wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) 363488ebc48SDavid Härdeman { 364488ebc48SDavid Härdeman u8 irdata; 365488ebc48SDavid Härdeman DEFINE_IR_RAW_EVENT(rawir); 36637b0b4e9SSean Young unsigned duration; 367488ebc48SDavid Härdeman 3685b2e303fSDavid Härdeman /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ 369488ebc48SDavid Härdeman while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { 370488ebc48SDavid Härdeman irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); 371c829f267SDavid Härdeman if (data->rxstate == WBCIR_RXSTATE_ERROR) 3725b2e303fSDavid Härdeman continue; 37337b0b4e9SSean Young 3746f2627c2SSean Young duration = ((irdata & 0x7F) + 1) * 3756f2627c2SSean Young (data->carrier_report_enabled ? 2 : 10); 376488ebc48SDavid Härdeman rawir.pulse = irdata & 0x80 ? false : true; 37737b0b4e9SSean Young rawir.duration = US_TO_NS(duration); 37837b0b4e9SSean Young 37937b0b4e9SSean Young if (rawir.pulse) 38037b0b4e9SSean Young data->pulse_duration += duration; 38137b0b4e9SSean Young 382488ebc48SDavid Härdeman ir_raw_event_store_with_filter(data->dev, &rawir); 3835b2e303fSDavid Härdeman } 3845b2e303fSDavid Härdeman 3855b2e303fSDavid Härdeman ir_raw_event_handle(data->dev); 386c829f267SDavid Härdeman } 3875b2e303fSDavid Härdeman 388c829f267SDavid Härdeman static void 389c829f267SDavid Härdeman wbcir_irq_tx(struct wbcir_data *data) 390c829f267SDavid Härdeman { 391c829f267SDavid Härdeman unsigned int space; 392c829f267SDavid Härdeman unsigned int used; 393c829f267SDavid Härdeman u8 bytes[16]; 394c829f267SDavid Härdeman u8 byte; 395c829f267SDavid Härdeman 396c829f267SDavid Härdeman if (!data->txbuf) 397c829f267SDavid Härdeman return; 398c829f267SDavid Härdeman 399c829f267SDavid Härdeman switch (data->txstate) { 400c829f267SDavid Härdeman case WBCIR_TXSTATE_INACTIVE: 401c829f267SDavid Härdeman /* TX FIFO empty */ 402c829f267SDavid Härdeman space = 16; 403c829f267SDavid Härdeman break; 404c829f267SDavid Härdeman case WBCIR_TXSTATE_ACTIVE: 405c829f267SDavid Härdeman /* TX FIFO low (3 bytes or less) */ 406c829f267SDavid Härdeman space = 13; 407c829f267SDavid Härdeman break; 408c829f267SDavid Härdeman case WBCIR_TXSTATE_ERROR: 409c829f267SDavid Härdeman space = 0; 410c829f267SDavid Härdeman break; 411c829f267SDavid Härdeman default: 412c829f267SDavid Härdeman return; 413c829f267SDavid Härdeman } 414c829f267SDavid Härdeman 415c829f267SDavid Härdeman /* 416c829f267SDavid Härdeman * TX data is run-length coded in bytes: YXXXXXXX 417c829f267SDavid Härdeman * Y = space (1) or pulse (0) 418c829f267SDavid Härdeman * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) 419c829f267SDavid Härdeman */ 420c829f267SDavid Härdeman for (used = 0; used < space && data->txoff != data->txlen; used++) { 421c829f267SDavid Härdeman if (data->txbuf[data->txoff] == 0) { 422c829f267SDavid Härdeman data->txoff++; 423c829f267SDavid Härdeman continue; 424c829f267SDavid Härdeman } 425c829f267SDavid Härdeman byte = min((u32)0x80, data->txbuf[data->txoff]); 426c829f267SDavid Härdeman data->txbuf[data->txoff] -= byte; 427c829f267SDavid Härdeman byte--; 428c829f267SDavid Härdeman byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ 429c829f267SDavid Härdeman bytes[used] = byte; 430c829f267SDavid Härdeman } 431c829f267SDavid Härdeman 432c829f267SDavid Härdeman while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen) 433c829f267SDavid Härdeman data->txoff++; 434c829f267SDavid Härdeman 435c829f267SDavid Härdeman if (used == 0) { 436c829f267SDavid Härdeman /* Finished */ 437c829f267SDavid Härdeman if (data->txstate == WBCIR_TXSTATE_ERROR) 438c829f267SDavid Härdeman /* Clear TX underrun bit */ 439c829f267SDavid Härdeman outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); 440c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); 4417bfb5dc1SDavid Härdeman kfree(data->txbuf); 4427bfb5dc1SDavid Härdeman data->txbuf = NULL; 4437bfb5dc1SDavid Härdeman data->txstate = WBCIR_TXSTATE_INACTIVE; 444c829f267SDavid Härdeman } else if (data->txoff == data->txlen) { 445c829f267SDavid Härdeman /* At the end of transmission, tell the hw before last byte */ 446c829f267SDavid Härdeman outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); 447c829f267SDavid Härdeman outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); 448c829f267SDavid Härdeman outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); 449c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | 450c829f267SDavid Härdeman WBCIR_IRQ_TX_EMPTY); 451c829f267SDavid Härdeman } else { 452c829f267SDavid Härdeman /* More data to follow... */ 453c829f267SDavid Härdeman outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); 454c829f267SDavid Härdeman if (data->txstate == WBCIR_TXSTATE_INACTIVE) { 455c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | 456c829f267SDavid Härdeman WBCIR_IRQ_TX_LOW); 457c829f267SDavid Härdeman data->txstate = WBCIR_TXSTATE_ACTIVE; 458c829f267SDavid Härdeman } 459c829f267SDavid Härdeman } 460c829f267SDavid Härdeman } 461c829f267SDavid Härdeman 462c829f267SDavid Härdeman static irqreturn_t 463c829f267SDavid Härdeman wbcir_irq_handler(int irqno, void *cookie) 464c829f267SDavid Härdeman { 465c829f267SDavid Härdeman struct pnp_dev *device = cookie; 466c829f267SDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device); 467c829f267SDavid Härdeman unsigned long flags; 468c829f267SDavid Härdeman u8 status; 469c829f267SDavid Härdeman 470c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags); 471c829f267SDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0); 472c829f267SDavid Härdeman status = inb(data->sbase + WBCIR_REG_SP3_EIR); 473c829f267SDavid Härdeman status &= data->irqmask; 474c829f267SDavid Härdeman 475c829f267SDavid Härdeman if (!status) { 476c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 477c829f267SDavid Härdeman return IRQ_NONE; 478c829f267SDavid Härdeman } 479c829f267SDavid Härdeman 480c829f267SDavid Härdeman if (status & WBCIR_IRQ_ERR) { 481c829f267SDavid Härdeman /* RX overflow? (read clears bit) */ 482c829f267SDavid Härdeman if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { 483c829f267SDavid Härdeman data->rxstate = WBCIR_RXSTATE_ERROR; 484c829f267SDavid Härdeman ir_raw_event_reset(data->dev); 485c829f267SDavid Härdeman } 486c829f267SDavid Härdeman 487c829f267SDavid Härdeman /* TX underflow? */ 488c829f267SDavid Härdeman if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) 489c829f267SDavid Härdeman data->txstate = WBCIR_TXSTATE_ERROR; 490c829f267SDavid Härdeman } 491c829f267SDavid Härdeman 492c829f267SDavid Härdeman if (status & WBCIR_IRQ_RX) 493c829f267SDavid Härdeman wbcir_irq_rx(data, device); 494c829f267SDavid Härdeman 495c829f267SDavid Härdeman if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) 496c829f267SDavid Härdeman wbcir_irq_tx(data); 497c829f267SDavid Härdeman 4985b2e303fSDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 4995b2e303fSDavid Härdeman return IRQ_HANDLED; 5005b2e303fSDavid Härdeman } 5015b2e303fSDavid Härdeman 502c829f267SDavid Härdeman /***************************************************************************** 503c829f267SDavid Härdeman * 504c829f267SDavid Härdeman * RC-CORE INTERFACE FUNCTIONS 505c829f267SDavid Härdeman * 506c829f267SDavid Härdeman *****************************************************************************/ 5075b2e303fSDavid Härdeman 508c829f267SDavid Härdeman static int 50937b0b4e9SSean Young wbcir_set_carrier_report(struct rc_dev *dev, int enable) 51037b0b4e9SSean Young { 51137b0b4e9SSean Young struct wbcir_data *data = dev->priv; 51237b0b4e9SSean Young unsigned long flags; 51337b0b4e9SSean Young 51437b0b4e9SSean Young spin_lock_irqsave(&data->spinlock, flags); 51537b0b4e9SSean Young 51637b0b4e9SSean Young if (data->carrier_report_enabled == enable) { 51737b0b4e9SSean Young spin_unlock_irqrestore(&data->spinlock, flags); 51837b0b4e9SSean Young return 0; 51937b0b4e9SSean Young } 52037b0b4e9SSean Young 52137b0b4e9SSean Young data->pulse_duration = 0; 52237b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, 52337b0b4e9SSean Young WBCIR_CNTR_EN | WBCIR_CNTR_R); 52437b0b4e9SSean Young 52537b0b4e9SSean Young if (enable && data->dev->idle) 52637b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, 52737b0b4e9SSean Young WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R); 52837b0b4e9SSean Young 5296f2627c2SSean Young /* Set a higher sampling resolution if carrier reports are enabled */ 5306f2627c2SSean Young wbcir_select_bank(data, WBCIR_BANK_2); 5316f2627c2SSean Young data->dev->rx_resolution = US_TO_NS(enable ? 2 : 10); 5326f2627c2SSean Young outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL); 5336f2627c2SSean Young outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); 5346f2627c2SSean Young 5356f2627c2SSean Young /* Enable oversampling if carrier reports are enabled */ 5366f2627c2SSean Young wbcir_select_bank(data, WBCIR_BANK_7); 5376f2627c2SSean Young wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG, 5386f2627c2SSean Young enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV); 5396f2627c2SSean Young 54037b0b4e9SSean Young data->carrier_report_enabled = enable; 54137b0b4e9SSean Young spin_unlock_irqrestore(&data->spinlock, flags); 54237b0b4e9SSean Young 54337b0b4e9SSean Young return 0; 54437b0b4e9SSean Young } 54537b0b4e9SSean Young 54637b0b4e9SSean Young static int 547c829f267SDavid Härdeman wbcir_txcarrier(struct rc_dev *dev, u32 carrier) 548c829f267SDavid Härdeman { 549c829f267SDavid Härdeman struct wbcir_data *data = dev->priv; 550c829f267SDavid Härdeman unsigned long flags; 551c829f267SDavid Härdeman u8 val; 552c829f267SDavid Härdeman u32 freq; 553c829f267SDavid Härdeman 554c829f267SDavid Härdeman freq = DIV_ROUND_CLOSEST(carrier, 1000); 555c829f267SDavid Härdeman if (freq < 30 || freq > 60) 556c829f267SDavid Härdeman return -EINVAL; 557c829f267SDavid Härdeman 558c829f267SDavid Härdeman switch (freq) { 559c829f267SDavid Härdeman case 58: 560c829f267SDavid Härdeman case 59: 561c829f267SDavid Härdeman case 60: 562c829f267SDavid Härdeman val = freq - 58; 563c829f267SDavid Härdeman freq *= 1000; 564c829f267SDavid Härdeman break; 565c829f267SDavid Härdeman case 57: 566c829f267SDavid Härdeman val = freq - 27; 567c829f267SDavid Härdeman freq = 56900; 568c829f267SDavid Härdeman break; 569c829f267SDavid Härdeman default: 570c829f267SDavid Härdeman val = freq - 27; 571c829f267SDavid Härdeman freq *= 1000; 572c829f267SDavid Härdeman break; 573c829f267SDavid Härdeman } 574c829f267SDavid Härdeman 575c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags); 576c829f267SDavid Härdeman if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 577c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 578c829f267SDavid Härdeman return -EBUSY; 579c829f267SDavid Härdeman } 580c829f267SDavid Härdeman 581c829f267SDavid Härdeman if (data->txcarrier != freq) { 582c829f267SDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_7); 583c829f267SDavid Härdeman wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); 584c829f267SDavid Härdeman data->txcarrier = freq; 585c829f267SDavid Härdeman } 586c829f267SDavid Härdeman 587c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 588c829f267SDavid Härdeman return 0; 589c829f267SDavid Härdeman } 590c829f267SDavid Härdeman 591c829f267SDavid Härdeman static int 592c829f267SDavid Härdeman wbcir_txmask(struct rc_dev *dev, u32 mask) 593c829f267SDavid Härdeman { 594c829f267SDavid Härdeman struct wbcir_data *data = dev->priv; 595c829f267SDavid Härdeman unsigned long flags; 596c829f267SDavid Härdeman u8 val; 597c829f267SDavid Härdeman 59820f5a827SSean Young /* return the number of transmitters */ 59920f5a827SSean Young if (mask > 15) 60020f5a827SSean Young return 4; 60120f5a827SSean Young 602c829f267SDavid Härdeman /* Four outputs, only one output can be enabled at a time */ 603c829f267SDavid Härdeman switch (mask) { 604c829f267SDavid Härdeman case 0x1: 605c829f267SDavid Härdeman val = 0x0; 606c829f267SDavid Härdeman break; 607c829f267SDavid Härdeman case 0x2: 608c829f267SDavid Härdeman val = 0x1; 609c829f267SDavid Härdeman break; 610c829f267SDavid Härdeman case 0x4: 611c829f267SDavid Härdeman val = 0x2; 612c829f267SDavid Härdeman break; 613c829f267SDavid Härdeman case 0x8: 614c829f267SDavid Härdeman val = 0x3; 615c829f267SDavid Härdeman break; 616c829f267SDavid Härdeman default: 617c829f267SDavid Härdeman return -EINVAL; 618c829f267SDavid Härdeman } 619c829f267SDavid Härdeman 620c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags); 621c829f267SDavid Härdeman if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 622c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 623c829f267SDavid Härdeman return -EBUSY; 624c829f267SDavid Härdeman } 625c829f267SDavid Härdeman 626c829f267SDavid Härdeman if (data->txmask != mask) { 627c829f267SDavid Härdeman wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); 628c829f267SDavid Härdeman data->txmask = mask; 629c829f267SDavid Härdeman } 630c829f267SDavid Härdeman 631c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 632c829f267SDavid Härdeman return 0; 633c829f267SDavid Härdeman } 634c829f267SDavid Härdeman 635c829f267SDavid Härdeman static int 6367bfb5dc1SDavid Härdeman wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) 637c829f267SDavid Härdeman { 638c829f267SDavid Härdeman struct wbcir_data *data = dev->priv; 6397bfb5dc1SDavid Härdeman unsigned *buf; 640c829f267SDavid Härdeman unsigned i; 641c829f267SDavid Härdeman unsigned long flags; 642c829f267SDavid Härdeman 643ce3aeaf2SMarkus Elfring buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL); 6447bfb5dc1SDavid Härdeman if (!buf) 6457bfb5dc1SDavid Härdeman return -ENOMEM; 6467bfb5dc1SDavid Härdeman 6477bfb5dc1SDavid Härdeman /* Convert values to multiples of 10us */ 6487bfb5dc1SDavid Härdeman for (i = 0; i < count; i++) 6497bfb5dc1SDavid Härdeman buf[i] = DIV_ROUND_CLOSEST(b[i], 10); 6507bfb5dc1SDavid Härdeman 651c829f267SDavid Härdeman /* Not sure if this is possible, but better safe than sorry */ 652c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags); 653c829f267SDavid Härdeman if (data->txstate != WBCIR_TXSTATE_INACTIVE) { 654c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 6557bfb5dc1SDavid Härdeman kfree(buf); 656c829f267SDavid Härdeman return -EBUSY; 657c829f267SDavid Härdeman } 658c829f267SDavid Härdeman 659c829f267SDavid Härdeman /* Fill the TX fifo once, the irq handler will do the rest */ 660c829f267SDavid Härdeman data->txbuf = buf; 661c829f267SDavid Härdeman data->txlen = count; 662c829f267SDavid Härdeman data->txoff = 0; 663c829f267SDavid Härdeman wbcir_irq_tx(data); 664c829f267SDavid Härdeman 665c829f267SDavid Härdeman /* We're done */ 666c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags); 667c829f267SDavid Härdeman return count; 668c829f267SDavid Härdeman } 6695b2e303fSDavid Härdeman 6705b2e303fSDavid Härdeman /***************************************************************************** 6715b2e303fSDavid Härdeman * 6725b2e303fSDavid Härdeman * SETUP/INIT/SUSPEND/RESUME FUNCTIONS 6735b2e303fSDavid Härdeman * 6745b2e303fSDavid Härdeman *****************************************************************************/ 6755b2e303fSDavid Härdeman 6765b2e303fSDavid Härdeman static void 6775b2e303fSDavid Härdeman wbcir_shutdown(struct pnp_dev *device) 6785b2e303fSDavid Härdeman { 6795b2e303fSDavid Härdeman struct device *dev = &device->dev; 6805b2e303fSDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device); 681f4742e1dSSean Young struct rc_dev *rc = data->dev; 68267cdd42eSDavid Härdeman bool do_wake = true; 6835b2e303fSDavid Härdeman u8 match[11]; 6845b2e303fSDavid Härdeman u8 mask[11]; 6855b2e303fSDavid Härdeman u8 rc6_csl = 0; 686f4742e1dSSean Young u8 proto; 687f4742e1dSSean Young u32 wake_sc = rc->scancode_wakeup_filter.data; 688f4742e1dSSean Young u32 mask_sc = rc->scancode_wakeup_filter.mask; 6895b2e303fSDavid Härdeman int i; 6905b2e303fSDavid Härdeman 6915b2e303fSDavid Härdeman memset(match, 0, sizeof(match)); 6925b2e303fSDavid Härdeman memset(mask, 0, sizeof(mask)); 6935b2e303fSDavid Härdeman 694f4742e1dSSean Young if (!mask_sc || !device_may_wakeup(dev)) { 69567cdd42eSDavid Härdeman do_wake = false; 6965b2e303fSDavid Härdeman goto finish; 6975b2e303fSDavid Härdeman } 6985b2e303fSDavid Härdeman 699f4742e1dSSean Young switch (rc->wakeup_protocol) { 700f4742e1dSSean Young case RC_TYPE_RC5: 7015b2e303fSDavid Härdeman /* Mask = 13 bits, ex toggle */ 702f4742e1dSSean Young mask[0] = (mask_sc & 0x003f); 703f4742e1dSSean Young mask[0] |= (mask_sc & 0x0300) >> 2; 704f4742e1dSSean Young mask[1] = (mask_sc & 0x1c00) >> 10; 705f4742e1dSSean Young if (mask_sc & 0x0040) /* 2nd start bit */ 706f4742e1dSSean Young match[1] |= 0x10; 7075b2e303fSDavid Härdeman 7085b2e303fSDavid Härdeman match[0] = (wake_sc & 0x003F); /* 6 command bits */ 709f4742e1dSSean Young match[0] |= (wake_sc & 0x0300) >> 2; /* 2 address bits */ 710f4742e1dSSean Young match[1] = (wake_sc & 0x1c00) >> 10; /* 3 address bits */ 7115b2e303fSDavid Härdeman if (!(wake_sc & 0x0040)) /* 2nd start bit */ 7125b2e303fSDavid Härdeman match[1] |= 0x10; 7135b2e303fSDavid Härdeman 714f4742e1dSSean Young proto = IR_PROTOCOL_RC5; 7155b2e303fSDavid Härdeman break; 7165b2e303fSDavid Härdeman 717f4742e1dSSean Young case RC_TYPE_NEC: 718f4742e1dSSean Young mask[1] = bitrev8(mask_sc); 719f4742e1dSSean Young mask[0] = mask[1]; 720f4742e1dSSean Young mask[3] = bitrev8(mask_sc >> 8); 721f4742e1dSSean Young mask[2] = mask[3]; 7225b2e303fSDavid Härdeman 723f4742e1dSSean Young match[1] = bitrev8(wake_sc); 7245b2e303fSDavid Härdeman match[0] = ~match[1]; 725f4742e1dSSean Young match[3] = bitrev8(wake_sc >> 8); 7265b2e303fSDavid Härdeman match[2] = ~match[3]; 7275b2e303fSDavid Härdeman 728f4742e1dSSean Young proto = IR_PROTOCOL_NEC; 7295b2e303fSDavid Härdeman break; 7305b2e303fSDavid Härdeman 731f4742e1dSSean Young case RC_TYPE_NECX: 732f4742e1dSSean Young mask[1] = bitrev8(mask_sc); 733f4742e1dSSean Young mask[0] = mask[1]; 734f4742e1dSSean Young mask[2] = bitrev8(mask_sc >> 8); 735f4742e1dSSean Young mask[3] = bitrev8(mask_sc >> 16); 7365b2e303fSDavid Härdeman 737f4742e1dSSean Young match[1] = bitrev8(wake_sc); 738f4742e1dSSean Young match[0] = ~match[1]; 739f4742e1dSSean Young match[2] = bitrev8(wake_sc >> 8); 740f4742e1dSSean Young match[3] = bitrev8(wake_sc >> 16); 741f4742e1dSSean Young 742f4742e1dSSean Young proto = IR_PROTOCOL_NEC; 7435b2e303fSDavid Härdeman break; 7445b2e303fSDavid Härdeman 745f4742e1dSSean Young case RC_TYPE_NEC32: 746f4742e1dSSean Young mask[0] = bitrev8(mask_sc); 747f4742e1dSSean Young mask[1] = bitrev8(mask_sc >> 8); 748f4742e1dSSean Young mask[2] = bitrev8(mask_sc >> 16); 749f4742e1dSSean Young mask[3] = bitrev8(mask_sc >> 24); 750f4742e1dSSean Young 751f4742e1dSSean Young match[0] = bitrev8(wake_sc); 752f4742e1dSSean Young match[1] = bitrev8(wake_sc >> 8); 753f4742e1dSSean Young match[2] = bitrev8(wake_sc >> 16); 754f4742e1dSSean Young match[3] = bitrev8(wake_sc >> 24); 755f4742e1dSSean Young 756f4742e1dSSean Young proto = IR_PROTOCOL_NEC; 757f4742e1dSSean Young break; 758f4742e1dSSean Young 759f4742e1dSSean Young case RC_TYPE_RC6_0: 7605b2e303fSDavid Härdeman /* Command */ 7615b2e303fSDavid Härdeman match[0] = wbcir_to_rc6cells(wake_sc >> 0); 762f4742e1dSSean Young mask[0] = wbcir_to_rc6cells(mask_sc >> 0); 7635b2e303fSDavid Härdeman match[1] = wbcir_to_rc6cells(wake_sc >> 4); 764f4742e1dSSean Young mask[1] = wbcir_to_rc6cells(mask_sc >> 4); 7655b2e303fSDavid Härdeman 7665b2e303fSDavid Härdeman /* Address */ 7675b2e303fSDavid Härdeman match[2] = wbcir_to_rc6cells(wake_sc >> 8); 768f4742e1dSSean Young mask[2] = wbcir_to_rc6cells(mask_sc >> 8); 7695b2e303fSDavid Härdeman match[3] = wbcir_to_rc6cells(wake_sc >> 12); 770f4742e1dSSean Young mask[3] = wbcir_to_rc6cells(mask_sc >> 12); 7715b2e303fSDavid Härdeman 7725b2e303fSDavid Härdeman /* Header */ 7735b2e303fSDavid Härdeman match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ 7745b2e303fSDavid Härdeman mask[4] = 0xF0; 7755b2e303fSDavid Härdeman match[5] = 0x09; /* start bit = 1, mode2 = 0 */ 7765b2e303fSDavid Härdeman mask[5] = 0x0F; 7775b2e303fSDavid Härdeman 7785b2e303fSDavid Härdeman rc6_csl = 44; 779f4742e1dSSean Young proto = IR_PROTOCOL_RC6; 780f4742e1dSSean Young break; 7815b2e303fSDavid Härdeman 782f4742e1dSSean Young case RC_TYPE_RC6_6A_24: 783f4742e1dSSean Young case RC_TYPE_RC6_6A_32: 784f4742e1dSSean Young case RC_TYPE_RC6_MCE: 7855b2e303fSDavid Härdeman i = 0; 7865b2e303fSDavid Härdeman 7875b2e303fSDavid Härdeman /* Command */ 7885b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 0); 789f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 0); 7905b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 4); 791f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 4); 7925b2e303fSDavid Härdeman 7935b2e303fSDavid Härdeman /* Address + Toggle */ 7945b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 8); 795f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 8); 7965b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 12); 797f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 12); 7985b2e303fSDavid Härdeman 7995b2e303fSDavid Härdeman /* Customer bits 7 - 0 */ 8005b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 16); 801f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 16); 8025b2e303fSDavid Härdeman 803f4742e1dSSean Young if (rc->wakeup_protocol == RC_TYPE_RC6_6A_20) { 804f4742e1dSSean Young rc6_csl = 52; 805f4742e1dSSean Young } else { 806f4742e1dSSean Young match[i] = wbcir_to_rc6cells(wake_sc >> 20); 807f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 20); 808f4742e1dSSean Young 809f4742e1dSSean Young if (rc->wakeup_protocol == RC_TYPE_RC6_6A_24) { 8105b2e303fSDavid Härdeman rc6_csl = 60; 8115b2e303fSDavid Härdeman } else { 812f4742e1dSSean Young /* Customer range bit and bits 15 - 8 */ 813f4742e1dSSean Young match[i] = wbcir_to_rc6cells(wake_sc >> 24); 814f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 24); 815f4742e1dSSean Young match[i] = wbcir_to_rc6cells(wake_sc >> 28); 816f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 28); 817f4742e1dSSean Young rc6_csl = 76; 818f4742e1dSSean Young } 8195b2e303fSDavid Härdeman } 8205b2e303fSDavid Härdeman 8215b2e303fSDavid Härdeman /* Header */ 8225b2e303fSDavid Härdeman match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ 8235b2e303fSDavid Härdeman mask[i++] = 0xFF; 8245b2e303fSDavid Härdeman match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ 8255b2e303fSDavid Härdeman mask[i++] = 0x0F; 826f4742e1dSSean Young proto = IR_PROTOCOL_RC6; 8275b2e303fSDavid Härdeman break; 8285b2e303fSDavid Härdeman default: 82967cdd42eSDavid Härdeman do_wake = false; 8305b2e303fSDavid Härdeman break; 8315b2e303fSDavid Härdeman } 8325b2e303fSDavid Härdeman 8335b2e303fSDavid Härdeman finish: 8345b2e303fSDavid Härdeman if (do_wake) { 8355b2e303fSDavid Härdeman /* Set compare and compare mask */ 8365b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, 8375b2e303fSDavid Härdeman WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, 8385b2e303fSDavid Härdeman 0x3F); 8395b2e303fSDavid Härdeman outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); 8405b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, 8415b2e303fSDavid Härdeman WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, 8425b2e303fSDavid Härdeman 0x3F); 8435b2e303fSDavid Härdeman outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); 8445b2e303fSDavid Härdeman 8455b2e303fSDavid Härdeman /* RC6 Compare String Len */ 8465b2e303fSDavid Härdeman outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); 8475b2e303fSDavid Härdeman 8485b2e303fSDavid Härdeman /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 8495b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 8505b2e303fSDavid Härdeman 8515b2e303fSDavid Härdeman /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ 8525b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); 8535b2e303fSDavid Härdeman 8545b2e303fSDavid Härdeman /* Set CEIR_EN */ 855f4742e1dSSean Young wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 856f4742e1dSSean Young (proto << 4) | 0x01, 0x31); 8575b2e303fSDavid Härdeman 8585b2e303fSDavid Härdeman } else { 8595b2e303fSDavid Härdeman /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ 8605b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 8615b2e303fSDavid Härdeman 8625b2e303fSDavid Härdeman /* Clear CEIR_EN */ 8635b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); 8645b2e303fSDavid Härdeman } 8655b2e303fSDavid Härdeman 8665b2e303fSDavid Härdeman /* 8675b2e303fSDavid Härdeman * ACPI will set the HW disable bit for SP3 which means that the 8685b2e303fSDavid Härdeman * output signals are left in an undefined state which may cause 8695b2e303fSDavid Härdeman * spurious interrupts which we need to ignore until the hardware 8705b2e303fSDavid Härdeman * is reinitialized. 8715b2e303fSDavid Härdeman */ 872c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 8735b2e303fSDavid Härdeman disable_irq(data->irq); 8745b2e303fSDavid Härdeman } 8755b2e303fSDavid Härdeman 876f4742e1dSSean Young /* 877f4742e1dSSean Young * Wakeup handling is done on shutdown. 878f4742e1dSSean Young */ 879f4742e1dSSean Young static int 880f4742e1dSSean Young wbcir_set_wakeup_filter(struct rc_dev *rc, struct rc_scancode_filter *filter) 881f4742e1dSSean Young { 882f4742e1dSSean Young return 0; 883f4742e1dSSean Young } 884f4742e1dSSean Young 8855b2e303fSDavid Härdeman static int 8865b2e303fSDavid Härdeman wbcir_suspend(struct pnp_dev *device, pm_message_t state) 8875b2e303fSDavid Härdeman { 8881ac7fdeeSSean Young struct wbcir_data *data = pnp_get_drvdata(device); 8891ac7fdeeSSean Young led_classdev_suspend(&data->led); 8905b2e303fSDavid Härdeman wbcir_shutdown(device); 8915b2e303fSDavid Härdeman return 0; 8925b2e303fSDavid Härdeman } 8935b2e303fSDavid Härdeman 8945b2e303fSDavid Härdeman static void 8955b2e303fSDavid Härdeman wbcir_init_hw(struct wbcir_data *data) 8965b2e303fSDavid Härdeman { 8975b2e303fSDavid Härdeman /* Disable interrupts */ 898c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 8995b2e303fSDavid Härdeman 900f4742e1dSSean Young /* Set RX_INV, Clear CEIR_EN (needed for the led) */ 901f4742e1dSSean Young wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, invert ? 8 : 0, 0x09); 9025b2e303fSDavid Härdeman 9035b2e303fSDavid Härdeman /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 9045b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 9055b2e303fSDavid Härdeman 9065b2e303fSDavid Härdeman /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ 9075b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 9085b2e303fSDavid Härdeman 9095b2e303fSDavid Härdeman /* Set RC5 cell time to correspond to 36 kHz */ 9105b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); 9115b2e303fSDavid Härdeman 9125b2e303fSDavid Härdeman /* Set IRTX_INV */ 9135b2e303fSDavid Härdeman if (invert) 91437b0b4e9SSean Young outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL); 9155b2e303fSDavid Härdeman else 9165b2e303fSDavid Härdeman outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); 9175b2e303fSDavid Härdeman 9185b2e303fSDavid Härdeman /* 919c829f267SDavid Härdeman * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, 9205b2e303fSDavid Härdeman * set SP3_IRRX_SW to binary 01, helpfully not documented 9215b2e303fSDavid Härdeman */ 9225b2e303fSDavid Härdeman outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); 923c829f267SDavid Härdeman data->txmask = 0x1; 9245b2e303fSDavid Härdeman 9255b2e303fSDavid Härdeman /* Enable extended mode */ 9265b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_2); 9275b2e303fSDavid Härdeman outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); 9285b2e303fSDavid Härdeman 9295b2e303fSDavid Härdeman /* 9305b2e303fSDavid Härdeman * Configure baud generator, IR data will be sampled at 9315b2e303fSDavid Härdeman * a bitrate of: (24Mhz * prescaler) / (divisor * 16). 9325b2e303fSDavid Härdeman * 9335b2e303fSDavid Härdeman * The ECIR registers include a flag to change the 9345b2e303fSDavid Härdeman * 24Mhz clock freq to 48Mhz. 9355b2e303fSDavid Härdeman * 9365b2e303fSDavid Härdeman * It's not documented in the specs, but fifo levels 9375b2e303fSDavid Härdeman * other than 16 seems to be unsupported. 9385b2e303fSDavid Härdeman */ 9395b2e303fSDavid Härdeman 9405b2e303fSDavid Härdeman /* prescaler 1.0, tx/rx fifo lvl 16 */ 9415b2e303fSDavid Härdeman outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); 9425b2e303fSDavid Härdeman 9436f2627c2SSean Young /* Set baud divisor to sample every 10 us */ 9446f2627c2SSean Young outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL); 9455b2e303fSDavid Härdeman outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); 9465b2e303fSDavid Härdeman 9475b2e303fSDavid Härdeman /* Set CEIR mode */ 9485b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0); 9495b2e303fSDavid Härdeman outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); 9505b2e303fSDavid Härdeman inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ 9515b2e303fSDavid Härdeman inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ 9525b2e303fSDavid Härdeman 9536f2627c2SSean Young /* Disable RX demod, enable run-length enc/dec, set freq span */ 9545b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_7); 9556f2627c2SSean Young outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG); 9565b2e303fSDavid Härdeman 9575b2e303fSDavid Härdeman /* Disable timer */ 9585b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_4); 9595b2e303fSDavid Härdeman outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); 9605b2e303fSDavid Härdeman 961c829f267SDavid Härdeman /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ 9625b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_5); 963c829f267SDavid Härdeman outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); 9645b2e303fSDavid Härdeman 9655b2e303fSDavid Härdeman /* Disable CRC */ 9665b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_6); 9675b2e303fSDavid Härdeman outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); 9685b2e303fSDavid Härdeman 969c829f267SDavid Härdeman /* Set RX demodulation freq, not really used */ 9705b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_7); 9715b2e303fSDavid Härdeman outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); 972c829f267SDavid Härdeman 973c829f267SDavid Härdeman /* Set TX modulation, 36kHz, 7us pulse width */ 9745b2e303fSDavid Härdeman outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); 975c829f267SDavid Härdeman data->txcarrier = 36000; 9765b2e303fSDavid Härdeman 9775b2e303fSDavid Härdeman /* Set invert and pin direction */ 9785b2e303fSDavid Härdeman if (invert) 9795b2e303fSDavid Härdeman outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); 9805b2e303fSDavid Härdeman else 9815b2e303fSDavid Härdeman outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); 9825b2e303fSDavid Härdeman 9835b2e303fSDavid Härdeman /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ 9845b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0); 9855b2e303fSDavid Härdeman outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); 9865b2e303fSDavid Härdeman 9875b2e303fSDavid Härdeman /* Clear AUX status bits */ 9885b2e303fSDavid Härdeman outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); 9895b2e303fSDavid Härdeman 990c829f267SDavid Härdeman /* Clear RX state */ 991c829f267SDavid Härdeman data->rxstate = WBCIR_RXSTATE_INACTIVE; 9925b2e303fSDavid Härdeman ir_raw_event_reset(data->dev); 993e5eda7faSSean Young ir_raw_event_set_idle(data->dev, true); 9945b2e303fSDavid Härdeman 9957bfb5dc1SDavid Härdeman /* Clear TX state */ 996c829f267SDavid Härdeman if (data->txstate == WBCIR_TXSTATE_ACTIVE) { 9977bfb5dc1SDavid Härdeman kfree(data->txbuf); 9987bfb5dc1SDavid Härdeman data->txbuf = NULL; 9997bfb5dc1SDavid Härdeman data->txstate = WBCIR_TXSTATE_INACTIVE; 1000c829f267SDavid Härdeman } 1001c829f267SDavid Härdeman 10025b2e303fSDavid Härdeman /* Enable interrupts */ 1003c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); 10045b2e303fSDavid Härdeman } 10055b2e303fSDavid Härdeman 10065b2e303fSDavid Härdeman static int 10075b2e303fSDavid Härdeman wbcir_resume(struct pnp_dev *device) 10085b2e303fSDavid Härdeman { 10095b2e303fSDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device); 10105b2e303fSDavid Härdeman 10115b2e303fSDavid Härdeman wbcir_init_hw(data); 10125b2e303fSDavid Härdeman enable_irq(data->irq); 10131ac7fdeeSSean Young led_classdev_resume(&data->led); 10145b2e303fSDavid Härdeman 10155b2e303fSDavid Härdeman return 0; 10165b2e303fSDavid Härdeman } 10175b2e303fSDavid Härdeman 10184c62e976SGreg Kroah-Hartman static int 10195b2e303fSDavid Härdeman wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) 10205b2e303fSDavid Härdeman { 10215b2e303fSDavid Härdeman struct device *dev = &device->dev; 10225b2e303fSDavid Härdeman struct wbcir_data *data; 10235b2e303fSDavid Härdeman int err; 10245b2e303fSDavid Härdeman 10255b2e303fSDavid Härdeman if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && 10265b2e303fSDavid Härdeman pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && 10275b2e303fSDavid Härdeman pnp_port_len(device, 2) == SP_IOMEM_LEN)) { 10285b2e303fSDavid Härdeman dev_err(dev, "Invalid resources\n"); 10295b2e303fSDavid Härdeman return -ENODEV; 10305b2e303fSDavid Härdeman } 10315b2e303fSDavid Härdeman 10325b2e303fSDavid Härdeman data = kzalloc(sizeof(*data), GFP_KERNEL); 10335b2e303fSDavid Härdeman if (!data) { 10345b2e303fSDavid Härdeman err = -ENOMEM; 10355b2e303fSDavid Härdeman goto exit; 10365b2e303fSDavid Härdeman } 10375b2e303fSDavid Härdeman 10385b2e303fSDavid Härdeman pnp_set_drvdata(device, data); 10395b2e303fSDavid Härdeman 10405b2e303fSDavid Härdeman spin_lock_init(&data->spinlock); 10415b2e303fSDavid Härdeman data->ebase = pnp_port_start(device, 0); 10425b2e303fSDavid Härdeman data->wbase = pnp_port_start(device, 1); 10435b2e303fSDavid Härdeman data->sbase = pnp_port_start(device, 2); 10445b2e303fSDavid Härdeman data->irq = pnp_irq(device, 0); 10455b2e303fSDavid Härdeman 10465b2e303fSDavid Härdeman if (data->wbase == 0 || data->ebase == 0 || 10475b2e303fSDavid Härdeman data->sbase == 0 || data->irq == 0) { 10485b2e303fSDavid Härdeman err = -ENODEV; 10495b2e303fSDavid Härdeman dev_err(dev, "Invalid resources\n"); 10505b2e303fSDavid Härdeman goto exit_free_data; 10515b2e303fSDavid Härdeman } 10525b2e303fSDavid Härdeman 105325ec587cSMauro Carvalho Chehab dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", 10545b2e303fSDavid Härdeman data->wbase, data->ebase, data->sbase, data->irq); 10555b2e303fSDavid Härdeman 10565b2e303fSDavid Härdeman data->led.name = "cir::activity"; 10571ac7fdeeSSean Young data->led.default_trigger = "rc-feedback"; 10585b2e303fSDavid Härdeman data->led.brightness_set = wbcir_led_brightness_set; 10595b2e303fSDavid Härdeman data->led.brightness_get = wbcir_led_brightness_get; 10605b2e303fSDavid Härdeman err = led_classdev_register(&device->dev, &data->led); 10615b2e303fSDavid Härdeman if (err) 10621ac7fdeeSSean Young goto exit_free_data; 10635b2e303fSDavid Härdeman 10645b2e303fSDavid Härdeman data->dev = rc_allocate_device(); 10655b2e303fSDavid Härdeman if (!data->dev) { 10665b2e303fSDavid Härdeman err = -ENOMEM; 10675b2e303fSDavid Härdeman goto exit_unregister_led; 10685b2e303fSDavid Härdeman } 10695b2e303fSDavid Härdeman 1070d9b78695SDavid Härdeman data->dev->driver_type = RC_DRIVER_IR_RAW; 1071a66cd0b6SSean Young data->dev->driver_name = DRVNAME; 10725b2e303fSDavid Härdeman data->dev->input_name = WBCIR_NAME; 10735b2e303fSDavid Härdeman data->dev->input_phys = "wbcir/cir0"; 10745b2e303fSDavid Härdeman data->dev->input_id.bustype = BUS_HOST; 10755b2e303fSDavid Härdeman data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; 10765b2e303fSDavid Härdeman data->dev->input_id.product = WBCIR_ID_FAMILY; 10775b2e303fSDavid Härdeman data->dev->input_id.version = WBCIR_ID_CHIP; 1078c829f267SDavid Härdeman data->dev->map_name = RC_MAP_RC6_MCE; 1079488ebc48SDavid Härdeman data->dev->s_idle = wbcir_idle_rx; 108037b0b4e9SSean Young data->dev->s_carrier_report = wbcir_set_carrier_report; 1081c829f267SDavid Härdeman data->dev->s_tx_mask = wbcir_txmask; 1082c829f267SDavid Härdeman data->dev->s_tx_carrier = wbcir_txcarrier; 1083c829f267SDavid Härdeman data->dev->tx_ir = wbcir_tx; 10845b2e303fSDavid Härdeman data->dev->priv = data; 10855b2e303fSDavid Härdeman data->dev->dev.parent = &device->dev; 10868299d628SAnton Blanchard data->dev->timeout = MS_TO_NS(100); 1087c496e716SSean Young data->dev->rx_resolution = US_TO_NS(2); 10888c34b5c4SSean Young data->dev->allowed_protocols = RC_BIT_ALL_IR_DECODER; 1089f4742e1dSSean Young data->dev->allowed_wakeup_protocols = RC_BIT_NEC | RC_BIT_NECX | 1090f4742e1dSSean Young RC_BIT_NEC32 | RC_BIT_RC5 | RC_BIT_RC6_0 | 1091f4742e1dSSean Young RC_BIT_RC6_6A_20 | RC_BIT_RC6_6A_24 | 1092f4742e1dSSean Young RC_BIT_RC6_6A_32 | RC_BIT_RC6_MCE; 1093f4742e1dSSean Young data->dev->wakeup_protocol = RC_TYPE_RC6_MCE; 1094f4742e1dSSean Young data->dev->scancode_wakeup_filter.data = 0x800f040c; 1095f4742e1dSSean Young data->dev->scancode_wakeup_filter.mask = 0xffff7fff; 1096f4742e1dSSean Young data->dev->s_wakeup_filter = wbcir_set_wakeup_filter; 10975b2e303fSDavid Härdeman 10989fa35204SMatthijs Kooijman err = rc_register_device(data->dev); 10999fa35204SMatthijs Kooijman if (err) 11009fa35204SMatthijs Kooijman goto exit_free_rc; 11019fa35204SMatthijs Kooijman 11029ef449c6SLuis Henriques if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { 11039ef449c6SLuis Henriques dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 11049ef449c6SLuis Henriques data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); 11059ef449c6SLuis Henriques err = -EBUSY; 11069fa35204SMatthijs Kooijman goto exit_unregister_device; 11079ef449c6SLuis Henriques } 11089ef449c6SLuis Henriques 11099ef449c6SLuis Henriques if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { 11109ef449c6SLuis Henriques dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 11119ef449c6SLuis Henriques data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); 11129ef449c6SLuis Henriques err = -EBUSY; 11139ef449c6SLuis Henriques goto exit_release_wbase; 11149ef449c6SLuis Henriques } 11159ef449c6SLuis Henriques 11169ef449c6SLuis Henriques if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { 11179ef449c6SLuis Henriques dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", 11189ef449c6SLuis Henriques data->sbase, data->sbase + SP_IOMEM_LEN - 1); 11199ef449c6SLuis Henriques err = -EBUSY; 11209ef449c6SLuis Henriques goto exit_release_ebase; 11219ef449c6SLuis Henriques } 11229ef449c6SLuis Henriques 11239ef449c6SLuis Henriques err = request_irq(data->irq, wbcir_irq_handler, 1124b9e9f02aSMichael Opdenacker 0, DRVNAME, device); 11259ef449c6SLuis Henriques if (err) { 11269ef449c6SLuis Henriques dev_err(dev, "Failed to claim IRQ %u\n", data->irq); 11279ef449c6SLuis Henriques err = -EBUSY; 11289ef449c6SLuis Henriques goto exit_release_sbase; 11299ef449c6SLuis Henriques } 11309ef449c6SLuis Henriques 11315b2e303fSDavid Härdeman device_init_wakeup(&device->dev, 1); 11325b2e303fSDavid Härdeman 11335b2e303fSDavid Härdeman wbcir_init_hw(data); 11345b2e303fSDavid Härdeman 11355b2e303fSDavid Härdeman return 0; 11365b2e303fSDavid Härdeman 11375b2e303fSDavid Härdeman exit_release_sbase: 11385b2e303fSDavid Härdeman release_region(data->sbase, SP_IOMEM_LEN); 11395b2e303fSDavid Härdeman exit_release_ebase: 11405b2e303fSDavid Härdeman release_region(data->ebase, EHFUNC_IOMEM_LEN); 11415b2e303fSDavid Härdeman exit_release_wbase: 11425b2e303fSDavid Härdeman release_region(data->wbase, WAKEUP_IOMEM_LEN); 11439fa35204SMatthijs Kooijman exit_unregister_device: 11449fa35204SMatthijs Kooijman rc_unregister_device(data->dev); 11454ec16da7SWei Yongjun data->dev = NULL; 11469ef449c6SLuis Henriques exit_free_rc: 11479ef449c6SLuis Henriques rc_free_device(data->dev); 11489ef449c6SLuis Henriques exit_unregister_led: 11499ef449c6SLuis Henriques led_classdev_unregister(&data->led); 11505b2e303fSDavid Härdeman exit_free_data: 11515b2e303fSDavid Härdeman kfree(data); 11525b2e303fSDavid Härdeman pnp_set_drvdata(device, NULL); 11535b2e303fSDavid Härdeman exit: 11545b2e303fSDavid Härdeman return err; 11555b2e303fSDavid Härdeman } 11565b2e303fSDavid Härdeman 11574c62e976SGreg Kroah-Hartman static void 11585b2e303fSDavid Härdeman wbcir_remove(struct pnp_dev *device) 11595b2e303fSDavid Härdeman { 11605b2e303fSDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device); 11615b2e303fSDavid Härdeman 11625b2e303fSDavid Härdeman /* Disable interrupts */ 1163c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_NONE); 11645b2e303fSDavid Härdeman free_irq(data->irq, device); 11655b2e303fSDavid Härdeman 11665b2e303fSDavid Härdeman /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ 11675b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); 11685b2e303fSDavid Härdeman 11695b2e303fSDavid Härdeman /* Clear CEIR_EN */ 11705b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); 11715b2e303fSDavid Härdeman 11725b2e303fSDavid Härdeman /* Clear BUFF_EN, END_EN, MATCH_EN */ 11735b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); 11745b2e303fSDavid Härdeman 11755b2e303fSDavid Härdeman rc_unregister_device(data->dev); 11765b2e303fSDavid Härdeman 11775b2e303fSDavid Härdeman led_classdev_unregister(&data->led); 11785b2e303fSDavid Härdeman 11795b2e303fSDavid Härdeman /* This is ok since &data->led isn't actually used */ 11805b2e303fSDavid Härdeman wbcir_led_brightness_set(&data->led, LED_OFF); 11815b2e303fSDavid Härdeman 11825b2e303fSDavid Härdeman release_region(data->wbase, WAKEUP_IOMEM_LEN); 11835b2e303fSDavid Härdeman release_region(data->ebase, EHFUNC_IOMEM_LEN); 11845b2e303fSDavid Härdeman release_region(data->sbase, SP_IOMEM_LEN); 11855b2e303fSDavid Härdeman 11865b2e303fSDavid Härdeman kfree(data); 11875b2e303fSDavid Härdeman 11885b2e303fSDavid Härdeman pnp_set_drvdata(device, NULL); 11895b2e303fSDavid Härdeman } 11905b2e303fSDavid Härdeman 11915b2e303fSDavid Härdeman static const struct pnp_device_id wbcir_ids[] = { 11925b2e303fSDavid Härdeman { "WEC1022", 0 }, 11935b2e303fSDavid Härdeman { "", 0 } 11945b2e303fSDavid Härdeman }; 11955b2e303fSDavid Härdeman MODULE_DEVICE_TABLE(pnp, wbcir_ids); 11965b2e303fSDavid Härdeman 11975b2e303fSDavid Härdeman static struct pnp_driver wbcir_driver = { 11986932234fSSean Young .name = DRVNAME, 11995b2e303fSDavid Härdeman .id_table = wbcir_ids, 12005b2e303fSDavid Härdeman .probe = wbcir_probe, 12014c62e976SGreg Kroah-Hartman .remove = wbcir_remove, 12025b2e303fSDavid Härdeman .suspend = wbcir_suspend, 12035b2e303fSDavid Härdeman .resume = wbcir_resume, 12045b2e303fSDavid Härdeman .shutdown = wbcir_shutdown 12055b2e303fSDavid Härdeman }; 12065b2e303fSDavid Härdeman 12075b2e303fSDavid Härdeman static int __init 12085b2e303fSDavid Härdeman wbcir_init(void) 12095b2e303fSDavid Härdeman { 12105b2e303fSDavid Härdeman int ret; 12115b2e303fSDavid Härdeman 12125b2e303fSDavid Härdeman ret = pnp_register_driver(&wbcir_driver); 12135b2e303fSDavid Härdeman if (ret) 1214d8a10ac9SJoe Perches pr_err("Unable to register driver\n"); 12155b2e303fSDavid Härdeman 12165b2e303fSDavid Härdeman return ret; 12175b2e303fSDavid Härdeman } 12185b2e303fSDavid Härdeman 12195b2e303fSDavid Härdeman static void __exit 12205b2e303fSDavid Härdeman wbcir_exit(void) 12215b2e303fSDavid Härdeman { 12225b2e303fSDavid Härdeman pnp_unregister_driver(&wbcir_driver); 12235b2e303fSDavid Härdeman } 12245b2e303fSDavid Härdeman 12255b2e303fSDavid Härdeman module_init(wbcir_init); 12265b2e303fSDavid Härdeman module_exit(wbcir_exit); 12275b2e303fSDavid Härdeman 1228d36b6910SAl Viro MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); 12295b2e303fSDavid Härdeman MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); 12305b2e303fSDavid Härdeman MODULE_LICENSE("GPL"); 1231