1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
25b2e303fSDavid Härdeman /*
35b2e303fSDavid Härdeman * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
45b2e303fSDavid Härdeman * SuperI/O chips.
55b2e303fSDavid Härdeman *
65b2e303fSDavid Härdeman * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
75b2e303fSDavid Härdeman * could probably support others (Winbond WEC102X, NatSemi, etc)
85b2e303fSDavid Härdeman * with minor modifications.
95b2e303fSDavid Härdeman *
10b87f2eddSDavid Härdeman * Original Author: David Härdeman <david@hardeman.nu>
1137b0b4e9SSean Young * Copyright (C) 2012 Sean Young <sean@mess.org>
12b87f2eddSDavid Härdeman * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
135b2e303fSDavid Härdeman *
145b2e303fSDavid Härdeman * Dedicated to my daughter Matilda, without whose loving attention this
155b2e303fSDavid Härdeman * driver would have been finished in half the time and with a fraction
165b2e303fSDavid Härdeman * of the bugs.
175b2e303fSDavid Härdeman *
185b2e303fSDavid Härdeman * Written using:
195b2e303fSDavid Härdeman * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
205b2e303fSDavid Härdeman * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
215b2e303fSDavid Härdeman * o DSDT dumps
225b2e303fSDavid Härdeman *
235b2e303fSDavid Härdeman * Supported features:
24c829f267SDavid Härdeman * o IR Receive
25c829f267SDavid Härdeman * o IR Transmit
265b2e303fSDavid Härdeman * o Wake-On-CIR functionality
2737b0b4e9SSean Young * o Carrier detection
285b2e303fSDavid Härdeman */
295b2e303fSDavid Härdeman
30d8a10ac9SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31d8a10ac9SJoe Perches
325b2e303fSDavid Härdeman #include <linux/module.h>
335b2e303fSDavid Härdeman #include <linux/pnp.h>
345b2e303fSDavid Härdeman #include <linux/interrupt.h>
355b2e303fSDavid Härdeman #include <linux/timer.h>
365b2e303fSDavid Härdeman #include <linux/leds.h>
375b2e303fSDavid Härdeman #include <linux/spinlock.h>
385b2e303fSDavid Härdeman #include <linux/pci_ids.h>
395b2e303fSDavid Härdeman #include <linux/io.h>
405b2e303fSDavid Härdeman #include <linux/bitrev.h>
415b2e303fSDavid Härdeman #include <linux/slab.h>
42c829f267SDavid Härdeman #include <linux/wait.h>
43c829f267SDavid Härdeman #include <linux/sched.h>
446bda9644SMauro Carvalho Chehab #include <media/rc-core.h>
455b2e303fSDavid Härdeman
465b2e303fSDavid Härdeman #define DRVNAME "winbond-cir"
475b2e303fSDavid Härdeman
485b2e303fSDavid Härdeman /* CEIR Wake-Up Registers, relative to data->wbase */
495b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
505b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
515b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
525b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
535b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
545b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
555b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
565b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
575b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
585b2e303fSDavid Härdeman #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
595b2e303fSDavid Härdeman
605b2e303fSDavid Härdeman /* CEIR Enhanced Functionality Registers, relative to data->ebase */
615b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
625b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
635b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
645b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
655b2e303fSDavid Härdeman #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
665b2e303fSDavid Härdeman
675b2e303fSDavid Härdeman /* SP3 Banked Registers, relative to data->sbase */
685b2e303fSDavid Härdeman #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
695b2e303fSDavid Härdeman /* Bank 0 */
705b2e303fSDavid Härdeman #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
715b2e303fSDavid Härdeman #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
725b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
735b2e303fSDavid Härdeman #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
745b2e303fSDavid Härdeman #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
755b2e303fSDavid Härdeman #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
765b2e303fSDavid Härdeman #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
775b2e303fSDavid Härdeman #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
785b2e303fSDavid Härdeman #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
795b2e303fSDavid Härdeman /* Bank 2 */
805b2e303fSDavid Härdeman #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
815b2e303fSDavid Härdeman #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
825b2e303fSDavid Härdeman #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
835b2e303fSDavid Härdeman #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
845b2e303fSDavid Härdeman #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
855b2e303fSDavid Härdeman #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
865b2e303fSDavid Härdeman /* Bank 3 */
875b2e303fSDavid Härdeman #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
885b2e303fSDavid Härdeman #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
895b2e303fSDavid Härdeman #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
905b2e303fSDavid Härdeman /* Bank 4 */
915b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
925b2e303fSDavid Härdeman /* Bank 5 */
935b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
945b2e303fSDavid Härdeman /* Bank 6 */
955b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
965b2e303fSDavid Härdeman #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
975b2e303fSDavid Härdeman /* Bank 7 */
985b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
995b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
1005b2e303fSDavid Härdeman #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
1015b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
1025b2e303fSDavid Härdeman #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
1035b2e303fSDavid Härdeman
1045b2e303fSDavid Härdeman /*
1055b2e303fSDavid Härdeman * Magic values follow
1065b2e303fSDavid Härdeman */
1075b2e303fSDavid Härdeman
1085b2e303fSDavid Härdeman /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
1095b2e303fSDavid Härdeman #define WBCIR_IRQ_NONE 0x00
1105b2e303fSDavid Härdeman /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
1115b2e303fSDavid Härdeman #define WBCIR_IRQ_RX 0x01
112c829f267SDavid Härdeman /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
113c829f267SDavid Härdeman #define WBCIR_IRQ_TX_LOW 0x02
1145b2e303fSDavid Härdeman /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
1155b2e303fSDavid Härdeman #define WBCIR_IRQ_ERR 0x04
116c829f267SDavid Härdeman /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
117c829f267SDavid Härdeman #define WBCIR_IRQ_TX_EMPTY 0x20
1185b2e303fSDavid Härdeman /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
1195b2e303fSDavid Härdeman #define WBCIR_LED_ENABLE 0x80
1205b2e303fSDavid Härdeman /* RX data available bit for WBCIR_REG_SP3_LSR */
1215b2e303fSDavid Härdeman #define WBCIR_RX_AVAIL 0x01
122c829f267SDavid Härdeman /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
123c829f267SDavid Härdeman #define WBCIR_RX_OVERRUN 0x02
124c829f267SDavid Härdeman /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
125c829f267SDavid Härdeman #define WBCIR_TX_EOT 0x04
1265b2e303fSDavid Härdeman /* RX disable bit for WBCIR_REG_SP3_ASCR */
1275b2e303fSDavid Härdeman #define WBCIR_RX_DISABLE 0x20
128c829f267SDavid Härdeman /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
129c829f267SDavid Härdeman #define WBCIR_TX_UNDERRUN 0x40
1305b2e303fSDavid Härdeman /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
1315b2e303fSDavid Härdeman #define WBCIR_EXT_ENABLE 0x01
1325b2e303fSDavid Härdeman /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
1335b2e303fSDavid Härdeman #define WBCIR_REGSEL_COMPARE 0x10
1345b2e303fSDavid Härdeman /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
1355b2e303fSDavid Härdeman #define WBCIR_REGSEL_MASK 0x20
1365b2e303fSDavid Härdeman /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
1375b2e303fSDavid Härdeman #define WBCIR_REG_ADDR0 0x00
13837b0b4e9SSean Young /* Enable carrier counter */
13937b0b4e9SSean Young #define WBCIR_CNTR_EN 0x01
14037b0b4e9SSean Young /* Reset carrier counter */
14137b0b4e9SSean Young #define WBCIR_CNTR_R 0x02
14237b0b4e9SSean Young /* Invert TX */
14337b0b4e9SSean Young #define WBCIR_IRTX_INV 0x04
1446f2627c2SSean Young /* Receiver oversampling */
1456f2627c2SSean Young #define WBCIR_RX_T_OV 0x40
1465b2e303fSDavid Härdeman
1475b2e303fSDavid Härdeman /* Valid banks for the SP3 UART */
1485b2e303fSDavid Härdeman enum wbcir_bank {
1495b2e303fSDavid Härdeman WBCIR_BANK_0 = 0x00,
1505b2e303fSDavid Härdeman WBCIR_BANK_1 = 0x80,
1515b2e303fSDavid Härdeman WBCIR_BANK_2 = 0xE0,
1525b2e303fSDavid Härdeman WBCIR_BANK_3 = 0xE4,
1535b2e303fSDavid Härdeman WBCIR_BANK_4 = 0xE8,
1545b2e303fSDavid Härdeman WBCIR_BANK_5 = 0xEC,
1555b2e303fSDavid Härdeman WBCIR_BANK_6 = 0xF0,
1565b2e303fSDavid Härdeman WBCIR_BANK_7 = 0xF4,
1575b2e303fSDavid Härdeman };
1585b2e303fSDavid Härdeman
1595b2e303fSDavid Härdeman /* Supported power-on IR Protocols */
1605b2e303fSDavid Härdeman enum wbcir_protocol {
1615b2e303fSDavid Härdeman IR_PROTOCOL_RC5 = 0x0,
1625b2e303fSDavid Härdeman IR_PROTOCOL_NEC = 0x1,
1635b2e303fSDavid Härdeman IR_PROTOCOL_RC6 = 0x2,
1645b2e303fSDavid Härdeman };
1655b2e303fSDavid Härdeman
166c829f267SDavid Härdeman /* Possible states for IR reception */
167c829f267SDavid Härdeman enum wbcir_rxstate {
168c829f267SDavid Härdeman WBCIR_RXSTATE_INACTIVE = 0,
169c829f267SDavid Härdeman WBCIR_RXSTATE_ACTIVE,
170c829f267SDavid Härdeman WBCIR_RXSTATE_ERROR
171c829f267SDavid Härdeman };
172c829f267SDavid Härdeman
173c829f267SDavid Härdeman /* Possible states for IR transmission */
174c829f267SDavid Härdeman enum wbcir_txstate {
175c829f267SDavid Härdeman WBCIR_TXSTATE_INACTIVE = 0,
176c829f267SDavid Härdeman WBCIR_TXSTATE_ACTIVE,
177c829f267SDavid Härdeman WBCIR_TXSTATE_ERROR
178c829f267SDavid Härdeman };
179c829f267SDavid Härdeman
1805b2e303fSDavid Härdeman /* Misc */
181a66cd0b6SSean Young #define WBCIR_NAME "Winbond CIR"
1825b2e303fSDavid Härdeman #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
1835b2e303fSDavid Härdeman #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
1845b2e303fSDavid Härdeman #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
1855b2e303fSDavid Härdeman #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
1865b2e303fSDavid Härdeman #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
1875b2e303fSDavid Härdeman
1885b2e303fSDavid Härdeman /* Per-device data */
1895b2e303fSDavid Härdeman struct wbcir_data {
1905b2e303fSDavid Härdeman spinlock_t spinlock;
191c829f267SDavid Härdeman struct rc_dev *dev;
192c829f267SDavid Härdeman struct led_classdev led;
1935b2e303fSDavid Härdeman
1945b2e303fSDavid Härdeman unsigned long wbase; /* Wake-Up Baseaddr */
1955b2e303fSDavid Härdeman unsigned long ebase; /* Enhanced Func. Baseaddr */
1965b2e303fSDavid Härdeman unsigned long sbase; /* Serial Port Baseaddr */
1975b2e303fSDavid Härdeman unsigned int irq; /* Serial Port IRQ */
198c829f267SDavid Härdeman u8 irqmask;
1995b2e303fSDavid Härdeman
200c829f267SDavid Härdeman /* RX state */
201c829f267SDavid Härdeman enum wbcir_rxstate rxstate;
20237b0b4e9SSean Young int carrier_report_enabled;
20337b0b4e9SSean Young u32 pulse_duration;
2045b2e303fSDavid Härdeman
205c829f267SDavid Härdeman /* TX state */
206c829f267SDavid Härdeman enum wbcir_txstate txstate;
207c829f267SDavid Härdeman u32 txlen;
208c829f267SDavid Härdeman u32 txoff;
209c829f267SDavid Härdeman u32 *txbuf;
210c829f267SDavid Härdeman u8 txmask;
211c829f267SDavid Härdeman u32 txcarrier;
2125b2e303fSDavid Härdeman };
2135b2e303fSDavid Härdeman
21490ab5ee9SRusty Russell static bool invert; /* default = 0 */
2155b2e303fSDavid Härdeman module_param(invert, bool, 0444);
2165b2e303fSDavid Härdeman MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
2175b2e303fSDavid Härdeman
21890ab5ee9SRusty Russell static bool txandrx; /* default = 0 */
219c829f267SDavid Härdeman module_param(txandrx, bool, 0444);
22057f4422fSAnton Blanchard MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
221c829f267SDavid Härdeman
2225b2e303fSDavid Härdeman
2235b2e303fSDavid Härdeman /*****************************************************************************
2245b2e303fSDavid Härdeman *
2255b2e303fSDavid Härdeman * UTILITY FUNCTIONS
2265b2e303fSDavid Härdeman *
2275b2e303fSDavid Härdeman *****************************************************************************/
2285b2e303fSDavid Härdeman
2295b2e303fSDavid Härdeman /* Caller needs to hold wbcir_lock */
2305b2e303fSDavid Härdeman static void
wbcir_set_bits(unsigned long addr,u8 bits,u8 mask)2315b2e303fSDavid Härdeman wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
2325b2e303fSDavid Härdeman {
2335b2e303fSDavid Härdeman u8 val;
2345b2e303fSDavid Härdeman
2355b2e303fSDavid Härdeman val = inb(addr);
2365b2e303fSDavid Härdeman val = ((val & ~mask) | (bits & mask));
2375b2e303fSDavid Härdeman outb(val, addr);
2385b2e303fSDavid Härdeman }
2395b2e303fSDavid Härdeman
2405b2e303fSDavid Härdeman /* Selects the register bank for the serial port */
2415b2e303fSDavid Härdeman static inline void
wbcir_select_bank(struct wbcir_data * data,enum wbcir_bank bank)2425b2e303fSDavid Härdeman wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
2435b2e303fSDavid Härdeman {
2445b2e303fSDavid Härdeman outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
2455b2e303fSDavid Härdeman }
2465b2e303fSDavid Härdeman
247c829f267SDavid Härdeman static inline void
wbcir_set_irqmask(struct wbcir_data * data,u8 irqmask)248c829f267SDavid Härdeman wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
249c829f267SDavid Härdeman {
250c829f267SDavid Härdeman if (data->irqmask == irqmask)
251c829f267SDavid Härdeman return;
252c829f267SDavid Härdeman
253c829f267SDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0);
254c829f267SDavid Härdeman outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
255c829f267SDavid Härdeman data->irqmask = irqmask;
256c829f267SDavid Härdeman }
257c829f267SDavid Härdeman
2585b2e303fSDavid Härdeman static enum led_brightness
wbcir_led_brightness_get(struct led_classdev * led_cdev)2595b2e303fSDavid Härdeman wbcir_led_brightness_get(struct led_classdev *led_cdev)
2605b2e303fSDavid Härdeman {
2615b2e303fSDavid Härdeman struct wbcir_data *data = container_of(led_cdev,
2625b2e303fSDavid Härdeman struct wbcir_data,
2635b2e303fSDavid Härdeman led);
2645b2e303fSDavid Härdeman
2655b2e303fSDavid Härdeman if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
2665b2e303fSDavid Härdeman return LED_FULL;
2675b2e303fSDavid Härdeman else
2685b2e303fSDavid Härdeman return LED_OFF;
2695b2e303fSDavid Härdeman }
2705b2e303fSDavid Härdeman
2715b2e303fSDavid Härdeman static void
wbcir_led_brightness_set(struct led_classdev * led_cdev,enum led_brightness brightness)2725b2e303fSDavid Härdeman wbcir_led_brightness_set(struct led_classdev *led_cdev,
2735b2e303fSDavid Härdeman enum led_brightness brightness)
2745b2e303fSDavid Härdeman {
2755b2e303fSDavid Härdeman struct wbcir_data *data = container_of(led_cdev,
2765b2e303fSDavid Härdeman struct wbcir_data,
2775b2e303fSDavid Härdeman led);
2785b2e303fSDavid Härdeman
2795b2e303fSDavid Härdeman wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
2805b2e303fSDavid Härdeman brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
2815b2e303fSDavid Härdeman WBCIR_LED_ENABLE);
2825b2e303fSDavid Härdeman }
2835b2e303fSDavid Härdeman
2845b2e303fSDavid Härdeman /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
2855b2e303fSDavid Härdeman static u8
wbcir_to_rc6cells(u8 val)2865b2e303fSDavid Härdeman wbcir_to_rc6cells(u8 val)
2875b2e303fSDavid Härdeman {
2885b2e303fSDavid Härdeman u8 coded = 0x00;
2895b2e303fSDavid Härdeman int i;
2905b2e303fSDavid Härdeman
2915b2e303fSDavid Härdeman val &= 0x0F;
2925b2e303fSDavid Härdeman for (i = 0; i < 4; i++) {
2935b2e303fSDavid Härdeman if (val & 0x01)
2945b2e303fSDavid Härdeman coded |= 0x02 << (i * 2);
2955b2e303fSDavid Härdeman else
2965b2e303fSDavid Härdeman coded |= 0x01 << (i * 2);
2975b2e303fSDavid Härdeman val >>= 1;
2985b2e303fSDavid Härdeman }
2995b2e303fSDavid Härdeman
3005b2e303fSDavid Härdeman return coded;
3015b2e303fSDavid Härdeman }
3025b2e303fSDavid Härdeman
3035b2e303fSDavid Härdeman /*****************************************************************************
3045b2e303fSDavid Härdeman *
3055b2e303fSDavid Härdeman * INTERRUPT FUNCTIONS
3065b2e303fSDavid Härdeman *
3075b2e303fSDavid Härdeman *****************************************************************************/
3085b2e303fSDavid Härdeman
309c829f267SDavid Härdeman static void
wbcir_carrier_report(struct wbcir_data * data)31037b0b4e9SSean Young wbcir_carrier_report(struct wbcir_data *data)
31137b0b4e9SSean Young {
31237b0b4e9SSean Young unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) |
31337b0b4e9SSean Young inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8;
31437b0b4e9SSean Young
31537b0b4e9SSean Young if (counter > 0 && counter < 0xffff) {
316183e19f5SSean Young struct ir_raw_event ev = {
317183e19f5SSean Young .carrier_report = 1,
318183e19f5SSean Young .carrier = DIV_ROUND_CLOSEST(counter * 1000000u,
319183e19f5SSean Young data->pulse_duration)
320183e19f5SSean Young };
32137b0b4e9SSean Young
32237b0b4e9SSean Young ir_raw_event_store(data->dev, &ev);
32337b0b4e9SSean Young }
32437b0b4e9SSean Young
32537b0b4e9SSean Young /* reset and restart the counter */
32637b0b4e9SSean Young data->pulse_duration = 0;
32737b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
32837b0b4e9SSean Young WBCIR_CNTR_EN | WBCIR_CNTR_R);
32937b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN,
33037b0b4e9SSean Young WBCIR_CNTR_EN | WBCIR_CNTR_R);
33137b0b4e9SSean Young }
33237b0b4e9SSean Young
33337b0b4e9SSean Young static void
wbcir_idle_rx(struct rc_dev * dev,bool idle)334488ebc48SDavid Härdeman wbcir_idle_rx(struct rc_dev *dev, bool idle)
3355b2e303fSDavid Härdeman {
336488ebc48SDavid Härdeman struct wbcir_data *data = dev->priv;
3375b2e303fSDavid Härdeman
3381ac7fdeeSSean Young if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE)
339c829f267SDavid Härdeman data->rxstate = WBCIR_RXSTATE_ACTIVE;
3405b2e303fSDavid Härdeman
341e5eda7faSSean Young if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) {
342e5eda7faSSean Young data->rxstate = WBCIR_RXSTATE_INACTIVE;
34337b0b4e9SSean Young
34437b0b4e9SSean Young if (data->carrier_report_enabled)
34537b0b4e9SSean Young wbcir_carrier_report(data);
34637b0b4e9SSean Young
347488ebc48SDavid Härdeman /* Tell hardware to go idle by setting RXINACTIVE */
348488ebc48SDavid Härdeman outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
349488ebc48SDavid Härdeman }
350e5eda7faSSean Young }
351488ebc48SDavid Härdeman
352488ebc48SDavid Härdeman static void
wbcir_irq_rx(struct wbcir_data * data,struct pnp_dev * device)353488ebc48SDavid Härdeman wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
354488ebc48SDavid Härdeman {
355488ebc48SDavid Härdeman u8 irdata;
356183e19f5SSean Young struct ir_raw_event rawir = {};
357488ebc48SDavid Härdeman
3585b2e303fSDavid Härdeman /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
359488ebc48SDavid Härdeman while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
360488ebc48SDavid Härdeman irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
361c829f267SDavid Härdeman if (data->rxstate == WBCIR_RXSTATE_ERROR)
3625b2e303fSDavid Härdeman continue;
36337b0b4e9SSean Young
364528222d8SSean Young rawir.duration = ((irdata & 0x7F) + 1) *
3656f2627c2SSean Young (data->carrier_report_enabled ? 2 : 10);
366488ebc48SDavid Härdeman rawir.pulse = irdata & 0x80 ? false : true;
36737b0b4e9SSean Young
36837b0b4e9SSean Young if (rawir.pulse)
369528222d8SSean Young data->pulse_duration += rawir.duration;
37037b0b4e9SSean Young
371488ebc48SDavid Härdeman ir_raw_event_store_with_filter(data->dev, &rawir);
3725b2e303fSDavid Härdeman }
3735b2e303fSDavid Härdeman
3745b2e303fSDavid Härdeman ir_raw_event_handle(data->dev);
375c829f267SDavid Härdeman }
3765b2e303fSDavid Härdeman
377c829f267SDavid Härdeman static void
wbcir_irq_tx(struct wbcir_data * data)378c829f267SDavid Härdeman wbcir_irq_tx(struct wbcir_data *data)
379c829f267SDavid Härdeman {
380c829f267SDavid Härdeman unsigned int space;
381c829f267SDavid Härdeman unsigned int used;
382c829f267SDavid Härdeman u8 bytes[16];
383c829f267SDavid Härdeman u8 byte;
384c829f267SDavid Härdeman
385c829f267SDavid Härdeman if (!data->txbuf)
386c829f267SDavid Härdeman return;
387c829f267SDavid Härdeman
388c829f267SDavid Härdeman switch (data->txstate) {
389c829f267SDavid Härdeman case WBCIR_TXSTATE_INACTIVE:
390c829f267SDavid Härdeman /* TX FIFO empty */
391c829f267SDavid Härdeman space = 16;
392c829f267SDavid Härdeman break;
393c829f267SDavid Härdeman case WBCIR_TXSTATE_ACTIVE:
394c829f267SDavid Härdeman /* TX FIFO low (3 bytes or less) */
395c829f267SDavid Härdeman space = 13;
396c829f267SDavid Härdeman break;
397c829f267SDavid Härdeman case WBCIR_TXSTATE_ERROR:
398c829f267SDavid Härdeman space = 0;
399c829f267SDavid Härdeman break;
400c829f267SDavid Härdeman default:
401c829f267SDavid Härdeman return;
402c829f267SDavid Härdeman }
403c829f267SDavid Härdeman
404c829f267SDavid Härdeman /*
405c829f267SDavid Härdeman * TX data is run-length coded in bytes: YXXXXXXX
406c829f267SDavid Härdeman * Y = space (1) or pulse (0)
407c829f267SDavid Härdeman * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
408c829f267SDavid Härdeman */
409c829f267SDavid Härdeman for (used = 0; used < space && data->txoff != data->txlen; used++) {
410c829f267SDavid Härdeman if (data->txbuf[data->txoff] == 0) {
411c829f267SDavid Härdeman data->txoff++;
412c829f267SDavid Härdeman continue;
413c829f267SDavid Härdeman }
414c829f267SDavid Härdeman byte = min((u32)0x80, data->txbuf[data->txoff]);
415c829f267SDavid Härdeman data->txbuf[data->txoff] -= byte;
416c829f267SDavid Härdeman byte--;
417c829f267SDavid Härdeman byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
418c829f267SDavid Härdeman bytes[used] = byte;
419c829f267SDavid Härdeman }
420c829f267SDavid Härdeman
4214fe055ecSSean Young while (data->txoff != data->txlen && data->txbuf[data->txoff] == 0)
422c829f267SDavid Härdeman data->txoff++;
423c829f267SDavid Härdeman
424c829f267SDavid Härdeman if (used == 0) {
425c829f267SDavid Härdeman /* Finished */
426c829f267SDavid Härdeman if (data->txstate == WBCIR_TXSTATE_ERROR)
427c829f267SDavid Härdeman /* Clear TX underrun bit */
428c829f267SDavid Härdeman outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
429c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
4307bfb5dc1SDavid Härdeman kfree(data->txbuf);
4317bfb5dc1SDavid Härdeman data->txbuf = NULL;
4327bfb5dc1SDavid Härdeman data->txstate = WBCIR_TXSTATE_INACTIVE;
433c829f267SDavid Härdeman } else if (data->txoff == data->txlen) {
434c829f267SDavid Härdeman /* At the end of transmission, tell the hw before last byte */
435c829f267SDavid Härdeman outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
436c829f267SDavid Härdeman outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
437c829f267SDavid Härdeman outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
438c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
439c829f267SDavid Härdeman WBCIR_IRQ_TX_EMPTY);
440c829f267SDavid Härdeman } else {
441c829f267SDavid Härdeman /* More data to follow... */
442c829f267SDavid Härdeman outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
443c829f267SDavid Härdeman if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
444c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
445c829f267SDavid Härdeman WBCIR_IRQ_TX_LOW);
446c829f267SDavid Härdeman data->txstate = WBCIR_TXSTATE_ACTIVE;
447c829f267SDavid Härdeman }
448c829f267SDavid Härdeman }
449c829f267SDavid Härdeman }
450c829f267SDavid Härdeman
451c829f267SDavid Härdeman static irqreturn_t
wbcir_irq_handler(int irqno,void * cookie)452c829f267SDavid Härdeman wbcir_irq_handler(int irqno, void *cookie)
453c829f267SDavid Härdeman {
454c829f267SDavid Härdeman struct pnp_dev *device = cookie;
455c829f267SDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device);
456c829f267SDavid Härdeman unsigned long flags;
457c829f267SDavid Härdeman u8 status;
458c829f267SDavid Härdeman
459c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags);
460c829f267SDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0);
461c829f267SDavid Härdeman status = inb(data->sbase + WBCIR_REG_SP3_EIR);
462c829f267SDavid Härdeman status &= data->irqmask;
463c829f267SDavid Härdeman
464c829f267SDavid Härdeman if (!status) {
465c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
466c829f267SDavid Härdeman return IRQ_NONE;
467c829f267SDavid Härdeman }
468c829f267SDavid Härdeman
469c829f267SDavid Härdeman if (status & WBCIR_IRQ_ERR) {
470c829f267SDavid Härdeman /* RX overflow? (read clears bit) */
471c829f267SDavid Härdeman if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
472c829f267SDavid Härdeman data->rxstate = WBCIR_RXSTATE_ERROR;
473*950170d6SSean Young ir_raw_event_overflow(data->dev);
474c829f267SDavid Härdeman }
475c829f267SDavid Härdeman
476c829f267SDavid Härdeman /* TX underflow? */
477c829f267SDavid Härdeman if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
478c829f267SDavid Härdeman data->txstate = WBCIR_TXSTATE_ERROR;
479c829f267SDavid Härdeman }
480c829f267SDavid Härdeman
481c829f267SDavid Härdeman if (status & WBCIR_IRQ_RX)
482c829f267SDavid Härdeman wbcir_irq_rx(data, device);
483c829f267SDavid Härdeman
484c829f267SDavid Härdeman if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
485c829f267SDavid Härdeman wbcir_irq_tx(data);
486c829f267SDavid Härdeman
4875b2e303fSDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
4885b2e303fSDavid Härdeman return IRQ_HANDLED;
4895b2e303fSDavid Härdeman }
4905b2e303fSDavid Härdeman
491c829f267SDavid Härdeman /*****************************************************************************
492c829f267SDavid Härdeman *
493c829f267SDavid Härdeman * RC-CORE INTERFACE FUNCTIONS
494c829f267SDavid Härdeman *
495c829f267SDavid Härdeman *****************************************************************************/
4965b2e303fSDavid Härdeman
497c829f267SDavid Härdeman static int
wbcir_set_carrier_report(struct rc_dev * dev,int enable)49837b0b4e9SSean Young wbcir_set_carrier_report(struct rc_dev *dev, int enable)
49937b0b4e9SSean Young {
50037b0b4e9SSean Young struct wbcir_data *data = dev->priv;
50137b0b4e9SSean Young unsigned long flags;
50237b0b4e9SSean Young
50337b0b4e9SSean Young spin_lock_irqsave(&data->spinlock, flags);
50437b0b4e9SSean Young
50537b0b4e9SSean Young if (data->carrier_report_enabled == enable) {
50637b0b4e9SSean Young spin_unlock_irqrestore(&data->spinlock, flags);
50737b0b4e9SSean Young return 0;
50837b0b4e9SSean Young }
50937b0b4e9SSean Young
51037b0b4e9SSean Young data->pulse_duration = 0;
51137b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R,
51237b0b4e9SSean Young WBCIR_CNTR_EN | WBCIR_CNTR_R);
51337b0b4e9SSean Young
51437b0b4e9SSean Young if (enable && data->dev->idle)
51537b0b4e9SSean Young wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL,
51637b0b4e9SSean Young WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R);
51737b0b4e9SSean Young
5186f2627c2SSean Young /* Set a higher sampling resolution if carrier reports are enabled */
5196f2627c2SSean Young wbcir_select_bank(data, WBCIR_BANK_2);
520528222d8SSean Young data->dev->rx_resolution = enable ? 2 : 10;
5216f2627c2SSean Young outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
5226f2627c2SSean Young outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
5236f2627c2SSean Young
5246f2627c2SSean Young /* Enable oversampling if carrier reports are enabled */
5256f2627c2SSean Young wbcir_select_bank(data, WBCIR_BANK_7);
5266f2627c2SSean Young wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG,
5276f2627c2SSean Young enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV);
5286f2627c2SSean Young
52937b0b4e9SSean Young data->carrier_report_enabled = enable;
53037b0b4e9SSean Young spin_unlock_irqrestore(&data->spinlock, flags);
53137b0b4e9SSean Young
53237b0b4e9SSean Young return 0;
53337b0b4e9SSean Young }
53437b0b4e9SSean Young
53537b0b4e9SSean Young static int
wbcir_txcarrier(struct rc_dev * dev,u32 carrier)536c829f267SDavid Härdeman wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
537c829f267SDavid Härdeman {
538c829f267SDavid Härdeman struct wbcir_data *data = dev->priv;
539c829f267SDavid Härdeman unsigned long flags;
540c829f267SDavid Härdeman u8 val;
541c829f267SDavid Härdeman u32 freq;
542c829f267SDavid Härdeman
543c829f267SDavid Härdeman freq = DIV_ROUND_CLOSEST(carrier, 1000);
544c829f267SDavid Härdeman if (freq < 30 || freq > 60)
545c829f267SDavid Härdeman return -EINVAL;
546c829f267SDavid Härdeman
547c829f267SDavid Härdeman switch (freq) {
548c829f267SDavid Härdeman case 58:
549c829f267SDavid Härdeman case 59:
550c829f267SDavid Härdeman case 60:
551c829f267SDavid Härdeman val = freq - 58;
552c829f267SDavid Härdeman freq *= 1000;
553c829f267SDavid Härdeman break;
554c829f267SDavid Härdeman case 57:
555c829f267SDavid Härdeman val = freq - 27;
556c829f267SDavid Härdeman freq = 56900;
557c829f267SDavid Härdeman break;
558c829f267SDavid Härdeman default:
559c829f267SDavid Härdeman val = freq - 27;
560c829f267SDavid Härdeman freq *= 1000;
561c829f267SDavid Härdeman break;
562c829f267SDavid Härdeman }
563c829f267SDavid Härdeman
564c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags);
565c829f267SDavid Härdeman if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
566c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
567c829f267SDavid Härdeman return -EBUSY;
568c829f267SDavid Härdeman }
569c829f267SDavid Härdeman
570c829f267SDavid Härdeman if (data->txcarrier != freq) {
571c829f267SDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_7);
572c829f267SDavid Härdeman wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
573c829f267SDavid Härdeman data->txcarrier = freq;
574c829f267SDavid Härdeman }
575c829f267SDavid Härdeman
576c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
577c829f267SDavid Härdeman return 0;
578c829f267SDavid Härdeman }
579c829f267SDavid Härdeman
580c829f267SDavid Härdeman static int
wbcir_txmask(struct rc_dev * dev,u32 mask)581c829f267SDavid Härdeman wbcir_txmask(struct rc_dev *dev, u32 mask)
582c829f267SDavid Härdeman {
583c829f267SDavid Härdeman struct wbcir_data *data = dev->priv;
584c829f267SDavid Härdeman unsigned long flags;
585c829f267SDavid Härdeman u8 val;
586c829f267SDavid Härdeman
58720f5a827SSean Young /* return the number of transmitters */
58820f5a827SSean Young if (mask > 15)
58920f5a827SSean Young return 4;
59020f5a827SSean Young
591c829f267SDavid Härdeman /* Four outputs, only one output can be enabled at a time */
592c829f267SDavid Härdeman switch (mask) {
593c829f267SDavid Härdeman case 0x1:
594c829f267SDavid Härdeman val = 0x0;
595c829f267SDavid Härdeman break;
596c829f267SDavid Härdeman case 0x2:
597c829f267SDavid Härdeman val = 0x1;
598c829f267SDavid Härdeman break;
599c829f267SDavid Härdeman case 0x4:
600c829f267SDavid Härdeman val = 0x2;
601c829f267SDavid Härdeman break;
602c829f267SDavid Härdeman case 0x8:
603c829f267SDavid Härdeman val = 0x3;
604c829f267SDavid Härdeman break;
605c829f267SDavid Härdeman default:
606c829f267SDavid Härdeman return -EINVAL;
607c829f267SDavid Härdeman }
608c829f267SDavid Härdeman
609c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags);
610c829f267SDavid Härdeman if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
611c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
612c829f267SDavid Härdeman return -EBUSY;
613c829f267SDavid Härdeman }
614c829f267SDavid Härdeman
615c829f267SDavid Härdeman if (data->txmask != mask) {
616c829f267SDavid Härdeman wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
617c829f267SDavid Härdeman data->txmask = mask;
618c829f267SDavid Härdeman }
619c829f267SDavid Härdeman
620c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
621c829f267SDavid Härdeman return 0;
622c829f267SDavid Härdeman }
623c829f267SDavid Härdeman
624c829f267SDavid Härdeman static int
wbcir_tx(struct rc_dev * dev,unsigned * b,unsigned count)6257bfb5dc1SDavid Härdeman wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
626c829f267SDavid Härdeman {
627c829f267SDavid Härdeman struct wbcir_data *data = dev->priv;
6287bfb5dc1SDavid Härdeman unsigned *buf;
629c829f267SDavid Härdeman unsigned i;
630c829f267SDavid Härdeman unsigned long flags;
631c829f267SDavid Härdeman
632ce3aeaf2SMarkus Elfring buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL);
6337bfb5dc1SDavid Härdeman if (!buf)
6347bfb5dc1SDavid Härdeman return -ENOMEM;
6357bfb5dc1SDavid Härdeman
6367bfb5dc1SDavid Härdeman /* Convert values to multiples of 10us */
6377bfb5dc1SDavid Härdeman for (i = 0; i < count; i++)
6387bfb5dc1SDavid Härdeman buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
6397bfb5dc1SDavid Härdeman
640c829f267SDavid Härdeman /* Not sure if this is possible, but better safe than sorry */
641c829f267SDavid Härdeman spin_lock_irqsave(&data->spinlock, flags);
642c829f267SDavid Härdeman if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
643c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
6447bfb5dc1SDavid Härdeman kfree(buf);
645c829f267SDavid Härdeman return -EBUSY;
646c829f267SDavid Härdeman }
647c829f267SDavid Härdeman
648c829f267SDavid Härdeman /* Fill the TX fifo once, the irq handler will do the rest */
649c829f267SDavid Härdeman data->txbuf = buf;
650c829f267SDavid Härdeman data->txlen = count;
651c829f267SDavid Härdeman data->txoff = 0;
652c829f267SDavid Härdeman wbcir_irq_tx(data);
653c829f267SDavid Härdeman
654c829f267SDavid Härdeman /* We're done */
655c829f267SDavid Härdeman spin_unlock_irqrestore(&data->spinlock, flags);
656c829f267SDavid Härdeman return count;
657c829f267SDavid Härdeman }
6585b2e303fSDavid Härdeman
6595b2e303fSDavid Härdeman /*****************************************************************************
6605b2e303fSDavid Härdeman *
6615b2e303fSDavid Härdeman * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
6625b2e303fSDavid Härdeman *
6635b2e303fSDavid Härdeman *****************************************************************************/
6645b2e303fSDavid Härdeman
6655b2e303fSDavid Härdeman static void
wbcir_shutdown(struct pnp_dev * device)6665b2e303fSDavid Härdeman wbcir_shutdown(struct pnp_dev *device)
6675b2e303fSDavid Härdeman {
6685b2e303fSDavid Härdeman struct device *dev = &device->dev;
6695b2e303fSDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device);
670f4742e1dSSean Young struct rc_dev *rc = data->dev;
67167cdd42eSDavid Härdeman bool do_wake = true;
6725b2e303fSDavid Härdeman u8 match[11];
6735b2e303fSDavid Härdeman u8 mask[11];
6745b2e303fSDavid Härdeman u8 rc6_csl = 0;
675f4742e1dSSean Young u8 proto;
676f4742e1dSSean Young u32 wake_sc = rc->scancode_wakeup_filter.data;
677f4742e1dSSean Young u32 mask_sc = rc->scancode_wakeup_filter.mask;
6785b2e303fSDavid Härdeman int i;
6795b2e303fSDavid Härdeman
6805b2e303fSDavid Härdeman memset(match, 0, sizeof(match));
6815b2e303fSDavid Härdeman memset(mask, 0, sizeof(mask));
6825b2e303fSDavid Härdeman
683f4742e1dSSean Young if (!mask_sc || !device_may_wakeup(dev)) {
68467cdd42eSDavid Härdeman do_wake = false;
6855b2e303fSDavid Härdeman goto finish;
6865b2e303fSDavid Härdeman }
6875b2e303fSDavid Härdeman
688f4742e1dSSean Young switch (rc->wakeup_protocol) {
6896d741bfeSSean Young case RC_PROTO_RC5:
6905b2e303fSDavid Härdeman /* Mask = 13 bits, ex toggle */
691f4742e1dSSean Young mask[0] = (mask_sc & 0x003f);
692f4742e1dSSean Young mask[0] |= (mask_sc & 0x0300) >> 2;
693f4742e1dSSean Young mask[1] = (mask_sc & 0x1c00) >> 10;
694f4742e1dSSean Young if (mask_sc & 0x0040) /* 2nd start bit */
695f4742e1dSSean Young match[1] |= 0x10;
6965b2e303fSDavid Härdeman
6975b2e303fSDavid Härdeman match[0] = (wake_sc & 0x003F); /* 6 command bits */
698f4742e1dSSean Young match[0] |= (wake_sc & 0x0300) >> 2; /* 2 address bits */
699f4742e1dSSean Young match[1] = (wake_sc & 0x1c00) >> 10; /* 3 address bits */
7005b2e303fSDavid Härdeman if (!(wake_sc & 0x0040)) /* 2nd start bit */
7015b2e303fSDavid Härdeman match[1] |= 0x10;
7025b2e303fSDavid Härdeman
703f4742e1dSSean Young proto = IR_PROTOCOL_RC5;
7045b2e303fSDavid Härdeman break;
7055b2e303fSDavid Härdeman
7066d741bfeSSean Young case RC_PROTO_NEC:
707f4742e1dSSean Young mask[1] = bitrev8(mask_sc);
708f4742e1dSSean Young mask[0] = mask[1];
709f4742e1dSSean Young mask[3] = bitrev8(mask_sc >> 8);
710f4742e1dSSean Young mask[2] = mask[3];
7115b2e303fSDavid Härdeman
712f4742e1dSSean Young match[1] = bitrev8(wake_sc);
7135b2e303fSDavid Härdeman match[0] = ~match[1];
714f4742e1dSSean Young match[3] = bitrev8(wake_sc >> 8);
7155b2e303fSDavid Härdeman match[2] = ~match[3];
7165b2e303fSDavid Härdeman
717f4742e1dSSean Young proto = IR_PROTOCOL_NEC;
7185b2e303fSDavid Härdeman break;
7195b2e303fSDavid Härdeman
7206d741bfeSSean Young case RC_PROTO_NECX:
721f4742e1dSSean Young mask[1] = bitrev8(mask_sc);
722f4742e1dSSean Young mask[0] = mask[1];
723f4742e1dSSean Young mask[2] = bitrev8(mask_sc >> 8);
724f4742e1dSSean Young mask[3] = bitrev8(mask_sc >> 16);
7255b2e303fSDavid Härdeman
726f4742e1dSSean Young match[1] = bitrev8(wake_sc);
727f4742e1dSSean Young match[0] = ~match[1];
728f4742e1dSSean Young match[2] = bitrev8(wake_sc >> 8);
729f4742e1dSSean Young match[3] = bitrev8(wake_sc >> 16);
730f4742e1dSSean Young
731f4742e1dSSean Young proto = IR_PROTOCOL_NEC;
7325b2e303fSDavid Härdeman break;
7335b2e303fSDavid Härdeman
7346d741bfeSSean Young case RC_PROTO_NEC32:
735f4742e1dSSean Young mask[0] = bitrev8(mask_sc);
736f4742e1dSSean Young mask[1] = bitrev8(mask_sc >> 8);
737f4742e1dSSean Young mask[2] = bitrev8(mask_sc >> 16);
738f4742e1dSSean Young mask[3] = bitrev8(mask_sc >> 24);
739f4742e1dSSean Young
740f4742e1dSSean Young match[0] = bitrev8(wake_sc);
741f4742e1dSSean Young match[1] = bitrev8(wake_sc >> 8);
742f4742e1dSSean Young match[2] = bitrev8(wake_sc >> 16);
743f4742e1dSSean Young match[3] = bitrev8(wake_sc >> 24);
744f4742e1dSSean Young
745f4742e1dSSean Young proto = IR_PROTOCOL_NEC;
746f4742e1dSSean Young break;
747f4742e1dSSean Young
7486d741bfeSSean Young case RC_PROTO_RC6_0:
7495b2e303fSDavid Härdeman /* Command */
7505b2e303fSDavid Härdeman match[0] = wbcir_to_rc6cells(wake_sc >> 0);
751f4742e1dSSean Young mask[0] = wbcir_to_rc6cells(mask_sc >> 0);
7525b2e303fSDavid Härdeman match[1] = wbcir_to_rc6cells(wake_sc >> 4);
753f4742e1dSSean Young mask[1] = wbcir_to_rc6cells(mask_sc >> 4);
7545b2e303fSDavid Härdeman
7555b2e303fSDavid Härdeman /* Address */
7565b2e303fSDavid Härdeman match[2] = wbcir_to_rc6cells(wake_sc >> 8);
757f4742e1dSSean Young mask[2] = wbcir_to_rc6cells(mask_sc >> 8);
7585b2e303fSDavid Härdeman match[3] = wbcir_to_rc6cells(wake_sc >> 12);
759f4742e1dSSean Young mask[3] = wbcir_to_rc6cells(mask_sc >> 12);
7605b2e303fSDavid Härdeman
7615b2e303fSDavid Härdeman /* Header */
7625b2e303fSDavid Härdeman match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
7635b2e303fSDavid Härdeman mask[4] = 0xF0;
7645b2e303fSDavid Härdeman match[5] = 0x09; /* start bit = 1, mode2 = 0 */
7655b2e303fSDavid Härdeman mask[5] = 0x0F;
7665b2e303fSDavid Härdeman
7675b2e303fSDavid Härdeman rc6_csl = 44;
768f4742e1dSSean Young proto = IR_PROTOCOL_RC6;
769f4742e1dSSean Young break;
7705b2e303fSDavid Härdeman
7716d741bfeSSean Young case RC_PROTO_RC6_6A_24:
7726d741bfeSSean Young case RC_PROTO_RC6_6A_32:
7736d741bfeSSean Young case RC_PROTO_RC6_MCE:
7745b2e303fSDavid Härdeman i = 0;
7755b2e303fSDavid Härdeman
7765b2e303fSDavid Härdeman /* Command */
7775b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 0);
778f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 0);
7795b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 4);
780f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 4);
7815b2e303fSDavid Härdeman
7825b2e303fSDavid Härdeman /* Address + Toggle */
7835b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 8);
784f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 8);
7855b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 12);
786f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 12);
7875b2e303fSDavid Härdeman
7885b2e303fSDavid Härdeman /* Customer bits 7 - 0 */
7895b2e303fSDavid Härdeman match[i] = wbcir_to_rc6cells(wake_sc >> 16);
790f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 16);
7915b2e303fSDavid Härdeman
7926d741bfeSSean Young if (rc->wakeup_protocol == RC_PROTO_RC6_6A_20) {
793f4742e1dSSean Young rc6_csl = 52;
794f4742e1dSSean Young } else {
795f4742e1dSSean Young match[i] = wbcir_to_rc6cells(wake_sc >> 20);
796f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 20);
797f4742e1dSSean Young
7986d741bfeSSean Young if (rc->wakeup_protocol == RC_PROTO_RC6_6A_24) {
7995b2e303fSDavid Härdeman rc6_csl = 60;
8005b2e303fSDavid Härdeman } else {
801f4742e1dSSean Young /* Customer range bit and bits 15 - 8 */
802f4742e1dSSean Young match[i] = wbcir_to_rc6cells(wake_sc >> 24);
803f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 24);
804f4742e1dSSean Young match[i] = wbcir_to_rc6cells(wake_sc >> 28);
805f4742e1dSSean Young mask[i++] = wbcir_to_rc6cells(mask_sc >> 28);
806f4742e1dSSean Young rc6_csl = 76;
807f4742e1dSSean Young }
8085b2e303fSDavid Härdeman }
8095b2e303fSDavid Härdeman
8105b2e303fSDavid Härdeman /* Header */
8115b2e303fSDavid Härdeman match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
8125b2e303fSDavid Härdeman mask[i++] = 0xFF;
8135b2e303fSDavid Härdeman match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
8145b2e303fSDavid Härdeman mask[i++] = 0x0F;
815f4742e1dSSean Young proto = IR_PROTOCOL_RC6;
8165b2e303fSDavid Härdeman break;
8175b2e303fSDavid Härdeman default:
81867cdd42eSDavid Härdeman do_wake = false;
8195b2e303fSDavid Härdeman break;
8205b2e303fSDavid Härdeman }
8215b2e303fSDavid Härdeman
8225b2e303fSDavid Härdeman finish:
8235b2e303fSDavid Härdeman if (do_wake) {
8245b2e303fSDavid Härdeman /* Set compare and compare mask */
8255b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
8265b2e303fSDavid Härdeman WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
8275b2e303fSDavid Härdeman 0x3F);
8285b2e303fSDavid Härdeman outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
8295b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
8305b2e303fSDavid Härdeman WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
8315b2e303fSDavid Härdeman 0x3F);
8325b2e303fSDavid Härdeman outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
8335b2e303fSDavid Härdeman
8345b2e303fSDavid Härdeman /* RC6 Compare String Len */
8355b2e303fSDavid Härdeman outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
8365b2e303fSDavid Härdeman
8375b2e303fSDavid Härdeman /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
8385b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
8395b2e303fSDavid Härdeman
8405b2e303fSDavid Härdeman /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
8415b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
8425b2e303fSDavid Härdeman
8435b2e303fSDavid Härdeman /* Set CEIR_EN */
844f4742e1dSSean Young wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL,
845f4742e1dSSean Young (proto << 4) | 0x01, 0x31);
8465b2e303fSDavid Härdeman
8475b2e303fSDavid Härdeman } else {
8485b2e303fSDavid Härdeman /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
8495b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
8505b2e303fSDavid Härdeman
8515b2e303fSDavid Härdeman /* Clear CEIR_EN */
8525b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
8535b2e303fSDavid Härdeman }
8545b2e303fSDavid Härdeman
8555b2e303fSDavid Härdeman /*
8565b2e303fSDavid Härdeman * ACPI will set the HW disable bit for SP3 which means that the
8575b2e303fSDavid Härdeman * output signals are left in an undefined state which may cause
8585b2e303fSDavid Härdeman * spurious interrupts which we need to ignore until the hardware
8595b2e303fSDavid Härdeman * is reinitialized.
8605b2e303fSDavid Härdeman */
861c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
8625b2e303fSDavid Härdeman disable_irq(data->irq);
8635b2e303fSDavid Härdeman }
8645b2e303fSDavid Härdeman
865f4742e1dSSean Young /*
866f4742e1dSSean Young * Wakeup handling is done on shutdown.
867f4742e1dSSean Young */
868f4742e1dSSean Young static int
wbcir_set_wakeup_filter(struct rc_dev * rc,struct rc_scancode_filter * filter)869f4742e1dSSean Young wbcir_set_wakeup_filter(struct rc_dev *rc, struct rc_scancode_filter *filter)
870f4742e1dSSean Young {
871f4742e1dSSean Young return 0;
872f4742e1dSSean Young }
873f4742e1dSSean Young
8745b2e303fSDavid Härdeman static int
wbcir_suspend(struct pnp_dev * device,pm_message_t state)8755b2e303fSDavid Härdeman wbcir_suspend(struct pnp_dev *device, pm_message_t state)
8765b2e303fSDavid Härdeman {
8771ac7fdeeSSean Young struct wbcir_data *data = pnp_get_drvdata(device);
8781ac7fdeeSSean Young led_classdev_suspend(&data->led);
8795b2e303fSDavid Härdeman wbcir_shutdown(device);
8805b2e303fSDavid Härdeman return 0;
8815b2e303fSDavid Härdeman }
8825b2e303fSDavid Härdeman
8835b2e303fSDavid Härdeman static void
wbcir_init_hw(struct wbcir_data * data)8845b2e303fSDavid Härdeman wbcir_init_hw(struct wbcir_data *data)
8855b2e303fSDavid Härdeman {
8865b2e303fSDavid Härdeman /* Disable interrupts */
887c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
8885b2e303fSDavid Härdeman
889f4742e1dSSean Young /* Set RX_INV, Clear CEIR_EN (needed for the led) */
890f4742e1dSSean Young wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, invert ? 8 : 0, 0x09);
8915b2e303fSDavid Härdeman
8925b2e303fSDavid Härdeman /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
8935b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
8945b2e303fSDavid Härdeman
8955b2e303fSDavid Härdeman /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
8965b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
8975b2e303fSDavid Härdeman
8985b2e303fSDavid Härdeman /* Set RC5 cell time to correspond to 36 kHz */
8995b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
9005b2e303fSDavid Härdeman
9015b2e303fSDavid Härdeman /* Set IRTX_INV */
9025b2e303fSDavid Härdeman if (invert)
90337b0b4e9SSean Young outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL);
9045b2e303fSDavid Härdeman else
9055b2e303fSDavid Härdeman outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
9065b2e303fSDavid Härdeman
9075b2e303fSDavid Härdeman /*
908c829f267SDavid Härdeman * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
9095b2e303fSDavid Härdeman * set SP3_IRRX_SW to binary 01, helpfully not documented
9105b2e303fSDavid Härdeman */
9115b2e303fSDavid Härdeman outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
912c829f267SDavid Härdeman data->txmask = 0x1;
9135b2e303fSDavid Härdeman
9145b2e303fSDavid Härdeman /* Enable extended mode */
9155b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_2);
9165b2e303fSDavid Härdeman outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
9175b2e303fSDavid Härdeman
9185b2e303fSDavid Härdeman /*
9195b2e303fSDavid Härdeman * Configure baud generator, IR data will be sampled at
9205b2e303fSDavid Härdeman * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
9215b2e303fSDavid Härdeman *
9225b2e303fSDavid Härdeman * The ECIR registers include a flag to change the
9235b2e303fSDavid Härdeman * 24Mhz clock freq to 48Mhz.
9245b2e303fSDavid Härdeman *
9255b2e303fSDavid Härdeman * It's not documented in the specs, but fifo levels
9265b2e303fSDavid Härdeman * other than 16 seems to be unsupported.
9275b2e303fSDavid Härdeman */
9285b2e303fSDavid Härdeman
9295b2e303fSDavid Härdeman /* prescaler 1.0, tx/rx fifo lvl 16 */
9305b2e303fSDavid Härdeman outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
9315b2e303fSDavid Härdeman
9326f2627c2SSean Young /* Set baud divisor to sample every 10 us */
9336f2627c2SSean Young outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL);
9345b2e303fSDavid Härdeman outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
9355b2e303fSDavid Härdeman
9365b2e303fSDavid Härdeman /* Set CEIR mode */
9375b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0);
9385b2e303fSDavid Härdeman outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
9395b2e303fSDavid Härdeman inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
9405b2e303fSDavid Härdeman inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
9415b2e303fSDavid Härdeman
9426f2627c2SSean Young /* Disable RX demod, enable run-length enc/dec, set freq span */
9435b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_7);
9446f2627c2SSean Young outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
9455b2e303fSDavid Härdeman
9465b2e303fSDavid Härdeman /* Disable timer */
9475b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_4);
9485b2e303fSDavid Härdeman outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
9495b2e303fSDavid Härdeman
950c829f267SDavid Härdeman /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
9515b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_5);
952c829f267SDavid Härdeman outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
9535b2e303fSDavid Härdeman
9545b2e303fSDavid Härdeman /* Disable CRC */
9555b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_6);
9565b2e303fSDavid Härdeman outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
9575b2e303fSDavid Härdeman
958c829f267SDavid Härdeman /* Set RX demodulation freq, not really used */
9595b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_7);
9605b2e303fSDavid Härdeman outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
961c829f267SDavid Härdeman
962c829f267SDavid Härdeman /* Set TX modulation, 36kHz, 7us pulse width */
9635b2e303fSDavid Härdeman outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
964c829f267SDavid Härdeman data->txcarrier = 36000;
9655b2e303fSDavid Härdeman
9665b2e303fSDavid Härdeman /* Set invert and pin direction */
9675b2e303fSDavid Härdeman if (invert)
9685b2e303fSDavid Härdeman outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
9695b2e303fSDavid Härdeman else
9705b2e303fSDavid Härdeman outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
9715b2e303fSDavid Härdeman
9725b2e303fSDavid Härdeman /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
9735b2e303fSDavid Härdeman wbcir_select_bank(data, WBCIR_BANK_0);
9745b2e303fSDavid Härdeman outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
9755b2e303fSDavid Härdeman
9765b2e303fSDavid Härdeman /* Clear AUX status bits */
9775b2e303fSDavid Härdeman outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
9785b2e303fSDavid Härdeman
979c829f267SDavid Härdeman /* Clear RX state */
980c829f267SDavid Härdeman data->rxstate = WBCIR_RXSTATE_INACTIVE;
9815dae9ceaSSean Young wbcir_idle_rx(data->dev, true);
9825b2e303fSDavid Härdeman
9837bfb5dc1SDavid Härdeman /* Clear TX state */
984c829f267SDavid Härdeman if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
9857bfb5dc1SDavid Härdeman kfree(data->txbuf);
9867bfb5dc1SDavid Härdeman data->txbuf = NULL;
9877bfb5dc1SDavid Härdeman data->txstate = WBCIR_TXSTATE_INACTIVE;
988c829f267SDavid Härdeman }
989c829f267SDavid Härdeman
9905b2e303fSDavid Härdeman /* Enable interrupts */
991c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
9925b2e303fSDavid Härdeman }
9935b2e303fSDavid Härdeman
9945b2e303fSDavid Härdeman static int
wbcir_resume(struct pnp_dev * device)9955b2e303fSDavid Härdeman wbcir_resume(struct pnp_dev *device)
9965b2e303fSDavid Härdeman {
9975b2e303fSDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device);
9985b2e303fSDavid Härdeman
9995b2e303fSDavid Härdeman wbcir_init_hw(data);
10005b2e303fSDavid Härdeman enable_irq(data->irq);
10011ac7fdeeSSean Young led_classdev_resume(&data->led);
10025b2e303fSDavid Härdeman
10035b2e303fSDavid Härdeman return 0;
10045b2e303fSDavid Härdeman }
10055b2e303fSDavid Härdeman
10064c62e976SGreg Kroah-Hartman static int
wbcir_probe(struct pnp_dev * device,const struct pnp_device_id * dev_id)10075b2e303fSDavid Härdeman wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
10085b2e303fSDavid Härdeman {
10095b2e303fSDavid Härdeman struct device *dev = &device->dev;
10105b2e303fSDavid Härdeman struct wbcir_data *data;
10115b2e303fSDavid Härdeman int err;
10125b2e303fSDavid Härdeman
10135b2e303fSDavid Härdeman if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
10145b2e303fSDavid Härdeman pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
10155b2e303fSDavid Härdeman pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
10165b2e303fSDavid Härdeman dev_err(dev, "Invalid resources\n");
10175b2e303fSDavid Härdeman return -ENODEV;
10185b2e303fSDavid Härdeman }
10195b2e303fSDavid Härdeman
10205b2e303fSDavid Härdeman data = kzalloc(sizeof(*data), GFP_KERNEL);
10215b2e303fSDavid Härdeman if (!data) {
10225b2e303fSDavid Härdeman err = -ENOMEM;
10235b2e303fSDavid Härdeman goto exit;
10245b2e303fSDavid Härdeman }
10255b2e303fSDavid Härdeman
10265b2e303fSDavid Härdeman pnp_set_drvdata(device, data);
10275b2e303fSDavid Härdeman
10285b2e303fSDavid Härdeman spin_lock_init(&data->spinlock);
10295b2e303fSDavid Härdeman data->ebase = pnp_port_start(device, 0);
10305b2e303fSDavid Härdeman data->wbase = pnp_port_start(device, 1);
10315b2e303fSDavid Härdeman data->sbase = pnp_port_start(device, 2);
10325b2e303fSDavid Härdeman data->irq = pnp_irq(device, 0);
10335b2e303fSDavid Härdeman
10345b2e303fSDavid Härdeman if (data->wbase == 0 || data->ebase == 0 ||
1035621fa19aSArvind Yadav data->sbase == 0 || data->irq == -1) {
10365b2e303fSDavid Härdeman err = -ENODEV;
10375b2e303fSDavid Härdeman dev_err(dev, "Invalid resources\n");
10385b2e303fSDavid Härdeman goto exit_free_data;
10395b2e303fSDavid Härdeman }
10405b2e303fSDavid Härdeman
104125ec587cSMauro Carvalho Chehab dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
10425b2e303fSDavid Härdeman data->wbase, data->ebase, data->sbase, data->irq);
10435b2e303fSDavid Härdeman
10445b2e303fSDavid Härdeman data->led.name = "cir::activity";
10451ac7fdeeSSean Young data->led.default_trigger = "rc-feedback";
10465b2e303fSDavid Härdeman data->led.brightness_set = wbcir_led_brightness_set;
10475b2e303fSDavid Härdeman data->led.brightness_get = wbcir_led_brightness_get;
10485b2e303fSDavid Härdeman err = led_classdev_register(&device->dev, &data->led);
10495b2e303fSDavid Härdeman if (err)
10501ac7fdeeSSean Young goto exit_free_data;
10515b2e303fSDavid Härdeman
10520f7499fdSAndi Shyti data->dev = rc_allocate_device(RC_DRIVER_IR_RAW);
10535b2e303fSDavid Härdeman if (!data->dev) {
10545b2e303fSDavid Härdeman err = -ENOMEM;
10555b2e303fSDavid Härdeman goto exit_unregister_led;
10565b2e303fSDavid Härdeman }
10575b2e303fSDavid Härdeman
1058a66cd0b6SSean Young data->dev->driver_name = DRVNAME;
1059518f4b26SSean Young data->dev->device_name = WBCIR_NAME;
10605b2e303fSDavid Härdeman data->dev->input_phys = "wbcir/cir0";
10615b2e303fSDavid Härdeman data->dev->input_id.bustype = BUS_HOST;
10625b2e303fSDavid Härdeman data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
10635b2e303fSDavid Härdeman data->dev->input_id.product = WBCIR_ID_FAMILY;
10645b2e303fSDavid Härdeman data->dev->input_id.version = WBCIR_ID_CHIP;
1065c829f267SDavid Härdeman data->dev->map_name = RC_MAP_RC6_MCE;
1066488ebc48SDavid Härdeman data->dev->s_idle = wbcir_idle_rx;
106737b0b4e9SSean Young data->dev->s_carrier_report = wbcir_set_carrier_report;
1068c829f267SDavid Härdeman data->dev->s_tx_mask = wbcir_txmask;
1069c829f267SDavid Härdeman data->dev->s_tx_carrier = wbcir_txcarrier;
1070c829f267SDavid Härdeman data->dev->tx_ir = wbcir_tx;
10715b2e303fSDavid Härdeman data->dev->priv = data;
10725b2e303fSDavid Härdeman data->dev->dev.parent = &device->dev;
1073ea80fb6dSSean Young data->dev->min_timeout = 1;
1074ea80fb6dSSean Young data->dev->timeout = IR_DEFAULT_TIMEOUT;
1075ea80fb6dSSean Young data->dev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
1076528222d8SSean Young data->dev->rx_resolution = 2;
10776d741bfeSSean Young data->dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
10786d741bfeSSean Young data->dev->allowed_wakeup_protocols = RC_PROTO_BIT_NEC |
10796d741bfeSSean Young RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | RC_PROTO_BIT_RC5 |
10806d741bfeSSean Young RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 |
10816d741bfeSSean Young RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 |
10826d741bfeSSean Young RC_PROTO_BIT_RC6_MCE;
10836d741bfeSSean Young data->dev->wakeup_protocol = RC_PROTO_RC6_MCE;
1084f4742e1dSSean Young data->dev->scancode_wakeup_filter.data = 0x800f040c;
1085f4742e1dSSean Young data->dev->scancode_wakeup_filter.mask = 0xffff7fff;
1086f4742e1dSSean Young data->dev->s_wakeup_filter = wbcir_set_wakeup_filter;
10875b2e303fSDavid Härdeman
10889fa35204SMatthijs Kooijman err = rc_register_device(data->dev);
10899fa35204SMatthijs Kooijman if (err)
10909fa35204SMatthijs Kooijman goto exit_free_rc;
10919fa35204SMatthijs Kooijman
10929ef449c6SLuis Henriques if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
10939ef449c6SLuis Henriques dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
10949ef449c6SLuis Henriques data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
10959ef449c6SLuis Henriques err = -EBUSY;
10969fa35204SMatthijs Kooijman goto exit_unregister_device;
10979ef449c6SLuis Henriques }
10989ef449c6SLuis Henriques
10999ef449c6SLuis Henriques if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
11009ef449c6SLuis Henriques dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
11019ef449c6SLuis Henriques data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
11029ef449c6SLuis Henriques err = -EBUSY;
11039ef449c6SLuis Henriques goto exit_release_wbase;
11049ef449c6SLuis Henriques }
11059ef449c6SLuis Henriques
11069ef449c6SLuis Henriques if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
11079ef449c6SLuis Henriques dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
11089ef449c6SLuis Henriques data->sbase, data->sbase + SP_IOMEM_LEN - 1);
11099ef449c6SLuis Henriques err = -EBUSY;
11109ef449c6SLuis Henriques goto exit_release_ebase;
11119ef449c6SLuis Henriques }
11129ef449c6SLuis Henriques
11139ef449c6SLuis Henriques err = request_irq(data->irq, wbcir_irq_handler,
1114b9e9f02aSMichael Opdenacker 0, DRVNAME, device);
11159ef449c6SLuis Henriques if (err) {
11169ef449c6SLuis Henriques dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
11179ef449c6SLuis Henriques err = -EBUSY;
11189ef449c6SLuis Henriques goto exit_release_sbase;
11199ef449c6SLuis Henriques }
11209ef449c6SLuis Henriques
11215b2e303fSDavid Härdeman device_init_wakeup(&device->dev, 1);
11225b2e303fSDavid Härdeman
11235b2e303fSDavid Härdeman wbcir_init_hw(data);
11245b2e303fSDavid Härdeman
11255b2e303fSDavid Härdeman return 0;
11265b2e303fSDavid Härdeman
11275b2e303fSDavid Härdeman exit_release_sbase:
11285b2e303fSDavid Härdeman release_region(data->sbase, SP_IOMEM_LEN);
11295b2e303fSDavid Härdeman exit_release_ebase:
11305b2e303fSDavid Härdeman release_region(data->ebase, EHFUNC_IOMEM_LEN);
11315b2e303fSDavid Härdeman exit_release_wbase:
11325b2e303fSDavid Härdeman release_region(data->wbase, WAKEUP_IOMEM_LEN);
11339fa35204SMatthijs Kooijman exit_unregister_device:
11349fa35204SMatthijs Kooijman rc_unregister_device(data->dev);
11354ec16da7SWei Yongjun data->dev = NULL;
11369ef449c6SLuis Henriques exit_free_rc:
11379ef449c6SLuis Henriques rc_free_device(data->dev);
11389ef449c6SLuis Henriques exit_unregister_led:
11399ef449c6SLuis Henriques led_classdev_unregister(&data->led);
11405b2e303fSDavid Härdeman exit_free_data:
11415b2e303fSDavid Härdeman kfree(data);
11425b2e303fSDavid Härdeman pnp_set_drvdata(device, NULL);
11435b2e303fSDavid Härdeman exit:
11445b2e303fSDavid Härdeman return err;
11455b2e303fSDavid Härdeman }
11465b2e303fSDavid Härdeman
11474c62e976SGreg Kroah-Hartman static void
wbcir_remove(struct pnp_dev * device)11485b2e303fSDavid Härdeman wbcir_remove(struct pnp_dev *device)
11495b2e303fSDavid Härdeman {
11505b2e303fSDavid Härdeman struct wbcir_data *data = pnp_get_drvdata(device);
11515b2e303fSDavid Härdeman
11525b2e303fSDavid Härdeman /* Disable interrupts */
1153c829f267SDavid Härdeman wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
11545b2e303fSDavid Härdeman free_irq(data->irq, device);
11555b2e303fSDavid Härdeman
11565b2e303fSDavid Härdeman /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
11575b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
11585b2e303fSDavid Härdeman
11595b2e303fSDavid Härdeman /* Clear CEIR_EN */
11605b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
11615b2e303fSDavid Härdeman
11625b2e303fSDavid Härdeman /* Clear BUFF_EN, END_EN, MATCH_EN */
11635b2e303fSDavid Härdeman wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
11645b2e303fSDavid Härdeman
11655b2e303fSDavid Härdeman rc_unregister_device(data->dev);
11665b2e303fSDavid Härdeman
11675b2e303fSDavid Härdeman led_classdev_unregister(&data->led);
11685b2e303fSDavid Härdeman
11695b2e303fSDavid Härdeman /* This is ok since &data->led isn't actually used */
11705b2e303fSDavid Härdeman wbcir_led_brightness_set(&data->led, LED_OFF);
11715b2e303fSDavid Härdeman
11725b2e303fSDavid Härdeman release_region(data->wbase, WAKEUP_IOMEM_LEN);
11735b2e303fSDavid Härdeman release_region(data->ebase, EHFUNC_IOMEM_LEN);
11745b2e303fSDavid Härdeman release_region(data->sbase, SP_IOMEM_LEN);
11755b2e303fSDavid Härdeman
11765b2e303fSDavid Härdeman kfree(data);
11775b2e303fSDavid Härdeman
11785b2e303fSDavid Härdeman pnp_set_drvdata(device, NULL);
11795b2e303fSDavid Härdeman }
11805b2e303fSDavid Härdeman
11815b2e303fSDavid Härdeman static const struct pnp_device_id wbcir_ids[] = {
11825b2e303fSDavid Härdeman { "WEC1022", 0 },
11835b2e303fSDavid Härdeman { "", 0 }
11845b2e303fSDavid Härdeman };
11855b2e303fSDavid Härdeman MODULE_DEVICE_TABLE(pnp, wbcir_ids);
11865b2e303fSDavid Härdeman
11875b2e303fSDavid Härdeman static struct pnp_driver wbcir_driver = {
11886932234fSSean Young .name = DRVNAME,
11895b2e303fSDavid Härdeman .id_table = wbcir_ids,
11905b2e303fSDavid Härdeman .probe = wbcir_probe,
11914c62e976SGreg Kroah-Hartman .remove = wbcir_remove,
11925b2e303fSDavid Härdeman .suspend = wbcir_suspend,
11935b2e303fSDavid Härdeman .resume = wbcir_resume,
11945b2e303fSDavid Härdeman .shutdown = wbcir_shutdown
11955b2e303fSDavid Härdeman };
11965b2e303fSDavid Härdeman
11975b2e303fSDavid Härdeman static int __init
wbcir_init(void)11985b2e303fSDavid Härdeman wbcir_init(void)
11995b2e303fSDavid Härdeman {
12005b2e303fSDavid Härdeman int ret;
12015b2e303fSDavid Härdeman
12025b2e303fSDavid Härdeman ret = pnp_register_driver(&wbcir_driver);
12035b2e303fSDavid Härdeman if (ret)
1204d8a10ac9SJoe Perches pr_err("Unable to register driver\n");
12055b2e303fSDavid Härdeman
12065b2e303fSDavid Härdeman return ret;
12075b2e303fSDavid Härdeman }
12085b2e303fSDavid Härdeman
12095b2e303fSDavid Härdeman static void __exit
wbcir_exit(void)12105b2e303fSDavid Härdeman wbcir_exit(void)
12115b2e303fSDavid Härdeman {
12125b2e303fSDavid Härdeman pnp_unregister_driver(&wbcir_driver);
12135b2e303fSDavid Härdeman }
12145b2e303fSDavid Härdeman
12155b2e303fSDavid Härdeman module_init(wbcir_init);
12165b2e303fSDavid Härdeman module_exit(wbcir_exit);
12175b2e303fSDavid Härdeman
1218d36b6910SAl Viro MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
12195b2e303fSDavid Härdeman MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
12205b2e303fSDavid Härdeman MODULE_LICENSE("GPL");
1221