1 /* 2 * Copyright (C) 2013 STMicroelectronics Limited 3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/clk.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <media/rc-core.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/pm_wakeirq.h> 20 21 struct st_rc_device { 22 struct device *dev; 23 int irq; 24 int irq_wake; 25 struct clk *sys_clock; 26 void __iomem *base; /* Register base address */ 27 void __iomem *rx_base;/* RX Register base address */ 28 struct rc_dev *rdev; 29 bool overclocking; 30 int sample_mult; 31 int sample_div; 32 bool rxuhfmode; 33 struct reset_control *rstc; 34 }; 35 36 /* Registers */ 37 #define IRB_SAMPLE_RATE_COMM 0x64 /* sample freq divisor*/ 38 #define IRB_CLOCK_SEL 0x70 /* clock select */ 39 #define IRB_CLOCK_SEL_STATUS 0x74 /* clock status */ 40 /* IRB IR/UHF receiver registers */ 41 #define IRB_RX_ON 0x40 /* pulse time capture */ 42 #define IRB_RX_SYS 0X44 /* sym period capture */ 43 #define IRB_RX_INT_EN 0x48 /* IRQ enable (R/W) */ 44 #define IRB_RX_INT_STATUS 0x4c /* IRQ status (R/W) */ 45 #define IRB_RX_EN 0x50 /* Receive enable */ 46 #define IRB_MAX_SYM_PERIOD 0x54 /* max sym value */ 47 #define IRB_RX_INT_CLEAR 0x58 /* overrun status */ 48 #define IRB_RX_STATUS 0x6c /* receive status */ 49 #define IRB_RX_NOISE_SUPPR 0x5c /* noise suppression */ 50 #define IRB_RX_POLARITY_INV 0x68 /* polarity inverter */ 51 52 /* 53 * IRQ set: Enable full FIFO 1 -> bit 3; 54 * Enable overrun IRQ 1 -> bit 2; 55 * Enable last symbol IRQ 1 -> bit 1: 56 * Enable RX interrupt 1 -> bit 0; 57 */ 58 #define IRB_RX_INTS 0x0f 59 #define IRB_RX_OVERRUN_INT 0x04 60 /* maximum symbol period (microsecs),timeout to detect end of symbol train */ 61 #define MAX_SYMB_TIME 0x5000 62 #define IRB_SAMPLE_FREQ 10000000 63 #define IRB_FIFO_NOT_EMPTY 0xff00 64 #define IRB_OVERFLOW 0x4 65 #define IRB_TIMEOUT 0xffff 66 #define IR_ST_NAME "st-rc" 67 68 static void st_rc_send_lirc_timeout(struct rc_dev *rdev) 69 { 70 struct ir_raw_event ev = { .timeout = true, .duration = rdev->timeout }; 71 ir_raw_event_store(rdev, &ev); 72 } 73 74 /* 75 * RX graphical example to better understand the difference between ST IR block 76 * output and standard definition used by LIRC (and most of the world!) 77 * 78 * mark mark 79 * |-IRB_RX_ON-| |-IRB_RX_ON-| 80 * ___ ___ ___ ___ ___ ___ _ 81 * | | | | | | | | | | | | | 82 * | | | | | | space 0 | | | | | | space 1 | 83 * _____| |__| |__| |____________________________| |__| |__| |_____________| 84 * 85 * |--------------- IRB_RX_SYS -------------|------ IRB_RX_SYS -------| 86 * 87 * |------------- encoding bit 0 -----------|---- encoding bit 1 -----| 88 * 89 * ST hardware returns mark (IRB_RX_ON) and total symbol time (IRB_RX_SYS), so 90 * convert to standard mark/space we have to calculate space=(IRB_RX_SYS-mark) 91 * The mark time represents the amount of time the carrier (usually 36-40kHz) 92 * is detected.The above examples shows Pulse Width Modulation encoding where 93 * bit 0 is represented by space>mark. 94 */ 95 96 static irqreturn_t st_rc_rx_interrupt(int irq, void *data) 97 { 98 unsigned long timeout; 99 unsigned int symbol, mark = 0; 100 struct st_rc_device *dev = data; 101 int last_symbol = 0; 102 u32 status, int_status; 103 struct ir_raw_event ev = {}; 104 105 if (dev->irq_wake) 106 pm_wakeup_event(dev->dev, 0); 107 108 /* FIXME: is 10ms good enough ? */ 109 timeout = jiffies + msecs_to_jiffies(10); 110 do { 111 status = readl(dev->rx_base + IRB_RX_STATUS); 112 if (!(status & (IRB_FIFO_NOT_EMPTY | IRB_OVERFLOW))) 113 break; 114 115 int_status = readl(dev->rx_base + IRB_RX_INT_STATUS); 116 if (unlikely(int_status & IRB_RX_OVERRUN_INT)) { 117 /* discard the entire collection in case of errors! */ 118 ir_raw_event_reset(dev->rdev); 119 dev_info(dev->dev, "IR RX overrun\n"); 120 writel(IRB_RX_OVERRUN_INT, 121 dev->rx_base + IRB_RX_INT_CLEAR); 122 continue; 123 } 124 125 symbol = readl(dev->rx_base + IRB_RX_SYS); 126 mark = readl(dev->rx_base + IRB_RX_ON); 127 128 if (symbol == IRB_TIMEOUT) 129 last_symbol = 1; 130 131 /* Ignore any noise */ 132 if ((mark > 2) && (symbol > 1)) { 133 symbol -= mark; 134 if (dev->overclocking) { /* adjustments to timings */ 135 symbol *= dev->sample_mult; 136 symbol /= dev->sample_div; 137 mark *= dev->sample_mult; 138 mark /= dev->sample_div; 139 } 140 141 ev.duration = US_TO_NS(mark); 142 ev.pulse = true; 143 ir_raw_event_store(dev->rdev, &ev); 144 145 if (!last_symbol) { 146 ev.duration = US_TO_NS(symbol); 147 ev.pulse = false; 148 ir_raw_event_store(dev->rdev, &ev); 149 } else { 150 st_rc_send_lirc_timeout(dev->rdev); 151 } 152 153 } 154 last_symbol = 0; 155 } while (time_is_after_jiffies(timeout)); 156 157 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); 158 159 /* Empty software fifo */ 160 ir_raw_event_handle(dev->rdev); 161 return IRQ_HANDLED; 162 } 163 164 static void st_rc_hardware_init(struct st_rc_device *dev) 165 { 166 int baseclock, freqdiff; 167 unsigned int rx_max_symbol_per = MAX_SYMB_TIME; 168 unsigned int rx_sampling_freq_div; 169 170 /* Enable the IP */ 171 reset_control_deassert(dev->rstc); 172 173 clk_prepare_enable(dev->sys_clock); 174 baseclock = clk_get_rate(dev->sys_clock); 175 176 /* IRB input pins are inverted internally from high to low. */ 177 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); 178 179 rx_sampling_freq_div = baseclock / IRB_SAMPLE_FREQ; 180 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); 181 182 freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ); 183 if (freqdiff) { /* over clocking, workout the adjustment factors */ 184 dev->overclocking = true; 185 dev->sample_mult = 1000; 186 dev->sample_div = baseclock / (10000 * rx_sampling_freq_div); 187 rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div; 188 } 189 190 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); 191 } 192 193 static int st_rc_remove(struct platform_device *pdev) 194 { 195 struct st_rc_device *rc_dev = platform_get_drvdata(pdev); 196 197 dev_pm_clear_wake_irq(&pdev->dev); 198 device_init_wakeup(&pdev->dev, false); 199 clk_disable_unprepare(rc_dev->sys_clock); 200 rc_unregister_device(rc_dev->rdev); 201 return 0; 202 } 203 204 static int st_rc_open(struct rc_dev *rdev) 205 { 206 struct st_rc_device *dev = rdev->priv; 207 unsigned long flags; 208 local_irq_save(flags); 209 /* enable interrupts and receiver */ 210 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); 211 writel(0x01, dev->rx_base + IRB_RX_EN); 212 local_irq_restore(flags); 213 214 return 0; 215 } 216 217 static void st_rc_close(struct rc_dev *rdev) 218 { 219 struct st_rc_device *dev = rdev->priv; 220 /* disable interrupts and receiver */ 221 writel(0x00, dev->rx_base + IRB_RX_EN); 222 writel(0x00, dev->rx_base + IRB_RX_INT_EN); 223 } 224 225 static int st_rc_probe(struct platform_device *pdev) 226 { 227 int ret = -EINVAL; 228 struct rc_dev *rdev; 229 struct device *dev = &pdev->dev; 230 struct resource *res; 231 struct st_rc_device *rc_dev; 232 struct device_node *np = pdev->dev.of_node; 233 const char *rx_mode; 234 235 rc_dev = devm_kzalloc(dev, sizeof(struct st_rc_device), GFP_KERNEL); 236 237 if (!rc_dev) 238 return -ENOMEM; 239 240 rdev = rc_allocate_device(RC_DRIVER_IR_RAW); 241 242 if (!rdev) 243 return -ENOMEM; 244 245 if (np && !of_property_read_string(np, "rx-mode", &rx_mode)) { 246 247 if (!strcmp(rx_mode, "uhf")) { 248 rc_dev->rxuhfmode = true; 249 } else if (!strcmp(rx_mode, "infrared")) { 250 rc_dev->rxuhfmode = false; 251 } else { 252 dev_err(dev, "Unsupported rx mode [%s]\n", rx_mode); 253 goto err; 254 } 255 256 } else { 257 goto err; 258 } 259 260 rc_dev->sys_clock = devm_clk_get(dev, NULL); 261 if (IS_ERR(rc_dev->sys_clock)) { 262 dev_err(dev, "System clock not found\n"); 263 ret = PTR_ERR(rc_dev->sys_clock); 264 goto err; 265 } 266 267 rc_dev->irq = platform_get_irq(pdev, 0); 268 if (rc_dev->irq < 0) { 269 ret = rc_dev->irq; 270 goto err; 271 } 272 273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 274 275 rc_dev->base = devm_ioremap_resource(dev, res); 276 if (IS_ERR(rc_dev->base)) { 277 ret = PTR_ERR(rc_dev->base); 278 goto err; 279 } 280 281 if (rc_dev->rxuhfmode) 282 rc_dev->rx_base = rc_dev->base + 0x40; 283 else 284 rc_dev->rx_base = rc_dev->base; 285 286 rc_dev->rstc = reset_control_get_optional_exclusive(dev, NULL); 287 if (IS_ERR(rc_dev->rstc)) { 288 ret = PTR_ERR(rc_dev->rstc); 289 goto err; 290 } 291 292 rc_dev->dev = dev; 293 platform_set_drvdata(pdev, rc_dev); 294 st_rc_hardware_init(rc_dev); 295 296 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 297 /* rx sampling rate is 10Mhz */ 298 rdev->rx_resolution = 100; 299 rdev->timeout = US_TO_NS(MAX_SYMB_TIME); 300 rdev->priv = rc_dev; 301 rdev->open = st_rc_open; 302 rdev->close = st_rc_close; 303 rdev->driver_name = IR_ST_NAME; 304 rdev->map_name = RC_MAP_EMPTY; 305 rdev->device_name = "ST Remote Control Receiver"; 306 307 ret = rc_register_device(rdev); 308 if (ret < 0) 309 goto clkerr; 310 311 rc_dev->rdev = rdev; 312 if (devm_request_irq(dev, rc_dev->irq, st_rc_rx_interrupt, 313 0, IR_ST_NAME, rc_dev) < 0) { 314 dev_err(dev, "IRQ %d register failed\n", rc_dev->irq); 315 ret = -EINVAL; 316 goto rcerr; 317 } 318 319 /* enable wake via this device */ 320 device_init_wakeup(dev, true); 321 dev_pm_set_wake_irq(dev, rc_dev->irq); 322 323 /* 324 * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW 325 * lircd expects a long space first before a signal train to sync. 326 */ 327 st_rc_send_lirc_timeout(rdev); 328 329 dev_info(dev, "setup in %s mode\n", rc_dev->rxuhfmode ? "UHF" : "IR"); 330 331 return ret; 332 rcerr: 333 rc_unregister_device(rdev); 334 rdev = NULL; 335 clkerr: 336 clk_disable_unprepare(rc_dev->sys_clock); 337 err: 338 rc_free_device(rdev); 339 dev_err(dev, "Unable to register device (%d)\n", ret); 340 return ret; 341 } 342 343 #ifdef CONFIG_PM_SLEEP 344 static int st_rc_suspend(struct device *dev) 345 { 346 struct st_rc_device *rc_dev = dev_get_drvdata(dev); 347 348 if (device_may_wakeup(dev)) { 349 if (!enable_irq_wake(rc_dev->irq)) 350 rc_dev->irq_wake = 1; 351 else 352 return -EINVAL; 353 } else { 354 pinctrl_pm_select_sleep_state(dev); 355 writel(0x00, rc_dev->rx_base + IRB_RX_EN); 356 writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN); 357 clk_disable_unprepare(rc_dev->sys_clock); 358 reset_control_assert(rc_dev->rstc); 359 } 360 361 return 0; 362 } 363 364 static int st_rc_resume(struct device *dev) 365 { 366 struct st_rc_device *rc_dev = dev_get_drvdata(dev); 367 struct rc_dev *rdev = rc_dev->rdev; 368 369 if (rc_dev->irq_wake) { 370 disable_irq_wake(rc_dev->irq); 371 rc_dev->irq_wake = 0; 372 } else { 373 pinctrl_pm_select_default_state(dev); 374 st_rc_hardware_init(rc_dev); 375 if (rdev->users) { 376 writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN); 377 writel(0x01, rc_dev->rx_base + IRB_RX_EN); 378 } 379 } 380 381 return 0; 382 } 383 384 #endif 385 386 static SIMPLE_DEV_PM_OPS(st_rc_pm_ops, st_rc_suspend, st_rc_resume); 387 388 #ifdef CONFIG_OF 389 static const struct of_device_id st_rc_match[] = { 390 { .compatible = "st,comms-irb", }, 391 {}, 392 }; 393 394 MODULE_DEVICE_TABLE(of, st_rc_match); 395 #endif 396 397 static struct platform_driver st_rc_driver = { 398 .driver = { 399 .name = IR_ST_NAME, 400 .of_match_table = of_match_ptr(st_rc_match), 401 .pm = &st_rc_pm_ops, 402 }, 403 .probe = st_rc_probe, 404 .remove = st_rc_remove, 405 }; 406 407 module_platform_driver(st_rc_driver); 408 409 MODULE_DESCRIPTION("RC Transceiver driver for STMicroelectronics platforms"); 410 MODULE_AUTHOR("STMicroelectronics (R&D) Ltd"); 411 MODULE_LICENSE("GPL"); 412