1 /* 2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 3 * 4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 5 * Copyright (C) 2009 Nuvoton PS Team 6 * 7 * Special thanks to Nuvoton for providing hardware, spec sheets and 8 * sample code upon which portions of this driver are based. Indirect 9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 10 * modeled after. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 25 * USA 26 */ 27 28 #include <linux/spinlock.h> 29 #include <linux/ioctl.h> 30 31 /* platform driver name to register */ 32 #define NVT_DRIVER_NAME "nuvoton-cir" 33 34 /* debugging module parameter */ 35 static int debug; 36 37 38 #define nvt_dbg(text, ...) \ 39 if (debug) \ 40 printk(KERN_DEBUG \ 41 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 42 43 #define nvt_dbg_verbose(text, ...) \ 44 if (debug > 1) \ 45 printk(KERN_DEBUG \ 46 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 47 48 #define nvt_dbg_wake(text, ...) \ 49 if (debug > 2) \ 50 printk(KERN_DEBUG \ 51 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 52 53 54 /* 55 * Original lirc driver said min value of 76, and recommended value of 256 56 * for the buffer length, but then used 2048. Never mind that the size of the 57 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm 58 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes), 59 * and I don't have TX-capable hardware to test/debug on... 60 */ 61 #define TX_BUF_LEN 256 62 #define RX_BUF_LEN 32 63 64 #define SIO_ID_MASK 0xfff0 65 66 enum nvt_chip_ver { 67 NVT_UNKNOWN = 0, 68 NVT_W83667HG = 0xa510, 69 NVT_6775F = 0xb470, 70 NVT_6776F = 0xc330, 71 NVT_6779D = 0xc560, 72 NVT_INVALID = 0xffff, 73 }; 74 75 struct nvt_chip { 76 const char *name; 77 enum nvt_chip_ver chip_ver; 78 }; 79 80 struct nvt_dev { 81 struct pnp_dev *pdev; 82 struct rc_dev *rdev; 83 84 spinlock_t nvt_lock; 85 86 /* for rx */ 87 u8 buf[RX_BUF_LEN]; 88 unsigned int pkts; 89 90 struct { 91 spinlock_t lock; 92 u8 buf[TX_BUF_LEN]; 93 unsigned int buf_count; 94 unsigned int cur_buf_num; 95 wait_queue_head_t queue; 96 u8 tx_state; 97 } tx; 98 99 /* EFER Config register index/data pair */ 100 u32 cr_efir; 101 u32 cr_efdr; 102 103 /* hardware I/O settings */ 104 unsigned long cir_addr; 105 unsigned long cir_wake_addr; 106 int cir_irq; 107 108 enum nvt_chip_ver chip_ver; 109 /* hardware id */ 110 u8 chip_major; 111 u8 chip_minor; 112 113 /* hardware features */ 114 bool hw_tx_capable; 115 116 /* carrier period = 1 / frequency */ 117 u32 carrier; 118 }; 119 120 /* send states */ 121 #define ST_TX_NONE 0x0 122 #define ST_TX_REQUEST 0x2 123 #define ST_TX_REPLY 0x4 124 125 /* buffer packet constants */ 126 #define BUF_PULSE_BIT 0x80 127 #define BUF_LEN_MASK 0x7f 128 #define BUF_REPEAT_BYTE 0x70 129 #define BUF_REPEAT_MASK 0xf0 130 131 /* CIR settings */ 132 133 /* total length of CIR and CIR WAKE */ 134 #define CIR_IOREG_LENGTH 0x0f 135 136 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */ 137 #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD)) 138 139 /* CIR Regs */ 140 #define CIR_IRCON 0x00 141 #define CIR_IRSTS 0x01 142 #define CIR_IREN 0x02 143 #define CIR_RXFCONT 0x03 144 #define CIR_CP 0x04 145 #define CIR_CC 0x05 146 #define CIR_SLCH 0x06 147 #define CIR_SLCL 0x07 148 #define CIR_FIFOCON 0x08 149 #define CIR_IRFIFOSTS 0x09 150 #define CIR_SRXFIFO 0x0a 151 #define CIR_TXFCONT 0x0b 152 #define CIR_STXFIFO 0x0c 153 #define CIR_FCCH 0x0d 154 #define CIR_FCCL 0x0e 155 #define CIR_IRFSM 0x0f 156 157 /* CIR IRCON settings */ 158 #define CIR_IRCON_RECV 0x80 159 #define CIR_IRCON_WIREN 0x40 160 #define CIR_IRCON_TXEN 0x20 161 #define CIR_IRCON_RXEN 0x10 162 #define CIR_IRCON_WRXINV 0x08 163 #define CIR_IRCON_RXINV 0x04 164 165 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 166 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 167 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 168 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 169 170 /* FIXME: make this a runtime option */ 171 /* select sample period as 50us */ 172 #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 173 174 /* CIR IRSTS settings */ 175 #define CIR_IRSTS_RDR 0x80 176 #define CIR_IRSTS_RTR 0x40 177 #define CIR_IRSTS_PE 0x20 178 #define CIR_IRSTS_RFO 0x10 179 #define CIR_IRSTS_TE 0x08 180 #define CIR_IRSTS_TTR 0x04 181 #define CIR_IRSTS_TFU 0x02 182 #define CIR_IRSTS_GH 0x01 183 184 /* CIR IREN settings */ 185 #define CIR_IREN_RDR 0x80 186 #define CIR_IREN_RTR 0x40 187 #define CIR_IREN_PE 0x20 188 #define CIR_IREN_RFO 0x10 189 #define CIR_IREN_TE 0x08 190 #define CIR_IREN_TTR 0x04 191 #define CIR_IREN_TFU 0x02 192 #define CIR_IREN_GH 0x01 193 194 /* CIR FIFOCON settings */ 195 #define CIR_FIFOCON_TXFIFOCLR 0x80 196 197 #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 198 #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 199 #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 200 #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 201 202 /* FIXME: make this a runtime option */ 203 /* select TX trigger level as 16 */ 204 #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 205 206 #define CIR_FIFOCON_RXFIFOCLR 0x08 207 208 #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 209 #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 210 #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 211 #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 212 213 /* FIXME: make this a runtime option */ 214 /* select RX trigger level as 24 */ 215 #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 216 217 /* CIR IRFIFOSTS settings */ 218 #define CIR_IRFIFOSTS_IR_PENDING 0x80 219 #define CIR_IRFIFOSTS_RX_GS 0x40 220 #define CIR_IRFIFOSTS_RX_FTA 0x20 221 #define CIR_IRFIFOSTS_RX_EMPTY 0x10 222 #define CIR_IRFIFOSTS_RX_FULL 0x08 223 #define CIR_IRFIFOSTS_TX_FTA 0x04 224 #define CIR_IRFIFOSTS_TX_EMPTY 0x02 225 #define CIR_IRFIFOSTS_TX_FULL 0x01 226 227 228 /* CIR WAKE UP Regs */ 229 #define CIR_WAKE_IRCON 0x00 230 #define CIR_WAKE_IRSTS 0x01 231 #define CIR_WAKE_IREN 0x02 232 #define CIR_WAKE_FIFO_CMP_DEEP 0x03 233 #define CIR_WAKE_FIFO_CMP_TOL 0x04 234 #define CIR_WAKE_FIFO_COUNT 0x05 235 #define CIR_WAKE_SLCH 0x06 236 #define CIR_WAKE_SLCL 0x07 237 #define CIR_WAKE_FIFOCON 0x08 238 #define CIR_WAKE_SRXFSTS 0x09 239 #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a 240 #define CIR_WAKE_WR_FIFO_DATA 0x0b 241 #define CIR_WAKE_RD_FIFO_ONLY 0x0c 242 #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d 243 #define CIR_WAKE_FIFO_IGNORE 0x0e 244 #define CIR_WAKE_IRFSM 0x0f 245 246 /* CIR WAKE UP IRCON settings */ 247 #define CIR_WAKE_IRCON_DEC_RST 0x80 248 #define CIR_WAKE_IRCON_MODE1 0x40 249 #define CIR_WAKE_IRCON_MODE0 0x20 250 #define CIR_WAKE_IRCON_RXEN 0x10 251 #define CIR_WAKE_IRCON_R 0x08 252 #define CIR_WAKE_IRCON_RXINV 0x04 253 254 /* FIXME/jarod: make this a runtime option */ 255 /* select a same sample period like cir register */ 256 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 257 258 /* CIR WAKE IRSTS Bits */ 259 #define CIR_WAKE_IRSTS_RDR 0x80 260 #define CIR_WAKE_IRSTS_RTR 0x40 261 #define CIR_WAKE_IRSTS_PE 0x20 262 #define CIR_WAKE_IRSTS_RFO 0x10 263 #define CIR_WAKE_IRSTS_GH 0x08 264 #define CIR_WAKE_IRSTS_IR_PENDING 0x01 265 266 /* CIR WAKE UP IREN Bits */ 267 #define CIR_WAKE_IREN_RDR 0x80 268 #define CIR_WAKE_IREN_RTR 0x40 269 #define CIR_WAKE_IREN_PE 0x20 270 #define CIR_WAKE_IREN_RFO 0x10 271 #define CIR_WAKE_IREN_GH 0x08 272 273 /* CIR WAKE FIFOCON settings */ 274 #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 275 276 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 277 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 278 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 279 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 280 281 /* FIXME: make this a runtime option */ 282 /* select WAKE UP RX trigger level as 67 */ 283 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 284 285 /* CIR WAKE SRXFSTS settings */ 286 #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 287 #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 288 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 289 #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 290 291 /* 292 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes 293 * the system comparing only 65 bytes (fails with this set to 67) 294 */ 295 #define CIR_WAKE_FIFO_CMP_BYTES 65 296 /* CIR Wake byte comparison tolerance */ 297 #define CIR_WAKE_CMP_TOLERANCE 5 298 299 /* 300 * Extended Function Enable Registers: 301 * Extended Function Index Register 302 * Extended Function Data Register 303 */ 304 #define CR_EFIR 0x2e 305 #define CR_EFDR 0x2f 306 307 /* Possible alternate EFER values, depends on how the chip is wired */ 308 #define CR_EFIR2 0x4e 309 #define CR_EFDR2 0x4f 310 311 /* Extended Function Mode enable/disable magic values */ 312 #define EFER_EFM_ENABLE 0x87 313 #define EFER_EFM_DISABLE 0xaa 314 315 /* Config regs we need to care about */ 316 #define CR_SOFTWARE_RESET 0x02 317 #define CR_LOGICAL_DEV_SEL 0x07 318 #define CR_CHIP_ID_HI 0x20 319 #define CR_CHIP_ID_LO 0x21 320 #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 321 #define CR_OUTPUT_PIN_SEL 0x27 322 #define CR_MULTIFUNC_PIN_SEL 0x2c 323 #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 324 /* next three regs valid for both the CIR and CIR_WAKE logical devices */ 325 #define CR_CIR_BASE_ADDR_HI 0x60 326 #define CR_CIR_BASE_ADDR_LO 0x61 327 #define CR_CIR_IRQ_RSRC 0x70 328 /* next three regs valid only for ACPI logical dev */ 329 #define CR_ACPI_CIR_WAKE 0xe0 330 #define CR_ACPI_IRQ_EVENTS 0xf6 331 #define CR_ACPI_IRQ_EVENTS2 0xf7 332 333 /* Logical devices that we need to care about */ 334 #define LOGICAL_DEV_LPT 0x01 335 #define LOGICAL_DEV_CIR 0x06 336 #define LOGICAL_DEV_ACPI 0x0a 337 #define LOGICAL_DEV_CIR_WAKE 0x0e 338 339 #define LOGICAL_DEV_DISABLE 0x00 340 #define LOGICAL_DEV_ENABLE 0x01 341 342 #define CIR_WAKE_ENABLE_BIT 0x08 343 #define PME_INTR_CIR_PASS_BIT 0x08 344 345 /* w83677hg CIR pin config */ 346 #define OUTPUT_PIN_SEL_MASK 0xbc 347 #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 348 #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 349 350 /* w83667hg CIR pin config */ 351 #define MULTIFUNC_PIN_SEL_MASK 0x1f 352 #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */ 353 #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */ 354 355 /* MCE CIR signal length, related on sample period */ 356 357 /* MCE CIR controller signal length: about 43ms 358 * 43ms / 50us (sample period) * 0.85 (inaccuracy) 359 */ 360 #define CONTROLLER_BUF_LEN_MIN 830 361 362 /* MCE CIR keyboard signal length: about 26ms 363 * 26ms / 50us (sample period) * 0.85 (inaccuracy) 364 */ 365 #define KEYBOARD_BUF_LEN_MAX 650 366 #define KEYBOARD_BUF_LEN_MIN 610 367 368 /* MCE CIR mouse signal length: about 24ms 369 * 24ms / 50us (sample period) * 0.85 (inaccuracy) 370 */ 371 #define MOUSE_BUF_LEN_MIN 565 372 373 #define CIR_SAMPLE_PERIOD 50 374 #define CIR_SAMPLE_LOW_INACCURACY 0.85 375 376 /* MAX silence time that driver will sent to lirc */ 377 #define MAX_SILENCE_TIME 60000 378 379 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 380 #define SAMPLE_PERIOD 100 381 382 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 383 #define SAMPLE_PERIOD 50 384 385 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 386 #define SAMPLE_PERIOD 25 387 388 #else 389 #define SAMPLE_PERIOD 1 390 #endif 391 392 /* as VISTA MCE definition, valid carrier value */ 393 #define MAX_CARRIER 60000 394 #define MIN_CARRIER 30000 395 396 /* max wakeup sequence length */ 397 #define WAKEUP_MAX_SIZE 65 398