1 /* 2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 3 * 4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 5 * Copyright (C) 2009 Nuvoton PS Team 6 * 7 * Special thanks to Nuvoton for providing hardware, spec sheets and 8 * sample code upon which portions of this driver are based. Indirect 9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 10 * modeled after. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 25 * USA 26 */ 27 28 #include <linux/spinlock.h> 29 #include <linux/ioctl.h> 30 31 /* platform driver name to register */ 32 #define NVT_DRIVER_NAME "nuvoton-cir" 33 34 /* debugging module parameter */ 35 static int debug; 36 37 38 #define nvt_dbg(text, ...) \ 39 if (debug) \ 40 printk(KERN_DEBUG \ 41 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 42 43 #define nvt_dbg_verbose(text, ...) \ 44 if (debug > 1) \ 45 printk(KERN_DEBUG \ 46 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 47 48 #define nvt_dbg_wake(text, ...) \ 49 if (debug > 2) \ 50 printk(KERN_DEBUG \ 51 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 52 53 54 /* 55 * Original lirc driver said min value of 76, and recommended value of 256 56 * for the buffer length, but then used 2048. Never mind that the size of the 57 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm 58 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes), 59 * and I don't have TX-capable hardware to test/debug on... 60 */ 61 #define TX_BUF_LEN 256 62 #define RX_BUF_LEN 32 63 64 #define SIO_ID_MASK 0xfff0 65 66 enum nvt_chip_ver { 67 NVT_UNKNOWN = 0, 68 NVT_W83667HG = 0xa510, 69 NVT_6775F = 0xb470, 70 NVT_6776F = 0xc330, 71 NVT_6779D = 0xc560, 72 NVT_INVALID = 0xffff, 73 }; 74 75 struct nvt_chip { 76 const char *name; 77 enum nvt_chip_ver chip_ver; 78 }; 79 80 struct nvt_dev { 81 struct rc_dev *rdev; 82 83 spinlock_t lock; 84 85 /* for rx */ 86 u8 buf[RX_BUF_LEN]; 87 unsigned int pkts; 88 89 struct { 90 u8 buf[TX_BUF_LEN]; 91 unsigned int buf_count; 92 unsigned int cur_buf_num; 93 wait_queue_head_t queue; 94 u8 tx_state; 95 } tx; 96 97 /* EFER Config register index/data pair */ 98 u32 cr_efir; 99 u32 cr_efdr; 100 101 /* hardware I/O settings */ 102 unsigned long cir_addr; 103 unsigned long cir_wake_addr; 104 int cir_irq; 105 106 enum nvt_chip_ver chip_ver; 107 /* hardware id */ 108 u8 chip_major; 109 u8 chip_minor; 110 111 /* hardware features */ 112 bool hw_tx_capable; 113 114 /* carrier period = 1 / frequency */ 115 u32 carrier; 116 }; 117 118 /* send states */ 119 #define ST_TX_NONE 0x0 120 #define ST_TX_REQUEST 0x2 121 #define ST_TX_REPLY 0x4 122 123 /* buffer packet constants */ 124 #define BUF_PULSE_BIT 0x80 125 #define BUF_LEN_MASK 0x7f 126 #define BUF_REPEAT_BYTE 0x70 127 #define BUF_REPEAT_MASK 0xf0 128 129 /* CIR settings */ 130 131 /* total length of CIR and CIR WAKE */ 132 #define CIR_IOREG_LENGTH 0x0f 133 134 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */ 135 #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD)) 136 137 /* CIR Regs */ 138 #define CIR_IRCON 0x00 139 #define CIR_IRSTS 0x01 140 #define CIR_IREN 0x02 141 #define CIR_RXFCONT 0x03 142 #define CIR_CP 0x04 143 #define CIR_CC 0x05 144 #define CIR_SLCH 0x06 145 #define CIR_SLCL 0x07 146 #define CIR_FIFOCON 0x08 147 #define CIR_IRFIFOSTS 0x09 148 #define CIR_SRXFIFO 0x0a 149 #define CIR_TXFCONT 0x0b 150 #define CIR_STXFIFO 0x0c 151 #define CIR_FCCH 0x0d 152 #define CIR_FCCL 0x0e 153 #define CIR_IRFSM 0x0f 154 155 /* CIR IRCON settings */ 156 #define CIR_IRCON_RECV 0x80 157 #define CIR_IRCON_WIREN 0x40 158 #define CIR_IRCON_TXEN 0x20 159 #define CIR_IRCON_RXEN 0x10 160 #define CIR_IRCON_WRXINV 0x08 161 #define CIR_IRCON_RXINV 0x04 162 163 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 164 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 165 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 166 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 167 168 /* FIXME: make this a runtime option */ 169 /* select sample period as 50us */ 170 #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 171 172 /* CIR IRSTS settings */ 173 #define CIR_IRSTS_RDR 0x80 174 #define CIR_IRSTS_RTR 0x40 175 #define CIR_IRSTS_PE 0x20 176 #define CIR_IRSTS_RFO 0x10 177 #define CIR_IRSTS_TE 0x08 178 #define CIR_IRSTS_TTR 0x04 179 #define CIR_IRSTS_TFU 0x02 180 #define CIR_IRSTS_GH 0x01 181 182 /* CIR IREN settings */ 183 #define CIR_IREN_RDR 0x80 184 #define CIR_IREN_RTR 0x40 185 #define CIR_IREN_PE 0x20 186 #define CIR_IREN_RFO 0x10 187 #define CIR_IREN_TE 0x08 188 #define CIR_IREN_TTR 0x04 189 #define CIR_IREN_TFU 0x02 190 #define CIR_IREN_GH 0x01 191 192 /* CIR FIFOCON settings */ 193 #define CIR_FIFOCON_TXFIFOCLR 0x80 194 195 #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 196 #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 197 #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 198 #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 199 200 /* FIXME: make this a runtime option */ 201 /* select TX trigger level as 16 */ 202 #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 203 204 #define CIR_FIFOCON_RXFIFOCLR 0x08 205 206 #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 207 #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 208 #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 209 #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 210 211 /* FIXME: make this a runtime option */ 212 /* select RX trigger level as 24 */ 213 #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 214 215 /* CIR IRFIFOSTS settings */ 216 #define CIR_IRFIFOSTS_IR_PENDING 0x80 217 #define CIR_IRFIFOSTS_RX_GS 0x40 218 #define CIR_IRFIFOSTS_RX_FTA 0x20 219 #define CIR_IRFIFOSTS_RX_EMPTY 0x10 220 #define CIR_IRFIFOSTS_RX_FULL 0x08 221 #define CIR_IRFIFOSTS_TX_FTA 0x04 222 #define CIR_IRFIFOSTS_TX_EMPTY 0x02 223 #define CIR_IRFIFOSTS_TX_FULL 0x01 224 225 226 /* CIR WAKE UP Regs */ 227 #define CIR_WAKE_IRCON 0x00 228 #define CIR_WAKE_IRSTS 0x01 229 #define CIR_WAKE_IREN 0x02 230 #define CIR_WAKE_FIFO_CMP_DEEP 0x03 231 #define CIR_WAKE_FIFO_CMP_TOL 0x04 232 #define CIR_WAKE_FIFO_COUNT 0x05 233 #define CIR_WAKE_SLCH 0x06 234 #define CIR_WAKE_SLCL 0x07 235 #define CIR_WAKE_FIFOCON 0x08 236 #define CIR_WAKE_SRXFSTS 0x09 237 #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a 238 #define CIR_WAKE_WR_FIFO_DATA 0x0b 239 #define CIR_WAKE_RD_FIFO_ONLY 0x0c 240 #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d 241 #define CIR_WAKE_FIFO_IGNORE 0x0e 242 #define CIR_WAKE_IRFSM 0x0f 243 244 /* CIR WAKE UP IRCON settings */ 245 #define CIR_WAKE_IRCON_DEC_RST 0x80 246 #define CIR_WAKE_IRCON_MODE1 0x40 247 #define CIR_WAKE_IRCON_MODE0 0x20 248 #define CIR_WAKE_IRCON_RXEN 0x10 249 #define CIR_WAKE_IRCON_R 0x08 250 #define CIR_WAKE_IRCON_RXINV 0x04 251 252 /* FIXME/jarod: make this a runtime option */ 253 /* select a same sample period like cir register */ 254 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 255 256 /* CIR WAKE IRSTS Bits */ 257 #define CIR_WAKE_IRSTS_RDR 0x80 258 #define CIR_WAKE_IRSTS_RTR 0x40 259 #define CIR_WAKE_IRSTS_PE 0x20 260 #define CIR_WAKE_IRSTS_RFO 0x10 261 #define CIR_WAKE_IRSTS_GH 0x08 262 #define CIR_WAKE_IRSTS_IR_PENDING 0x01 263 264 /* CIR WAKE UP IREN Bits */ 265 #define CIR_WAKE_IREN_RDR 0x80 266 #define CIR_WAKE_IREN_RTR 0x40 267 #define CIR_WAKE_IREN_PE 0x20 268 #define CIR_WAKE_IREN_RFO 0x10 269 #define CIR_WAKE_IREN_GH 0x08 270 271 /* CIR WAKE FIFOCON settings */ 272 #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 273 274 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 275 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 276 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 277 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 278 279 /* FIXME: make this a runtime option */ 280 /* select WAKE UP RX trigger level as 67 */ 281 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 282 283 /* CIR WAKE SRXFSTS settings */ 284 #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 285 #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 286 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 287 #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 288 289 /* 290 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes 291 * the system comparing only 65 bytes (fails with this set to 67) 292 */ 293 #define CIR_WAKE_FIFO_CMP_BYTES 65 294 /* CIR Wake byte comparison tolerance */ 295 #define CIR_WAKE_CMP_TOLERANCE 5 296 297 /* 298 * Extended Function Enable Registers: 299 * Extended Function Index Register 300 * Extended Function Data Register 301 */ 302 #define CR_EFIR 0x2e 303 #define CR_EFDR 0x2f 304 305 /* Possible alternate EFER values, depends on how the chip is wired */ 306 #define CR_EFIR2 0x4e 307 #define CR_EFDR2 0x4f 308 309 /* Extended Function Mode enable/disable magic values */ 310 #define EFER_EFM_ENABLE 0x87 311 #define EFER_EFM_DISABLE 0xaa 312 313 /* Config regs we need to care about */ 314 #define CR_SOFTWARE_RESET 0x02 315 #define CR_LOGICAL_DEV_SEL 0x07 316 #define CR_CHIP_ID_HI 0x20 317 #define CR_CHIP_ID_LO 0x21 318 #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 319 #define CR_OUTPUT_PIN_SEL 0x27 320 #define CR_MULTIFUNC_PIN_SEL 0x2c 321 #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 322 /* next three regs valid for both the CIR and CIR_WAKE logical devices */ 323 #define CR_CIR_BASE_ADDR_HI 0x60 324 #define CR_CIR_BASE_ADDR_LO 0x61 325 #define CR_CIR_IRQ_RSRC 0x70 326 /* next three regs valid only for ACPI logical dev */ 327 #define CR_ACPI_CIR_WAKE 0xe0 328 #define CR_ACPI_IRQ_EVENTS 0xf6 329 #define CR_ACPI_IRQ_EVENTS2 0xf7 330 331 /* Logical devices that we need to care about */ 332 #define LOGICAL_DEV_LPT 0x01 333 #define LOGICAL_DEV_CIR 0x06 334 #define LOGICAL_DEV_ACPI 0x0a 335 #define LOGICAL_DEV_CIR_WAKE 0x0e 336 337 #define LOGICAL_DEV_DISABLE 0x00 338 #define LOGICAL_DEV_ENABLE 0x01 339 340 #define CIR_WAKE_ENABLE_BIT 0x08 341 #define PME_INTR_CIR_PASS_BIT 0x08 342 343 /* w83677hg CIR pin config */ 344 #define OUTPUT_PIN_SEL_MASK 0xbc 345 #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 346 #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 347 348 /* w83667hg CIR pin config */ 349 #define MULTIFUNC_PIN_SEL_MASK 0x1f 350 #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */ 351 #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */ 352 353 /* MCE CIR signal length, related on sample period */ 354 355 /* MCE CIR controller signal length: about 43ms 356 * 43ms / 50us (sample period) * 0.85 (inaccuracy) 357 */ 358 #define CONTROLLER_BUF_LEN_MIN 830 359 360 /* MCE CIR keyboard signal length: about 26ms 361 * 26ms / 50us (sample period) * 0.85 (inaccuracy) 362 */ 363 #define KEYBOARD_BUF_LEN_MAX 650 364 #define KEYBOARD_BUF_LEN_MIN 610 365 366 /* MCE CIR mouse signal length: about 24ms 367 * 24ms / 50us (sample period) * 0.85 (inaccuracy) 368 */ 369 #define MOUSE_BUF_LEN_MIN 565 370 371 #define CIR_SAMPLE_PERIOD 50 372 #define CIR_SAMPLE_LOW_INACCURACY 0.85 373 374 /* MAX silence time that driver will sent to lirc */ 375 #define MAX_SILENCE_TIME 60000 376 377 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 378 #define SAMPLE_PERIOD 100 379 380 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 381 #define SAMPLE_PERIOD 50 382 383 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 384 #define SAMPLE_PERIOD 25 385 386 #else 387 #define SAMPLE_PERIOD 1 388 #endif 389 390 /* as VISTA MCE definition, valid carrier value */ 391 #define MAX_CARRIER 60000 392 #define MIN_CARRIER 30000 393 394 /* max wakeup sequence length */ 395 #define WAKEUP_MAX_SIZE 65 396