1 /* 2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 3 * 4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 5 * Copyright (C) 2009 Nuvoton PS Team 6 * 7 * Special thanks to Nuvoton for providing hardware, spec sheets and 8 * sample code upon which portions of this driver are based. Indirect 9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 10 * modeled after. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 */ 22 23 #include <linux/spinlock.h> 24 #include <linux/ioctl.h> 25 26 /* platform driver name to register */ 27 #define NVT_DRIVER_NAME "nuvoton-cir" 28 29 /* debugging module parameter */ 30 static int debug; 31 32 33 #define nvt_dbg(text, ...) \ 34 if (debug) \ 35 printk(KERN_DEBUG \ 36 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 37 38 #define nvt_dbg_verbose(text, ...) \ 39 if (debug > 1) \ 40 printk(KERN_DEBUG \ 41 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 42 43 #define nvt_dbg_wake(text, ...) \ 44 if (debug > 2) \ 45 printk(KERN_DEBUG \ 46 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 47 48 49 /* 50 * Original lirc driver said min value of 76, and recommended value of 256 51 * for the buffer length, but then used 2048. Never mind that the size of the 52 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm 53 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes), 54 * and I don't have TX-capable hardware to test/debug on... 55 */ 56 #define TX_BUF_LEN 256 57 #define RX_BUF_LEN 32 58 59 #define SIO_ID_MASK 0xfff0 60 61 enum nvt_chip_ver { 62 NVT_UNKNOWN = 0, 63 NVT_W83667HG = 0xa510, 64 NVT_6775F = 0xb470, 65 NVT_6776F = 0xc330, 66 NVT_6779D = 0xc560, 67 NVT_INVALID = 0xffff, 68 }; 69 70 struct nvt_chip { 71 const char *name; 72 enum nvt_chip_ver chip_ver; 73 }; 74 75 struct nvt_dev { 76 struct rc_dev *rdev; 77 78 spinlock_t lock; 79 80 /* for rx */ 81 u8 buf[RX_BUF_LEN]; 82 unsigned int pkts; 83 84 struct { 85 u8 buf[TX_BUF_LEN]; 86 unsigned int buf_count; 87 unsigned int cur_buf_num; 88 wait_queue_head_t queue; 89 u8 tx_state; 90 } tx; 91 92 /* EFER Config register index/data pair */ 93 u32 cr_efir; 94 u32 cr_efdr; 95 96 /* hardware I/O settings */ 97 unsigned long cir_addr; 98 unsigned long cir_wake_addr; 99 int cir_irq; 100 101 enum nvt_chip_ver chip_ver; 102 /* hardware id */ 103 u8 chip_major; 104 u8 chip_minor; 105 106 /* hardware features */ 107 bool hw_tx_capable; 108 109 /* carrier period = 1 / frequency */ 110 u32 carrier; 111 }; 112 113 /* send states */ 114 #define ST_TX_NONE 0x0 115 #define ST_TX_REQUEST 0x2 116 #define ST_TX_REPLY 0x4 117 118 /* buffer packet constants */ 119 #define BUF_PULSE_BIT 0x80 120 #define BUF_LEN_MASK 0x7f 121 #define BUF_REPEAT_BYTE 0x70 122 #define BUF_REPEAT_MASK 0xf0 123 124 /* CIR settings */ 125 126 /* total length of CIR and CIR WAKE */ 127 #define CIR_IOREG_LENGTH 0x0f 128 129 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */ 130 #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD)) 131 132 /* CIR Regs */ 133 #define CIR_IRCON 0x00 134 #define CIR_IRSTS 0x01 135 #define CIR_IREN 0x02 136 #define CIR_RXFCONT 0x03 137 #define CIR_CP 0x04 138 #define CIR_CC 0x05 139 #define CIR_SLCH 0x06 140 #define CIR_SLCL 0x07 141 #define CIR_FIFOCON 0x08 142 #define CIR_IRFIFOSTS 0x09 143 #define CIR_SRXFIFO 0x0a 144 #define CIR_TXFCONT 0x0b 145 #define CIR_STXFIFO 0x0c 146 #define CIR_FCCH 0x0d 147 #define CIR_FCCL 0x0e 148 #define CIR_IRFSM 0x0f 149 150 /* CIR IRCON settings */ 151 #define CIR_IRCON_RECV 0x80 152 #define CIR_IRCON_WIREN 0x40 153 #define CIR_IRCON_TXEN 0x20 154 #define CIR_IRCON_RXEN 0x10 155 #define CIR_IRCON_WRXINV 0x08 156 #define CIR_IRCON_RXINV 0x04 157 158 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 159 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 160 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 161 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 162 163 /* FIXME: make this a runtime option */ 164 /* select sample period as 50us */ 165 #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 166 167 /* CIR IRSTS settings */ 168 #define CIR_IRSTS_RDR 0x80 169 #define CIR_IRSTS_RTR 0x40 170 #define CIR_IRSTS_PE 0x20 171 #define CIR_IRSTS_RFO 0x10 172 #define CIR_IRSTS_TE 0x08 173 #define CIR_IRSTS_TTR 0x04 174 #define CIR_IRSTS_TFU 0x02 175 #define CIR_IRSTS_GH 0x01 176 177 /* CIR IREN settings */ 178 #define CIR_IREN_RDR 0x80 179 #define CIR_IREN_RTR 0x40 180 #define CIR_IREN_PE 0x20 181 #define CIR_IREN_RFO 0x10 182 #define CIR_IREN_TE 0x08 183 #define CIR_IREN_TTR 0x04 184 #define CIR_IREN_TFU 0x02 185 #define CIR_IREN_GH 0x01 186 187 /* CIR FIFOCON settings */ 188 #define CIR_FIFOCON_TXFIFOCLR 0x80 189 190 #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 191 #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 192 #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 193 #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 194 195 /* FIXME: make this a runtime option */ 196 /* select TX trigger level as 16 */ 197 #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 198 199 #define CIR_FIFOCON_RXFIFOCLR 0x08 200 201 #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 202 #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 203 #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 204 #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 205 206 /* FIXME: make this a runtime option */ 207 /* select RX trigger level as 24 */ 208 #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 209 210 /* CIR IRFIFOSTS settings */ 211 #define CIR_IRFIFOSTS_IR_PENDING 0x80 212 #define CIR_IRFIFOSTS_RX_GS 0x40 213 #define CIR_IRFIFOSTS_RX_FTA 0x20 214 #define CIR_IRFIFOSTS_RX_EMPTY 0x10 215 #define CIR_IRFIFOSTS_RX_FULL 0x08 216 #define CIR_IRFIFOSTS_TX_FTA 0x04 217 #define CIR_IRFIFOSTS_TX_EMPTY 0x02 218 #define CIR_IRFIFOSTS_TX_FULL 0x01 219 220 221 /* CIR WAKE UP Regs */ 222 #define CIR_WAKE_IRCON 0x00 223 #define CIR_WAKE_IRSTS 0x01 224 #define CIR_WAKE_IREN 0x02 225 #define CIR_WAKE_FIFO_CMP_DEEP 0x03 226 #define CIR_WAKE_FIFO_CMP_TOL 0x04 227 #define CIR_WAKE_FIFO_COUNT 0x05 228 #define CIR_WAKE_SLCH 0x06 229 #define CIR_WAKE_SLCL 0x07 230 #define CIR_WAKE_FIFOCON 0x08 231 #define CIR_WAKE_SRXFSTS 0x09 232 #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a 233 #define CIR_WAKE_WR_FIFO_DATA 0x0b 234 #define CIR_WAKE_RD_FIFO_ONLY 0x0c 235 #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d 236 #define CIR_WAKE_FIFO_IGNORE 0x0e 237 #define CIR_WAKE_IRFSM 0x0f 238 239 /* CIR WAKE UP IRCON settings */ 240 #define CIR_WAKE_IRCON_DEC_RST 0x80 241 #define CIR_WAKE_IRCON_MODE1 0x40 242 #define CIR_WAKE_IRCON_MODE0 0x20 243 #define CIR_WAKE_IRCON_RXEN 0x10 244 #define CIR_WAKE_IRCON_R 0x08 245 #define CIR_WAKE_IRCON_RXINV 0x04 246 247 /* FIXME/jarod: make this a runtime option */ 248 /* select a same sample period like cir register */ 249 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 250 251 /* CIR WAKE IRSTS Bits */ 252 #define CIR_WAKE_IRSTS_RDR 0x80 253 #define CIR_WAKE_IRSTS_RTR 0x40 254 #define CIR_WAKE_IRSTS_PE 0x20 255 #define CIR_WAKE_IRSTS_RFO 0x10 256 #define CIR_WAKE_IRSTS_GH 0x08 257 #define CIR_WAKE_IRSTS_IR_PENDING 0x01 258 259 /* CIR WAKE UP IREN Bits */ 260 #define CIR_WAKE_IREN_RDR 0x80 261 #define CIR_WAKE_IREN_RTR 0x40 262 #define CIR_WAKE_IREN_PE 0x20 263 #define CIR_WAKE_IREN_RFO 0x10 264 #define CIR_WAKE_IREN_GH 0x08 265 266 /* CIR WAKE FIFOCON settings */ 267 #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 268 269 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 270 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 271 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 272 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 273 274 /* FIXME: make this a runtime option */ 275 /* select WAKE UP RX trigger level as 67 */ 276 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 277 278 /* CIR WAKE SRXFSTS settings */ 279 #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 280 #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 281 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 282 #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 283 284 /* 285 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes 286 * the system comparing only 65 bytes (fails with this set to 67) 287 */ 288 #define CIR_WAKE_FIFO_CMP_BYTES 65 289 /* CIR Wake byte comparison tolerance */ 290 #define CIR_WAKE_CMP_TOLERANCE 5 291 292 /* 293 * Extended Function Enable Registers: 294 * Extended Function Index Register 295 * Extended Function Data Register 296 */ 297 #define CR_EFIR 0x2e 298 #define CR_EFDR 0x2f 299 300 /* Possible alternate EFER values, depends on how the chip is wired */ 301 #define CR_EFIR2 0x4e 302 #define CR_EFDR2 0x4f 303 304 /* Extended Function Mode enable/disable magic values */ 305 #define EFER_EFM_ENABLE 0x87 306 #define EFER_EFM_DISABLE 0xaa 307 308 /* Config regs we need to care about */ 309 #define CR_SOFTWARE_RESET 0x02 310 #define CR_LOGICAL_DEV_SEL 0x07 311 #define CR_CHIP_ID_HI 0x20 312 #define CR_CHIP_ID_LO 0x21 313 #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 314 #define CR_OUTPUT_PIN_SEL 0x27 315 #define CR_MULTIFUNC_PIN_SEL 0x2c 316 #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 317 /* next three regs valid for both the CIR and CIR_WAKE logical devices */ 318 #define CR_CIR_BASE_ADDR_HI 0x60 319 #define CR_CIR_BASE_ADDR_LO 0x61 320 #define CR_CIR_IRQ_RSRC 0x70 321 /* next three regs valid only for ACPI logical dev */ 322 #define CR_ACPI_CIR_WAKE 0xe0 323 #define CR_ACPI_IRQ_EVENTS 0xf6 324 #define CR_ACPI_IRQ_EVENTS2 0xf7 325 326 /* Logical devices that we need to care about */ 327 #define LOGICAL_DEV_LPT 0x01 328 #define LOGICAL_DEV_CIR 0x06 329 #define LOGICAL_DEV_ACPI 0x0a 330 #define LOGICAL_DEV_CIR_WAKE 0x0e 331 332 #define LOGICAL_DEV_DISABLE 0x00 333 #define LOGICAL_DEV_ENABLE 0x01 334 335 #define CIR_WAKE_ENABLE_BIT 0x08 336 #define PME_INTR_CIR_PASS_BIT 0x08 337 338 /* w83677hg CIR pin config */ 339 #define OUTPUT_PIN_SEL_MASK 0xbc 340 #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 341 #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 342 343 /* w83667hg CIR pin config */ 344 #define MULTIFUNC_PIN_SEL_MASK 0x1f 345 #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */ 346 #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */ 347 348 /* MCE CIR signal length, related on sample period */ 349 350 /* MCE CIR controller signal length: about 43ms 351 * 43ms / 50us (sample period) * 0.85 (inaccuracy) 352 */ 353 #define CONTROLLER_BUF_LEN_MIN 830 354 355 /* MCE CIR keyboard signal length: about 26ms 356 * 26ms / 50us (sample period) * 0.85 (inaccuracy) 357 */ 358 #define KEYBOARD_BUF_LEN_MAX 650 359 #define KEYBOARD_BUF_LEN_MIN 610 360 361 /* MCE CIR mouse signal length: about 24ms 362 * 24ms / 50us (sample period) * 0.85 (inaccuracy) 363 */ 364 #define MOUSE_BUF_LEN_MIN 565 365 366 #define CIR_SAMPLE_PERIOD 50 367 #define CIR_SAMPLE_LOW_INACCURACY 0.85 368 369 /* MAX silence time that driver will sent to lirc */ 370 #define MAX_SILENCE_TIME 60000 371 372 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 373 #define SAMPLE_PERIOD 100 374 375 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 376 #define SAMPLE_PERIOD 50 377 378 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 379 #define SAMPLE_PERIOD 25 380 381 #else 382 #define SAMPLE_PERIOD 1 383 #endif 384 385 /* as VISTA MCE definition, valid carrier value */ 386 #define MAX_CARRIER 60000 387 #define MIN_CARRIER 30000 388 389 /* max wakeup sequence length */ 390 #define WAKEUP_MAX_SIZE 65 391