1 /* 2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 3 * 4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 5 * Copyright (C) 2009 Nuvoton PS Team 6 * 7 * Special thanks to Nuvoton for providing hardware, spec sheets and 8 * sample code upon which portions of this driver are based. Indirect 9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 10 * modeled after. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 25 * USA 26 */ 27 28 #include <linux/spinlock.h> 29 #include <linux/ioctl.h> 30 31 /* platform driver name to register */ 32 #define NVT_DRIVER_NAME "nuvoton-cir" 33 34 /* debugging module parameter */ 35 static int debug; 36 37 38 #define nvt_pr(level, text, ...) \ 39 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) 40 41 #define nvt_dbg(text, ...) \ 42 if (debug) \ 43 printk(KERN_DEBUG \ 44 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 45 46 #define nvt_dbg_verbose(text, ...) \ 47 if (debug > 1) \ 48 printk(KERN_DEBUG \ 49 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 50 51 #define nvt_dbg_wake(text, ...) \ 52 if (debug > 2) \ 53 printk(KERN_DEBUG \ 54 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 55 56 57 /* 58 * Original lirc driver said min value of 76, and recommended value of 256 59 * for the buffer length, but then used 2048. Never mind that the size of the 60 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm 61 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes), 62 * and I don't have TX-capable hardware to test/debug on... 63 */ 64 #define TX_BUF_LEN 256 65 #define RX_BUF_LEN 32 66 67 struct nvt_dev { 68 struct pnp_dev *pdev; 69 struct rc_dev *rdev; 70 struct ir_raw_event rawir; 71 72 spinlock_t nvt_lock; 73 bool in_use; 74 75 /* for rx */ 76 u8 buf[RX_BUF_LEN]; 77 unsigned int pkts; 78 79 struct { 80 spinlock_t lock; 81 u8 buf[TX_BUF_LEN]; 82 unsigned int buf_count; 83 unsigned int cur_buf_num; 84 wait_queue_head_t queue; 85 u8 tx_state; 86 } tx; 87 88 /* EFER Config register index/data pair */ 89 u8 cr_efir; 90 u8 cr_efdr; 91 92 /* hardware I/O settings */ 93 unsigned long cir_addr; 94 unsigned long cir_wake_addr; 95 int cir_irq; 96 int cir_wake_irq; 97 98 /* hardware id */ 99 u8 chip_major; 100 u8 chip_minor; 101 102 /* hardware features */ 103 bool hw_learning_capable; 104 bool hw_tx_capable; 105 106 /* rx settings */ 107 bool learning_enabled; 108 bool carrier_detect_enabled; 109 110 /* track cir wake state */ 111 u8 wake_state; 112 /* for study */ 113 u8 study_state; 114 /* carrier period = 1 / frequency */ 115 u32 carrier; 116 }; 117 118 /* study states */ 119 #define ST_STUDY_NONE 0x0 120 #define ST_STUDY_START 0x1 121 #define ST_STUDY_CARRIER 0x2 122 #define ST_STUDY_ALL_RECV 0x4 123 124 /* wake states */ 125 #define ST_WAKE_NONE 0x0 126 #define ST_WAKE_START 0x1 127 #define ST_WAKE_FINISH 0x2 128 129 /* receive states */ 130 #define ST_RX_WAIT_7F 0x1 131 #define ST_RX_WAIT_HEAD 0x2 132 #define ST_RX_WAIT_SILENT_END 0x4 133 134 /* send states */ 135 #define ST_TX_NONE 0x0 136 #define ST_TX_REQUEST 0x2 137 #define ST_TX_REPLY 0x4 138 139 /* buffer packet constants */ 140 #define BUF_PULSE_BIT 0x80 141 #define BUF_LEN_MASK 0x7f 142 #define BUF_REPEAT_BYTE 0x70 143 #define BUF_REPEAT_MASK 0xf0 144 145 /* CIR settings */ 146 147 /* total length of CIR and CIR WAKE */ 148 #define CIR_IOREG_LENGTH 0x0f 149 150 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */ 151 #define CIR_RX_LIMIT_COUNT 0x7d0 152 153 /* CIR Regs */ 154 #define CIR_IRCON 0x00 155 #define CIR_IRSTS 0x01 156 #define CIR_IREN 0x02 157 #define CIR_RXFCONT 0x03 158 #define CIR_CP 0x04 159 #define CIR_CC 0x05 160 #define CIR_SLCH 0x06 161 #define CIR_SLCL 0x07 162 #define CIR_FIFOCON 0x08 163 #define CIR_IRFIFOSTS 0x09 164 #define CIR_SRXFIFO 0x0a 165 #define CIR_TXFCONT 0x0b 166 #define CIR_STXFIFO 0x0c 167 #define CIR_FCCH 0x0d 168 #define CIR_FCCL 0x0e 169 #define CIR_IRFSM 0x0f 170 171 /* CIR IRCON settings */ 172 #define CIR_IRCON_RECV 0x80 173 #define CIR_IRCON_WIREN 0x40 174 #define CIR_IRCON_TXEN 0x20 175 #define CIR_IRCON_RXEN 0x10 176 #define CIR_IRCON_WRXINV 0x08 177 #define CIR_IRCON_RXINV 0x04 178 179 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 180 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 181 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 182 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 183 184 /* FIXME: make this a runtime option */ 185 /* select sample period as 50us */ 186 #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 187 188 /* CIR IRSTS settings */ 189 #define CIR_IRSTS_RDR 0x80 190 #define CIR_IRSTS_RTR 0x40 191 #define CIR_IRSTS_PE 0x20 192 #define CIR_IRSTS_RFO 0x10 193 #define CIR_IRSTS_TE 0x08 194 #define CIR_IRSTS_TTR 0x04 195 #define CIR_IRSTS_TFU 0x02 196 #define CIR_IRSTS_GH 0x01 197 198 /* CIR IREN settings */ 199 #define CIR_IREN_RDR 0x80 200 #define CIR_IREN_RTR 0x40 201 #define CIR_IREN_PE 0x20 202 #define CIR_IREN_RFO 0x10 203 #define CIR_IREN_TE 0x08 204 #define CIR_IREN_TTR 0x04 205 #define CIR_IREN_TFU 0x02 206 #define CIR_IREN_GH 0x01 207 208 /* CIR FIFOCON settings */ 209 #define CIR_FIFOCON_TXFIFOCLR 0x80 210 211 #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 212 #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 213 #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 214 #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 215 216 /* FIXME: make this a runtime option */ 217 /* select TX trigger level as 16 */ 218 #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 219 220 #define CIR_FIFOCON_RXFIFOCLR 0x08 221 222 #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 223 #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 224 #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 225 #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 226 227 /* FIXME: make this a runtime option */ 228 /* select RX trigger level as 24 */ 229 #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 230 231 /* CIR IRFIFOSTS settings */ 232 #define CIR_IRFIFOSTS_IR_PENDING 0x80 233 #define CIR_IRFIFOSTS_RX_GS 0x40 234 #define CIR_IRFIFOSTS_RX_FTA 0x20 235 #define CIR_IRFIFOSTS_RX_EMPTY 0x10 236 #define CIR_IRFIFOSTS_RX_FULL 0x08 237 #define CIR_IRFIFOSTS_TX_FTA 0x04 238 #define CIR_IRFIFOSTS_TX_EMPTY 0x02 239 #define CIR_IRFIFOSTS_TX_FULL 0x01 240 241 242 /* CIR WAKE UP Regs */ 243 #define CIR_WAKE_IRCON 0x00 244 #define CIR_WAKE_IRSTS 0x01 245 #define CIR_WAKE_IREN 0x02 246 #define CIR_WAKE_FIFO_CMP_DEEP 0x03 247 #define CIR_WAKE_FIFO_CMP_TOL 0x04 248 #define CIR_WAKE_FIFO_COUNT 0x05 249 #define CIR_WAKE_SLCH 0x06 250 #define CIR_WAKE_SLCL 0x07 251 #define CIR_WAKE_FIFOCON 0x08 252 #define CIR_WAKE_SRXFSTS 0x09 253 #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a 254 #define CIR_WAKE_WR_FIFO_DATA 0x0b 255 #define CIR_WAKE_RD_FIFO_ONLY 0x0c 256 #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d 257 #define CIR_WAKE_FIFO_IGNORE 0x0e 258 #define CIR_WAKE_IRFSM 0x0f 259 260 /* CIR WAKE UP IRCON settings */ 261 #define CIR_WAKE_IRCON_DEC_RST 0x80 262 #define CIR_WAKE_IRCON_MODE1 0x40 263 #define CIR_WAKE_IRCON_MODE0 0x20 264 #define CIR_WAKE_IRCON_RXEN 0x10 265 #define CIR_WAKE_IRCON_R 0x08 266 #define CIR_WAKE_IRCON_RXINV 0x04 267 268 /* FIXME/jarod: make this a runtime option */ 269 /* select a same sample period like cir register */ 270 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 271 272 /* CIR WAKE IRSTS Bits */ 273 #define CIR_WAKE_IRSTS_RDR 0x80 274 #define CIR_WAKE_IRSTS_RTR 0x40 275 #define CIR_WAKE_IRSTS_PE 0x20 276 #define CIR_WAKE_IRSTS_RFO 0x10 277 #define CIR_WAKE_IRSTS_GH 0x08 278 #define CIR_WAKE_IRSTS_IR_PENDING 0x01 279 280 /* CIR WAKE UP IREN Bits */ 281 #define CIR_WAKE_IREN_RDR 0x80 282 #define CIR_WAKE_IREN_RTR 0x40 283 #define CIR_WAKE_IREN_PE 0x20 284 #define CIR_WAKE_IREN_RFO 0x10 285 #define CIR_WAKE_IREN_TE 0x08 286 #define CIR_WAKE_IREN_TTR 0x04 287 #define CIR_WAKE_IREN_TFU 0x02 288 #define CIR_WAKE_IREN_GH 0x01 289 290 /* CIR WAKE FIFOCON settings */ 291 #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 292 293 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 294 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 295 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 296 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 297 298 /* FIXME: make this a runtime option */ 299 /* select WAKE UP RX trigger level as 67 */ 300 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 301 302 /* CIR WAKE SRXFSTS settings */ 303 #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 304 #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 305 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 306 #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 307 308 /* 309 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes 310 * the system comparing only 65 bytes (fails with this set to 67) 311 */ 312 #define CIR_WAKE_FIFO_CMP_BYTES 65 313 /* CIR Wake byte comparison tolerance */ 314 #define CIR_WAKE_CMP_TOLERANCE 5 315 316 /* 317 * Extended Function Enable Registers: 318 * Extended Function Index Register 319 * Extended Function Data Register 320 */ 321 #define CR_EFIR 0x2e 322 #define CR_EFDR 0x2f 323 324 /* Possible alternate EFER values, depends on how the chip is wired */ 325 #define CR_EFIR2 0x4e 326 #define CR_EFDR2 0x4f 327 328 /* Extended Function Mode enable/disable magic values */ 329 #define EFER_EFM_ENABLE 0x87 330 #define EFER_EFM_DISABLE 0xaa 331 332 /* Chip IDs found in CR_CHIP_ID_{HI,LO} */ 333 #define CHIP_ID_HIGH 0xb4 334 #define CHIP_ID_LOW 0x72 335 #define CHIP_ID_LOW2 0x73 336 337 /* Config regs we need to care about */ 338 #define CR_SOFTWARE_RESET 0x02 339 #define CR_LOGICAL_DEV_SEL 0x07 340 #define CR_CHIP_ID_HI 0x20 341 #define CR_CHIP_ID_LO 0x21 342 #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 343 #define CR_OUTPUT_PIN_SEL 0x27 344 #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 345 /* next three regs valid for both the CIR and CIR_WAKE logical devices */ 346 #define CR_CIR_BASE_ADDR_HI 0x60 347 #define CR_CIR_BASE_ADDR_LO 0x61 348 #define CR_CIR_IRQ_RSRC 0x70 349 /* next three regs valid only for ACPI logical dev */ 350 #define CR_ACPI_CIR_WAKE 0xe0 351 #define CR_ACPI_IRQ_EVENTS 0xf6 352 #define CR_ACPI_IRQ_EVENTS2 0xf7 353 354 /* Logical devices that we need to care about */ 355 #define LOGICAL_DEV_LPT 0x01 356 #define LOGICAL_DEV_CIR 0x06 357 #define LOGICAL_DEV_ACPI 0x0a 358 #define LOGICAL_DEV_CIR_WAKE 0x0e 359 360 #define LOGICAL_DEV_DISABLE 0x00 361 #define LOGICAL_DEV_ENABLE 0x01 362 363 #define CIR_WAKE_ENABLE_BIT 0x08 364 #define CIR_INTR_MOUSE_IRQ_BIT 0x80 365 #define PME_INTR_CIR_PASS_BIT 0x08 366 367 #define OUTPUT_PIN_SEL_MASK 0xbc 368 #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 369 #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 370 371 /* MCE CIR signal length, related on sample period */ 372 373 /* MCE CIR controller signal length: about 43ms 374 * 43ms / 50us (sample period) * 0.85 (inaccuracy) 375 */ 376 #define CONTROLLER_BUF_LEN_MIN 830 377 378 /* MCE CIR keyboard signal length: about 26ms 379 * 26ms / 50us (sample period) * 0.85 (inaccuracy) 380 */ 381 #define KEYBOARD_BUF_LEN_MAX 650 382 #define KEYBOARD_BUF_LEN_MIN 610 383 384 /* MCE CIR mouse signal length: about 24ms 385 * 24ms / 50us (sample period) * 0.85 (inaccuracy) 386 */ 387 #define MOUSE_BUF_LEN_MIN 565 388 389 #define CIR_SAMPLE_PERIOD 50 390 #define CIR_SAMPLE_LOW_INACCURACY 0.85 391 392 /* MAX silence time that driver will sent to lirc */ 393 #define MAX_SILENCE_TIME 60000 394 395 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 396 #define SAMPLE_PERIOD 100 397 398 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 399 #define SAMPLE_PERIOD 50 400 401 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 402 #define SAMPLE_PERIOD 25 403 404 #else 405 #define SAMPLE_PERIOD 1 406 #endif 407 408 /* as VISTA MCE definition, valid carrier value */ 409 #define MAX_CARRIER 60000 410 #define MIN_CARRIER 30000 411