132cf86f6SMauro Carvalho Chehab /* 232cf86f6SMauro Carvalho Chehab * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 332cf86f6SMauro Carvalho Chehab * 432cf86f6SMauro Carvalho Chehab * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 532cf86f6SMauro Carvalho Chehab * Copyright (C) 2009 Nuvoton PS Team 632cf86f6SMauro Carvalho Chehab * 732cf86f6SMauro Carvalho Chehab * Special thanks to Nuvoton for providing hardware, spec sheets and 832cf86f6SMauro Carvalho Chehab * sample code upon which portions of this driver are based. Indirect 932cf86f6SMauro Carvalho Chehab * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 1032cf86f6SMauro Carvalho Chehab * modeled after. 1132cf86f6SMauro Carvalho Chehab * 1232cf86f6SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or 1332cf86f6SMauro Carvalho Chehab * modify it under the terms of the GNU General Public License as 1432cf86f6SMauro Carvalho Chehab * published by the Free Software Foundation; either version 2 of the 1532cf86f6SMauro Carvalho Chehab * License, or (at your option) any later version. 1632cf86f6SMauro Carvalho Chehab * 1732cf86f6SMauro Carvalho Chehab * This program is distributed in the hope that it will be useful, but 1832cf86f6SMauro Carvalho Chehab * WITHOUT ANY WARRANTY; without even the implied warranty of 1932cf86f6SMauro Carvalho Chehab * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 2032cf86f6SMauro Carvalho Chehab * General Public License for more details. 2132cf86f6SMauro Carvalho Chehab * 2232cf86f6SMauro Carvalho Chehab * You should have received a copy of the GNU General Public License 2332cf86f6SMauro Carvalho Chehab * along with this program; if not, write to the Free Software 2432cf86f6SMauro Carvalho Chehab * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 2532cf86f6SMauro Carvalho Chehab * USA 2632cf86f6SMauro Carvalho Chehab */ 2732cf86f6SMauro Carvalho Chehab 2832cf86f6SMauro Carvalho Chehab #include <linux/spinlock.h> 2932cf86f6SMauro Carvalho Chehab #include <linux/ioctl.h> 3032cf86f6SMauro Carvalho Chehab 3132cf86f6SMauro Carvalho Chehab /* platform driver name to register */ 3232cf86f6SMauro Carvalho Chehab #define NVT_DRIVER_NAME "nuvoton-cir" 3332cf86f6SMauro Carvalho Chehab 3432cf86f6SMauro Carvalho Chehab /* debugging module parameter */ 3532cf86f6SMauro Carvalho Chehab static int debug; 3632cf86f6SMauro Carvalho Chehab 3732cf86f6SMauro Carvalho Chehab 3832cf86f6SMauro Carvalho Chehab #define nvt_pr(level, text, ...) \ 3932cf86f6SMauro Carvalho Chehab printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) 4032cf86f6SMauro Carvalho Chehab 4132cf86f6SMauro Carvalho Chehab #define nvt_dbg(text, ...) \ 4232cf86f6SMauro Carvalho Chehab if (debug) \ 4332cf86f6SMauro Carvalho Chehab printk(KERN_DEBUG \ 4432cf86f6SMauro Carvalho Chehab KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 4532cf86f6SMauro Carvalho Chehab 4632cf86f6SMauro Carvalho Chehab #define nvt_dbg_verbose(text, ...) \ 4732cf86f6SMauro Carvalho Chehab if (debug > 1) \ 4832cf86f6SMauro Carvalho Chehab printk(KERN_DEBUG \ 4932cf86f6SMauro Carvalho Chehab KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 5032cf86f6SMauro Carvalho Chehab 5132cf86f6SMauro Carvalho Chehab #define nvt_dbg_wake(text, ...) \ 5232cf86f6SMauro Carvalho Chehab if (debug > 2) \ 5332cf86f6SMauro Carvalho Chehab printk(KERN_DEBUG \ 5432cf86f6SMauro Carvalho Chehab KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 5532cf86f6SMauro Carvalho Chehab 5632cf86f6SMauro Carvalho Chehab 5732cf86f6SMauro Carvalho Chehab /* 5832cf86f6SMauro Carvalho Chehab * Original lirc driver said min value of 76, and recommended value of 256 5932cf86f6SMauro Carvalho Chehab * for the buffer length, but then used 2048. Never mind that the size of the 6032cf86f6SMauro Carvalho Chehab * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm 6132cf86f6SMauro Carvalho Chehab * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes), 6232cf86f6SMauro Carvalho Chehab * and I don't have TX-capable hardware to test/debug on... 6332cf86f6SMauro Carvalho Chehab */ 6432cf86f6SMauro Carvalho Chehab #define TX_BUF_LEN 256 6532cf86f6SMauro Carvalho Chehab #define RX_BUF_LEN 32 6632cf86f6SMauro Carvalho Chehab 67b5cf725cSHeiner Kallweit #define SIO_ID_MASK 0xfff0 68b5cf725cSHeiner Kallweit 69b5cf725cSHeiner Kallweit enum nvt_chip_ver { 70b5cf725cSHeiner Kallweit NVT_UNKNOWN = 0, 71b5cf725cSHeiner Kallweit NVT_W83667HG = 0xa510, 72b5cf725cSHeiner Kallweit NVT_6775F = 0xb470, 73b5cf725cSHeiner Kallweit NVT_6776F = 0xc330 74b5cf725cSHeiner Kallweit }; 75b5cf725cSHeiner Kallweit 76b5cf725cSHeiner Kallweit struct nvt_chip { 77b5cf725cSHeiner Kallweit const char *name; 78b5cf725cSHeiner Kallweit enum nvt_chip_ver chip_ver; 79b5cf725cSHeiner Kallweit }; 80b5cf725cSHeiner Kallweit 8132cf86f6SMauro Carvalho Chehab struct nvt_dev { 8232cf86f6SMauro Carvalho Chehab struct pnp_dev *pdev; 83d8b4b582SDavid Härdeman struct rc_dev *rdev; 8432cf86f6SMauro Carvalho Chehab 8532cf86f6SMauro Carvalho Chehab spinlock_t nvt_lock; 8632cf86f6SMauro Carvalho Chehab 8732cf86f6SMauro Carvalho Chehab /* for rx */ 8832cf86f6SMauro Carvalho Chehab u8 buf[RX_BUF_LEN]; 8932cf86f6SMauro Carvalho Chehab unsigned int pkts; 9032cf86f6SMauro Carvalho Chehab 9132cf86f6SMauro Carvalho Chehab struct { 9232cf86f6SMauro Carvalho Chehab spinlock_t lock; 9332cf86f6SMauro Carvalho Chehab u8 buf[TX_BUF_LEN]; 9432cf86f6SMauro Carvalho Chehab unsigned int buf_count; 9532cf86f6SMauro Carvalho Chehab unsigned int cur_buf_num; 9632cf86f6SMauro Carvalho Chehab wait_queue_head_t queue; 9732cf86f6SMauro Carvalho Chehab u8 tx_state; 9832cf86f6SMauro Carvalho Chehab } tx; 9932cf86f6SMauro Carvalho Chehab 10032cf86f6SMauro Carvalho Chehab /* EFER Config register index/data pair */ 101221cefa4SMauro Carvalho Chehab u32 cr_efir; 102221cefa4SMauro Carvalho Chehab u32 cr_efdr; 10332cf86f6SMauro Carvalho Chehab 10432cf86f6SMauro Carvalho Chehab /* hardware I/O settings */ 10532cf86f6SMauro Carvalho Chehab unsigned long cir_addr; 10632cf86f6SMauro Carvalho Chehab unsigned long cir_wake_addr; 10732cf86f6SMauro Carvalho Chehab int cir_irq; 10832cf86f6SMauro Carvalho Chehab int cir_wake_irq; 10932cf86f6SMauro Carvalho Chehab 110b5cf725cSHeiner Kallweit enum nvt_chip_ver chip_ver; 11132cf86f6SMauro Carvalho Chehab /* hardware id */ 11232cf86f6SMauro Carvalho Chehab u8 chip_major; 11332cf86f6SMauro Carvalho Chehab u8 chip_minor; 11432cf86f6SMauro Carvalho Chehab 11532cf86f6SMauro Carvalho Chehab /* hardware features */ 11632cf86f6SMauro Carvalho Chehab bool hw_learning_capable; 11732cf86f6SMauro Carvalho Chehab bool hw_tx_capable; 11832cf86f6SMauro Carvalho Chehab 11932cf86f6SMauro Carvalho Chehab /* rx settings */ 12032cf86f6SMauro Carvalho Chehab bool learning_enabled; 12132cf86f6SMauro Carvalho Chehab 12232cf86f6SMauro Carvalho Chehab /* track cir wake state */ 12332cf86f6SMauro Carvalho Chehab u8 wake_state; 12432cf86f6SMauro Carvalho Chehab /* for study */ 12532cf86f6SMauro Carvalho Chehab u8 study_state; 12632cf86f6SMauro Carvalho Chehab /* carrier period = 1 / frequency */ 12732cf86f6SMauro Carvalho Chehab u32 carrier; 12832cf86f6SMauro Carvalho Chehab }; 12932cf86f6SMauro Carvalho Chehab 13032cf86f6SMauro Carvalho Chehab /* study states */ 13132cf86f6SMauro Carvalho Chehab #define ST_STUDY_NONE 0x0 13232cf86f6SMauro Carvalho Chehab #define ST_STUDY_START 0x1 13332cf86f6SMauro Carvalho Chehab #define ST_STUDY_CARRIER 0x2 13432cf86f6SMauro Carvalho Chehab #define ST_STUDY_ALL_RECV 0x4 13532cf86f6SMauro Carvalho Chehab 13632cf86f6SMauro Carvalho Chehab /* wake states */ 13732cf86f6SMauro Carvalho Chehab #define ST_WAKE_NONE 0x0 13832cf86f6SMauro Carvalho Chehab #define ST_WAKE_START 0x1 13932cf86f6SMauro Carvalho Chehab #define ST_WAKE_FINISH 0x2 14032cf86f6SMauro Carvalho Chehab 14132cf86f6SMauro Carvalho Chehab /* receive states */ 14232cf86f6SMauro Carvalho Chehab #define ST_RX_WAIT_7F 0x1 14332cf86f6SMauro Carvalho Chehab #define ST_RX_WAIT_HEAD 0x2 14432cf86f6SMauro Carvalho Chehab #define ST_RX_WAIT_SILENT_END 0x4 14532cf86f6SMauro Carvalho Chehab 14632cf86f6SMauro Carvalho Chehab /* send states */ 14732cf86f6SMauro Carvalho Chehab #define ST_TX_NONE 0x0 14832cf86f6SMauro Carvalho Chehab #define ST_TX_REQUEST 0x2 14932cf86f6SMauro Carvalho Chehab #define ST_TX_REPLY 0x4 15032cf86f6SMauro Carvalho Chehab 15132cf86f6SMauro Carvalho Chehab /* buffer packet constants */ 15232cf86f6SMauro Carvalho Chehab #define BUF_PULSE_BIT 0x80 15332cf86f6SMauro Carvalho Chehab #define BUF_LEN_MASK 0x7f 15432cf86f6SMauro Carvalho Chehab #define BUF_REPEAT_BYTE 0x70 15532cf86f6SMauro Carvalho Chehab #define BUF_REPEAT_MASK 0xf0 15632cf86f6SMauro Carvalho Chehab 15732cf86f6SMauro Carvalho Chehab /* CIR settings */ 15832cf86f6SMauro Carvalho Chehab 15932cf86f6SMauro Carvalho Chehab /* total length of CIR and CIR WAKE */ 16032cf86f6SMauro Carvalho Chehab #define CIR_IOREG_LENGTH 0x0f 16132cf86f6SMauro Carvalho Chehab 16232cf86f6SMauro Carvalho Chehab /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */ 16332cf86f6SMauro Carvalho Chehab #define CIR_RX_LIMIT_COUNT 0x7d0 16432cf86f6SMauro Carvalho Chehab 16532cf86f6SMauro Carvalho Chehab /* CIR Regs */ 16632cf86f6SMauro Carvalho Chehab #define CIR_IRCON 0x00 16732cf86f6SMauro Carvalho Chehab #define CIR_IRSTS 0x01 16832cf86f6SMauro Carvalho Chehab #define CIR_IREN 0x02 16932cf86f6SMauro Carvalho Chehab #define CIR_RXFCONT 0x03 17032cf86f6SMauro Carvalho Chehab #define CIR_CP 0x04 17132cf86f6SMauro Carvalho Chehab #define CIR_CC 0x05 17232cf86f6SMauro Carvalho Chehab #define CIR_SLCH 0x06 17332cf86f6SMauro Carvalho Chehab #define CIR_SLCL 0x07 17432cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON 0x08 17532cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS 0x09 17632cf86f6SMauro Carvalho Chehab #define CIR_SRXFIFO 0x0a 17732cf86f6SMauro Carvalho Chehab #define CIR_TXFCONT 0x0b 17832cf86f6SMauro Carvalho Chehab #define CIR_STXFIFO 0x0c 17932cf86f6SMauro Carvalho Chehab #define CIR_FCCH 0x0d 18032cf86f6SMauro Carvalho Chehab #define CIR_FCCL 0x0e 18132cf86f6SMauro Carvalho Chehab #define CIR_IRFSM 0x0f 18232cf86f6SMauro Carvalho Chehab 18332cf86f6SMauro Carvalho Chehab /* CIR IRCON settings */ 18432cf86f6SMauro Carvalho Chehab #define CIR_IRCON_RECV 0x80 18532cf86f6SMauro Carvalho Chehab #define CIR_IRCON_WIREN 0x40 18632cf86f6SMauro Carvalho Chehab #define CIR_IRCON_TXEN 0x20 18732cf86f6SMauro Carvalho Chehab #define CIR_IRCON_RXEN 0x10 18832cf86f6SMauro Carvalho Chehab #define CIR_IRCON_WRXINV 0x08 18932cf86f6SMauro Carvalho Chehab #define CIR_IRCON_RXINV 0x04 19032cf86f6SMauro Carvalho Chehab 19132cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 19232cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 19332cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 19432cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 19532cf86f6SMauro Carvalho Chehab 19632cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 19732cf86f6SMauro Carvalho Chehab /* select sample period as 50us */ 19832cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 19932cf86f6SMauro Carvalho Chehab 20032cf86f6SMauro Carvalho Chehab /* CIR IRSTS settings */ 20132cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_RDR 0x80 20232cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_RTR 0x40 20332cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_PE 0x20 20432cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_RFO 0x10 20532cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_TE 0x08 20632cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_TTR 0x04 20732cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_TFU 0x02 20832cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_GH 0x01 20932cf86f6SMauro Carvalho Chehab 21032cf86f6SMauro Carvalho Chehab /* CIR IREN settings */ 21132cf86f6SMauro Carvalho Chehab #define CIR_IREN_RDR 0x80 21232cf86f6SMauro Carvalho Chehab #define CIR_IREN_RTR 0x40 21332cf86f6SMauro Carvalho Chehab #define CIR_IREN_PE 0x20 21432cf86f6SMauro Carvalho Chehab #define CIR_IREN_RFO 0x10 21532cf86f6SMauro Carvalho Chehab #define CIR_IREN_TE 0x08 21632cf86f6SMauro Carvalho Chehab #define CIR_IREN_TTR 0x04 21732cf86f6SMauro Carvalho Chehab #define CIR_IREN_TFU 0x02 21832cf86f6SMauro Carvalho Chehab #define CIR_IREN_GH 0x01 21932cf86f6SMauro Carvalho Chehab 22032cf86f6SMauro Carvalho Chehab /* CIR FIFOCON settings */ 22132cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TXFIFOCLR 0x80 22232cf86f6SMauro Carvalho Chehab 22332cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 22432cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 22532cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 22632cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 22732cf86f6SMauro Carvalho Chehab 22832cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 22932cf86f6SMauro Carvalho Chehab /* select TX trigger level as 16 */ 23032cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 23132cf86f6SMauro Carvalho Chehab 23232cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RXFIFOCLR 0x08 23332cf86f6SMauro Carvalho Chehab 23432cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 23532cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 23632cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 23732cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 23832cf86f6SMauro Carvalho Chehab 23932cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 24032cf86f6SMauro Carvalho Chehab /* select RX trigger level as 24 */ 24132cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 24232cf86f6SMauro Carvalho Chehab 24332cf86f6SMauro Carvalho Chehab /* CIR IRFIFOSTS settings */ 24432cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_IR_PENDING 0x80 24532cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_GS 0x40 24632cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_FTA 0x20 24732cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_EMPTY 0x10 24832cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_FULL 0x08 24932cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_TX_FTA 0x04 25032cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_TX_EMPTY 0x02 25132cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_TX_FULL 0x01 25232cf86f6SMauro Carvalho Chehab 25332cf86f6SMauro Carvalho Chehab 25432cf86f6SMauro Carvalho Chehab /* CIR WAKE UP Regs */ 25532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON 0x00 25632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS 0x01 25732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN 0x02 25832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_CMP_DEEP 0x03 25932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_CMP_TOL 0x04 26032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_COUNT 0x05 26132cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SLCH 0x06 26232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SLCL 0x07 26332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON 0x08 26432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SRXFSTS 0x09 26532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a 26632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_WR_FIFO_DATA 0x0b 26732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_RD_FIFO_ONLY 0x0c 26832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d 26932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_IGNORE 0x0e 27032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFSM 0x0f 27132cf86f6SMauro Carvalho Chehab 27232cf86f6SMauro Carvalho Chehab /* CIR WAKE UP IRCON settings */ 27332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_DEC_RST 0x80 27432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_MODE1 0x40 27532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_MODE0 0x20 27632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_RXEN 0x10 27732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_R 0x08 27832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_RXINV 0x04 27932cf86f6SMauro Carvalho Chehab 28032cf86f6SMauro Carvalho Chehab /* FIXME/jarod: make this a runtime option */ 28132cf86f6SMauro Carvalho Chehab /* select a same sample period like cir register */ 28232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 28332cf86f6SMauro Carvalho Chehab 28432cf86f6SMauro Carvalho Chehab /* CIR WAKE IRSTS Bits */ 28532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_RDR 0x80 28632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_RTR 0x40 28732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_PE 0x20 28832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_RFO 0x10 28932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_GH 0x08 29032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_IR_PENDING 0x01 29132cf86f6SMauro Carvalho Chehab 29232cf86f6SMauro Carvalho Chehab /* CIR WAKE UP IREN Bits */ 29332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_RDR 0x80 29432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_RTR 0x40 29532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_PE 0x20 29632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_RFO 0x10 29732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_TE 0x08 29832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_TTR 0x04 29932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_TFU 0x02 30032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_GH 0x01 30132cf86f6SMauro Carvalho Chehab 30232cf86f6SMauro Carvalho Chehab /* CIR WAKE FIFOCON settings */ 30332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 30432cf86f6SMauro Carvalho Chehab 30532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 30632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 30732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 30832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 30932cf86f6SMauro Carvalho Chehab 31032cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 31132cf86f6SMauro Carvalho Chehab /* select WAKE UP RX trigger level as 67 */ 31232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 31332cf86f6SMauro Carvalho Chehab 31432cf86f6SMauro Carvalho Chehab /* CIR WAKE SRXFSTS settings */ 31532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 31632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 31732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 31832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 31932cf86f6SMauro Carvalho Chehab 3203198ed16SJarod Wilson /* 3213198ed16SJarod Wilson * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes 3223198ed16SJarod Wilson * the system comparing only 65 bytes (fails with this set to 67) 3233198ed16SJarod Wilson */ 3243198ed16SJarod Wilson #define CIR_WAKE_FIFO_CMP_BYTES 65 32532cf86f6SMauro Carvalho Chehab /* CIR Wake byte comparison tolerance */ 32632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_CMP_TOLERANCE 5 32732cf86f6SMauro Carvalho Chehab 32832cf86f6SMauro Carvalho Chehab /* 32932cf86f6SMauro Carvalho Chehab * Extended Function Enable Registers: 33032cf86f6SMauro Carvalho Chehab * Extended Function Index Register 33132cf86f6SMauro Carvalho Chehab * Extended Function Data Register 33232cf86f6SMauro Carvalho Chehab */ 33332cf86f6SMauro Carvalho Chehab #define CR_EFIR 0x2e 33432cf86f6SMauro Carvalho Chehab #define CR_EFDR 0x2f 33532cf86f6SMauro Carvalho Chehab 33632cf86f6SMauro Carvalho Chehab /* Possible alternate EFER values, depends on how the chip is wired */ 33732cf86f6SMauro Carvalho Chehab #define CR_EFIR2 0x4e 33832cf86f6SMauro Carvalho Chehab #define CR_EFDR2 0x4f 33932cf86f6SMauro Carvalho Chehab 34032cf86f6SMauro Carvalho Chehab /* Extended Function Mode enable/disable magic values */ 34132cf86f6SMauro Carvalho Chehab #define EFER_EFM_ENABLE 0x87 34232cf86f6SMauro Carvalho Chehab #define EFER_EFM_DISABLE 0xaa 34332cf86f6SMauro Carvalho Chehab 34432cf86f6SMauro Carvalho Chehab /* Config regs we need to care about */ 34532cf86f6SMauro Carvalho Chehab #define CR_SOFTWARE_RESET 0x02 34632cf86f6SMauro Carvalho Chehab #define CR_LOGICAL_DEV_SEL 0x07 34732cf86f6SMauro Carvalho Chehab #define CR_CHIP_ID_HI 0x20 34832cf86f6SMauro Carvalho Chehab #define CR_CHIP_ID_LO 0x21 34932cf86f6SMauro Carvalho Chehab #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 35032cf86f6SMauro Carvalho Chehab #define CR_OUTPUT_PIN_SEL 0x27 35139381d4fSJarod Wilson #define CR_MULTIFUNC_PIN_SEL 0x2c 35232cf86f6SMauro Carvalho Chehab #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 35332cf86f6SMauro Carvalho Chehab /* next three regs valid for both the CIR and CIR_WAKE logical devices */ 35432cf86f6SMauro Carvalho Chehab #define CR_CIR_BASE_ADDR_HI 0x60 35532cf86f6SMauro Carvalho Chehab #define CR_CIR_BASE_ADDR_LO 0x61 35632cf86f6SMauro Carvalho Chehab #define CR_CIR_IRQ_RSRC 0x70 35732cf86f6SMauro Carvalho Chehab /* next three regs valid only for ACPI logical dev */ 35832cf86f6SMauro Carvalho Chehab #define CR_ACPI_CIR_WAKE 0xe0 35932cf86f6SMauro Carvalho Chehab #define CR_ACPI_IRQ_EVENTS 0xf6 36032cf86f6SMauro Carvalho Chehab #define CR_ACPI_IRQ_EVENTS2 0xf7 36132cf86f6SMauro Carvalho Chehab 36232cf86f6SMauro Carvalho Chehab /* Logical devices that we need to care about */ 36332cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_LPT 0x01 36432cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_CIR 0x06 36532cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_ACPI 0x0a 36632cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_CIR_WAKE 0x0e 36732cf86f6SMauro Carvalho Chehab 36832cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_DISABLE 0x00 36932cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_ENABLE 0x01 37032cf86f6SMauro Carvalho Chehab 37132cf86f6SMauro Carvalho Chehab #define CIR_WAKE_ENABLE_BIT 0x08 37232cf86f6SMauro Carvalho Chehab #define PME_INTR_CIR_PASS_BIT 0x08 37332cf86f6SMauro Carvalho Chehab 37439381d4fSJarod Wilson /* w83677hg CIR pin config */ 37532cf86f6SMauro Carvalho Chehab #define OUTPUT_PIN_SEL_MASK 0xbc 37632cf86f6SMauro Carvalho Chehab #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 37732cf86f6SMauro Carvalho Chehab #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 37832cf86f6SMauro Carvalho Chehab 37939381d4fSJarod Wilson /* w83667hg CIR pin config */ 38039381d4fSJarod Wilson #define MULTIFUNC_PIN_SEL_MASK 0x1f 38139381d4fSJarod Wilson #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */ 38239381d4fSJarod Wilson #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */ 38339381d4fSJarod Wilson 38432cf86f6SMauro Carvalho Chehab /* MCE CIR signal length, related on sample period */ 38532cf86f6SMauro Carvalho Chehab 38632cf86f6SMauro Carvalho Chehab /* MCE CIR controller signal length: about 43ms 38732cf86f6SMauro Carvalho Chehab * 43ms / 50us (sample period) * 0.85 (inaccuracy) 38832cf86f6SMauro Carvalho Chehab */ 38932cf86f6SMauro Carvalho Chehab #define CONTROLLER_BUF_LEN_MIN 830 39032cf86f6SMauro Carvalho Chehab 39132cf86f6SMauro Carvalho Chehab /* MCE CIR keyboard signal length: about 26ms 39232cf86f6SMauro Carvalho Chehab * 26ms / 50us (sample period) * 0.85 (inaccuracy) 39332cf86f6SMauro Carvalho Chehab */ 39432cf86f6SMauro Carvalho Chehab #define KEYBOARD_BUF_LEN_MAX 650 39532cf86f6SMauro Carvalho Chehab #define KEYBOARD_BUF_LEN_MIN 610 39632cf86f6SMauro Carvalho Chehab 39732cf86f6SMauro Carvalho Chehab /* MCE CIR mouse signal length: about 24ms 39832cf86f6SMauro Carvalho Chehab * 24ms / 50us (sample period) * 0.85 (inaccuracy) 39932cf86f6SMauro Carvalho Chehab */ 40032cf86f6SMauro Carvalho Chehab #define MOUSE_BUF_LEN_MIN 565 40132cf86f6SMauro Carvalho Chehab 40232cf86f6SMauro Carvalho Chehab #define CIR_SAMPLE_PERIOD 50 40332cf86f6SMauro Carvalho Chehab #define CIR_SAMPLE_LOW_INACCURACY 0.85 40432cf86f6SMauro Carvalho Chehab 40532cf86f6SMauro Carvalho Chehab /* MAX silence time that driver will sent to lirc */ 40632cf86f6SMauro Carvalho Chehab #define MAX_SILENCE_TIME 60000 40732cf86f6SMauro Carvalho Chehab 40832cf86f6SMauro Carvalho Chehab #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 40932cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 100 41032cf86f6SMauro Carvalho Chehab 41132cf86f6SMauro Carvalho Chehab #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 41232cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 50 41332cf86f6SMauro Carvalho Chehab 41432cf86f6SMauro Carvalho Chehab #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 41532cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 25 41632cf86f6SMauro Carvalho Chehab 41732cf86f6SMauro Carvalho Chehab #else 41832cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 1 41932cf86f6SMauro Carvalho Chehab #endif 42032cf86f6SMauro Carvalho Chehab 42132cf86f6SMauro Carvalho Chehab /* as VISTA MCE definition, valid carrier value */ 42232cf86f6SMauro Carvalho Chehab #define MAX_CARRIER 60000 42332cf86f6SMauro Carvalho Chehab #define MIN_CARRIER 30000 424