1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 232cf86f6SMauro Carvalho Chehab /* 332cf86f6SMauro Carvalho Chehab * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 432cf86f6SMauro Carvalho Chehab * 532cf86f6SMauro Carvalho Chehab * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 632cf86f6SMauro Carvalho Chehab * Copyright (C) 2009 Nuvoton PS Team 732cf86f6SMauro Carvalho Chehab * 832cf86f6SMauro Carvalho Chehab * Special thanks to Nuvoton for providing hardware, spec sheets and 932cf86f6SMauro Carvalho Chehab * sample code upon which portions of this driver are based. Indirect 1032cf86f6SMauro Carvalho Chehab * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 1132cf86f6SMauro Carvalho Chehab * modeled after. 1232cf86f6SMauro Carvalho Chehab */ 1332cf86f6SMauro Carvalho Chehab 1432cf86f6SMauro Carvalho Chehab #include <linux/spinlock.h> 1532cf86f6SMauro Carvalho Chehab #include <linux/ioctl.h> 1632cf86f6SMauro Carvalho Chehab 1732cf86f6SMauro Carvalho Chehab /* platform driver name to register */ 1832cf86f6SMauro Carvalho Chehab #define NVT_DRIVER_NAME "nuvoton-cir" 1932cf86f6SMauro Carvalho Chehab 2032cf86f6SMauro Carvalho Chehab /* debugging module parameter */ 2132cf86f6SMauro Carvalho Chehab static int debug; 2232cf86f6SMauro Carvalho Chehab 2332cf86f6SMauro Carvalho Chehab 2432cf86f6SMauro Carvalho Chehab #define nvt_dbg(text, ...) \ 2532cf86f6SMauro Carvalho Chehab if (debug) \ 2632cf86f6SMauro Carvalho Chehab printk(KERN_DEBUG \ 2732cf86f6SMauro Carvalho Chehab KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 2832cf86f6SMauro Carvalho Chehab 2932cf86f6SMauro Carvalho Chehab #define nvt_dbg_verbose(text, ...) \ 3032cf86f6SMauro Carvalho Chehab if (debug > 1) \ 3132cf86f6SMauro Carvalho Chehab printk(KERN_DEBUG \ 3232cf86f6SMauro Carvalho Chehab KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 3332cf86f6SMauro Carvalho Chehab 3432cf86f6SMauro Carvalho Chehab #define nvt_dbg_wake(text, ...) \ 3532cf86f6SMauro Carvalho Chehab if (debug > 2) \ 3632cf86f6SMauro Carvalho Chehab printk(KERN_DEBUG \ 3732cf86f6SMauro Carvalho Chehab KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__) 3832cf86f6SMauro Carvalho Chehab 3932cf86f6SMauro Carvalho Chehab 4032cf86f6SMauro Carvalho Chehab #define RX_BUF_LEN 32 4132cf86f6SMauro Carvalho Chehab 42b5cf725cSHeiner Kallweit #define SIO_ID_MASK 0xfff0 43b5cf725cSHeiner Kallweit 44b5cf725cSHeiner Kallweit enum nvt_chip_ver { 45b5cf725cSHeiner Kallweit NVT_UNKNOWN = 0, 46b5cf725cSHeiner Kallweit NVT_W83667HG = 0xa510, 47b5cf725cSHeiner Kallweit NVT_6775F = 0xb470, 48d0b528d5SHeiner Kallweit NVT_6776F = 0xc330, 493f1321cbSHeiner Kallweit NVT_6779D = 0xc560, 503f1321cbSHeiner Kallweit NVT_INVALID = 0xffff, 51b5cf725cSHeiner Kallweit }; 52b5cf725cSHeiner Kallweit 53b5cf725cSHeiner Kallweit struct nvt_chip { 54b5cf725cSHeiner Kallweit const char *name; 55b5cf725cSHeiner Kallweit enum nvt_chip_ver chip_ver; 56b5cf725cSHeiner Kallweit }; 57b5cf725cSHeiner Kallweit 5832cf86f6SMauro Carvalho Chehab struct nvt_dev { 59d8b4b582SDavid Härdeman struct rc_dev *rdev; 6032cf86f6SMauro Carvalho Chehab 6173d4576dSHeiner Kallweit spinlock_t lock; 6232cf86f6SMauro Carvalho Chehab 6332cf86f6SMauro Carvalho Chehab /* for rx */ 6432cf86f6SMauro Carvalho Chehab u8 buf[RX_BUF_LEN]; 6532cf86f6SMauro Carvalho Chehab unsigned int pkts; 6632cf86f6SMauro Carvalho Chehab 6732cf86f6SMauro Carvalho Chehab /* EFER Config register index/data pair */ 68221cefa4SMauro Carvalho Chehab u32 cr_efir; 69221cefa4SMauro Carvalho Chehab u32 cr_efdr; 7032cf86f6SMauro Carvalho Chehab 7132cf86f6SMauro Carvalho Chehab /* hardware I/O settings */ 7232cf86f6SMauro Carvalho Chehab unsigned long cir_addr; 7332cf86f6SMauro Carvalho Chehab unsigned long cir_wake_addr; 7432cf86f6SMauro Carvalho Chehab int cir_irq; 7532cf86f6SMauro Carvalho Chehab 76b5cf725cSHeiner Kallweit enum nvt_chip_ver chip_ver; 7732cf86f6SMauro Carvalho Chehab /* hardware id */ 7832cf86f6SMauro Carvalho Chehab u8 chip_major; 7932cf86f6SMauro Carvalho Chehab u8 chip_minor; 8032cf86f6SMauro Carvalho Chehab 8132cf86f6SMauro Carvalho Chehab /* carrier period = 1 / frequency */ 8232cf86f6SMauro Carvalho Chehab u32 carrier; 8332cf86f6SMauro Carvalho Chehab }; 8432cf86f6SMauro Carvalho Chehab 8532cf86f6SMauro Carvalho Chehab /* buffer packet constants */ 8632cf86f6SMauro Carvalho Chehab #define BUF_PULSE_BIT 0x80 8732cf86f6SMauro Carvalho Chehab #define BUF_LEN_MASK 0x7f 8832cf86f6SMauro Carvalho Chehab #define BUF_REPEAT_BYTE 0x70 8932cf86f6SMauro Carvalho Chehab #define BUF_REPEAT_MASK 0xf0 9032cf86f6SMauro Carvalho Chehab 9132cf86f6SMauro Carvalho Chehab /* CIR settings */ 9232cf86f6SMauro Carvalho Chehab 9332cf86f6SMauro Carvalho Chehab /* total length of CIR and CIR WAKE */ 9432cf86f6SMauro Carvalho Chehab #define CIR_IOREG_LENGTH 0x0f 9532cf86f6SMauro Carvalho Chehab 96f2c2ba0eSHeiner Kallweit /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */ 97528222d8SSean Young #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / SAMPLE_PERIOD) 9832cf86f6SMauro Carvalho Chehab 9932cf86f6SMauro Carvalho Chehab /* CIR Regs */ 10032cf86f6SMauro Carvalho Chehab #define CIR_IRCON 0x00 10132cf86f6SMauro Carvalho Chehab #define CIR_IRSTS 0x01 10232cf86f6SMauro Carvalho Chehab #define CIR_IREN 0x02 10332cf86f6SMauro Carvalho Chehab #define CIR_RXFCONT 0x03 10432cf86f6SMauro Carvalho Chehab #define CIR_CP 0x04 10532cf86f6SMauro Carvalho Chehab #define CIR_CC 0x05 10632cf86f6SMauro Carvalho Chehab #define CIR_SLCH 0x06 10732cf86f6SMauro Carvalho Chehab #define CIR_SLCL 0x07 10832cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON 0x08 10932cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS 0x09 11032cf86f6SMauro Carvalho Chehab #define CIR_SRXFIFO 0x0a 11132cf86f6SMauro Carvalho Chehab #define CIR_TXFCONT 0x0b 11232cf86f6SMauro Carvalho Chehab #define CIR_STXFIFO 0x0c 11332cf86f6SMauro Carvalho Chehab #define CIR_FCCH 0x0d 11432cf86f6SMauro Carvalho Chehab #define CIR_FCCL 0x0e 11532cf86f6SMauro Carvalho Chehab #define CIR_IRFSM 0x0f 11632cf86f6SMauro Carvalho Chehab 11732cf86f6SMauro Carvalho Chehab /* CIR IRCON settings */ 11832cf86f6SMauro Carvalho Chehab #define CIR_IRCON_RECV 0x80 11932cf86f6SMauro Carvalho Chehab #define CIR_IRCON_WIREN 0x40 12032cf86f6SMauro Carvalho Chehab #define CIR_IRCON_TXEN 0x20 12132cf86f6SMauro Carvalho Chehab #define CIR_IRCON_RXEN 0x10 12232cf86f6SMauro Carvalho Chehab #define CIR_IRCON_WRXINV 0x08 12332cf86f6SMauro Carvalho Chehab #define CIR_IRCON_RXINV 0x04 12432cf86f6SMauro Carvalho Chehab 12532cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00 12632cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01 12732cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02 12832cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03 12932cf86f6SMauro Carvalho Chehab 13032cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 13132cf86f6SMauro Carvalho Chehab /* select sample period as 50us */ 13232cf86f6SMauro Carvalho Chehab #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 13332cf86f6SMauro Carvalho Chehab 13432cf86f6SMauro Carvalho Chehab /* CIR IRSTS settings */ 13532cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_RDR 0x80 13632cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_RTR 0x40 13732cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_PE 0x20 13832cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_RFO 0x10 13932cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_TE 0x08 14032cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_TTR 0x04 14132cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_TFU 0x02 14232cf86f6SMauro Carvalho Chehab #define CIR_IRSTS_GH 0x01 14332cf86f6SMauro Carvalho Chehab 14432cf86f6SMauro Carvalho Chehab /* CIR IREN settings */ 14532cf86f6SMauro Carvalho Chehab #define CIR_IREN_RDR 0x80 14632cf86f6SMauro Carvalho Chehab #define CIR_IREN_RTR 0x40 14732cf86f6SMauro Carvalho Chehab #define CIR_IREN_PE 0x20 14832cf86f6SMauro Carvalho Chehab #define CIR_IREN_RFO 0x10 14932cf86f6SMauro Carvalho Chehab #define CIR_IREN_TE 0x08 15032cf86f6SMauro Carvalho Chehab #define CIR_IREN_TTR 0x04 15132cf86f6SMauro Carvalho Chehab #define CIR_IREN_TFU 0x02 15232cf86f6SMauro Carvalho Chehab #define CIR_IREN_GH 0x01 15332cf86f6SMauro Carvalho Chehab 15432cf86f6SMauro Carvalho Chehab /* CIR FIFOCON settings */ 15532cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TXFIFOCLR 0x80 15632cf86f6SMauro Carvalho Chehab 15732cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00 15832cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10 15932cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20 16032cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30 16132cf86f6SMauro Carvalho Chehab 16232cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 16332cf86f6SMauro Carvalho Chehab /* select TX trigger level as 16 */ 16432cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16 16532cf86f6SMauro Carvalho Chehab 16632cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RXFIFOCLR 0x08 16732cf86f6SMauro Carvalho Chehab 16832cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00 16932cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01 17032cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02 17132cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03 17232cf86f6SMauro Carvalho Chehab 17332cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 17432cf86f6SMauro Carvalho Chehab /* select RX trigger level as 24 */ 17532cf86f6SMauro Carvalho Chehab #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24 17632cf86f6SMauro Carvalho Chehab 17732cf86f6SMauro Carvalho Chehab /* CIR IRFIFOSTS settings */ 17832cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_IR_PENDING 0x80 17932cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_GS 0x40 18032cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_FTA 0x20 18132cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_EMPTY 0x10 18232cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_RX_FULL 0x08 18332cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_TX_FTA 0x04 18432cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_TX_EMPTY 0x02 18532cf86f6SMauro Carvalho Chehab #define CIR_IRFIFOSTS_TX_FULL 0x01 18632cf86f6SMauro Carvalho Chehab 18732cf86f6SMauro Carvalho Chehab 18832cf86f6SMauro Carvalho Chehab /* CIR WAKE UP Regs */ 18932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON 0x00 19032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS 0x01 19132cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN 0x02 19232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_CMP_DEEP 0x03 19332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_CMP_TOL 0x04 19432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_COUNT 0x05 19532cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SLCH 0x06 19632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SLCL 0x07 19732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON 0x08 19832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SRXFSTS 0x09 19932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a 20032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_WR_FIFO_DATA 0x0b 20132cf86f6SMauro Carvalho Chehab #define CIR_WAKE_RD_FIFO_ONLY 0x0c 20232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d 20332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFO_IGNORE 0x0e 20432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFSM 0x0f 20532cf86f6SMauro Carvalho Chehab 20632cf86f6SMauro Carvalho Chehab /* CIR WAKE UP IRCON settings */ 20732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_DEC_RST 0x80 20832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_MODE1 0x40 20932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_MODE0 0x20 21032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_RXEN 0x10 21132cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_R 0x08 21232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_RXINV 0x04 21332cf86f6SMauro Carvalho Chehab 21432cf86f6SMauro Carvalho Chehab /* FIXME/jarod: make this a runtime option */ 21532cf86f6SMauro Carvalho Chehab /* select a same sample period like cir register */ 21632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50 21732cf86f6SMauro Carvalho Chehab 21832cf86f6SMauro Carvalho Chehab /* CIR WAKE IRSTS Bits */ 21932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_RDR 0x80 22032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_RTR 0x40 22132cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_PE 0x20 22232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_RFO 0x10 22332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_GH 0x08 22432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRSTS_IR_PENDING 0x01 22532cf86f6SMauro Carvalho Chehab 22632cf86f6SMauro Carvalho Chehab /* CIR WAKE UP IREN Bits */ 22732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_RDR 0x80 22832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_RTR 0x40 22932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_PE 0x20 23032cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IREN_RFO 0x10 23188205f01SHeiner Kallweit #define CIR_WAKE_IREN_GH 0x08 23232cf86f6SMauro Carvalho Chehab 23332cf86f6SMauro Carvalho Chehab /* CIR WAKE FIFOCON settings */ 23432cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08 23532cf86f6SMauro Carvalho Chehab 23632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00 23732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01 23832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02 23932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03 24032cf86f6SMauro Carvalho Chehab 24132cf86f6SMauro Carvalho Chehab /* FIXME: make this a runtime option */ 24232cf86f6SMauro Carvalho Chehab /* select WAKE UP RX trigger level as 67 */ 24332cf86f6SMauro Carvalho Chehab #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 24432cf86f6SMauro Carvalho Chehab 24532cf86f6SMauro Carvalho Chehab /* CIR WAKE SRXFSTS settings */ 24632cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80 24732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40 24832cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20 24932cf86f6SMauro Carvalho Chehab #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10 25032cf86f6SMauro Carvalho Chehab 2513198ed16SJarod Wilson /* 2523198ed16SJarod Wilson * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes 2533198ed16SJarod Wilson * the system comparing only 65 bytes (fails with this set to 67) 2543198ed16SJarod Wilson */ 2553198ed16SJarod Wilson #define CIR_WAKE_FIFO_CMP_BYTES 65 25632cf86f6SMauro Carvalho Chehab /* CIR Wake byte comparison tolerance */ 25732cf86f6SMauro Carvalho Chehab #define CIR_WAKE_CMP_TOLERANCE 5 25832cf86f6SMauro Carvalho Chehab 25932cf86f6SMauro Carvalho Chehab /* 26032cf86f6SMauro Carvalho Chehab * Extended Function Enable Registers: 26132cf86f6SMauro Carvalho Chehab * Extended Function Index Register 26232cf86f6SMauro Carvalho Chehab * Extended Function Data Register 26332cf86f6SMauro Carvalho Chehab */ 26432cf86f6SMauro Carvalho Chehab #define CR_EFIR 0x2e 26532cf86f6SMauro Carvalho Chehab #define CR_EFDR 0x2f 26632cf86f6SMauro Carvalho Chehab 26732cf86f6SMauro Carvalho Chehab /* Possible alternate EFER values, depends on how the chip is wired */ 26832cf86f6SMauro Carvalho Chehab #define CR_EFIR2 0x4e 26932cf86f6SMauro Carvalho Chehab #define CR_EFDR2 0x4f 27032cf86f6SMauro Carvalho Chehab 27132cf86f6SMauro Carvalho Chehab /* Extended Function Mode enable/disable magic values */ 27232cf86f6SMauro Carvalho Chehab #define EFER_EFM_ENABLE 0x87 27332cf86f6SMauro Carvalho Chehab #define EFER_EFM_DISABLE 0xaa 27432cf86f6SMauro Carvalho Chehab 27532cf86f6SMauro Carvalho Chehab /* Config regs we need to care about */ 27632cf86f6SMauro Carvalho Chehab #define CR_SOFTWARE_RESET 0x02 27732cf86f6SMauro Carvalho Chehab #define CR_LOGICAL_DEV_SEL 0x07 27832cf86f6SMauro Carvalho Chehab #define CR_CHIP_ID_HI 0x20 27932cf86f6SMauro Carvalho Chehab #define CR_CHIP_ID_LO 0x21 28032cf86f6SMauro Carvalho Chehab #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 28132cf86f6SMauro Carvalho Chehab #define CR_OUTPUT_PIN_SEL 0x27 28239381d4fSJarod Wilson #define CR_MULTIFUNC_PIN_SEL 0x2c 28332cf86f6SMauro Carvalho Chehab #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 28432cf86f6SMauro Carvalho Chehab /* next three regs valid for both the CIR and CIR_WAKE logical devices */ 28532cf86f6SMauro Carvalho Chehab #define CR_CIR_BASE_ADDR_HI 0x60 28632cf86f6SMauro Carvalho Chehab #define CR_CIR_BASE_ADDR_LO 0x61 28732cf86f6SMauro Carvalho Chehab #define CR_CIR_IRQ_RSRC 0x70 28832cf86f6SMauro Carvalho Chehab /* next three regs valid only for ACPI logical dev */ 28932cf86f6SMauro Carvalho Chehab #define CR_ACPI_CIR_WAKE 0xe0 29032cf86f6SMauro Carvalho Chehab #define CR_ACPI_IRQ_EVENTS 0xf6 29132cf86f6SMauro Carvalho Chehab #define CR_ACPI_IRQ_EVENTS2 0xf7 29232cf86f6SMauro Carvalho Chehab 29332cf86f6SMauro Carvalho Chehab /* Logical devices that we need to care about */ 29432cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_LPT 0x01 29532cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_CIR 0x06 29632cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_ACPI 0x0a 29732cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_CIR_WAKE 0x0e 29832cf86f6SMauro Carvalho Chehab 29932cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_DISABLE 0x00 30032cf86f6SMauro Carvalho Chehab #define LOGICAL_DEV_ENABLE 0x01 30132cf86f6SMauro Carvalho Chehab 30232cf86f6SMauro Carvalho Chehab #define CIR_WAKE_ENABLE_BIT 0x08 30332cf86f6SMauro Carvalho Chehab #define PME_INTR_CIR_PASS_BIT 0x08 30432cf86f6SMauro Carvalho Chehab 30539381d4fSJarod Wilson /* w83677hg CIR pin config */ 30632cf86f6SMauro Carvalho Chehab #define OUTPUT_PIN_SEL_MASK 0xbc 30732cf86f6SMauro Carvalho Chehab #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 30832cf86f6SMauro Carvalho Chehab #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 30932cf86f6SMauro Carvalho Chehab 31039381d4fSJarod Wilson /* w83667hg CIR pin config */ 31139381d4fSJarod Wilson #define MULTIFUNC_PIN_SEL_MASK 0x1f 31239381d4fSJarod Wilson #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */ 31339381d4fSJarod Wilson #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */ 31439381d4fSJarod Wilson 31532cf86f6SMauro Carvalho Chehab /* MCE CIR signal length, related on sample period */ 31632cf86f6SMauro Carvalho Chehab 31732cf86f6SMauro Carvalho Chehab /* MCE CIR controller signal length: about 43ms 31832cf86f6SMauro Carvalho Chehab * 43ms / 50us (sample period) * 0.85 (inaccuracy) 31932cf86f6SMauro Carvalho Chehab */ 32032cf86f6SMauro Carvalho Chehab #define CONTROLLER_BUF_LEN_MIN 830 32132cf86f6SMauro Carvalho Chehab 32232cf86f6SMauro Carvalho Chehab /* MCE CIR keyboard signal length: about 26ms 32332cf86f6SMauro Carvalho Chehab * 26ms / 50us (sample period) * 0.85 (inaccuracy) 32432cf86f6SMauro Carvalho Chehab */ 32532cf86f6SMauro Carvalho Chehab #define KEYBOARD_BUF_LEN_MAX 650 32632cf86f6SMauro Carvalho Chehab #define KEYBOARD_BUF_LEN_MIN 610 32732cf86f6SMauro Carvalho Chehab 32832cf86f6SMauro Carvalho Chehab /* MCE CIR mouse signal length: about 24ms 32932cf86f6SMauro Carvalho Chehab * 24ms / 50us (sample period) * 0.85 (inaccuracy) 33032cf86f6SMauro Carvalho Chehab */ 33132cf86f6SMauro Carvalho Chehab #define MOUSE_BUF_LEN_MIN 565 33232cf86f6SMauro Carvalho Chehab 33332cf86f6SMauro Carvalho Chehab #define CIR_SAMPLE_PERIOD 50 33432cf86f6SMauro Carvalho Chehab #define CIR_SAMPLE_LOW_INACCURACY 0.85 33532cf86f6SMauro Carvalho Chehab 33632cf86f6SMauro Carvalho Chehab /* MAX silence time that driver will sent to lirc */ 33732cf86f6SMauro Carvalho Chehab #define MAX_SILENCE_TIME 60000 33832cf86f6SMauro Carvalho Chehab 33932cf86f6SMauro Carvalho Chehab #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 34032cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 100 34132cf86f6SMauro Carvalho Chehab 34232cf86f6SMauro Carvalho Chehab #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 34332cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 50 34432cf86f6SMauro Carvalho Chehab 34532cf86f6SMauro Carvalho Chehab #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 34632cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 25 34732cf86f6SMauro Carvalho Chehab 34832cf86f6SMauro Carvalho Chehab #else 34932cf86f6SMauro Carvalho Chehab #define SAMPLE_PERIOD 1 35032cf86f6SMauro Carvalho Chehab #endif 35132cf86f6SMauro Carvalho Chehab 35232cf86f6SMauro Carvalho Chehab /* as VISTA MCE definition, valid carrier value */ 35332cf86f6SMauro Carvalho Chehab #define MAX_CARRIER 60000 35432cf86f6SMauro Carvalho Chehab #define MIN_CARRIER 30000 355449c1fcdSHeiner Kallweit 356449c1fcdSHeiner Kallweit /* max wakeup sequence length */ 357449c1fcdSHeiner Kallweit #define WAKEUP_MAX_SIZE 65 358