1 /* 2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR 3 * 4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> 5 * Copyright (C) 2009 Nuvoton PS Team 6 * 7 * Special thanks to Nuvoton for providing hardware, spec sheets and 8 * sample code upon which portions of this driver are based. Indirect 9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is 10 * modeled after. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 25 * USA 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/pnp.h> 33 #include <linux/io.h> 34 #include <linux/interrupt.h> 35 #include <linux/sched.h> 36 #include <linux/slab.h> 37 #include <media/rc-core.h> 38 #include <linux/pci_ids.h> 39 40 #include "nuvoton-cir.h" 41 42 /* write val to config reg */ 43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) 44 { 45 outb(reg, nvt->cr_efir); 46 outb(val, nvt->cr_efdr); 47 } 48 49 /* read val from config reg */ 50 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) 51 { 52 outb(reg, nvt->cr_efir); 53 return inb(nvt->cr_efdr); 54 } 55 56 /* update config register bit without changing other bits */ 57 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) 58 { 59 u8 tmp = nvt_cr_read(nvt, reg) | val; 60 nvt_cr_write(nvt, tmp, reg); 61 } 62 63 /* clear config register bit without changing other bits */ 64 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) 65 { 66 u8 tmp = nvt_cr_read(nvt, reg) & ~val; 67 nvt_cr_write(nvt, tmp, reg); 68 } 69 70 /* enter extended function mode */ 71 static inline void nvt_efm_enable(struct nvt_dev *nvt) 72 { 73 /* Enabling Extended Function Mode explicitly requires writing 2x */ 74 outb(EFER_EFM_ENABLE, nvt->cr_efir); 75 outb(EFER_EFM_ENABLE, nvt->cr_efir); 76 } 77 78 /* exit extended function mode */ 79 static inline void nvt_efm_disable(struct nvt_dev *nvt) 80 { 81 outb(EFER_EFM_DISABLE, nvt->cr_efir); 82 } 83 84 /* 85 * When you want to address a specific logical device, write its logical 86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing 87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. 88 */ 89 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) 90 { 91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir); 92 outb(ldev, nvt->cr_efdr); 93 } 94 95 /* write val to cir config register */ 96 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) 97 { 98 outb(val, nvt->cir_addr + offset); 99 } 100 101 /* read val from cir config register */ 102 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) 103 { 104 u8 val; 105 106 val = inb(nvt->cir_addr + offset); 107 108 return val; 109 } 110 111 /* write val to cir wake register */ 112 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, 113 u8 val, u8 offset) 114 { 115 outb(val, nvt->cir_wake_addr + offset); 116 } 117 118 /* read val from cir wake config register */ 119 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) 120 { 121 u8 val; 122 123 val = inb(nvt->cir_wake_addr + offset); 124 125 return val; 126 } 127 128 /* dump current cir register contents */ 129 static void cir_dump_regs(struct nvt_dev *nvt) 130 { 131 nvt_efm_enable(nvt); 132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 133 134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); 135 pr_info(" * CR CIR ACTIVE : 0x%x\n", 136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 137 pr_info(" * CR CIR BASE ADDR: 0x%x\n", 138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 140 pr_info(" * CR CIR IRQ NUM: 0x%x\n", 141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 142 143 nvt_efm_disable(nvt); 144 145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); 146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); 147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); 148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); 149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); 150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); 151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); 152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); 153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); 154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); 155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); 156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); 157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); 158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); 159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); 160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); 161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); 162 } 163 164 /* dump current cir wake register contents */ 165 static void cir_wake_dump_regs(struct nvt_dev *nvt) 166 { 167 u8 i, fifo_len; 168 169 nvt_efm_enable(nvt); 170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 171 172 pr_info("%s: Dump CIR WAKE logical device registers:\n", 173 NVT_DRIVER_NAME); 174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n", 175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", 177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n", 180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 181 182 nvt_efm_disable(nvt); 183 184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); 185 pr_info(" * IRCON: 0x%x\n", 186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); 187 pr_info(" * IRSTS: 0x%x\n", 188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); 189 pr_info(" * IREN: 0x%x\n", 190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); 191 pr_info(" * FIFO CMP DEEP: 0x%x\n", 192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); 193 pr_info(" * FIFO CMP TOL: 0x%x\n", 194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); 195 pr_info(" * FIFO COUNT: 0x%x\n", 196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); 197 pr_info(" * SLCH: 0x%x\n", 198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); 199 pr_info(" * SLCL: 0x%x\n", 200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); 201 pr_info(" * FIFOCON: 0x%x\n", 202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); 203 pr_info(" * SRXFSTS: 0x%x\n", 204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); 205 pr_info(" * SAMPLE RX FIFO: 0x%x\n", 206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); 207 pr_info(" * WR FIFO DATA: 0x%x\n", 208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); 209 pr_info(" * RD FIFO ONLY: 0x%x\n", 210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n", 212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); 213 pr_info(" * FIFO IGNORE: 0x%x\n", 214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); 215 pr_info(" * IRFSM: 0x%x\n", 216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); 217 218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); 219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); 220 pr_info("* Contents ="); 221 for (i = 0; i < fifo_len; i++) 222 pr_cont(" %02x", 223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 224 pr_cont("\n"); 225 } 226 227 /* detect hardware features */ 228 static int nvt_hw_detect(struct nvt_dev *nvt) 229 { 230 unsigned long flags; 231 u8 chip_major, chip_minor; 232 int ret = 0; 233 char chip_id[12]; 234 bool chip_unknown = false; 235 236 nvt_efm_enable(nvt); 237 238 /* Check if we're wired for the alternate EFER setup */ 239 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); 240 if (chip_major == 0xff) { 241 nvt->cr_efir = CR_EFIR2; 242 nvt->cr_efdr = CR_EFDR2; 243 nvt_efm_enable(nvt); 244 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); 245 } 246 247 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); 248 249 /* these are the known working chip revisions... */ 250 switch (chip_major) { 251 case CHIP_ID_HIGH_667: 252 strcpy(chip_id, "w83667hg\0"); 253 if (chip_minor != CHIP_ID_LOW_667) 254 chip_unknown = true; 255 break; 256 case CHIP_ID_HIGH_677B: 257 strcpy(chip_id, "w83677hg\0"); 258 if (chip_minor != CHIP_ID_LOW_677B2 && 259 chip_minor != CHIP_ID_LOW_677B3) 260 chip_unknown = true; 261 break; 262 case CHIP_ID_HIGH_677C: 263 strcpy(chip_id, "w83677hg-c\0"); 264 if (chip_minor != CHIP_ID_LOW_677C) 265 chip_unknown = true; 266 break; 267 default: 268 strcpy(chip_id, "w836x7hg\0"); 269 chip_unknown = true; 270 break; 271 } 272 273 /* warn, but still let the driver load, if we don't know this chip */ 274 if (chip_unknown) 275 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, " 276 "it may not work...", chip_id, chip_major, chip_minor); 277 else 278 nvt_dbg("%s: chip id: 0x%02x 0x%02x", 279 chip_id, chip_major, chip_minor); 280 281 nvt_efm_disable(nvt); 282 283 spin_lock_irqsave(&nvt->nvt_lock, flags); 284 nvt->chip_major = chip_major; 285 nvt->chip_minor = chip_minor; 286 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 287 288 return ret; 289 } 290 291 static void nvt_cir_ldev_init(struct nvt_dev *nvt) 292 { 293 u8 val, psreg, psmask, psval; 294 295 if (nvt->chip_major == CHIP_ID_HIGH_667) { 296 psreg = CR_MULTIFUNC_PIN_SEL; 297 psmask = MULTIFUNC_PIN_SEL_MASK; 298 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB; 299 } else { 300 psreg = CR_OUTPUT_PIN_SEL; 301 psmask = OUTPUT_PIN_SEL_MASK; 302 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB; 303 } 304 305 /* output pin selection: enable CIR, with WB sensor enabled */ 306 val = nvt_cr_read(nvt, psreg); 307 val &= psmask; 308 val |= psval; 309 nvt_cr_write(nvt, val, psreg); 310 311 /* Select CIR logical device and enable */ 312 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 313 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 314 315 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI); 316 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO); 317 318 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); 319 320 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", 321 nvt->cir_addr, nvt->cir_irq); 322 } 323 324 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) 325 { 326 /* Select ACPI logical device, enable it and CIR Wake */ 327 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); 328 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 329 330 /* Enable CIR Wake via PSOUT# (Pin60) */ 331 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); 332 333 /* enable pme interrupt of cir wakeup event */ 334 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); 335 336 /* Select CIR Wake logical device and enable */ 337 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 338 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 339 340 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI); 341 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO); 342 343 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC); 344 345 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d", 346 nvt->cir_wake_addr, nvt->cir_wake_irq); 347 } 348 349 /* clear out the hardware's cir rx fifo */ 350 static void nvt_clear_cir_fifo(struct nvt_dev *nvt) 351 { 352 u8 val; 353 354 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); 355 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); 356 } 357 358 /* clear out the hardware's cir wake rx fifo */ 359 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) 360 { 361 u8 val; 362 363 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); 364 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, 365 CIR_WAKE_FIFOCON); 366 } 367 368 /* clear out the hardware's cir tx fifo */ 369 static void nvt_clear_tx_fifo(struct nvt_dev *nvt) 370 { 371 u8 val; 372 373 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); 374 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); 375 } 376 377 /* enable RX Trigger Level Reach and Packet End interrupts */ 378 static void nvt_set_cir_iren(struct nvt_dev *nvt) 379 { 380 u8 iren; 381 382 iren = CIR_IREN_RTR | CIR_IREN_PE; 383 nvt_cir_reg_write(nvt, iren, CIR_IREN); 384 } 385 386 static void nvt_cir_regs_init(struct nvt_dev *nvt) 387 { 388 /* set sample limit count (PE interrupt raised when reached) */ 389 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); 390 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); 391 392 /* set fifo irq trigger levels */ 393 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | 394 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); 395 396 /* 397 * Enable TX and RX, specify carrier on = low, off = high, and set 398 * sample period (currently 50us) 399 */ 400 nvt_cir_reg_write(nvt, 401 CIR_IRCON_TXEN | CIR_IRCON_RXEN | 402 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, 403 CIR_IRCON); 404 405 /* clear hardware rx and tx fifos */ 406 nvt_clear_cir_fifo(nvt); 407 nvt_clear_tx_fifo(nvt); 408 409 /* clear any and all stray interrupts */ 410 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 411 412 /* and finally, enable interrupts */ 413 nvt_set_cir_iren(nvt); 414 } 415 416 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) 417 { 418 /* set number of bytes needed for wake from s3 (default 65) */ 419 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES, 420 CIR_WAKE_FIFO_CMP_DEEP); 421 422 /* set tolerance/variance allowed per byte during wake compare */ 423 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE, 424 CIR_WAKE_FIFO_CMP_TOL); 425 426 /* set sample limit count (PE interrupt raised when reached) */ 427 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH); 428 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL); 429 430 /* set cir wake fifo rx trigger level (currently 67) */ 431 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV, 432 CIR_WAKE_FIFOCON); 433 434 /* 435 * Enable TX and RX, specific carrier on = low, off = high, and set 436 * sample period (currently 50us) 437 */ 438 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | 439 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | 440 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, 441 CIR_WAKE_IRCON); 442 443 /* clear cir wake rx fifo */ 444 nvt_clear_cir_wake_fifo(nvt); 445 446 /* clear any and all stray interrupts */ 447 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); 448 } 449 450 static void nvt_enable_wake(struct nvt_dev *nvt) 451 { 452 nvt_efm_enable(nvt); 453 454 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); 455 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); 456 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); 457 458 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 459 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 460 461 nvt_efm_disable(nvt); 462 463 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | 464 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | 465 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, 466 CIR_WAKE_IRCON); 467 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); 468 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); 469 } 470 471 #if 0 /* Currently unused */ 472 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */ 473 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) 474 { 475 u32 count, carrier, duration = 0; 476 int i; 477 478 count = nvt_cir_reg_read(nvt, CIR_FCCL) | 479 nvt_cir_reg_read(nvt, CIR_FCCH) << 8; 480 481 for (i = 0; i < nvt->pkts; i++) { 482 if (nvt->buf[i] & BUF_PULSE_BIT) 483 duration += nvt->buf[i] & BUF_LEN_MASK; 484 } 485 486 duration *= SAMPLE_PERIOD; 487 488 if (!count || !duration) { 489 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)", 490 count, duration); 491 return 0; 492 } 493 494 carrier = MS_TO_NS(count) / duration; 495 496 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) 497 nvt_dbg("WTF? Carrier frequency out of range!"); 498 499 nvt_dbg("Carrier frequency: %u (count %u, duration %u)", 500 carrier, count, duration); 501 502 return carrier; 503 } 504 #endif 505 /* 506 * set carrier frequency 507 * 508 * set carrier on 2 registers: CP & CC 509 * always set CP as 0x81 510 * set CC by SPEC, CC = 3MHz/carrier - 1 511 */ 512 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) 513 { 514 struct nvt_dev *nvt = dev->priv; 515 u16 val; 516 517 if (carrier == 0) 518 return -EINVAL; 519 520 nvt_cir_reg_write(nvt, 1, CIR_CP); 521 val = 3000000 / (carrier) - 1; 522 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); 523 524 nvt_dbg("cp: 0x%x cc: 0x%x\n", 525 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); 526 527 return 0; 528 } 529 530 /* 531 * nvt_tx_ir 532 * 533 * 1) clean TX fifo first (handled by AP) 534 * 2) copy data from user space 535 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU 536 * 4) send 9 packets to TX FIFO to open TTR 537 * in interrupt_handler: 538 * 5) send all data out 539 * go back to write(): 540 * 6) disable TX interrupts, re-enable RX interupts 541 * 542 * The key problem of this function is user space data may larger than 543 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to 544 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf 545 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to 546 * set TXFCONT as 0xff, until buf_count less than 0xff. 547 */ 548 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n) 549 { 550 struct nvt_dev *nvt = dev->priv; 551 unsigned long flags; 552 unsigned int i; 553 u8 iren; 554 int ret; 555 556 spin_lock_irqsave(&nvt->tx.lock, flags); 557 558 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n); 559 nvt->tx.buf_count = (ret * sizeof(unsigned)); 560 561 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); 562 563 nvt->tx.cur_buf_num = 0; 564 565 /* save currently enabled interrupts */ 566 iren = nvt_cir_reg_read(nvt, CIR_IREN); 567 568 /* now disable all interrupts, save TFU & TTR */ 569 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); 570 571 nvt->tx.tx_state = ST_TX_REPLY; 572 573 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | 574 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); 575 576 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ 577 for (i = 0; i < 9; i++) 578 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); 579 580 spin_unlock_irqrestore(&nvt->tx.lock, flags); 581 582 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); 583 584 spin_lock_irqsave(&nvt->tx.lock, flags); 585 nvt->tx.tx_state = ST_TX_NONE; 586 spin_unlock_irqrestore(&nvt->tx.lock, flags); 587 588 /* restore enabled interrupts to prior state */ 589 nvt_cir_reg_write(nvt, iren, CIR_IREN); 590 591 return ret; 592 } 593 594 /* dump contents of the last rx buffer we got from the hw rx fifo */ 595 static void nvt_dump_rx_buf(struct nvt_dev *nvt) 596 { 597 int i; 598 599 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); 600 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) 601 printk(KERN_CONT "0x%02x ", nvt->buf[i]); 602 printk(KERN_CONT "\n"); 603 } 604 605 /* 606 * Process raw data in rx driver buffer, store it in raw IR event kfifo, 607 * trigger decode when appropriate. 608 * 609 * We get IR data samples one byte at a time. If the msb is set, its a pulse, 610 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD 611 * (default 50us) intervals for that pulse/space. A discrete signal is 612 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 613 * to signal more IR coming (repeats) or end of IR, respectively. We store 614 * sample data in the raw event kfifo until we see 0x7<something> (except f) 615 * or 0x80, at which time, we trigger a decode operation. 616 */ 617 static void nvt_process_rx_ir_data(struct nvt_dev *nvt) 618 { 619 DEFINE_IR_RAW_EVENT(rawir); 620 u8 sample; 621 int i; 622 623 nvt_dbg_verbose("%s firing", __func__); 624 625 if (debug) 626 nvt_dump_rx_buf(nvt); 627 628 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); 629 630 init_ir_raw_event(&rawir); 631 632 for (i = 0; i < nvt->pkts; i++) { 633 sample = nvt->buf[i]; 634 635 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); 636 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) 637 * SAMPLE_PERIOD); 638 639 nvt_dbg("Storing %s with duration %d", 640 rawir.pulse ? "pulse" : "space", rawir.duration); 641 642 ir_raw_event_store_with_filter(nvt->rdev, &rawir); 643 644 /* 645 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE 646 * indicates end of IR signal, but new data incoming. In both 647 * cases, it means we're ready to call ir_raw_event_handle 648 */ 649 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) { 650 nvt_dbg("Calling ir_raw_event_handle (signal end)\n"); 651 ir_raw_event_handle(nvt->rdev); 652 } 653 } 654 655 nvt->pkts = 0; 656 657 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n"); 658 ir_raw_event_handle(nvt->rdev); 659 660 nvt_dbg_verbose("%s done", __func__); 661 } 662 663 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) 664 { 665 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!"); 666 667 nvt->pkts = 0; 668 nvt_clear_cir_fifo(nvt); 669 ir_raw_event_reset(nvt->rdev); 670 } 671 672 /* copy data from hardware rx fifo into driver buffer */ 673 static void nvt_get_rx_ir_data(struct nvt_dev *nvt) 674 { 675 unsigned long flags; 676 u8 fifocount, val; 677 unsigned int b_idx; 678 bool overrun = false; 679 int i; 680 681 /* Get count of how many bytes to read from RX FIFO */ 682 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); 683 /* if we get 0xff, probably means the logical dev is disabled */ 684 if (fifocount == 0xff) 685 return; 686 /* watch out for a fifo overrun condition */ 687 else if (fifocount > RX_BUF_LEN) { 688 overrun = true; 689 fifocount = RX_BUF_LEN; 690 } 691 692 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); 693 694 spin_lock_irqsave(&nvt->nvt_lock, flags); 695 696 b_idx = nvt->pkts; 697 698 /* This should never happen, but lets check anyway... */ 699 if (b_idx + fifocount > RX_BUF_LEN) { 700 nvt_process_rx_ir_data(nvt); 701 b_idx = 0; 702 } 703 704 /* Read fifocount bytes from CIR Sample RX FIFO register */ 705 for (i = 0; i < fifocount; i++) { 706 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO); 707 nvt->buf[b_idx + i] = val; 708 } 709 710 nvt->pkts += fifocount; 711 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); 712 713 nvt_process_rx_ir_data(nvt); 714 715 if (overrun) 716 nvt_handle_rx_fifo_overrun(nvt); 717 718 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 719 } 720 721 static void nvt_cir_log_irqs(u8 status, u8 iren) 722 { 723 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", 724 status, iren, 725 status & CIR_IRSTS_RDR ? " RDR" : "", 726 status & CIR_IRSTS_RTR ? " RTR" : "", 727 status & CIR_IRSTS_PE ? " PE" : "", 728 status & CIR_IRSTS_RFO ? " RFO" : "", 729 status & CIR_IRSTS_TE ? " TE" : "", 730 status & CIR_IRSTS_TTR ? " TTR" : "", 731 status & CIR_IRSTS_TFU ? " TFU" : "", 732 status & CIR_IRSTS_GH ? " GH" : "", 733 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | 734 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | 735 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); 736 } 737 738 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) 739 { 740 unsigned long flags; 741 bool tx_inactive; 742 u8 tx_state; 743 744 spin_lock_irqsave(&nvt->tx.lock, flags); 745 tx_state = nvt->tx.tx_state; 746 spin_unlock_irqrestore(&nvt->tx.lock, flags); 747 748 tx_inactive = (tx_state == ST_TX_NONE); 749 750 return tx_inactive; 751 } 752 753 /* interrupt service routine for incoming and outgoing CIR data */ 754 static irqreturn_t nvt_cir_isr(int irq, void *data) 755 { 756 struct nvt_dev *nvt = data; 757 u8 status, iren, cur_state; 758 unsigned long flags; 759 760 nvt_dbg_verbose("%s firing", __func__); 761 762 nvt_efm_enable(nvt); 763 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 764 nvt_efm_disable(nvt); 765 766 /* 767 * Get IR Status register contents. Write 1 to ack/clear 768 * 769 * bit: reg name - description 770 * 7: CIR_IRSTS_RDR - RX Data Ready 771 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach 772 * 5: CIR_IRSTS_PE - Packet End 773 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) 774 * 3: CIR_IRSTS_TE - TX FIFO Empty 775 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach 776 * 1: CIR_IRSTS_TFU - TX FIFO Underrun 777 * 0: CIR_IRSTS_GH - Min Length Detected 778 */ 779 status = nvt_cir_reg_read(nvt, CIR_IRSTS); 780 if (!status) { 781 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); 782 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 783 return IRQ_RETVAL(IRQ_NONE); 784 } 785 786 /* ack/clear all irq flags we've got */ 787 nvt_cir_reg_write(nvt, status, CIR_IRSTS); 788 nvt_cir_reg_write(nvt, 0, CIR_IRSTS); 789 790 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */ 791 iren = nvt_cir_reg_read(nvt, CIR_IREN); 792 if (!iren) { 793 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__); 794 return IRQ_RETVAL(IRQ_NONE); 795 } 796 797 if (debug) 798 nvt_cir_log_irqs(status, iren); 799 800 if (status & CIR_IRSTS_RTR) { 801 /* FIXME: add code for study/learn mode */ 802 /* We only do rx if not tx'ing */ 803 if (nvt_cir_tx_inactive(nvt)) 804 nvt_get_rx_ir_data(nvt); 805 } 806 807 if (status & CIR_IRSTS_PE) { 808 if (nvt_cir_tx_inactive(nvt)) 809 nvt_get_rx_ir_data(nvt); 810 811 spin_lock_irqsave(&nvt->nvt_lock, flags); 812 813 cur_state = nvt->study_state; 814 815 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 816 817 if (cur_state == ST_STUDY_NONE) 818 nvt_clear_cir_fifo(nvt); 819 } 820 821 if (status & CIR_IRSTS_TE) 822 nvt_clear_tx_fifo(nvt); 823 824 if (status & CIR_IRSTS_TTR) { 825 unsigned int pos, count; 826 u8 tmp; 827 828 spin_lock_irqsave(&nvt->tx.lock, flags); 829 830 pos = nvt->tx.cur_buf_num; 831 count = nvt->tx.buf_count; 832 833 /* Write data into the hardware tx fifo while pos < count */ 834 if (pos < count) { 835 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); 836 nvt->tx.cur_buf_num++; 837 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ 838 } else { 839 tmp = nvt_cir_reg_read(nvt, CIR_IREN); 840 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); 841 } 842 843 spin_unlock_irqrestore(&nvt->tx.lock, flags); 844 845 } 846 847 if (status & CIR_IRSTS_TFU) { 848 spin_lock_irqsave(&nvt->tx.lock, flags); 849 if (nvt->tx.tx_state == ST_TX_REPLY) { 850 nvt->tx.tx_state = ST_TX_REQUEST; 851 wake_up(&nvt->tx.queue); 852 } 853 spin_unlock_irqrestore(&nvt->tx.lock, flags); 854 } 855 856 nvt_dbg_verbose("%s done", __func__); 857 return IRQ_RETVAL(IRQ_HANDLED); 858 } 859 860 /* Interrupt service routine for CIR Wake */ 861 static irqreturn_t nvt_cir_wake_isr(int irq, void *data) 862 { 863 u8 status, iren, val; 864 struct nvt_dev *nvt = data; 865 unsigned long flags; 866 867 nvt_dbg_wake("%s firing", __func__); 868 869 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS); 870 if (!status) 871 return IRQ_RETVAL(IRQ_NONE); 872 873 if (status & CIR_WAKE_IRSTS_IR_PENDING) 874 nvt_clear_cir_wake_fifo(nvt); 875 876 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS); 877 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS); 878 879 /* Interrupt may be shared with CIR, bail if Wake not enabled */ 880 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN); 881 if (!iren) { 882 nvt_dbg_wake("%s exiting, wake not enabled", __func__); 883 return IRQ_RETVAL(IRQ_HANDLED); 884 } 885 886 if ((status & CIR_WAKE_IRSTS_PE) && 887 (nvt->wake_state == ST_WAKE_START)) { 888 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) { 889 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); 890 nvt_dbg("setting wake up key: 0x%x", val); 891 } 892 893 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); 894 spin_lock_irqsave(&nvt->nvt_lock, flags); 895 nvt->wake_state = ST_WAKE_FINISH; 896 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 897 } 898 899 nvt_dbg_wake("%s done", __func__); 900 return IRQ_RETVAL(IRQ_HANDLED); 901 } 902 903 static void nvt_enable_cir(struct nvt_dev *nvt) 904 { 905 /* set function enable flags */ 906 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | 907 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, 908 CIR_IRCON); 909 910 nvt_efm_enable(nvt); 911 912 /* enable the CIR logical device */ 913 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 914 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 915 916 nvt_efm_disable(nvt); 917 918 /* clear all pending interrupts */ 919 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 920 921 /* enable interrupts */ 922 nvt_set_cir_iren(nvt); 923 } 924 925 static void nvt_disable_cir(struct nvt_dev *nvt) 926 { 927 /* disable CIR interrupts */ 928 nvt_cir_reg_write(nvt, 0, CIR_IREN); 929 930 /* clear any and all pending interrupts */ 931 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); 932 933 /* clear all function enable flags */ 934 nvt_cir_reg_write(nvt, 0, CIR_IRCON); 935 936 /* clear hardware rx and tx fifos */ 937 nvt_clear_cir_fifo(nvt); 938 nvt_clear_tx_fifo(nvt); 939 940 nvt_efm_enable(nvt); 941 942 /* disable the CIR logical device */ 943 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 944 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); 945 946 nvt_efm_disable(nvt); 947 } 948 949 static int nvt_open(struct rc_dev *dev) 950 { 951 struct nvt_dev *nvt = dev->priv; 952 unsigned long flags; 953 954 spin_lock_irqsave(&nvt->nvt_lock, flags); 955 nvt_enable_cir(nvt); 956 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 957 958 return 0; 959 } 960 961 static void nvt_close(struct rc_dev *dev) 962 { 963 struct nvt_dev *nvt = dev->priv; 964 unsigned long flags; 965 966 spin_lock_irqsave(&nvt->nvt_lock, flags); 967 nvt_disable_cir(nvt); 968 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 969 } 970 971 /* Allocate memory, probe hardware, and initialize everything */ 972 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) 973 { 974 struct nvt_dev *nvt; 975 struct rc_dev *rdev; 976 int ret = -ENOMEM; 977 978 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL); 979 if (!nvt) 980 return ret; 981 982 /* input device for IR remote (and tx) */ 983 rdev = rc_allocate_device(); 984 if (!rdev) 985 goto exit_free_dev_rdev; 986 987 ret = -ENODEV; 988 /* activate pnp device */ 989 if (pnp_activate_dev(pdev) < 0) { 990 dev_err(&pdev->dev, "Could not activate PNP device!\n"); 991 goto exit_free_dev_rdev; 992 } 993 994 /* validate pnp resources */ 995 if (!pnp_port_valid(pdev, 0) || 996 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { 997 dev_err(&pdev->dev, "IR PNP Port not valid!\n"); 998 goto exit_free_dev_rdev; 999 } 1000 1001 if (!pnp_irq_valid(pdev, 0)) { 1002 dev_err(&pdev->dev, "PNP IRQ not valid!\n"); 1003 goto exit_free_dev_rdev; 1004 } 1005 1006 if (!pnp_port_valid(pdev, 1) || 1007 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { 1008 dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); 1009 goto exit_free_dev_rdev; 1010 } 1011 1012 nvt->cir_addr = pnp_port_start(pdev, 0); 1013 nvt->cir_irq = pnp_irq(pdev, 0); 1014 1015 nvt->cir_wake_addr = pnp_port_start(pdev, 1); 1016 /* irq is always shared between cir and cir wake */ 1017 nvt->cir_wake_irq = nvt->cir_irq; 1018 1019 nvt->cr_efir = CR_EFIR; 1020 nvt->cr_efdr = CR_EFDR; 1021 1022 spin_lock_init(&nvt->nvt_lock); 1023 spin_lock_init(&nvt->tx.lock); 1024 1025 pnp_set_drvdata(pdev, nvt); 1026 nvt->pdev = pdev; 1027 1028 init_waitqueue_head(&nvt->tx.queue); 1029 1030 ret = nvt_hw_detect(nvt); 1031 if (ret) 1032 goto exit_free_dev_rdev; 1033 1034 /* Initialize CIR & CIR Wake Logical Devices */ 1035 nvt_efm_enable(nvt); 1036 nvt_cir_ldev_init(nvt); 1037 nvt_cir_wake_ldev_init(nvt); 1038 nvt_efm_disable(nvt); 1039 1040 /* Initialize CIR & CIR Wake Config Registers */ 1041 nvt_cir_regs_init(nvt); 1042 nvt_cir_wake_regs_init(nvt); 1043 1044 /* Set up the rc device */ 1045 rdev->priv = nvt; 1046 rdev->driver_type = RC_DRIVER_IR_RAW; 1047 rc_set_allowed_protocols(rdev, RC_BIT_ALL); 1048 rdev->open = nvt_open; 1049 rdev->close = nvt_close; 1050 rdev->tx_ir = nvt_tx_ir; 1051 rdev->s_tx_carrier = nvt_set_tx_carrier; 1052 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; 1053 rdev->input_phys = "nuvoton/cir0"; 1054 rdev->input_id.bustype = BUS_HOST; 1055 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; 1056 rdev->input_id.product = nvt->chip_major; 1057 rdev->input_id.version = nvt->chip_minor; 1058 rdev->dev.parent = &pdev->dev; 1059 rdev->driver_name = NVT_DRIVER_NAME; 1060 rdev->map_name = RC_MAP_RC6_MCE; 1061 rdev->timeout = MS_TO_NS(100); 1062 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ 1063 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); 1064 #if 0 1065 rdev->min_timeout = XYZ; 1066 rdev->max_timeout = XYZ; 1067 /* tx bits */ 1068 rdev->tx_resolution = XYZ; 1069 #endif 1070 nvt->rdev = rdev; 1071 1072 ret = rc_register_device(rdev); 1073 if (ret) 1074 goto exit_free_dev_rdev; 1075 1076 ret = -EBUSY; 1077 /* now claim resources */ 1078 if (!request_region(nvt->cir_addr, 1079 CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) 1080 goto exit_unregister_device; 1081 1082 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED, 1083 NVT_DRIVER_NAME, (void *)nvt)) 1084 goto exit_release_cir_addr; 1085 1086 if (!request_region(nvt->cir_wake_addr, 1087 CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) 1088 goto exit_free_irq; 1089 1090 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED, 1091 NVT_DRIVER_NAME, (void *)nvt)) 1092 goto exit_release_cir_wake_addr; 1093 1094 device_init_wakeup(&pdev->dev, true); 1095 1096 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n"); 1097 if (debug) { 1098 cir_dump_regs(nvt); 1099 cir_wake_dump_regs(nvt); 1100 } 1101 1102 return 0; 1103 1104 exit_release_cir_wake_addr: 1105 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); 1106 exit_free_irq: 1107 free_irq(nvt->cir_irq, nvt); 1108 exit_release_cir_addr: 1109 release_region(nvt->cir_addr, CIR_IOREG_LENGTH); 1110 exit_unregister_device: 1111 rc_unregister_device(rdev); 1112 rdev = NULL; 1113 exit_free_dev_rdev: 1114 rc_free_device(rdev); 1115 kfree(nvt); 1116 1117 return ret; 1118 } 1119 1120 static void nvt_remove(struct pnp_dev *pdev) 1121 { 1122 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1123 unsigned long flags; 1124 1125 spin_lock_irqsave(&nvt->nvt_lock, flags); 1126 /* disable CIR */ 1127 nvt_cir_reg_write(nvt, 0, CIR_IREN); 1128 nvt_disable_cir(nvt); 1129 /* enable CIR Wake (for IR power-on) */ 1130 nvt_enable_wake(nvt); 1131 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 1132 1133 /* free resources */ 1134 free_irq(nvt->cir_irq, nvt); 1135 free_irq(nvt->cir_wake_irq, nvt); 1136 release_region(nvt->cir_addr, CIR_IOREG_LENGTH); 1137 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); 1138 1139 rc_unregister_device(nvt->rdev); 1140 1141 kfree(nvt); 1142 } 1143 1144 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) 1145 { 1146 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1147 unsigned long flags; 1148 1149 nvt_dbg("%s called", __func__); 1150 1151 /* zero out misc state tracking */ 1152 spin_lock_irqsave(&nvt->nvt_lock, flags); 1153 nvt->study_state = ST_STUDY_NONE; 1154 nvt->wake_state = ST_WAKE_NONE; 1155 spin_unlock_irqrestore(&nvt->nvt_lock, flags); 1156 1157 spin_lock_irqsave(&nvt->tx.lock, flags); 1158 nvt->tx.tx_state = ST_TX_NONE; 1159 spin_unlock_irqrestore(&nvt->tx.lock, flags); 1160 1161 /* disable all CIR interrupts */ 1162 nvt_cir_reg_write(nvt, 0, CIR_IREN); 1163 1164 nvt_efm_enable(nvt); 1165 1166 /* disable cir logical dev */ 1167 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 1168 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); 1169 1170 nvt_efm_disable(nvt); 1171 1172 /* make sure wake is enabled */ 1173 nvt_enable_wake(nvt); 1174 1175 return 0; 1176 } 1177 1178 static int nvt_resume(struct pnp_dev *pdev) 1179 { 1180 int ret = 0; 1181 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1182 1183 nvt_dbg("%s called", __func__); 1184 1185 /* open interrupt */ 1186 nvt_set_cir_iren(nvt); 1187 1188 /* Enable CIR logical device */ 1189 nvt_efm_enable(nvt); 1190 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 1191 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); 1192 1193 nvt_efm_disable(nvt); 1194 1195 nvt_cir_regs_init(nvt); 1196 nvt_cir_wake_regs_init(nvt); 1197 1198 return ret; 1199 } 1200 1201 static void nvt_shutdown(struct pnp_dev *pdev) 1202 { 1203 struct nvt_dev *nvt = pnp_get_drvdata(pdev); 1204 nvt_enable_wake(nvt); 1205 } 1206 1207 static const struct pnp_device_id nvt_ids[] = { 1208 { "WEC0530", 0 }, /* CIR */ 1209 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ 1210 { "", 0 }, 1211 }; 1212 1213 static struct pnp_driver nvt_driver = { 1214 .name = NVT_DRIVER_NAME, 1215 .id_table = nvt_ids, 1216 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, 1217 .probe = nvt_probe, 1218 .remove = nvt_remove, 1219 .suspend = nvt_suspend, 1220 .resume = nvt_resume, 1221 .shutdown = nvt_shutdown, 1222 }; 1223 1224 static int nvt_init(void) 1225 { 1226 return pnp_register_driver(&nvt_driver); 1227 } 1228 1229 static void nvt_exit(void) 1230 { 1231 pnp_unregister_driver(&nvt_driver); 1232 } 1233 1234 module_param(debug, int, S_IRUGO | S_IWUSR); 1235 MODULE_PARM_DESC(debug, "Enable debugging output"); 1236 1237 MODULE_DEVICE_TABLE(pnp, nvt_ids); 1238 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); 1239 1240 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); 1241 MODULE_LICENSE("GPL"); 1242 1243 module_init(nvt_init); 1244 module_exit(nvt_exit); 1245