1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Mediatek IR Receiver Controller 4 * 5 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <linux/reset.h> 13 #include <media/rc-core.h> 14 15 #define MTK_IR_DEV KBUILD_MODNAME 16 17 /* Register to enable PWM and IR */ 18 #define MTK_CONFIG_HIGH_REG 0x0c 19 20 /* Bit to enable IR pulse width detection */ 21 #define MTK_PWM_EN BIT(13) 22 23 /* 24 * Register to setting ok count whose unit based on hardware sampling period 25 * indicating IR receiving completion and then making IRQ fires 26 */ 27 #define MTK_OK_COUNT_MASK (GENMASK(22, 16)) 28 #define MTK_OK_COUNT(x) ((x) << 16) 29 30 /* Bit to enable IR hardware function */ 31 #define MTK_IR_EN BIT(0) 32 33 /* Bit to restart IR receiving */ 34 #define MTK_IRCLR BIT(0) 35 36 /* Fields containing pulse width data */ 37 #define MTK_WIDTH_MASK (GENMASK(7, 0)) 38 39 /* IR threshold */ 40 #define MTK_IRTHD 0x14 41 #define MTK_DG_CNT_MASK (GENMASK(12, 8)) 42 #define MTK_DG_CNT(x) ((x) << 8) 43 44 /* Bit to enable interrupt */ 45 #define MTK_IRINT_EN BIT(0) 46 47 /* Bit to clear interrupt status */ 48 #define MTK_IRINT_CLR BIT(0) 49 50 /* Maximum count of samples */ 51 #define MTK_MAX_SAMPLES 0xff 52 /* Indicate the end of IR message */ 53 #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0) 54 /* Number of registers to record the pulse width */ 55 #define MTK_CHKDATA_SZ 17 56 /* Sample period in us */ 57 #define MTK_IR_SAMPLE 46 58 59 enum mtk_fields { 60 /* Register to setting software sampling period */ 61 MTK_CHK_PERIOD, 62 /* Register to setting hardware sampling period */ 63 MTK_HW_PERIOD, 64 }; 65 66 enum mtk_regs { 67 /* Register to clear state of state machine */ 68 MTK_IRCLR_REG, 69 /* Register containing pulse width data */ 70 MTK_CHKDATA_REG, 71 /* Register to enable IR interrupt */ 72 MTK_IRINT_EN_REG, 73 /* Register to ack IR interrupt */ 74 MTK_IRINT_CLR_REG 75 }; 76 77 static const u32 mt7623_regs[] = { 78 [MTK_IRCLR_REG] = 0x20, 79 [MTK_CHKDATA_REG] = 0x88, 80 [MTK_IRINT_EN_REG] = 0xcc, 81 [MTK_IRINT_CLR_REG] = 0xd0, 82 }; 83 84 static const u32 mt7622_regs[] = { 85 [MTK_IRCLR_REG] = 0x18, 86 [MTK_CHKDATA_REG] = 0x30, 87 [MTK_IRINT_EN_REG] = 0x1c, 88 [MTK_IRINT_CLR_REG] = 0x20, 89 }; 90 91 struct mtk_field_type { 92 u32 reg; 93 u8 offset; 94 u32 mask; 95 }; 96 97 /* 98 * struct mtk_ir_data - This is the structure holding all differences among 99 various hardwares 100 * @regs: The pointer to the array holding registers offset 101 * @fields: The pointer to the array holding fields location 102 * @div: The internal divisor for the based reference clock 103 * @ok_count: The count indicating the completion of IR data 104 * receiving when count is reached 105 * @hw_period: The value indicating the hardware sampling period 106 */ 107 struct mtk_ir_data { 108 const u32 *regs; 109 const struct mtk_field_type *fields; 110 u8 div; 111 u8 ok_count; 112 u32 hw_period; 113 }; 114 115 static const struct mtk_field_type mt7623_fields[] = { 116 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)}, 117 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)}, 118 }; 119 120 static const struct mtk_field_type mt7622_fields[] = { 121 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)}, 122 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)}, 123 }; 124 125 /* 126 * struct mtk_ir - This is the main datasructure for holding the state 127 * of the driver 128 * @dev: The device pointer 129 * @rc: The rc instrance 130 * @base: The mapped register i/o base 131 * @irq: The IRQ that we are using 132 * @clk: The clock that IR internal is using 133 * @bus: The clock that software decoder is using 134 * @data: Holding specific data for vaious platform 135 */ 136 struct mtk_ir { 137 struct device *dev; 138 struct rc_dev *rc; 139 void __iomem *base; 140 int irq; 141 struct clk *clk; 142 struct clk *bus; 143 const struct mtk_ir_data *data; 144 }; 145 146 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i) 147 { 148 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i; 149 } 150 151 static inline u32 mtk_chk_period(struct mtk_ir *ir) 152 { 153 u32 val; 154 155 /* 156 * Period for software decoder used in the 157 * unit of raw software sampling 158 */ 159 val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus), 160 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE); 161 162 dev_dbg(ir->dev, "@pwm clk = \t%lu\n", 163 clk_get_rate(ir->bus) / ir->data->div); 164 dev_dbg(ir->dev, "@chkperiod = %08x\n", val); 165 166 return val; 167 } 168 169 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) 170 { 171 u32 tmp; 172 173 tmp = __raw_readl(ir->base + reg); 174 tmp = (tmp & ~mask) | val; 175 __raw_writel(tmp, ir->base + reg); 176 } 177 178 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) 179 { 180 __raw_writel(val, ir->base + reg); 181 } 182 183 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg) 184 { 185 return __raw_readl(ir->base + reg); 186 } 187 188 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask) 189 { 190 u32 val; 191 192 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); 193 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); 194 } 195 196 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask) 197 { 198 u32 val; 199 200 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); 201 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); 202 } 203 204 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id) 205 { 206 struct ir_raw_event rawir = {}; 207 struct mtk_ir *ir = dev_id; 208 u32 i, j, val; 209 u8 wid; 210 211 /* 212 * Each pulse and space is encoded as a single byte, each byte 213 * alternating between pulse and space. If a pulse or space is longer 214 * than can be encoded in a single byte, it is encoded as the maximum 215 * value 0xff. 216 * 217 * If a space is longer than ok_count (about 23ms), the value is 218 * encoded as zero, and all following bytes are zero. Any IR that 219 * follows will be presented in the next interrupt. 220 * 221 * If there are more than 68 (=MTK_CHKDATA_SZ * 4) pulses and spaces, 222 * then the only the first 68 will be presented; the rest is lost. 223 */ 224 225 /* Handle all pulse and space IR controller captures */ 226 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) { 227 val = mtk_r32(ir, mtk_chkdata_reg(ir, i)); 228 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); 229 230 for (j = 0 ; j < 4 ; j++) { 231 wid = val & MTK_WIDTH_MASK; 232 val >>= 8; 233 rawir.pulse = !rawir.pulse; 234 rawir.duration = wid * (MTK_IR_SAMPLE + 1); 235 ir_raw_event_store_with_filter(ir->rc, &rawir); 236 } 237 } 238 239 /* 240 * The maximum number of edges the IR controller can 241 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages 242 * is over the limit, the last incomplete IR message would 243 * be appended trailing space and still would be sent into 244 * ir-rc-raw to decode. That helps it is possible that it 245 * has enough information to decode a scancode even if the 246 * trailing end of the message is missing. 247 */ 248 if (!MTK_IR_END(wid, rawir.pulse)) { 249 rawir.pulse = false; 250 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); 251 ir_raw_event_store_with_filter(ir->rc, &rawir); 252 } 253 254 ir_raw_event_handle(ir->rc); 255 256 /* 257 * Restart controller for the next receive that would 258 * clear up all CHKDATA registers 259 */ 260 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]); 261 262 /* Clear interrupt status */ 263 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, 264 ir->data->regs[MTK_IRINT_CLR_REG]); 265 266 return IRQ_HANDLED; 267 } 268 269 static const struct mtk_ir_data mt7623_data = { 270 .regs = mt7623_regs, 271 .fields = mt7623_fields, 272 .ok_count = 3, 273 .hw_period = 0xff, 274 .div = 4, 275 }; 276 277 static const struct mtk_ir_data mt7622_data = { 278 .regs = mt7622_regs, 279 .fields = mt7622_fields, 280 .ok_count = 3, 281 .hw_period = 0xffff, 282 .div = 32, 283 }; 284 285 static const struct of_device_id mtk_ir_match[] = { 286 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data}, 287 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data}, 288 {}, 289 }; 290 MODULE_DEVICE_TABLE(of, mtk_ir_match); 291 292 static int mtk_ir_probe(struct platform_device *pdev) 293 { 294 struct device *dev = &pdev->dev; 295 struct device_node *dn = dev->of_node; 296 struct mtk_ir *ir; 297 u32 val; 298 int ret = 0; 299 const char *map_name; 300 301 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL); 302 if (!ir) 303 return -ENOMEM; 304 305 ir->dev = dev; 306 ir->data = of_device_get_match_data(dev); 307 308 ir->clk = devm_clk_get(dev, "clk"); 309 if (IS_ERR(ir->clk)) { 310 dev_err(dev, "failed to get a ir clock.\n"); 311 return PTR_ERR(ir->clk); 312 } 313 314 ir->bus = devm_clk_get(dev, "bus"); 315 if (IS_ERR(ir->bus)) { 316 /* 317 * For compatibility with older device trees try unnamed 318 * ir->bus uses the same clock as ir->clock. 319 */ 320 ir->bus = ir->clk; 321 } 322 323 ir->base = devm_platform_ioremap_resource(pdev, 0); 324 if (IS_ERR(ir->base)) 325 return PTR_ERR(ir->base); 326 327 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); 328 if (!ir->rc) { 329 dev_err(dev, "failed to allocate device\n"); 330 return -ENOMEM; 331 } 332 333 ir->rc->priv = ir; 334 ir->rc->device_name = MTK_IR_DEV; 335 ir->rc->input_phys = MTK_IR_DEV "/input0"; 336 ir->rc->input_id.bustype = BUS_HOST; 337 ir->rc->input_id.vendor = 0x0001; 338 ir->rc->input_id.product = 0x0001; 339 ir->rc->input_id.version = 0x0001; 340 map_name = of_get_property(dn, "linux,rc-map-name", NULL); 341 ir->rc->map_name = map_name ?: RC_MAP_EMPTY; 342 ir->rc->dev.parent = dev; 343 ir->rc->driver_name = MTK_IR_DEV; 344 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 345 ir->rc->rx_resolution = MTK_IR_SAMPLE; 346 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); 347 348 ret = devm_rc_register_device(dev, ir->rc); 349 if (ret) { 350 dev_err(dev, "failed to register rc device\n"); 351 return ret; 352 } 353 354 platform_set_drvdata(pdev, ir); 355 356 ir->irq = platform_get_irq(pdev, 0); 357 if (ir->irq < 0) 358 return -ENODEV; 359 360 if (clk_prepare_enable(ir->clk)) { 361 dev_err(dev, "try to enable ir_clk failed\n"); 362 return -EINVAL; 363 } 364 365 if (clk_prepare_enable(ir->bus)) { 366 dev_err(dev, "try to enable ir_clk failed\n"); 367 ret = -EINVAL; 368 goto exit_clkdisable_clk; 369 } 370 371 /* 372 * Enable interrupt after proper hardware 373 * setup and IRQ handler registration 374 */ 375 mtk_irq_disable(ir, MTK_IRINT_EN); 376 377 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir); 378 if (ret) { 379 dev_err(dev, "failed request irq\n"); 380 goto exit_clkdisable_bus; 381 } 382 383 /* 384 * Setup software sample period as the reference of software decoder 385 */ 386 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & 387 ir->data->fields[MTK_CHK_PERIOD].mask; 388 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, 389 ir->data->fields[MTK_CHK_PERIOD].reg); 390 391 /* 392 * Setup hardware sampling period used to setup the proper timeout for 393 * indicating end of IR receiving completion 394 */ 395 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & 396 ir->data->fields[MTK_HW_PERIOD].mask; 397 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, 398 ir->data->fields[MTK_HW_PERIOD].reg); 399 400 /* Set de-glitch counter */ 401 mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD); 402 403 /* Enable IR and PWM */ 404 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG) & ~MTK_OK_COUNT_MASK; 405 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; 406 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG); 407 408 mtk_irq_enable(ir, MTK_IRINT_EN); 409 410 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n", 411 MTK_IR_SAMPLE); 412 413 return 0; 414 415 exit_clkdisable_bus: 416 clk_disable_unprepare(ir->bus); 417 exit_clkdisable_clk: 418 clk_disable_unprepare(ir->clk); 419 420 return ret; 421 } 422 423 static int mtk_ir_remove(struct platform_device *pdev) 424 { 425 struct mtk_ir *ir = platform_get_drvdata(pdev); 426 427 /* 428 * Avoid contention between remove handler and 429 * IRQ handler so that disabling IR interrupt and 430 * waiting for pending IRQ handler to complete 431 */ 432 mtk_irq_disable(ir, MTK_IRINT_EN); 433 synchronize_irq(ir->irq); 434 435 clk_disable_unprepare(ir->bus); 436 clk_disable_unprepare(ir->clk); 437 438 return 0; 439 } 440 441 static struct platform_driver mtk_ir_driver = { 442 .probe = mtk_ir_probe, 443 .remove = mtk_ir_remove, 444 .driver = { 445 .name = MTK_IR_DEV, 446 .of_match_table = mtk_ir_match, 447 }, 448 }; 449 450 module_platform_driver(mtk_ir_driver); 451 452 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver"); 453 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 454 MODULE_LICENSE("GPL"); 455