1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Mediatek IR Receiver Controller 4 * 5 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <linux/reset.h> 13 #include <media/rc-core.h> 14 15 #define MTK_IR_DEV KBUILD_MODNAME 16 17 /* Register to enable PWM and IR */ 18 #define MTK_CONFIG_HIGH_REG 0x0c 19 20 /* Bit to enable IR pulse width detection */ 21 #define MTK_PWM_EN BIT(13) 22 23 /* 24 * Register to setting ok count whose unit based on hardware sampling period 25 * indicating IR receiving completion and then making IRQ fires 26 */ 27 #define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16) 28 29 /* Bit to enable IR hardware function */ 30 #define MTK_IR_EN BIT(0) 31 32 /* Bit to restart IR receiving */ 33 #define MTK_IRCLR BIT(0) 34 35 /* Fields containing pulse width data */ 36 #define MTK_WIDTH_MASK (GENMASK(7, 0)) 37 38 /* Bit to enable interrupt */ 39 #define MTK_IRINT_EN BIT(0) 40 41 /* Bit to clear interrupt status */ 42 #define MTK_IRINT_CLR BIT(0) 43 44 /* Maximum count of samples */ 45 #define MTK_MAX_SAMPLES 0xff 46 /* Indicate the end of IR message */ 47 #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0) 48 /* Number of registers to record the pulse width */ 49 #define MTK_CHKDATA_SZ 17 50 /* Sample period in ns */ 51 #define MTK_IR_SAMPLE 46000 52 53 enum mtk_fields { 54 /* Register to setting software sampling period */ 55 MTK_CHK_PERIOD, 56 /* Register to setting hardware sampling period */ 57 MTK_HW_PERIOD, 58 }; 59 60 enum mtk_regs { 61 /* Register to clear state of state machine */ 62 MTK_IRCLR_REG, 63 /* Register containing pulse width data */ 64 MTK_CHKDATA_REG, 65 /* Register to enable IR interrupt */ 66 MTK_IRINT_EN_REG, 67 /* Register to ack IR interrupt */ 68 MTK_IRINT_CLR_REG 69 }; 70 71 static const u32 mt7623_regs[] = { 72 [MTK_IRCLR_REG] = 0x20, 73 [MTK_CHKDATA_REG] = 0x88, 74 [MTK_IRINT_EN_REG] = 0xcc, 75 [MTK_IRINT_CLR_REG] = 0xd0, 76 }; 77 78 static const u32 mt7622_regs[] = { 79 [MTK_IRCLR_REG] = 0x18, 80 [MTK_CHKDATA_REG] = 0x30, 81 [MTK_IRINT_EN_REG] = 0x1c, 82 [MTK_IRINT_CLR_REG] = 0x20, 83 }; 84 85 struct mtk_field_type { 86 u32 reg; 87 u8 offset; 88 u32 mask; 89 }; 90 91 /* 92 * struct mtk_ir_data - This is the structure holding all differences among 93 various hardwares 94 * @regs: The pointer to the array holding registers offset 95 * @fields: The pointer to the array holding fields location 96 * @div: The internal divisor for the based reference clock 97 * @ok_count: The count indicating the completion of IR data 98 * receiving when count is reached 99 * @hw_period: The value indicating the hardware sampling period 100 */ 101 struct mtk_ir_data { 102 const u32 *regs; 103 const struct mtk_field_type *fields; 104 u8 div; 105 u8 ok_count; 106 u32 hw_period; 107 }; 108 109 static const struct mtk_field_type mt7623_fields[] = { 110 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)}, 111 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)}, 112 }; 113 114 static const struct mtk_field_type mt7622_fields[] = { 115 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)}, 116 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)}, 117 }; 118 119 /* 120 * struct mtk_ir - This is the main datasructure for holding the state 121 * of the driver 122 * @dev: The device pointer 123 * @rc: The rc instrance 124 * @base: The mapped register i/o base 125 * @irq: The IRQ that we are using 126 * @clk: The clock that IR internal is using 127 * @bus: The clock that software decoder is using 128 * @data: Holding specific data for vaious platform 129 */ 130 struct mtk_ir { 131 struct device *dev; 132 struct rc_dev *rc; 133 void __iomem *base; 134 int irq; 135 struct clk *clk; 136 struct clk *bus; 137 const struct mtk_ir_data *data; 138 }; 139 140 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i) 141 { 142 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i; 143 } 144 145 static inline u32 mtk_chk_period(struct mtk_ir *ir) 146 { 147 u32 val; 148 149 /* Period of raw software sampling in ns */ 150 val = DIV_ROUND_CLOSEST(1000000000ul, 151 clk_get_rate(ir->bus) / ir->data->div); 152 153 /* 154 * Period for software decoder used in the 155 * unit of raw software sampling 156 */ 157 val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val); 158 159 dev_dbg(ir->dev, "@pwm clk = \t%lu\n", 160 clk_get_rate(ir->bus) / ir->data->div); 161 dev_dbg(ir->dev, "@chkperiod = %08x\n", val); 162 163 return val; 164 } 165 166 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) 167 { 168 u32 tmp; 169 170 tmp = __raw_readl(ir->base + reg); 171 tmp = (tmp & ~mask) | val; 172 __raw_writel(tmp, ir->base + reg); 173 } 174 175 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) 176 { 177 __raw_writel(val, ir->base + reg); 178 } 179 180 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg) 181 { 182 return __raw_readl(ir->base + reg); 183 } 184 185 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask) 186 { 187 u32 val; 188 189 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); 190 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); 191 } 192 193 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask) 194 { 195 u32 val; 196 197 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); 198 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); 199 } 200 201 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id) 202 { 203 struct mtk_ir *ir = dev_id; 204 u8 wid = 0; 205 u32 i, j, val; 206 struct ir_raw_event rawir = {}; 207 208 /* 209 * Reset decoder state machine explicitly is required 210 * because 1) the longest duration for space MTK IR hardware 211 * could record is not safely long. e.g 12ms if rx resolution 212 * is 46us by default. There is still the risk to satisfying 213 * every decoder to reset themselves through long enough 214 * trailing spaces and 2) the IRQ handler guarantees that 215 * start of IR message is always contained in and starting 216 * from register mtk_chkdata_reg(ir, i). 217 */ 218 ir_raw_event_reset(ir->rc); 219 220 /* First message must be pulse */ 221 rawir.pulse = false; 222 223 /* Handle all pulse and space IR controller captures */ 224 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) { 225 val = mtk_r32(ir, mtk_chkdata_reg(ir, i)); 226 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); 227 228 for (j = 0 ; j < 4 ; j++) { 229 wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8; 230 rawir.pulse = !rawir.pulse; 231 rawir.duration = wid * (MTK_IR_SAMPLE + 1); 232 ir_raw_event_store_with_filter(ir->rc, &rawir); 233 } 234 } 235 236 /* 237 * The maximum number of edges the IR controller can 238 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages 239 * is over the limit, the last incomplete IR message would 240 * be appended trailing space and still would be sent into 241 * ir-rc-raw to decode. That helps it is possible that it 242 * has enough information to decode a scancode even if the 243 * trailing end of the message is missing. 244 */ 245 if (!MTK_IR_END(wid, rawir.pulse)) { 246 rawir.pulse = false; 247 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); 248 ir_raw_event_store_with_filter(ir->rc, &rawir); 249 } 250 251 ir_raw_event_handle(ir->rc); 252 253 /* 254 * Restart controller for the next receive that would 255 * clear up all CHKDATA registers 256 */ 257 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]); 258 259 /* Clear interrupt status */ 260 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, 261 ir->data->regs[MTK_IRINT_CLR_REG]); 262 263 return IRQ_HANDLED; 264 } 265 266 static const struct mtk_ir_data mt7623_data = { 267 .regs = mt7623_regs, 268 .fields = mt7623_fields, 269 .ok_count = 0xf, 270 .hw_period = 0xff, 271 .div = 4, 272 }; 273 274 static const struct mtk_ir_data mt7622_data = { 275 .regs = mt7622_regs, 276 .fields = mt7622_fields, 277 .ok_count = 0xf, 278 .hw_period = 0xffff, 279 .div = 32, 280 }; 281 282 static const struct of_device_id mtk_ir_match[] = { 283 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data}, 284 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data}, 285 {}, 286 }; 287 MODULE_DEVICE_TABLE(of, mtk_ir_match); 288 289 static int mtk_ir_probe(struct platform_device *pdev) 290 { 291 struct device *dev = &pdev->dev; 292 struct device_node *dn = dev->of_node; 293 struct resource *res; 294 struct mtk_ir *ir; 295 u32 val; 296 int ret = 0; 297 const char *map_name; 298 299 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL); 300 if (!ir) 301 return -ENOMEM; 302 303 ir->dev = dev; 304 ir->data = of_device_get_match_data(dev); 305 306 ir->clk = devm_clk_get(dev, "clk"); 307 if (IS_ERR(ir->clk)) { 308 dev_err(dev, "failed to get a ir clock.\n"); 309 return PTR_ERR(ir->clk); 310 } 311 312 ir->bus = devm_clk_get(dev, "bus"); 313 if (IS_ERR(ir->bus)) { 314 /* 315 * For compatibility with older device trees try unnamed 316 * ir->bus uses the same clock as ir->clock. 317 */ 318 ir->bus = ir->clk; 319 } 320 321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 322 ir->base = devm_ioremap_resource(dev, res); 323 if (IS_ERR(ir->base)) { 324 dev_err(dev, "failed to map registers\n"); 325 return PTR_ERR(ir->base); 326 } 327 328 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); 329 if (!ir->rc) { 330 dev_err(dev, "failed to allocate device\n"); 331 return -ENOMEM; 332 } 333 334 ir->rc->priv = ir; 335 ir->rc->device_name = MTK_IR_DEV; 336 ir->rc->input_phys = MTK_IR_DEV "/input0"; 337 ir->rc->input_id.bustype = BUS_HOST; 338 ir->rc->input_id.vendor = 0x0001; 339 ir->rc->input_id.product = 0x0001; 340 ir->rc->input_id.version = 0x0001; 341 map_name = of_get_property(dn, "linux,rc-map-name", NULL); 342 ir->rc->map_name = map_name ?: RC_MAP_EMPTY; 343 ir->rc->dev.parent = dev; 344 ir->rc->driver_name = MTK_IR_DEV; 345 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL; 346 ir->rc->rx_resolution = MTK_IR_SAMPLE; 347 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); 348 349 ret = devm_rc_register_device(dev, ir->rc); 350 if (ret) { 351 dev_err(dev, "failed to register rc device\n"); 352 return ret; 353 } 354 355 platform_set_drvdata(pdev, ir); 356 357 ir->irq = platform_get_irq(pdev, 0); 358 if (ir->irq < 0) { 359 dev_err(dev, "no irq resource\n"); 360 return -ENODEV; 361 } 362 363 if (clk_prepare_enable(ir->clk)) { 364 dev_err(dev, "try to enable ir_clk failed\n"); 365 return -EINVAL; 366 } 367 368 if (clk_prepare_enable(ir->bus)) { 369 dev_err(dev, "try to enable ir_clk failed\n"); 370 ret = -EINVAL; 371 goto exit_clkdisable_clk; 372 } 373 374 /* 375 * Enable interrupt after proper hardware 376 * setup and IRQ handler registration 377 */ 378 mtk_irq_disable(ir, MTK_IRINT_EN); 379 380 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir); 381 if (ret) { 382 dev_err(dev, "failed request irq\n"); 383 goto exit_clkdisable_bus; 384 } 385 386 /* 387 * Setup software sample period as the reference of software decoder 388 */ 389 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & 390 ir->data->fields[MTK_CHK_PERIOD].mask; 391 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, 392 ir->data->fields[MTK_CHK_PERIOD].reg); 393 394 /* 395 * Setup hardware sampling period used to setup the proper timeout for 396 * indicating end of IR receiving completion 397 */ 398 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & 399 ir->data->fields[MTK_HW_PERIOD].mask; 400 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, 401 ir->data->fields[MTK_HW_PERIOD].reg); 402 403 /* Enable IR and PWM */ 404 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG); 405 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; 406 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG); 407 408 mtk_irq_enable(ir, MTK_IRINT_EN); 409 410 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n", 411 DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000)); 412 413 return 0; 414 415 exit_clkdisable_bus: 416 clk_disable_unprepare(ir->bus); 417 exit_clkdisable_clk: 418 clk_disable_unprepare(ir->clk); 419 420 return ret; 421 } 422 423 static int mtk_ir_remove(struct platform_device *pdev) 424 { 425 struct mtk_ir *ir = platform_get_drvdata(pdev); 426 427 /* 428 * Avoid contention between remove handler and 429 * IRQ handler so that disabling IR interrupt and 430 * waiting for pending IRQ handler to complete 431 */ 432 mtk_irq_disable(ir, MTK_IRINT_EN); 433 synchronize_irq(ir->irq); 434 435 clk_disable_unprepare(ir->bus); 436 clk_disable_unprepare(ir->clk); 437 438 return 0; 439 } 440 441 static struct platform_driver mtk_ir_driver = { 442 .probe = mtk_ir_probe, 443 .remove = mtk_ir_remove, 444 .driver = { 445 .name = MTK_IR_DEV, 446 .of_match_table = mtk_ir_match, 447 }, 448 }; 449 450 module_platform_driver(mtk_ir_driver); 451 452 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver"); 453 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 454 MODULE_LICENSE("GPL"); 455