1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Mediatek IR Receiver Controller 4 * 5 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 #include <media/rc-core.h> 15 16 #define MTK_IR_DEV KBUILD_MODNAME 17 18 /* Register to enable PWM and IR */ 19 #define MTK_CONFIG_HIGH_REG 0x0c 20 21 /* Bit to enable IR pulse width detection */ 22 #define MTK_PWM_EN BIT(13) 23 24 /* 25 * Register to setting ok count whose unit based on hardware sampling period 26 * indicating IR receiving completion and then making IRQ fires 27 */ 28 #define MTK_OK_COUNT_MASK (GENMASK(22, 16)) 29 #define MTK_OK_COUNT(x) ((x) << 16) 30 31 /* Bit to enable IR hardware function */ 32 #define MTK_IR_EN BIT(0) 33 34 /* Bit to restart IR receiving */ 35 #define MTK_IRCLR BIT(0) 36 37 /* Fields containing pulse width data */ 38 #define MTK_WIDTH_MASK (GENMASK(7, 0)) 39 40 /* IR threshold */ 41 #define MTK_IRTHD 0x14 42 #define MTK_DG_CNT_MASK (GENMASK(12, 8)) 43 #define MTK_DG_CNT(x) ((x) << 8) 44 45 /* Bit to enable interrupt */ 46 #define MTK_IRINT_EN BIT(0) 47 48 /* Bit to clear interrupt status */ 49 #define MTK_IRINT_CLR BIT(0) 50 51 /* Maximum count of samples */ 52 #define MTK_MAX_SAMPLES 0xff 53 /* Indicate the end of IR message */ 54 #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0) 55 /* Number of registers to record the pulse width */ 56 #define MTK_CHKDATA_SZ 17 57 /* Sample period in us */ 58 #define MTK_IR_SAMPLE 46 59 60 enum mtk_fields { 61 /* Register to setting software sampling period */ 62 MTK_CHK_PERIOD, 63 /* Register to setting hardware sampling period */ 64 MTK_HW_PERIOD, 65 }; 66 67 enum mtk_regs { 68 /* Register to clear state of state machine */ 69 MTK_IRCLR_REG, 70 /* Register containing pulse width data */ 71 MTK_CHKDATA_REG, 72 /* Register to enable IR interrupt */ 73 MTK_IRINT_EN_REG, 74 /* Register to ack IR interrupt */ 75 MTK_IRINT_CLR_REG 76 }; 77 78 static const u32 mt7623_regs[] = { 79 [MTK_IRCLR_REG] = 0x20, 80 [MTK_CHKDATA_REG] = 0x88, 81 [MTK_IRINT_EN_REG] = 0xcc, 82 [MTK_IRINT_CLR_REG] = 0xd0, 83 }; 84 85 static const u32 mt7622_regs[] = { 86 [MTK_IRCLR_REG] = 0x18, 87 [MTK_CHKDATA_REG] = 0x30, 88 [MTK_IRINT_EN_REG] = 0x1c, 89 [MTK_IRINT_CLR_REG] = 0x20, 90 }; 91 92 struct mtk_field_type { 93 u32 reg; 94 u8 offset; 95 u32 mask; 96 }; 97 98 /* 99 * struct mtk_ir_data - This is the structure holding all differences among 100 various hardwares 101 * @regs: The pointer to the array holding registers offset 102 * @fields: The pointer to the array holding fields location 103 * @div: The internal divisor for the based reference clock 104 * @ok_count: The count indicating the completion of IR data 105 * receiving when count is reached 106 * @hw_period: The value indicating the hardware sampling period 107 */ 108 struct mtk_ir_data { 109 const u32 *regs; 110 const struct mtk_field_type *fields; 111 u8 div; 112 u8 ok_count; 113 u32 hw_period; 114 }; 115 116 static const struct mtk_field_type mt7623_fields[] = { 117 [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)}, 118 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)}, 119 }; 120 121 static const struct mtk_field_type mt7622_fields[] = { 122 [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)}, 123 [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)}, 124 }; 125 126 /* 127 * struct mtk_ir - This is the main datasructure for holding the state 128 * of the driver 129 * @dev: The device pointer 130 * @rc: The rc instrance 131 * @base: The mapped register i/o base 132 * @irq: The IRQ that we are using 133 * @clk: The clock that IR internal is using 134 * @bus: The clock that software decoder is using 135 * @data: Holding specific data for vaious platform 136 */ 137 struct mtk_ir { 138 struct device *dev; 139 struct rc_dev *rc; 140 void __iomem *base; 141 int irq; 142 struct clk *clk; 143 struct clk *bus; 144 const struct mtk_ir_data *data; 145 }; 146 147 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i) 148 { 149 return ir->data->regs[MTK_CHKDATA_REG] + 4 * i; 150 } 151 152 static inline u32 mtk_chk_period(struct mtk_ir *ir) 153 { 154 u32 val; 155 156 /* 157 * Period for software decoder used in the 158 * unit of raw software sampling 159 */ 160 val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus), 161 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE); 162 163 dev_dbg(ir->dev, "@pwm clk = \t%lu\n", 164 clk_get_rate(ir->bus) / ir->data->div); 165 dev_dbg(ir->dev, "@chkperiod = %08x\n", val); 166 167 return val; 168 } 169 170 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) 171 { 172 u32 tmp; 173 174 tmp = __raw_readl(ir->base + reg); 175 tmp = (tmp & ~mask) | val; 176 __raw_writel(tmp, ir->base + reg); 177 } 178 179 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) 180 { 181 __raw_writel(val, ir->base + reg); 182 } 183 184 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg) 185 { 186 return __raw_readl(ir->base + reg); 187 } 188 189 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask) 190 { 191 u32 val; 192 193 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); 194 mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); 195 } 196 197 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask) 198 { 199 u32 val; 200 201 val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); 202 mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); 203 } 204 205 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id) 206 { 207 struct ir_raw_event rawir = {}; 208 struct mtk_ir *ir = dev_id; 209 u32 i, j, val; 210 u8 wid; 211 212 /* 213 * Each pulse and space is encoded as a single byte, each byte 214 * alternating between pulse and space. If a pulse or space is longer 215 * than can be encoded in a single byte, it is encoded as the maximum 216 * value 0xff. 217 * 218 * If a space is longer than ok_count (about 23ms), the value is 219 * encoded as zero, and all following bytes are zero. Any IR that 220 * follows will be presented in the next interrupt. 221 * 222 * If there are more than 68 (=MTK_CHKDATA_SZ * 4) pulses and spaces, 223 * then the only the first 68 will be presented; the rest is lost. 224 */ 225 226 /* Handle all pulse and space IR controller captures */ 227 for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) { 228 val = mtk_r32(ir, mtk_chkdata_reg(ir, i)); 229 dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); 230 231 for (j = 0 ; j < 4 ; j++) { 232 wid = val & MTK_WIDTH_MASK; 233 val >>= 8; 234 rawir.pulse = !rawir.pulse; 235 rawir.duration = wid * (MTK_IR_SAMPLE + 1); 236 ir_raw_event_store_with_filter(ir->rc, &rawir); 237 } 238 } 239 240 /* 241 * The maximum number of edges the IR controller can 242 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages 243 * is over the limit, the last incomplete IR message would 244 * be appended trailing space and still would be sent into 245 * ir-rc-raw to decode. That helps it is possible that it 246 * has enough information to decode a scancode even if the 247 * trailing end of the message is missing. 248 */ 249 if (!MTK_IR_END(wid, rawir.pulse)) { 250 rawir.pulse = false; 251 rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); 252 ir_raw_event_store_with_filter(ir->rc, &rawir); 253 } 254 255 ir_raw_event_handle(ir->rc); 256 257 /* 258 * Restart controller for the next receive that would 259 * clear up all CHKDATA registers 260 */ 261 mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]); 262 263 /* Clear interrupt status */ 264 mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, 265 ir->data->regs[MTK_IRINT_CLR_REG]); 266 267 return IRQ_HANDLED; 268 } 269 270 static const struct mtk_ir_data mt7623_data = { 271 .regs = mt7623_regs, 272 .fields = mt7623_fields, 273 .ok_count = 3, 274 .hw_period = 0xff, 275 .div = 4, 276 }; 277 278 static const struct mtk_ir_data mt7622_data = { 279 .regs = mt7622_regs, 280 .fields = mt7622_fields, 281 .ok_count = 3, 282 .hw_period = 0xffff, 283 .div = 32, 284 }; 285 286 static const struct of_device_id mtk_ir_match[] = { 287 { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data}, 288 { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data}, 289 {}, 290 }; 291 MODULE_DEVICE_TABLE(of, mtk_ir_match); 292 293 static int mtk_ir_probe(struct platform_device *pdev) 294 { 295 struct device *dev = &pdev->dev; 296 struct device_node *dn = dev->of_node; 297 struct mtk_ir *ir; 298 u32 val; 299 int ret = 0; 300 const char *map_name; 301 302 ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL); 303 if (!ir) 304 return -ENOMEM; 305 306 ir->dev = dev; 307 ir->data = of_device_get_match_data(dev); 308 309 ir->clk = devm_clk_get(dev, "clk"); 310 if (IS_ERR(ir->clk)) { 311 dev_err(dev, "failed to get a ir clock.\n"); 312 return PTR_ERR(ir->clk); 313 } 314 315 ir->bus = devm_clk_get(dev, "bus"); 316 if (IS_ERR(ir->bus)) { 317 /* 318 * For compatibility with older device trees try unnamed 319 * ir->bus uses the same clock as ir->clock. 320 */ 321 ir->bus = ir->clk; 322 } 323 324 ir->base = devm_platform_ioremap_resource(pdev, 0); 325 if (IS_ERR(ir->base)) 326 return PTR_ERR(ir->base); 327 328 ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); 329 if (!ir->rc) { 330 dev_err(dev, "failed to allocate device\n"); 331 return -ENOMEM; 332 } 333 334 ir->rc->priv = ir; 335 ir->rc->device_name = MTK_IR_DEV; 336 ir->rc->input_phys = MTK_IR_DEV "/input0"; 337 ir->rc->input_id.bustype = BUS_HOST; 338 ir->rc->input_id.vendor = 0x0001; 339 ir->rc->input_id.product = 0x0001; 340 ir->rc->input_id.version = 0x0001; 341 map_name = of_get_property(dn, "linux,rc-map-name", NULL); 342 ir->rc->map_name = map_name ?: RC_MAP_EMPTY; 343 ir->rc->dev.parent = dev; 344 ir->rc->driver_name = MTK_IR_DEV; 345 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 346 ir->rc->rx_resolution = MTK_IR_SAMPLE; 347 ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); 348 349 ret = devm_rc_register_device(dev, ir->rc); 350 if (ret) { 351 dev_err(dev, "failed to register rc device\n"); 352 return ret; 353 } 354 355 platform_set_drvdata(pdev, ir); 356 357 ir->irq = platform_get_irq(pdev, 0); 358 if (ir->irq < 0) 359 return -ENODEV; 360 361 if (clk_prepare_enable(ir->clk)) { 362 dev_err(dev, "try to enable ir_clk failed\n"); 363 return -EINVAL; 364 } 365 366 if (clk_prepare_enable(ir->bus)) { 367 dev_err(dev, "try to enable ir_clk failed\n"); 368 ret = -EINVAL; 369 goto exit_clkdisable_clk; 370 } 371 372 /* 373 * Enable interrupt after proper hardware 374 * setup and IRQ handler registration 375 */ 376 mtk_irq_disable(ir, MTK_IRINT_EN); 377 378 ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir); 379 if (ret) { 380 dev_err(dev, "failed request irq\n"); 381 goto exit_clkdisable_bus; 382 } 383 384 /* 385 * Setup software sample period as the reference of software decoder 386 */ 387 val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & 388 ir->data->fields[MTK_CHK_PERIOD].mask; 389 mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, 390 ir->data->fields[MTK_CHK_PERIOD].reg); 391 392 /* 393 * Setup hardware sampling period used to setup the proper timeout for 394 * indicating end of IR receiving completion 395 */ 396 val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & 397 ir->data->fields[MTK_HW_PERIOD].mask; 398 mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, 399 ir->data->fields[MTK_HW_PERIOD].reg); 400 401 /* Set de-glitch counter */ 402 mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD); 403 404 /* Enable IR and PWM */ 405 val = mtk_r32(ir, MTK_CONFIG_HIGH_REG) & ~MTK_OK_COUNT_MASK; 406 val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; 407 mtk_w32(ir, val, MTK_CONFIG_HIGH_REG); 408 409 mtk_irq_enable(ir, MTK_IRINT_EN); 410 411 dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n", 412 MTK_IR_SAMPLE); 413 414 return 0; 415 416 exit_clkdisable_bus: 417 clk_disable_unprepare(ir->bus); 418 exit_clkdisable_clk: 419 clk_disable_unprepare(ir->clk); 420 421 return ret; 422 } 423 424 static void mtk_ir_remove(struct platform_device *pdev) 425 { 426 struct mtk_ir *ir = platform_get_drvdata(pdev); 427 428 /* 429 * Avoid contention between remove handler and 430 * IRQ handler so that disabling IR interrupt and 431 * waiting for pending IRQ handler to complete 432 */ 433 mtk_irq_disable(ir, MTK_IRINT_EN); 434 synchronize_irq(ir->irq); 435 436 clk_disable_unprepare(ir->bus); 437 clk_disable_unprepare(ir->clk); 438 } 439 440 static struct platform_driver mtk_ir_driver = { 441 .probe = mtk_ir_probe, 442 .remove_new = mtk_ir_remove, 443 .driver = { 444 .name = MTK_IR_DEV, 445 .of_match_table = mtk_ir_match, 446 }, 447 }; 448 449 module_platform_driver(mtk_ir_driver); 450 451 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver"); 452 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 453 MODULE_LICENSE("GPL"); 454