1 /* 2 * Driver for ITE Tech Inc. IT8712F/IT8512F CIR 3 * 4 * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 /* platform driver name to register */ 18 #define ITE_DRIVER_NAME "ite-cir" 19 20 /* logging macros */ 21 #define ite_pr(level, text, ...) \ 22 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) 23 #define ite_dbg(text, ...) do { \ 24 if (debug) \ 25 printk(KERN_DEBUG \ 26 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \ 27 } while (0) 28 29 #define ite_dbg_verbose(text, ...) do {\ 30 if (debug > 1) \ 31 printk(KERN_DEBUG \ 32 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \ 33 } while (0) 34 35 /* FIFO sizes */ 36 #define ITE_TX_FIFO_LEN 32 37 #define ITE_RX_FIFO_LEN 32 38 39 /* interrupt types */ 40 #define ITE_IRQ_TX_FIFO 1 41 #define ITE_IRQ_RX_FIFO 2 42 #define ITE_IRQ_RX_FIFO_OVERRUN 4 43 44 /* forward declaration */ 45 struct ite_dev; 46 47 /* struct for storing the parameters of different recognized devices */ 48 struct ite_dev_params { 49 /* model of the device */ 50 const char *model; 51 52 /* size of the I/O region */ 53 int io_region_size; 54 55 /* IR pnp I/O resource number */ 56 int io_rsrc_no; 57 58 /* true if the hardware supports transmission */ 59 bool hw_tx_capable; 60 61 /* base sampling period, in ns */ 62 u32 sample_period; 63 64 /* rx low carrier frequency, in Hz, 0 means no demodulation */ 65 unsigned int rx_low_carrier_freq; 66 67 /* tx high carrier frequency, in Hz, 0 means no demodulation */ 68 unsigned int rx_high_carrier_freq; 69 70 /* tx carrier frequency, in Hz */ 71 unsigned int tx_carrier_freq; 72 73 /* duty cycle, 0-100 */ 74 int tx_duty_cycle; 75 76 /* hw-specific operation function pointers; most of these must be 77 * called while holding the spin lock, except for the TX FIFO length 78 * one */ 79 /* get pending interrupt causes */ 80 int (*get_irq_causes) (struct ite_dev *dev); 81 82 /* enable rx */ 83 void (*enable_rx) (struct ite_dev *dev); 84 85 /* make rx enter the idle state; keep listening for a pulse, but stop 86 * streaming space bytes */ 87 void (*idle_rx) (struct ite_dev *dev); 88 89 /* disable rx completely */ 90 void (*disable_rx) (struct ite_dev *dev); 91 92 /* read bytes from RX FIFO; return read count */ 93 int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size); 94 95 /* enable tx FIFO space available interrupt */ 96 void (*enable_tx_interrupt) (struct ite_dev *dev); 97 98 /* disable tx FIFO space available interrupt */ 99 void (*disable_tx_interrupt) (struct ite_dev *dev); 100 101 /* get number of full TX FIFO slots */ 102 int (*get_tx_used_slots) (struct ite_dev *dev); 103 104 /* put a byte to the TX FIFO */ 105 void (*put_tx_byte) (struct ite_dev *dev, u8 value); 106 107 /* disable hardware completely */ 108 void (*disable) (struct ite_dev *dev); 109 110 /* initialize the hardware */ 111 void (*init_hardware) (struct ite_dev *dev); 112 113 /* set the carrier parameters */ 114 void (*set_carrier_params) (struct ite_dev *dev, bool high_freq, 115 bool use_demodulator, u8 carrier_freq_bits, 116 u8 allowance_bits, u8 pulse_width_bits); 117 }; 118 119 /* ITE CIR device structure */ 120 struct ite_dev { 121 struct pnp_dev *pdev; 122 struct rc_dev *rdev; 123 struct ir_raw_event rawir; 124 125 /* sync data */ 126 spinlock_t lock; 127 bool in_use, transmitting; 128 129 /* transmit support */ 130 int tx_fifo_allowance; 131 wait_queue_head_t tx_queue, tx_ended; 132 133 /* hardware I/O settings */ 134 unsigned long cir_addr; 135 int cir_irq; 136 137 /* overridable copy of model parameters */ 138 struct ite_dev_params params; 139 }; 140 141 /* common values for all kinds of hardware */ 142 143 /* baud rate divisor default */ 144 #define ITE_BAUDRATE_DIVISOR 1 145 146 /* low-speed carrier frequency limits (Hz) */ 147 #define ITE_LCF_MIN_CARRIER_FREQ 27000 148 #define ITE_LCF_MAX_CARRIER_FREQ 58000 149 150 /* high-speed carrier frequency limits (Hz) */ 151 #define ITE_HCF_MIN_CARRIER_FREQ 400000 152 #define ITE_HCF_MAX_CARRIER_FREQ 500000 153 154 /* default carrier freq for when demodulator is off (Hz) */ 155 #define ITE_DEFAULT_CARRIER_FREQ 38000 156 157 /* default idling timeout in ns (0.2 seconds) */ 158 #define ITE_IDLE_TIMEOUT 200000000UL 159 160 /* limit timeout values */ 161 #define ITE_MIN_IDLE_TIMEOUT 100000000UL 162 #define ITE_MAX_IDLE_TIMEOUT 1000000000UL 163 164 /* convert bits to us */ 165 #define ITE_BITS_TO_NS(bits, sample_period) \ 166 ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period)) 167 168 /* 169 * n in RDCR produces a tolerance of +/- n * 6.25% around the center 170 * carrier frequency... 171 * 172 * From two limit frequencies, L (low) and H (high), we can get both the 173 * center frequency F = (L + H) / 2 and the variation from the center 174 * frequency A = (H - L) / (H + L). We can use this in order to honor the 175 * s_rx_carrier_range() call in ir-core. We'll suppose that any request 176 * setting L=0 means we must shut down the demodulator. 177 */ 178 #define ITE_RXDCR_PER_10000_STEP 625 179 180 /* high speed carrier freq values */ 181 #define ITE_CFQ_400 0x03 182 #define ITE_CFQ_450 0x08 183 #define ITE_CFQ_480 0x0b 184 #define ITE_CFQ_500 0x0d 185 186 /* values for pulse widths */ 187 #define ITE_TXMPW_A 0x02 188 #define ITE_TXMPW_B 0x03 189 #define ITE_TXMPW_C 0x04 190 #define ITE_TXMPW_D 0x05 191 #define ITE_TXMPW_E 0x06 192 193 /* values for demodulator carrier range allowance */ 194 #define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */ 195 #define ITE_RXDCR_MAX 0x07 /* default carrier range */ 196 197 /* DR TX bits */ 198 #define ITE_TX_PULSE 0x00 199 #define ITE_TX_SPACE 0x80 200 #define ITE_TX_MAX_RLE 0x80 201 #define ITE_TX_RLE_MASK 0x7f 202 203 /* 204 * IT8712F 205 * 206 * hardware data obtained from: 207 * 208 * IT8712F 209 * Environment Control – Low Pin Count Input / Output 210 * (EC - LPC I/O) 211 * Preliminary Specification V0. 81 212 */ 213 214 /* register offsets */ 215 #define IT87_DR 0x00 /* data register */ 216 #define IT87_IER 0x01 /* interrupt enable register */ 217 #define IT87_RCR 0x02 /* receiver control register */ 218 #define IT87_TCR1 0x03 /* transmitter control register 1 */ 219 #define IT87_TCR2 0x04 /* transmitter control register 2 */ 220 #define IT87_TSR 0x05 /* transmitter status register */ 221 #define IT87_RSR 0x06 /* receiver status register */ 222 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */ 223 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */ 224 #define IT87_IIR 0x07 /* interrupt identification register */ 225 226 #define IT87_IOREG_LENGTH 0x08 /* length of register file */ 227 228 /* IER bits */ 229 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */ 230 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */ 231 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */ 232 #define IT87_IEC 0x08 /* interrupt enable control */ 233 #define IT87_BR 0x10 /* baud rate register enable */ 234 #define IT87_RESET 0x20 /* reset */ 235 236 /* RCR bits */ 237 #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */ 238 #define IT87_RXACT 0x08 /* receiver active */ 239 #define IT87_RXEND 0x10 /* receiver demodulation enable */ 240 #define IT87_RXEN 0x20 /* receiver enable */ 241 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */ 242 #define IT87_RDWOS 0x80 /* receiver data without sync */ 243 244 /* TCR1 bits */ 245 #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */ 246 #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ 247 #define IT87_TXENDF 0x04 /* transmitter deferral */ 248 #define IT87_TXRLE 0x08 /* transmitter run length enable */ 249 #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */ 250 #define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default 251 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17, 252 * 0x30 -> 25 */ 253 #define IT87_ILE 0x40 /* internal loopback enable */ 254 #define IT87_FIFOCLR 0x80 /* FIFO clear bit */ 255 256 /* TCR2 bits */ 257 #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */ 258 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ 259 #define IT87_CFQ 0xf8 /* carrier frequency mask */ 260 #define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */ 261 262 /* TSR bits */ 263 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */ 264 265 /* RSR bits */ 266 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */ 267 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */ 268 269 /* IIR bits */ 270 #define IT87_IP 0x01 /* interrupt pending */ 271 #define IT87_II 0x06 /* interrupt identification mask */ 272 #define IT87_II_NOINT 0x00 /* no interrupt */ 273 #define IT87_II_TXLDL 0x02 /* transmitter low data level */ 274 #define IT87_II_RXDS 0x04 /* receiver data stored */ 275 #define IT87_II_RXFO 0x06 /* receiver FIFO overrun */ 276 277 /* 278 * IT8512E/F 279 * 280 * Hardware data obtained from: 281 * 282 * IT8512E/F 283 * Embedded Controller 284 * Preliminary Specification V0.4.1 285 * 286 * Note that the CIR registers are not directly available to the host, because 287 * they only are accessible to the integrated microcontroller. Thus, in order 288 * use it, some kind of bridging is required. As the bridging may depend on 289 * the controller firmware in use, we are going to use the PNP ID in order to 290 * determine the strategy and ports available. See after these generic 291 * IT8512E/F register definitions for register definitions for those 292 * strategies. 293 */ 294 295 /* register offsets */ 296 #define IT85_C0DR 0x00 /* data register */ 297 #define IT85_C0MSTCR 0x01 /* master control register */ 298 #define IT85_C0IER 0x02 /* interrupt enable register */ 299 #define IT85_C0IIR 0x03 /* interrupt identification register */ 300 #define IT85_C0CFR 0x04 /* carrier frequency register */ 301 #define IT85_C0RCR 0x05 /* receiver control register */ 302 #define IT85_C0TCR 0x06 /* transmitter control register */ 303 #define IT85_C0SCK 0x07 /* slow clock control register */ 304 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */ 305 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */ 306 #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */ 307 #define IT85_C0RFSR 0x0b /* receiver FIFO status register */ 308 #define IT85_C0WCL 0x0d /* wakeup code length register */ 309 #define IT85_C0WCR 0x0e /* wakeup code read/write register */ 310 #define IT85_C0WPS 0x0f /* wakeup power control/status register */ 311 312 #define IT85_IOREG_LENGTH 0x10 /* length of register file */ 313 314 /* C0MSTCR bits */ 315 #define IT85_RESET 0x01 /* reset */ 316 #define IT85_FIFOCLR 0x02 /* FIFO clear bit */ 317 #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */ 318 #define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default 319 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17, 320 * 0x0c -> 25 */ 321 #define IT85_ILE 0x10 /* internal loopback enable */ 322 #define IT85_ILSEL 0x20 /* internal loopback select */ 323 324 /* C0IER bits */ 325 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */ 326 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */ 327 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */ 328 #define IT85_IEC 0x80 /* interrupt enable function control */ 329 330 /* C0IIR bits */ 331 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */ 332 #define IT85_RDAI 0x02 /* receiver data available interrupt */ 333 #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */ 334 #define IT85_NIP 0x80 /* no interrupt pending */ 335 336 /* C0CFR bits */ 337 #define IT85_CFQ 0x1f /* carrier frequency mask */ 338 #define IT85_HCFS 0x20 /* high speed carrier frequency select */ 339 340 /* C0RCR bits */ 341 #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */ 342 #define IT85_RXACT 0x08 /* receiver active */ 343 #define IT85_RXEND 0x10 /* receiver demodulation enable */ 344 #define IT85_RDWOS 0x20 /* receiver data without sync */ 345 #define IT85_RXEN 0x80 /* receiver enable */ 346 347 /* C0TCR bits */ 348 #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */ 349 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ 350 #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */ 351 #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ 352 #define IT85_TXENDF 0x20 /* transmitter deferral */ 353 #define IT85_TXRLE 0x40 /* transmitter run length enable */ 354 355 /* C0SCK bits */ 356 #define IT85_SCKS 0x01 /* slow clock select */ 357 #define IT85_TXDCKG 0x02 /* TXD clock gating */ 358 #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */ 359 #define IT85_DLLTE 0x08 /* DLL test enable */ 360 #define IT85_BRCM 0x70 /* baud rate count mode */ 361 #define IT85_DLLOCK 0x80 /* DLL lock */ 362 363 /* C0TFSR bits */ 364 #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */ 365 366 /* C0RFSR bits */ 367 #define IT85_RXFBC 0x3f /* receiver FIFO count mask */ 368 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */ 369 370 /* C0WCL bits */ 371 #define IT85_WCL 0x3f /* wakeup code length mask */ 372 373 /* C0WPS bits */ 374 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */ 375 #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */ 376 #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */ 377 #define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */ 378 #define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */ 379 380 /* 381 * ITE8708 382 * 383 * Hardware data obtained from hacked driver for IT8512 in this forum post: 384 * 385 * http://ubuntuforums.org/showthread.php?t=1028640 386 * 387 * Although there's no official documentation for that driver, analysis would 388 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks, 389 * selectable by a single bank-select bit that's mapped onto both banks. The 390 * IT8512 registers are mapped in a different order, so that the first bank 391 * maps the ones that are used more often, and two registers that share a 392 * reserved high-order bit are placed at the same offset in both banks in 393 * order to reuse the reserved bit as the bank select bit. 394 */ 395 396 /* register offsets */ 397 398 /* mapped onto both banks */ 399 #define IT8708_BANKSEL 0x07 /* bank select register */ 400 #define IT8708_HRAE 0x80 /* high registers access enable */ 401 402 /* mapped onto the low bank */ 403 #define IT8708_C0DR 0x00 /* data register */ 404 #define IT8708_C0MSTCR 0x01 /* master control register */ 405 #define IT8708_C0IER 0x02 /* interrupt enable register */ 406 #define IT8708_C0IIR 0x03 /* interrupt identification register */ 407 #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */ 408 #define IT8708_C0RCR 0x05 /* receiver control register */ 409 #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */ 410 #define IT8708_C0TCR 0x07 /* transmitter control register */ 411 412 /* mapped onto the high bank */ 413 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */ 414 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */ 415 #define IT8708_C0CFR 0x04 /* carrier frequency register */ 416 417 /* registers whose bank mapping we don't know, since they weren't being used 418 * in the hacked driver... most probably they belong to the high bank too, 419 * since they fit in the holes the other registers leave */ 420 #define IT8708_C0SCK 0x03 /* slow clock control register */ 421 #define IT8708_C0WCL 0x05 /* wakeup code length register */ 422 #define IT8708_C0WCR 0x06 /* wakeup code read/write register */ 423 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */ 424 425 #define IT8708_IOREG_LENGTH 0x08 /* length of register file */ 426 427 /* two more registers that are defined in the hacked driver, but can't be 428 * found in the data sheets; no idea what they are or how they are accessed, 429 * since the hacked driver doesn't seem to use them */ 430 #define IT8708_CSCRR 0x00 431 #define IT8708_CGPINTR 0x01 432 433 /* CSCRR bits */ 434 #define IT8708_CSCRR_SCRB 0x3f 435 #define IT8708_CSCRR_PM 0x80 436 437 /* CGPINTR bits */ 438 #define IT8708_CGPINT 0x01 439 440 /* 441 * ITE8709 442 * 443 * Hardware interfacing data obtained from the original lirc_ite8709 driver. 444 * Verbatim from its sources: 445 * 446 * The ITE8709 device seems to be the combination of IT8512 superIO chip and 447 * a specific firmware running on the IT8512's embedded micro-controller. 448 * In addition of the embedded micro-controller, the IT8512 chip contains a 449 * CIR module and several other modules. A few modules are directly accessible 450 * by the host CPU, but most of them are only accessible by the 451 * micro-controller. The CIR module is only accessible by the 452 * micro-controller. 453 * 454 * The battery-backed SRAM module is accessible by the host CPU and the 455 * micro-controller. So one of the MC's firmware role is to act as a bridge 456 * between the host CPU and the CIR module. The firmware implements a kind of 457 * communication protocol using the SRAM module as a shared memory. The IT8512 458 * specification is publicly available on ITE's web site, but the 459 * communication protocol is not, so it was reverse-engineered. 460 */ 461 462 /* register offsets */ 463 #define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */ 464 #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */ 465 466 #define IT8709_IOREG_LENGTH 0x02 /* length of register file */ 467 468 /* register offsets inside the SRAM module */ 469 #define IT8709_MODE 0x1a /* request/ack byte */ 470 #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */ 471 #define IT8709_REG_VAL 0x1c /* value read/to be written */ 472 #define IT8709_IIR 0x1e /* interrupt identification register */ 473 #define IT8709_RFSR 0x1f /* receiver FIFO status register */ 474 #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */ 475 476 /* MODE values */ 477 #define IT8709_IDLE 0x00 478 #define IT8709_WRITE 0x01 479 #define IT8709_READ 0x02 480