1 /* 2 * Driver for ITE Tech Inc. IT8712F/IT8512F CIR 3 * 4 * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 19 * USA. 20 */ 21 22 /* platform driver name to register */ 23 #define ITE_DRIVER_NAME "ite-cir" 24 25 /* logging macros */ 26 #define ite_pr(level, text, ...) \ 27 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__) 28 #define ite_dbg(text, ...) do { \ 29 if (debug) \ 30 printk(KERN_DEBUG \ 31 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \ 32 } while (0) 33 34 #define ite_dbg_verbose(text, ...) do {\ 35 if (debug > 1) \ 36 printk(KERN_DEBUG \ 37 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \ 38 } while (0) 39 40 /* FIFO sizes */ 41 #define ITE_TX_FIFO_LEN 32 42 #define ITE_RX_FIFO_LEN 32 43 44 /* interrupt types */ 45 #define ITE_IRQ_TX_FIFO 1 46 #define ITE_IRQ_RX_FIFO 2 47 #define ITE_IRQ_RX_FIFO_OVERRUN 4 48 49 /* forward declaration */ 50 struct ite_dev; 51 52 /* struct for storing the parameters of different recognized devices */ 53 struct ite_dev_params { 54 /* model of the device */ 55 const char *model; 56 57 /* size of the I/O region */ 58 int io_region_size; 59 60 /* IR pnp I/O resource number */ 61 int io_rsrc_no; 62 63 /* true if the hardware supports transmission */ 64 bool hw_tx_capable; 65 66 /* base sampling period, in ns */ 67 u32 sample_period; 68 69 /* rx low carrier frequency, in Hz, 0 means no demodulation */ 70 unsigned int rx_low_carrier_freq; 71 72 /* tx high carrier frequency, in Hz, 0 means no demodulation */ 73 unsigned int rx_high_carrier_freq; 74 75 /* tx carrier frequency, in Hz */ 76 unsigned int tx_carrier_freq; 77 78 /* duty cycle, 0-100 */ 79 int tx_duty_cycle; 80 81 /* hw-specific operation function pointers; most of these must be 82 * called while holding the spin lock, except for the TX FIFO length 83 * one */ 84 /* get pending interrupt causes */ 85 int (*get_irq_causes) (struct ite_dev *dev); 86 87 /* enable rx */ 88 void (*enable_rx) (struct ite_dev *dev); 89 90 /* make rx enter the idle state; keep listening for a pulse, but stop 91 * streaming space bytes */ 92 void (*idle_rx) (struct ite_dev *dev); 93 94 /* disable rx completely */ 95 void (*disable_rx) (struct ite_dev *dev); 96 97 /* read bytes from RX FIFO; return read count */ 98 int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size); 99 100 /* enable tx FIFO space available interrupt */ 101 void (*enable_tx_interrupt) (struct ite_dev *dev); 102 103 /* disable tx FIFO space available interrupt */ 104 void (*disable_tx_interrupt) (struct ite_dev *dev); 105 106 /* get number of full TX FIFO slots */ 107 int (*get_tx_used_slots) (struct ite_dev *dev); 108 109 /* put a byte to the TX FIFO */ 110 void (*put_tx_byte) (struct ite_dev *dev, u8 value); 111 112 /* disable hardware completely */ 113 void (*disable) (struct ite_dev *dev); 114 115 /* initialize the hardware */ 116 void (*init_hardware) (struct ite_dev *dev); 117 118 /* set the carrier parameters */ 119 void (*set_carrier_params) (struct ite_dev *dev, bool high_freq, 120 bool use_demodulator, u8 carrier_freq_bits, 121 u8 allowance_bits, u8 pulse_width_bits); 122 }; 123 124 /* ITE CIR device structure */ 125 struct ite_dev { 126 struct pnp_dev *pdev; 127 struct rc_dev *rdev; 128 struct ir_raw_event rawir; 129 130 /* sync data */ 131 spinlock_t lock; 132 bool in_use, transmitting; 133 134 /* transmit support */ 135 int tx_fifo_allowance; 136 wait_queue_head_t tx_queue, tx_ended; 137 138 /* hardware I/O settings */ 139 unsigned long cir_addr; 140 int cir_irq; 141 142 /* overridable copy of model parameters */ 143 struct ite_dev_params params; 144 }; 145 146 /* common values for all kinds of hardware */ 147 148 /* baud rate divisor default */ 149 #define ITE_BAUDRATE_DIVISOR 1 150 151 /* low-speed carrier frequency limits (Hz) */ 152 #define ITE_LCF_MIN_CARRIER_FREQ 27000 153 #define ITE_LCF_MAX_CARRIER_FREQ 58000 154 155 /* high-speed carrier frequency limits (Hz) */ 156 #define ITE_HCF_MIN_CARRIER_FREQ 400000 157 #define ITE_HCF_MAX_CARRIER_FREQ 500000 158 159 /* default carrier freq for when demodulator is off (Hz) */ 160 #define ITE_DEFAULT_CARRIER_FREQ 38000 161 162 /* default idling timeout in ns (0.2 seconds) */ 163 #define ITE_IDLE_TIMEOUT 200000000UL 164 165 /* limit timeout values */ 166 #define ITE_MIN_IDLE_TIMEOUT 100000000UL 167 #define ITE_MAX_IDLE_TIMEOUT 1000000000UL 168 169 /* convert bits to us */ 170 #define ITE_BITS_TO_NS(bits, sample_period) \ 171 ((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period)) 172 173 /* 174 * n in RDCR produces a tolerance of +/- n * 6.25% around the center 175 * carrier frequency... 176 * 177 * From two limit frequencies, L (low) and H (high), we can get both the 178 * center frequency F = (L + H) / 2 and the variation from the center 179 * frequency A = (H - L) / (H + L). We can use this in order to honor the 180 * s_rx_carrier_range() call in ir-core. We'll suppose that any request 181 * setting L=0 means we must shut down the demodulator. 182 */ 183 #define ITE_RXDCR_PER_10000_STEP 625 184 185 /* high speed carrier freq values */ 186 #define ITE_CFQ_400 0x03 187 #define ITE_CFQ_450 0x08 188 #define ITE_CFQ_480 0x0b 189 #define ITE_CFQ_500 0x0d 190 191 /* values for pulse widths */ 192 #define ITE_TXMPW_A 0x02 193 #define ITE_TXMPW_B 0x03 194 #define ITE_TXMPW_C 0x04 195 #define ITE_TXMPW_D 0x05 196 #define ITE_TXMPW_E 0x06 197 198 /* values for demodulator carrier range allowance */ 199 #define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */ 200 #define ITE_RXDCR_MAX 0x07 /* default carrier range */ 201 202 /* DR TX bits */ 203 #define ITE_TX_PULSE 0x00 204 #define ITE_TX_SPACE 0x80 205 #define ITE_TX_MAX_RLE 0x80 206 #define ITE_TX_RLE_MASK 0x7f 207 208 /* 209 * IT8712F 210 * 211 * hardware data obtained from: 212 * 213 * IT8712F 214 * Environment Control – Low Pin Count Input / Output 215 * (EC - LPC I/O) 216 * Preliminary Specification V0. 81 217 */ 218 219 /* register offsets */ 220 #define IT87_DR 0x00 /* data register */ 221 #define IT87_IER 0x01 /* interrupt enable register */ 222 #define IT87_RCR 0x02 /* receiver control register */ 223 #define IT87_TCR1 0x03 /* transmitter control register 1 */ 224 #define IT87_TCR2 0x04 /* transmitter control register 2 */ 225 #define IT87_TSR 0x05 /* transmitter status register */ 226 #define IT87_RSR 0x06 /* receiver status register */ 227 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */ 228 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */ 229 #define IT87_IIR 0x07 /* interrupt identification register */ 230 231 #define IT87_IOREG_LENGTH 0x08 /* length of register file */ 232 233 /* IER bits */ 234 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */ 235 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */ 236 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */ 237 #define IT87_IEC 0x08 /* interrupt enable control */ 238 #define IT87_BR 0x10 /* baud rate register enable */ 239 #define IT87_RESET 0x20 /* reset */ 240 241 /* RCR bits */ 242 #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */ 243 #define IT87_RXACT 0x08 /* receiver active */ 244 #define IT87_RXEND 0x10 /* receiver demodulation enable */ 245 #define IT87_RXEN 0x20 /* receiver enable */ 246 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */ 247 #define IT87_RDWOS 0x80 /* receiver data without sync */ 248 249 /* TCR1 bits */ 250 #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */ 251 #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ 252 #define IT87_TXENDF 0x04 /* transmitter deferral */ 253 #define IT87_TXRLE 0x08 /* transmitter run length enable */ 254 #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */ 255 #define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default 256 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17, 257 * 0x30 -> 25 */ 258 #define IT87_ILE 0x40 /* internal loopback enable */ 259 #define IT87_FIFOCLR 0x80 /* FIFO clear bit */ 260 261 /* TCR2 bits */ 262 #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */ 263 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ 264 #define IT87_CFQ 0xf8 /* carrier frequency mask */ 265 #define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */ 266 267 /* TSR bits */ 268 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */ 269 270 /* RSR bits */ 271 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */ 272 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */ 273 274 /* IIR bits */ 275 #define IT87_IP 0x01 /* interrupt pending */ 276 #define IT87_II 0x06 /* interrupt identification mask */ 277 #define IT87_II_NOINT 0x00 /* no interrupt */ 278 #define IT87_II_TXLDL 0x02 /* transmitter low data level */ 279 #define IT87_II_RXDS 0x04 /* receiver data stored */ 280 #define IT87_II_RXFO 0x06 /* receiver FIFO overrun */ 281 282 /* 283 * IT8512E/F 284 * 285 * Hardware data obtained from: 286 * 287 * IT8512E/F 288 * Embedded Controller 289 * Preliminary Specification V0.4.1 290 * 291 * Note that the CIR registers are not directly available to the host, because 292 * they only are accessible to the integrated microcontroller. Thus, in order 293 * use it, some kind of bridging is required. As the bridging may depend on 294 * the controller firmware in use, we are going to use the PNP ID in order to 295 * determine the strategy and ports available. See after these generic 296 * IT8512E/F register definitions for register definitions for those 297 * strategies. 298 */ 299 300 /* register offsets */ 301 #define IT85_C0DR 0x00 /* data register */ 302 #define IT85_C0MSTCR 0x01 /* master control register */ 303 #define IT85_C0IER 0x02 /* interrupt enable register */ 304 #define IT85_C0IIR 0x03 /* interrupt identification register */ 305 #define IT85_C0CFR 0x04 /* carrier frequency register */ 306 #define IT85_C0RCR 0x05 /* receiver control register */ 307 #define IT85_C0TCR 0x06 /* transmitter control register */ 308 #define IT85_C0SCK 0x07 /* slow clock control register */ 309 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */ 310 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */ 311 #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */ 312 #define IT85_C0RFSR 0x0b /* receiver FIFO status register */ 313 #define IT85_C0WCL 0x0d /* wakeup code length register */ 314 #define IT85_C0WCR 0x0e /* wakeup code read/write register */ 315 #define IT85_C0WPS 0x0f /* wakeup power control/status register */ 316 317 #define IT85_IOREG_LENGTH 0x10 /* length of register file */ 318 319 /* C0MSTCR bits */ 320 #define IT85_RESET 0x01 /* reset */ 321 #define IT85_FIFOCLR 0x02 /* FIFO clear bit */ 322 #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */ 323 #define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default 324 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17, 325 * 0x0c -> 25 */ 326 #define IT85_ILE 0x10 /* internal loopback enable */ 327 #define IT85_ILSEL 0x20 /* internal loopback select */ 328 329 /* C0IER bits */ 330 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */ 331 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */ 332 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */ 333 #define IT85_IEC 0x80 /* interrupt enable function control */ 334 335 /* C0IIR bits */ 336 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */ 337 #define IT85_RDAI 0x02 /* receiver data available interrupt */ 338 #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */ 339 #define IT85_NIP 0x80 /* no interrupt pending */ 340 341 /* C0CFR bits */ 342 #define IT85_CFQ 0x1f /* carrier frequency mask */ 343 #define IT85_HCFS 0x20 /* high speed carrier frequency select */ 344 345 /* C0RCR bits */ 346 #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */ 347 #define IT85_RXACT 0x08 /* receiver active */ 348 #define IT85_RXEND 0x10 /* receiver demodulation enable */ 349 #define IT85_RDWOS 0x20 /* receiver data without sync */ 350 #define IT85_RXEN 0x80 /* receiver enable */ 351 352 /* C0TCR bits */ 353 #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */ 354 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ 355 #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */ 356 #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ 357 #define IT85_TXENDF 0x20 /* transmitter deferral */ 358 #define IT85_TXRLE 0x40 /* transmitter run length enable */ 359 360 /* C0SCK bits */ 361 #define IT85_SCKS 0x01 /* slow clock select */ 362 #define IT85_TXDCKG 0x02 /* TXD clock gating */ 363 #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */ 364 #define IT85_DLLTE 0x08 /* DLL test enable */ 365 #define IT85_BRCM 0x70 /* baud rate count mode */ 366 #define IT85_DLLOCK 0x80 /* DLL lock */ 367 368 /* C0TFSR bits */ 369 #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */ 370 371 /* C0RFSR bits */ 372 #define IT85_RXFBC 0x3f /* receiver FIFO count mask */ 373 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */ 374 375 /* C0WCL bits */ 376 #define IT85_WCL 0x3f /* wakeup code length mask */ 377 378 /* C0WPS bits */ 379 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */ 380 #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */ 381 #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */ 382 #define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */ 383 #define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */ 384 385 /* 386 * ITE8708 387 * 388 * Hardware data obtained from hacked driver for IT8512 in this forum post: 389 * 390 * http://ubuntuforums.org/showthread.php?t=1028640 391 * 392 * Although there's no official documentation for that driver, analysis would 393 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks, 394 * selectable by a single bank-select bit that's mapped onto both banks. The 395 * IT8512 registers are mapped in a different order, so that the first bank 396 * maps the ones that are used more often, and two registers that share a 397 * reserved high-order bit are placed at the same offset in both banks in 398 * order to reuse the reserved bit as the bank select bit. 399 */ 400 401 /* register offsets */ 402 403 /* mapped onto both banks */ 404 #define IT8708_BANKSEL 0x07 /* bank select register */ 405 #define IT8708_HRAE 0x80 /* high registers access enable */ 406 407 /* mapped onto the low bank */ 408 #define IT8708_C0DR 0x00 /* data register */ 409 #define IT8708_C0MSTCR 0x01 /* master control register */ 410 #define IT8708_C0IER 0x02 /* interrupt enable register */ 411 #define IT8708_C0IIR 0x03 /* interrupt identification register */ 412 #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */ 413 #define IT8708_C0RCR 0x05 /* receiver control register */ 414 #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */ 415 #define IT8708_C0TCR 0x07 /* transmitter control register */ 416 417 /* mapped onto the high bank */ 418 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */ 419 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */ 420 #define IT8708_C0CFR 0x04 /* carrier frequency register */ 421 422 /* registers whose bank mapping we don't know, since they weren't being used 423 * in the hacked driver... most probably they belong to the high bank too, 424 * since they fit in the holes the other registers leave */ 425 #define IT8708_C0SCK 0x03 /* slow clock control register */ 426 #define IT8708_C0WCL 0x05 /* wakeup code length register */ 427 #define IT8708_C0WCR 0x06 /* wakeup code read/write register */ 428 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */ 429 430 #define IT8708_IOREG_LENGTH 0x08 /* length of register file */ 431 432 /* two more registers that are defined in the hacked driver, but can't be 433 * found in the data sheets; no idea what they are or how they are accessed, 434 * since the hacked driver doesn't seem to use them */ 435 #define IT8708_CSCRR 0x00 436 #define IT8708_CGPINTR 0x01 437 438 /* CSCRR bits */ 439 #define IT8708_CSCRR_SCRB 0x3f 440 #define IT8708_CSCRR_PM 0x80 441 442 /* CGPINTR bits */ 443 #define IT8708_CGPINT 0x01 444 445 /* 446 * ITE8709 447 * 448 * Hardware interfacing data obtained from the original lirc_ite8709 driver. 449 * Verbatim from its sources: 450 * 451 * The ITE8709 device seems to be the combination of IT8512 superIO chip and 452 * a specific firmware running on the IT8512's embedded micro-controller. 453 * In addition of the embedded micro-controller, the IT8512 chip contains a 454 * CIR module and several other modules. A few modules are directly accessible 455 * by the host CPU, but most of them are only accessible by the 456 * micro-controller. The CIR module is only accessible by the 457 * micro-controller. 458 * 459 * The battery-backed SRAM module is accessible by the host CPU and the 460 * micro-controller. So one of the MC's firmware role is to act as a bridge 461 * between the host CPU and the CIR module. The firmware implements a kind of 462 * communication protocol using the SRAM module as a shared memory. The IT8512 463 * specification is publicly available on ITE's web site, but the 464 * communication protocol is not, so it was reverse-engineered. 465 */ 466 467 /* register offsets */ 468 #define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */ 469 #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */ 470 471 #define IT8709_IOREG_LENGTH 0x02 /* length of register file */ 472 473 /* register offsets inside the SRAM module */ 474 #define IT8709_MODE 0x1a /* request/ack byte */ 475 #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */ 476 #define IT8709_REG_VAL 0x1c /* value read/to be written */ 477 #define IT8709_IIR 0x1e /* interrupt identification register */ 478 #define IT8709_RFSR 0x1f /* receiver FIFO status register */ 479 #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */ 480 481 /* MODE values */ 482 #define IT8709_IDLE 0x00 483 #define IT8709_WRITE 0x01 484 #define IT8709_READ 0x02 485