1 /* 2 * Copyright (c) 2014 Linaro Ltd. 3 * Copyright (c) 2014 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/regmap.h> 17 #include <media/rc-core.h> 18 19 #define IR_ENABLE 0x00 20 #define IR_CONFIG 0x04 21 #define CNT_LEADS 0x08 22 #define CNT_LEADE 0x0c 23 #define CNT_SLEADE 0x10 24 #define CNT0_B 0x14 25 #define CNT1_B 0x18 26 #define IR_BUSY 0x1c 27 #define IR_DATAH 0x20 28 #define IR_DATAL 0x24 29 #define IR_INTM 0x28 30 #define IR_INTS 0x2c 31 #define IR_INTC 0x30 32 #define IR_START 0x34 33 34 /* interrupt mask */ 35 #define INTMS_SYMBRCV (BIT(24) | BIT(8)) 36 #define INTMS_TIMEOUT (BIT(25) | BIT(9)) 37 #define INTMS_OVERFLOW (BIT(26) | BIT(10)) 38 #define INT_CLR_OVERFLOW BIT(18) 39 #define INT_CLR_TIMEOUT BIT(17) 40 #define INT_CLR_RCV BIT(16) 41 #define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17)) 42 43 #define IR_CLK 0x48 44 #define IR_CLK_ENABLE BIT(4) 45 #define IR_CLK_RESET BIT(5) 46 47 #define IR_CFG_WIDTH_MASK 0xffff 48 #define IR_CFG_WIDTH_SHIFT 16 49 #define IR_CFG_FORMAT_MASK 0x3 50 #define IR_CFG_FORMAT_SHIFT 14 51 #define IR_CFG_INT_LEVEL_MASK 0x3f 52 #define IR_CFG_INT_LEVEL_SHIFT 8 53 /* only support raw mode */ 54 #define IR_CFG_MODE_RAW BIT(7) 55 #define IR_CFG_FREQ_MASK 0x7f 56 #define IR_CFG_FREQ_SHIFT 0 57 #define IR_CFG_INT_THRESHOLD 1 58 /* symbol start from low to high, symbol stream end at high*/ 59 #define IR_CFG_SYMBOL_FMT 0 60 #define IR_CFG_SYMBOL_MAXWIDTH 0x3e80 61 62 #define IR_HIX5HD2_NAME "hix5hd2-ir" 63 64 struct hix5hd2_ir_priv { 65 int irq; 66 void __iomem *base; 67 struct device *dev; 68 struct rc_dev *rdev; 69 struct regmap *regmap; 70 struct clk *clock; 71 unsigned long rate; 72 }; 73 74 static void hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on) 75 { 76 u32 val; 77 78 if (dev->regmap) { 79 regmap_read(dev->regmap, IR_CLK, &val); 80 if (on) { 81 val &= ~IR_CLK_RESET; 82 val |= IR_CLK_ENABLE; 83 } else { 84 val &= ~IR_CLK_ENABLE; 85 val |= IR_CLK_RESET; 86 } 87 regmap_write(dev->regmap, IR_CLK, val); 88 } else { 89 if (on) 90 clk_prepare_enable(dev->clock); 91 else 92 clk_disable_unprepare(dev->clock); 93 } 94 } 95 96 static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv) 97 { 98 int timeout = 10000; 99 u32 val, rate; 100 101 writel_relaxed(0x01, priv->base + IR_ENABLE); 102 while (readl_relaxed(priv->base + IR_BUSY)) { 103 if (timeout--) { 104 udelay(1); 105 } else { 106 dev_err(priv->dev, "IR_BUSY timeout\n"); 107 return -ETIMEDOUT; 108 } 109 } 110 111 /* Now only support raw mode, with symbol start from low to high */ 112 rate = DIV_ROUND_CLOSEST(priv->rate, 1000000); 113 val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT; 114 val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT; 115 val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK 116 << IR_CFG_INT_LEVEL_SHIFT; 117 val |= IR_CFG_MODE_RAW; 118 val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT; 119 writel_relaxed(val, priv->base + IR_CONFIG); 120 121 writel_relaxed(0x00, priv->base + IR_INTM); 122 /* write arbitrary value to start */ 123 writel_relaxed(0x01, priv->base + IR_START); 124 return 0; 125 } 126 127 static int hix5hd2_ir_open(struct rc_dev *rdev) 128 { 129 struct hix5hd2_ir_priv *priv = rdev->priv; 130 131 hix5hd2_ir_enable(priv, true); 132 return hix5hd2_ir_config(priv); 133 } 134 135 static void hix5hd2_ir_close(struct rc_dev *rdev) 136 { 137 struct hix5hd2_ir_priv *priv = rdev->priv; 138 139 hix5hd2_ir_enable(priv, false); 140 } 141 142 static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data) 143 { 144 u32 symb_num, symb_val, symb_time; 145 u32 data_l, data_h; 146 u32 irq_sr, i; 147 struct hix5hd2_ir_priv *priv = data; 148 149 irq_sr = readl_relaxed(priv->base + IR_INTS); 150 if (irq_sr & INTMS_OVERFLOW) { 151 /* 152 * we must read IR_DATAL first, then we can clean up 153 * IR_INTS availably since logic would not clear 154 * fifo when overflow, drv do the job 155 */ 156 ir_raw_event_reset(priv->rdev); 157 symb_num = readl_relaxed(priv->base + IR_DATAH); 158 for (i = 0; i < symb_num; i++) 159 readl_relaxed(priv->base + IR_DATAL); 160 161 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); 162 dev_info(priv->dev, "overflow, level=%d\n", 163 IR_CFG_INT_THRESHOLD); 164 } 165 166 if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) { 167 DEFINE_IR_RAW_EVENT(ev); 168 169 symb_num = readl_relaxed(priv->base + IR_DATAH); 170 for (i = 0; i < symb_num; i++) { 171 symb_val = readl_relaxed(priv->base + IR_DATAL); 172 data_l = ((symb_val & 0xffff) * 10); 173 data_h = ((symb_val >> 16) & 0xffff) * 10; 174 symb_time = (data_l + data_h) / 10; 175 176 ev.duration = US_TO_NS(data_l); 177 ev.pulse = true; 178 ir_raw_event_store(priv->rdev, &ev); 179 180 if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) { 181 ev.duration = US_TO_NS(data_h); 182 ev.pulse = false; 183 ir_raw_event_store(priv->rdev, &ev); 184 } else { 185 ir_raw_event_set_idle(priv->rdev, true); 186 } 187 } 188 189 if (irq_sr & INTMS_SYMBRCV) 190 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); 191 if (irq_sr & INTMS_TIMEOUT) 192 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); 193 } 194 195 /* Empty software fifo */ 196 ir_raw_event_handle(priv->rdev); 197 return IRQ_HANDLED; 198 } 199 200 static int hix5hd2_ir_probe(struct platform_device *pdev) 201 { 202 struct rc_dev *rdev; 203 struct device *dev = &pdev->dev; 204 struct resource *res; 205 struct hix5hd2_ir_priv *priv; 206 struct device_node *node = pdev->dev.of_node; 207 const char *map_name; 208 int ret; 209 210 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 211 if (!priv) 212 return -ENOMEM; 213 214 priv->regmap = syscon_regmap_lookup_by_phandle(node, 215 "hisilicon,power-syscon"); 216 if (IS_ERR(priv->regmap)) { 217 dev_info(dev, "no power-reg\n"); 218 priv->regmap = NULL; 219 } 220 221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 222 priv->base = devm_ioremap_resource(dev, res); 223 if (IS_ERR(priv->base)) 224 return PTR_ERR(priv->base); 225 226 priv->irq = platform_get_irq(pdev, 0); 227 if (priv->irq < 0) { 228 dev_err(dev, "irq can not get\n"); 229 return priv->irq; 230 } 231 232 rdev = rc_allocate_device(RC_DRIVER_IR_RAW); 233 if (!rdev) 234 return -ENOMEM; 235 236 priv->clock = devm_clk_get(dev, NULL); 237 if (IS_ERR(priv->clock)) { 238 dev_err(dev, "clock not found\n"); 239 ret = PTR_ERR(priv->clock); 240 goto err; 241 } 242 clk_prepare_enable(priv->clock); 243 priv->rate = clk_get_rate(priv->clock); 244 245 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 246 rdev->priv = priv; 247 rdev->open = hix5hd2_ir_open; 248 rdev->close = hix5hd2_ir_close; 249 rdev->driver_name = IR_HIX5HD2_NAME; 250 map_name = of_get_property(node, "linux,rc-map-name", NULL); 251 rdev->map_name = map_name ?: RC_MAP_EMPTY; 252 rdev->device_name = IR_HIX5HD2_NAME; 253 rdev->input_phys = IR_HIX5HD2_NAME "/input0"; 254 rdev->input_id.bustype = BUS_HOST; 255 rdev->input_id.vendor = 0x0001; 256 rdev->input_id.product = 0x0001; 257 rdev->input_id.version = 0x0100; 258 rdev->rx_resolution = US_TO_NS(10); 259 rdev->timeout = US_TO_NS(IR_CFG_SYMBOL_MAXWIDTH * 10); 260 261 ret = rc_register_device(rdev); 262 if (ret < 0) 263 goto clkerr; 264 265 if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt, 266 0, pdev->name, priv) < 0) { 267 dev_err(dev, "IRQ %d register failed\n", priv->irq); 268 ret = -EINVAL; 269 goto regerr; 270 } 271 272 priv->rdev = rdev; 273 priv->dev = dev; 274 platform_set_drvdata(pdev, priv); 275 276 return ret; 277 278 regerr: 279 rc_unregister_device(rdev); 280 rdev = NULL; 281 clkerr: 282 clk_disable_unprepare(priv->clock); 283 err: 284 rc_free_device(rdev); 285 dev_err(dev, "Unable to register device (%d)\n", ret); 286 return ret; 287 } 288 289 static int hix5hd2_ir_remove(struct platform_device *pdev) 290 { 291 struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev); 292 293 clk_disable_unprepare(priv->clock); 294 rc_unregister_device(priv->rdev); 295 return 0; 296 } 297 298 #ifdef CONFIG_PM_SLEEP 299 static int hix5hd2_ir_suspend(struct device *dev) 300 { 301 struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); 302 303 clk_disable_unprepare(priv->clock); 304 hix5hd2_ir_enable(priv, false); 305 306 return 0; 307 } 308 309 static int hix5hd2_ir_resume(struct device *dev) 310 { 311 struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); 312 313 hix5hd2_ir_enable(priv, true); 314 clk_prepare_enable(priv->clock); 315 316 writel_relaxed(0x01, priv->base + IR_ENABLE); 317 writel_relaxed(0x00, priv->base + IR_INTM); 318 writel_relaxed(0xff, priv->base + IR_INTC); 319 writel_relaxed(0x01, priv->base + IR_START); 320 321 return 0; 322 } 323 #endif 324 325 static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend, 326 hix5hd2_ir_resume); 327 328 static const struct of_device_id hix5hd2_ir_table[] = { 329 { .compatible = "hisilicon,hix5hd2-ir", }, 330 {}, 331 }; 332 MODULE_DEVICE_TABLE(of, hix5hd2_ir_table); 333 334 static struct platform_driver hix5hd2_ir_driver = { 335 .driver = { 336 .name = IR_HIX5HD2_NAME, 337 .of_match_table = hix5hd2_ir_table, 338 .pm = &hix5hd2_ir_pm_ops, 339 }, 340 .probe = hix5hd2_ir_probe, 341 .remove = hix5hd2_ir_remove, 342 }; 343 344 module_platform_driver(hix5hd2_ir_driver); 345 346 MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms"); 347 MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>"); 348 MODULE_LICENSE("GPL v2"); 349 MODULE_ALIAS("platform:hix5hd2-ir"); 350