1 /* 2 * Copyright (c) 2014 Linaro Ltd. 3 * Copyright (c) 2014 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/regmap.h> 17 #include <media/rc-core.h> 18 19 /* Allow the driver to compile on all architectures */ 20 #ifndef writel_relaxed 21 # define writel_relaxed writel 22 #endif 23 #ifndef readl_relaxed 24 # define readl_relaxed readl 25 #endif 26 27 #define IR_ENABLE 0x00 28 #define IR_CONFIG 0x04 29 #define CNT_LEADS 0x08 30 #define CNT_LEADE 0x0c 31 #define CNT_SLEADE 0x10 32 #define CNT0_B 0x14 33 #define CNT1_B 0x18 34 #define IR_BUSY 0x1c 35 #define IR_DATAH 0x20 36 #define IR_DATAL 0x24 37 #define IR_INTM 0x28 38 #define IR_INTS 0x2c 39 #define IR_INTC 0x30 40 #define IR_START 0x34 41 42 /* interrupt mask */ 43 #define INTMS_SYMBRCV (BIT(24) | BIT(8)) 44 #define INTMS_TIMEOUT (BIT(25) | BIT(9)) 45 #define INTMS_OVERFLOW (BIT(26) | BIT(10)) 46 #define INT_CLR_OVERFLOW BIT(18) 47 #define INT_CLR_TIMEOUT BIT(17) 48 #define INT_CLR_RCV BIT(16) 49 #define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17)) 50 51 #define IR_CLK 0x48 52 #define IR_CLK_ENABLE BIT(4) 53 #define IR_CLK_RESET BIT(5) 54 55 #define IR_CFG_WIDTH_MASK 0xffff 56 #define IR_CFG_WIDTH_SHIFT 16 57 #define IR_CFG_FORMAT_MASK 0x3 58 #define IR_CFG_FORMAT_SHIFT 14 59 #define IR_CFG_INT_LEVEL_MASK 0x3f 60 #define IR_CFG_INT_LEVEL_SHIFT 8 61 /* only support raw mode */ 62 #define IR_CFG_MODE_RAW BIT(7) 63 #define IR_CFG_FREQ_MASK 0x7f 64 #define IR_CFG_FREQ_SHIFT 0 65 #define IR_CFG_INT_THRESHOLD 1 66 /* symbol start from low to high, symbol stream end at high*/ 67 #define IR_CFG_SYMBOL_FMT 0 68 #define IR_CFG_SYMBOL_MAXWIDTH 0x3e80 69 70 #define IR_HIX5HD2_NAME "hix5hd2-ir" 71 72 struct hix5hd2_ir_priv { 73 int irq; 74 void volatile __iomem *base; 75 struct device *dev; 76 struct rc_dev *rdev; 77 struct regmap *regmap; 78 struct clk *clock; 79 unsigned long rate; 80 }; 81 82 static void hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on) 83 { 84 u32 val; 85 86 regmap_read(dev->regmap, IR_CLK, &val); 87 if (on) { 88 val &= ~IR_CLK_RESET; 89 val |= IR_CLK_ENABLE; 90 } else { 91 val &= ~IR_CLK_ENABLE; 92 val |= IR_CLK_RESET; 93 } 94 regmap_write(dev->regmap, IR_CLK, val); 95 } 96 97 static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv) 98 { 99 int timeout = 10000; 100 u32 val, rate; 101 102 writel_relaxed(0x01, priv->base + IR_ENABLE); 103 while (readl_relaxed(priv->base + IR_BUSY)) { 104 if (timeout--) { 105 udelay(1); 106 } else { 107 dev_err(priv->dev, "IR_BUSY timeout\n"); 108 return -ETIMEDOUT; 109 } 110 } 111 112 /* Now only support raw mode, with symbol start from low to high */ 113 rate = DIV_ROUND_CLOSEST(priv->rate, 1000000); 114 val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT; 115 val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT; 116 val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK 117 << IR_CFG_INT_LEVEL_SHIFT; 118 val |= IR_CFG_MODE_RAW; 119 val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT; 120 writel_relaxed(val, priv->base + IR_CONFIG); 121 122 writel_relaxed(0x00, priv->base + IR_INTM); 123 /* write arbitrary value to start */ 124 writel_relaxed(0x01, priv->base + IR_START); 125 return 0; 126 } 127 128 static int hix5hd2_ir_open(struct rc_dev *rdev) 129 { 130 struct hix5hd2_ir_priv *priv = rdev->priv; 131 132 hix5hd2_ir_enable(priv, true); 133 return hix5hd2_ir_config(priv); 134 } 135 136 static void hix5hd2_ir_close(struct rc_dev *rdev) 137 { 138 struct hix5hd2_ir_priv *priv = rdev->priv; 139 140 hix5hd2_ir_enable(priv, false); 141 } 142 143 static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data) 144 { 145 u32 symb_num, symb_val, symb_time; 146 u32 data_l, data_h; 147 u32 irq_sr, i; 148 struct hix5hd2_ir_priv *priv = data; 149 150 irq_sr = readl_relaxed(priv->base + IR_INTS); 151 if (irq_sr & INTMS_OVERFLOW) { 152 /* 153 * we must read IR_DATAL first, then we can clean up 154 * IR_INTS availably since logic would not clear 155 * fifo when overflow, drv do the job 156 */ 157 ir_raw_event_reset(priv->rdev); 158 symb_num = readl_relaxed(priv->base + IR_DATAH); 159 for (i = 0; i < symb_num; i++) 160 readl_relaxed(priv->base + IR_DATAL); 161 162 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); 163 dev_info(priv->dev, "overflow, level=%d\n", 164 IR_CFG_INT_THRESHOLD); 165 } 166 167 if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) { 168 DEFINE_IR_RAW_EVENT(ev); 169 170 symb_num = readl_relaxed(priv->base + IR_DATAH); 171 for (i = 0; i < symb_num; i++) { 172 symb_val = readl_relaxed(priv->base + IR_DATAL); 173 data_l = ((symb_val & 0xffff) * 10); 174 data_h = ((symb_val >> 16) & 0xffff) * 10; 175 symb_time = (data_l + data_h) / 10; 176 177 ev.duration = US_TO_NS(data_l); 178 ev.pulse = true; 179 ir_raw_event_store(priv->rdev, &ev); 180 181 if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) { 182 ev.duration = US_TO_NS(data_h); 183 ev.pulse = false; 184 ir_raw_event_store(priv->rdev, &ev); 185 } else { 186 ir_raw_event_set_idle(priv->rdev, true); 187 } 188 } 189 190 if (irq_sr & INTMS_SYMBRCV) 191 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); 192 if (irq_sr & INTMS_TIMEOUT) 193 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); 194 } 195 196 /* Empty software fifo */ 197 ir_raw_event_handle(priv->rdev); 198 return IRQ_HANDLED; 199 } 200 201 static int hix5hd2_ir_probe(struct platform_device *pdev) 202 { 203 struct rc_dev *rdev; 204 struct device *dev = &pdev->dev; 205 struct resource *res; 206 struct hix5hd2_ir_priv *priv; 207 struct device_node *node = pdev->dev.of_node; 208 const char *map_name; 209 int ret; 210 211 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 212 if (!priv) 213 return -ENOMEM; 214 215 priv->regmap = syscon_regmap_lookup_by_phandle(node, 216 "hisilicon,power-syscon"); 217 if (IS_ERR(priv->regmap)) { 218 dev_err(dev, "no power-reg\n"); 219 return -EINVAL; 220 } 221 222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 223 priv->base = devm_ioremap_resource(dev, res); 224 if (IS_ERR((__force void *)priv->base)) 225 return PTR_ERR((__force void *)priv->base); 226 227 priv->irq = platform_get_irq(pdev, 0); 228 if (priv->irq < 0) { 229 dev_err(dev, "irq can not get\n"); 230 return priv->irq; 231 } 232 233 rdev = rc_allocate_device(); 234 if (!rdev) 235 return -ENOMEM; 236 237 priv->clock = devm_clk_get(dev, NULL); 238 if (IS_ERR(priv->clock)) { 239 dev_err(dev, "clock not found\n"); 240 ret = PTR_ERR(priv->clock); 241 goto err; 242 } 243 clk_prepare_enable(priv->clock); 244 priv->rate = clk_get_rate(priv->clock); 245 246 rdev->driver_type = RC_DRIVER_IR_RAW; 247 rdev->allowed_protocols = RC_BIT_ALL; 248 rdev->priv = priv; 249 rdev->open = hix5hd2_ir_open; 250 rdev->close = hix5hd2_ir_close; 251 rdev->driver_name = IR_HIX5HD2_NAME; 252 map_name = of_get_property(node, "linux,rc-map-name", NULL); 253 rdev->map_name = map_name ?: RC_MAP_EMPTY; 254 rdev->input_name = IR_HIX5HD2_NAME; 255 rdev->input_phys = IR_HIX5HD2_NAME "/input0"; 256 rdev->input_id.bustype = BUS_HOST; 257 rdev->input_id.vendor = 0x0001; 258 rdev->input_id.product = 0x0001; 259 rdev->input_id.version = 0x0100; 260 rdev->rx_resolution = US_TO_NS(10); 261 rdev->timeout = US_TO_NS(IR_CFG_SYMBOL_MAXWIDTH * 10); 262 263 ret = rc_register_device(rdev); 264 if (ret < 0) 265 goto clkerr; 266 267 if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt, 268 IRQF_NO_SUSPEND, pdev->name, priv) < 0) { 269 dev_err(dev, "IRQ %d register failed\n", priv->irq); 270 ret = -EINVAL; 271 goto regerr; 272 } 273 274 priv->rdev = rdev; 275 priv->dev = dev; 276 platform_set_drvdata(pdev, priv); 277 278 return ret; 279 280 regerr: 281 rc_unregister_device(rdev); 282 rdev = NULL; 283 clkerr: 284 clk_disable_unprepare(priv->clock); 285 err: 286 rc_free_device(rdev); 287 dev_err(dev, "Unable to register device (%d)\n", ret); 288 return ret; 289 } 290 291 static int hix5hd2_ir_remove(struct platform_device *pdev) 292 { 293 struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev); 294 295 clk_disable_unprepare(priv->clock); 296 rc_unregister_device(priv->rdev); 297 return 0; 298 } 299 300 #ifdef CONFIG_PM_SLEEP 301 static int hix5hd2_ir_suspend(struct device *dev) 302 { 303 struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); 304 305 clk_disable_unprepare(priv->clock); 306 hix5hd2_ir_enable(priv, false); 307 308 return 0; 309 } 310 311 static int hix5hd2_ir_resume(struct device *dev) 312 { 313 struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); 314 315 hix5hd2_ir_enable(priv, true); 316 clk_prepare_enable(priv->clock); 317 318 writel_relaxed(0x01, priv->base + IR_ENABLE); 319 writel_relaxed(0x00, priv->base + IR_INTM); 320 writel_relaxed(0xff, priv->base + IR_INTC); 321 writel_relaxed(0x01, priv->base + IR_START); 322 323 return 0; 324 } 325 #endif 326 327 static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend, 328 hix5hd2_ir_resume); 329 330 static struct of_device_id hix5hd2_ir_table[] = { 331 { .compatible = "hisilicon,hix5hd2-ir", }, 332 {}, 333 }; 334 MODULE_DEVICE_TABLE(of, hix5hd2_ir_table); 335 336 static struct platform_driver hix5hd2_ir_driver = { 337 .driver = { 338 .name = IR_HIX5HD2_NAME, 339 .of_match_table = hix5hd2_ir_table, 340 .pm = &hix5hd2_ir_pm_ops, 341 }, 342 .probe = hix5hd2_ir_probe, 343 .remove = hix5hd2_ir_remove, 344 }; 345 346 module_platform_driver(hix5hd2_ir_driver); 347 348 MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms"); 349 MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>"); 350 MODULE_LICENSE("GPL v2"); 351 MODULE_ALIAS("platform:hix5hd2-ir"); 352