1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * ImgTec IR Decoder found in PowerDown Controller.
4 *
5 * Copyright 2010-2014 Imagination Technologies Ltd.
6 */
7
8 #ifndef _IMG_IR_H_
9 #define _IMG_IR_H_
10
11 #include <linux/io.h>
12 #include <linux/spinlock.h>
13
14 #include "img-ir-raw.h"
15 #include "img-ir-hw.h"
16
17 /* registers */
18
19 /* relative to the start of the IR block of registers */
20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
30 #define IMG_IR_POW_MOD_PARAMS 0x28
31 #define IMG_IR_POW_MOD_ENABLE 0x2c
32 #define IMG_IR_IRQ_MSG_DATA_LW 0x30
33 #define IMG_IR_IRQ_MSG_DATA_UP 0x34
34 #define IMG_IR_IRQ_MSG_MASK_LW 0x38
35 #define IMG_IR_IRQ_MSG_MASK_UP 0x3c
36 #define IMG_IR_IRQ_ENABLE 0x40
37 #define IMG_IR_IRQ_STATUS 0x44
38 #define IMG_IR_IRQ_CLEAR 0x48
39 #define IMG_IR_IRCORE_ID 0xf0
40 #define IMG_IR_CORE_REV 0xf4
41 #define IMG_IR_CORE_DES1 0xf8
42 #define IMG_IR_CORE_DES2 0xfc
43
44
45 /* field masks */
46
47 /* IMG_IR_CONTROL */
48 #define IMG_IR_DECODEN 0x40000000
49 #define IMG_IR_CODETYPE 0x30000000
50 #define IMG_IR_CODETYPE_SHIFT 28
51 #define IMG_IR_HDRTOG 0x08000000
52 #define IMG_IR_LDRDEC 0x04000000
53 #define IMG_IR_DECODINPOL 0x02000000 /* active high */
54 #define IMG_IR_BITORIEN 0x01000000 /* MSB first */
55 #define IMG_IR_D1VALIDSEL 0x00008000
56 #define IMG_IR_BITINV 0x00000040 /* don't invert */
57 #define IMG_IR_DECODEND2 0x00000010
58 #define IMG_IR_BITORIEND2 0x00000002 /* MSB first */
59 #define IMG_IR_BITINVD2 0x00000001 /* don't invert */
60
61 /* IMG_IR_STATUS */
62 #define IMG_IR_RXDVALD2 0x00001000
63 #define IMG_IR_IRRXD 0x00000400
64 #define IMG_IR_TOGSTATE 0x00000200
65 #define IMG_IR_RXDVAL 0x00000040
66 #define IMG_IR_RXDLEN 0x0000003f
67 #define IMG_IR_RXDLEN_SHIFT 0
68
69 /* IMG_IR_LEAD_SYMB_TIMING, IMG_IR_Sxx_SYMB_TIMING */
70 #define IMG_IR_PD_MAX 0xff000000
71 #define IMG_IR_PD_MAX_SHIFT 24
72 #define IMG_IR_PD_MIN 0x00ff0000
73 #define IMG_IR_PD_MIN_SHIFT 16
74 #define IMG_IR_W_MAX 0x0000ff00
75 #define IMG_IR_W_MAX_SHIFT 8
76 #define IMG_IR_W_MIN 0x000000ff
77 #define IMG_IR_W_MIN_SHIFT 0
78
79 /* IMG_IR_FREE_SYMB_TIMING */
80 #define IMG_IR_MAXLEN 0x0007e000
81 #define IMG_IR_MAXLEN_SHIFT 13
82 #define IMG_IR_MINLEN 0x00001f00
83 #define IMG_IR_MINLEN_SHIFT 8
84 #define IMG_IR_FT_MIN 0x000000ff
85 #define IMG_IR_FT_MIN_SHIFT 0
86
87 /* IMG_IR_POW_MOD_PARAMS */
88 #define IMG_IR_PERIOD_LEN 0x3f000000
89 #define IMG_IR_PERIOD_LEN_SHIFT 24
90 #define IMG_IR_PERIOD_DUTY 0x003f0000
91 #define IMG_IR_PERIOD_DUTY_SHIFT 16
92 #define IMG_IR_STABLE_STOP 0x00003f00
93 #define IMG_IR_STABLE_STOP_SHIFT 8
94 #define IMG_IR_STABLE_START 0x0000003f
95 #define IMG_IR_STABLE_START_SHIFT 0
96
97 /* IMG_IR_POW_MOD_ENABLE */
98 #define IMG_IR_POWER_OUT_EN 0x00000002
99 #define IMG_IR_POWER_MOD_EN 0x00000001
100
101 /* IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_STATUS, IMG_IR_IRQ_CLEAR */
102 #define IMG_IR_IRQ_DEC2_ERR 0x00000080
103 #define IMG_IR_IRQ_DEC_ERR 0x00000040
104 #define IMG_IR_IRQ_ACT_LEVEL 0x00000020
105 #define IMG_IR_IRQ_FALL_EDGE 0x00000010
106 #define IMG_IR_IRQ_RISE_EDGE 0x00000008
107 #define IMG_IR_IRQ_DATA_MATCH 0x00000004
108 #define IMG_IR_IRQ_DATA2_VALID 0x00000002
109 #define IMG_IR_IRQ_DATA_VALID 0x00000001
110 #define IMG_IR_IRQ_ALL 0x000000ff
111 #define IMG_IR_IRQ_EDGE (IMG_IR_IRQ_FALL_EDGE | IMG_IR_IRQ_RISE_EDGE)
112
113 /* IMG_IR_CORE_ID */
114 #define IMG_IR_CORE_ID 0x00ff0000
115 #define IMG_IR_CORE_ID_SHIFT 16
116 #define IMG_IR_CORE_CONFIG 0x0000ffff
117 #define IMG_IR_CORE_CONFIG_SHIFT 0
118
119 /* IMG_IR_CORE_REV */
120 #define IMG_IR_DESIGNER 0xff000000
121 #define IMG_IR_DESIGNER_SHIFT 24
122 #define IMG_IR_MAJOR_REV 0x00ff0000
123 #define IMG_IR_MAJOR_REV_SHIFT 16
124 #define IMG_IR_MINOR_REV 0x0000ff00
125 #define IMG_IR_MINOR_REV_SHIFT 8
126 #define IMG_IR_MAINT_REV 0x000000ff
127 #define IMG_IR_MAINT_REV_SHIFT 0
128
129 struct device;
130 struct clk;
131
132 /**
133 * struct img_ir_priv - Private driver data.
134 * @dev: Platform device.
135 * @irq: IRQ number.
136 * @clk: Input clock.
137 * @sys_clk: System clock.
138 * @reg_base: Iomem base address of IR register block.
139 * @lock: Protects IR registers and variables in this struct.
140 * @raw: Driver data for raw decoder.
141 * @hw: Driver data for hardware decoder.
142 */
143 struct img_ir_priv {
144 struct device *dev;
145 int irq;
146 struct clk *clk;
147 struct clk *sys_clk;
148 void __iomem *reg_base;
149 spinlock_t lock;
150
151 struct img_ir_priv_raw raw;
152 struct img_ir_priv_hw hw;
153 };
154
155 /* Hardware access */
156
img_ir_write(struct img_ir_priv * priv,unsigned int reg_offs,unsigned int data)157 static inline void img_ir_write(struct img_ir_priv *priv,
158 unsigned int reg_offs, unsigned int data)
159 {
160 iowrite32(data, priv->reg_base + reg_offs);
161 }
162
img_ir_read(struct img_ir_priv * priv,unsigned int reg_offs)163 static inline unsigned int img_ir_read(struct img_ir_priv *priv,
164 unsigned int reg_offs)
165 {
166 return ioread32(priv->reg_base + reg_offs);
167 }
168
169 #endif /* _IMG_IR_H_ */
170