1 /* 2 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR 3 * 4 * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com> 5 * 6 * Special thanks to Fintek for providing hardware and spec sheets. 7 * This driver is based upon the nuvoton, ite and ene drivers for 8 * similar hardware. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/pnp.h> 26 #include <linux/io.h> 27 #include <linux/interrupt.h> 28 #include <linux/sched.h> 29 #include <linux/slab.h> 30 #include <media/rc-core.h> 31 32 #include "fintek-cir.h" 33 34 /* write val to config reg */ 35 static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg) 36 { 37 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)", 38 __func__, reg, val, fintek->cr_ip, fintek->cr_dp); 39 outb(reg, fintek->cr_ip); 40 outb(val, fintek->cr_dp); 41 } 42 43 /* read val from config reg */ 44 static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg) 45 { 46 u8 val; 47 48 outb(reg, fintek->cr_ip); 49 val = inb(fintek->cr_dp); 50 51 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)", 52 __func__, reg, val, fintek->cr_ip, fintek->cr_dp); 53 return val; 54 } 55 56 /* update config register bit without changing other bits */ 57 static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) 58 { 59 u8 tmp = fintek_cr_read(fintek, reg) | val; 60 fintek_cr_write(fintek, tmp, reg); 61 } 62 63 /* clear config register bit without changing other bits */ 64 static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) 65 { 66 u8 tmp = fintek_cr_read(fintek, reg) & ~val; 67 fintek_cr_write(fintek, tmp, reg); 68 } 69 70 /* enter config mode */ 71 static inline void fintek_config_mode_enable(struct fintek_dev *fintek) 72 { 73 /* Enabling Config Mode explicitly requires writing 2x */ 74 outb(CONFIG_REG_ENABLE, fintek->cr_ip); 75 outb(CONFIG_REG_ENABLE, fintek->cr_ip); 76 } 77 78 /* exit config mode */ 79 static inline void fintek_config_mode_disable(struct fintek_dev *fintek) 80 { 81 outb(CONFIG_REG_DISABLE, fintek->cr_ip); 82 } 83 84 /* 85 * When you want to address a specific logical device, write its logical 86 * device number to GCR_LOGICAL_DEV_NO 87 */ 88 static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev) 89 { 90 fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO); 91 } 92 93 /* write val to cir config register */ 94 static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset) 95 { 96 outb(val, fintek->cir_addr + offset); 97 } 98 99 /* read val from cir config register */ 100 static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset) 101 { 102 return inb(fintek->cir_addr + offset); 103 } 104 105 /* dump current cir register contents */ 106 static void cir_dump_regs(struct fintek_dev *fintek) 107 { 108 fintek_config_mode_enable(fintek); 109 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 110 111 pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME); 112 pr_info(" * CR CIR BASE ADDR: 0x%x\n", 113 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) | 114 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO)); 115 pr_info(" * CR CIR IRQ NUM: 0x%x\n", 116 fintek_cr_read(fintek, CIR_CR_IRQ_SEL)); 117 118 fintek_config_mode_disable(fintek); 119 120 pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME); 121 pr_info(" * STATUS: 0x%x\n", 122 fintek_cir_reg_read(fintek, CIR_STATUS)); 123 pr_info(" * CONTROL: 0x%x\n", 124 fintek_cir_reg_read(fintek, CIR_CONTROL)); 125 pr_info(" * RX_DATA: 0x%x\n", 126 fintek_cir_reg_read(fintek, CIR_RX_DATA)); 127 pr_info(" * TX_CONTROL: 0x%x\n", 128 fintek_cir_reg_read(fintek, CIR_TX_CONTROL)); 129 pr_info(" * TX_DATA: 0x%x\n", 130 fintek_cir_reg_read(fintek, CIR_TX_DATA)); 131 } 132 133 /* detect hardware features */ 134 static int fintek_hw_detect(struct fintek_dev *fintek) 135 { 136 unsigned long flags; 137 u8 chip_major, chip_minor; 138 u8 vendor_major, vendor_minor; 139 u8 portsel, ir_class; 140 u16 vendor, chip; 141 142 fintek_config_mode_enable(fintek); 143 144 /* Check if we're using config port 0x4e or 0x2e */ 145 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL); 146 if (portsel == 0xff) { 147 fit_pr(KERN_INFO, "first portsel read was bunk, trying alt"); 148 fintek_config_mode_disable(fintek); 149 fintek->cr_ip = CR_INDEX_PORT2; 150 fintek->cr_dp = CR_DATA_PORT2; 151 fintek_config_mode_enable(fintek); 152 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL); 153 } 154 fit_dbg("portsel reg: 0x%02x", portsel); 155 156 ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS); 157 fit_dbg("ir_class reg: 0x%02x", ir_class); 158 159 switch (ir_class) { 160 case CLASS_RX_2TX: 161 case CLASS_RX_1TX: 162 fintek->hw_tx_capable = true; 163 break; 164 case CLASS_RX_ONLY: 165 default: 166 fintek->hw_tx_capable = false; 167 break; 168 } 169 170 chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI); 171 chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO); 172 chip = chip_major << 8 | chip_minor; 173 174 vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI); 175 vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO); 176 vendor = vendor_major << 8 | vendor_minor; 177 178 if (vendor != VENDOR_ID_FINTEK) 179 fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor); 180 else 181 fit_dbg("Read Fintek vendor ID from chip"); 182 183 fintek_config_mode_disable(fintek); 184 185 spin_lock_irqsave(&fintek->fintek_lock, flags); 186 fintek->chip_major = chip_major; 187 fintek->chip_minor = chip_minor; 188 fintek->chip_vendor = vendor; 189 190 /* 191 * Newer reviews of this chipset uses port 8 instead of 5 192 */ 193 if ((chip != 0x0408) && (chip != 0x0804)) 194 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2; 195 else 196 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1; 197 198 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 199 200 return 0; 201 } 202 203 static void fintek_cir_ldev_init(struct fintek_dev *fintek) 204 { 205 /* Select CIR logical device and enable */ 206 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 207 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); 208 209 /* Write allocated CIR address and IRQ information to hardware */ 210 fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI); 211 fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO); 212 213 fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL); 214 215 fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)", 216 fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len); 217 } 218 219 /* enable CIR interrupts */ 220 static void fintek_enable_cir_irq(struct fintek_dev *fintek) 221 { 222 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS); 223 } 224 225 static void fintek_cir_regs_init(struct fintek_dev *fintek) 226 { 227 /* clear any and all stray interrupts */ 228 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 229 230 /* and finally, enable interrupts */ 231 fintek_enable_cir_irq(fintek); 232 } 233 234 static void fintek_enable_wake(struct fintek_dev *fintek) 235 { 236 fintek_config_mode_enable(fintek); 237 fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI); 238 239 /* Allow CIR PME's to wake system */ 240 fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG); 241 /* Enable CIR PME's */ 242 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG); 243 /* Clear CIR PME status register */ 244 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG); 245 /* Save state */ 246 fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG); 247 248 fintek_config_mode_disable(fintek); 249 } 250 251 static int fintek_cmdsize(u8 cmd, u8 subcmd) 252 { 253 int datasize = 0; 254 255 switch (cmd) { 256 case BUF_COMMAND_NULL: 257 if (subcmd == BUF_HW_CMD_HEADER) 258 datasize = 1; 259 break; 260 case BUF_HW_CMD_HEADER: 261 if (subcmd == BUF_CMD_G_REVISION) 262 datasize = 2; 263 break; 264 case BUF_COMMAND_HEADER: 265 switch (subcmd) { 266 case BUF_CMD_S_CARRIER: 267 case BUF_CMD_S_TIMEOUT: 268 case BUF_RSP_PULSE_COUNT: 269 datasize = 2; 270 break; 271 case BUF_CMD_SIG_END: 272 case BUF_CMD_S_TXMASK: 273 case BUF_CMD_S_RXSENSOR: 274 datasize = 1; 275 break; 276 } 277 } 278 279 return datasize; 280 } 281 282 /* process ir data stored in driver buffer */ 283 static void fintek_process_rx_ir_data(struct fintek_dev *fintek) 284 { 285 DEFINE_IR_RAW_EVENT(rawir); 286 u8 sample; 287 bool event = false; 288 int i; 289 290 for (i = 0; i < fintek->pkts; i++) { 291 sample = fintek->buf[i]; 292 switch (fintek->parser_state) { 293 case CMD_HEADER: 294 fintek->cmd = sample; 295 if ((fintek->cmd == BUF_COMMAND_HEADER) || 296 ((fintek->cmd & BUF_COMMAND_MASK) != 297 BUF_PULSE_BIT)) { 298 fintek->parser_state = SUBCMD; 299 continue; 300 } 301 fintek->rem = (fintek->cmd & BUF_LEN_MASK); 302 fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem); 303 if (fintek->rem) 304 fintek->parser_state = PARSE_IRDATA; 305 else 306 ir_raw_event_reset(fintek->rdev); 307 break; 308 case SUBCMD: 309 fintek->rem = fintek_cmdsize(fintek->cmd, sample); 310 fintek->parser_state = CMD_DATA; 311 break; 312 case CMD_DATA: 313 fintek->rem--; 314 break; 315 case PARSE_IRDATA: 316 fintek->rem--; 317 init_ir_raw_event(&rawir); 318 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); 319 rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK) 320 * CIR_SAMPLE_PERIOD); 321 322 fit_dbg("Storing %s with duration %d", 323 rawir.pulse ? "pulse" : "space", 324 rawir.duration); 325 if (ir_raw_event_store_with_filter(fintek->rdev, 326 &rawir)) 327 event = true; 328 break; 329 } 330 331 if ((fintek->parser_state != CMD_HEADER) && !fintek->rem) 332 fintek->parser_state = CMD_HEADER; 333 } 334 335 fintek->pkts = 0; 336 337 if (event) { 338 fit_dbg("Calling ir_raw_event_handle"); 339 ir_raw_event_handle(fintek->rdev); 340 } 341 } 342 343 /* copy data from hardware rx register into driver buffer */ 344 static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs) 345 { 346 unsigned long flags; 347 u8 sample, status; 348 349 spin_lock_irqsave(&fintek->fintek_lock, flags); 350 351 /* 352 * We must read data from CIR_RX_DATA until the hardware IR buffer 353 * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in 354 * the CIR_STATUS register 355 */ 356 do { 357 sample = fintek_cir_reg_read(fintek, CIR_RX_DATA); 358 fit_dbg("%s: sample: 0x%02x", __func__, sample); 359 360 fintek->buf[fintek->pkts] = sample; 361 fintek->pkts++; 362 363 status = fintek_cir_reg_read(fintek, CIR_STATUS); 364 if (!(status & CIR_STATUS_IRQ_EN)) 365 break; 366 } while (status & rx_irqs); 367 368 fintek_process_rx_ir_data(fintek); 369 370 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 371 } 372 373 static void fintek_cir_log_irqs(u8 status) 374 { 375 fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status, 376 status & CIR_STATUS_IRQ_EN ? " IRQEN" : "", 377 status & CIR_STATUS_TX_FINISH ? " TXF" : "", 378 status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "", 379 status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "", 380 status & CIR_STATUS_RX_RECEIVE ? " RXOK" : ""); 381 } 382 383 /* interrupt service routine for incoming and outgoing CIR data */ 384 static irqreturn_t fintek_cir_isr(int irq, void *data) 385 { 386 struct fintek_dev *fintek = data; 387 u8 status, rx_irqs; 388 389 fit_dbg_verbose("%s firing", __func__); 390 391 fintek_config_mode_enable(fintek); 392 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 393 fintek_config_mode_disable(fintek); 394 395 /* 396 * Get IR Status register contents. Write 1 to ack/clear 397 * 398 * bit: reg name - description 399 * 3: TX_FINISH - TX is finished 400 * 2: TX_UNDERRUN - TX underrun 401 * 1: RX_TIMEOUT - RX data timeout 402 * 0: RX_RECEIVE - RX data received 403 */ 404 status = fintek_cir_reg_read(fintek, CIR_STATUS); 405 if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) { 406 fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status); 407 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 408 return IRQ_RETVAL(IRQ_NONE); 409 } 410 411 if (debug) 412 fintek_cir_log_irqs(status); 413 414 rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT); 415 if (rx_irqs) 416 fintek_get_rx_ir_data(fintek, rx_irqs); 417 418 /* ack/clear all irq flags we've got */ 419 fintek_cir_reg_write(fintek, status, CIR_STATUS); 420 421 fit_dbg_verbose("%s done", __func__); 422 return IRQ_RETVAL(IRQ_HANDLED); 423 } 424 425 static void fintek_enable_cir(struct fintek_dev *fintek) 426 { 427 /* set IRQ enabled */ 428 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS); 429 430 fintek_config_mode_enable(fintek); 431 432 /* enable the CIR logical device */ 433 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 434 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); 435 436 fintek_config_mode_disable(fintek); 437 438 /* clear all pending interrupts */ 439 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 440 441 /* enable interrupts */ 442 fintek_enable_cir_irq(fintek); 443 } 444 445 static void fintek_disable_cir(struct fintek_dev *fintek) 446 { 447 fintek_config_mode_enable(fintek); 448 449 /* disable the CIR logical device */ 450 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 451 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN); 452 453 fintek_config_mode_disable(fintek); 454 } 455 456 static int fintek_open(struct rc_dev *dev) 457 { 458 struct fintek_dev *fintek = dev->priv; 459 unsigned long flags; 460 461 spin_lock_irqsave(&fintek->fintek_lock, flags); 462 fintek_enable_cir(fintek); 463 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 464 465 return 0; 466 } 467 468 static void fintek_close(struct rc_dev *dev) 469 { 470 struct fintek_dev *fintek = dev->priv; 471 unsigned long flags; 472 473 spin_lock_irqsave(&fintek->fintek_lock, flags); 474 fintek_disable_cir(fintek); 475 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 476 } 477 478 /* Allocate memory, probe hardware, and initialize everything */ 479 static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) 480 { 481 struct fintek_dev *fintek; 482 struct rc_dev *rdev; 483 int ret = -ENOMEM; 484 485 fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL); 486 if (!fintek) 487 return ret; 488 489 /* input device for IR remote (and tx) */ 490 rdev = rc_allocate_device(RC_DRIVER_IR_RAW); 491 if (!rdev) 492 goto exit_free_dev_rdev; 493 494 ret = -ENODEV; 495 /* validate pnp resources */ 496 if (!pnp_port_valid(pdev, 0)) { 497 dev_err(&pdev->dev, "IR PNP Port not valid!\n"); 498 goto exit_free_dev_rdev; 499 } 500 501 if (!pnp_irq_valid(pdev, 0)) { 502 dev_err(&pdev->dev, "IR PNP IRQ not valid!\n"); 503 goto exit_free_dev_rdev; 504 } 505 506 fintek->cir_addr = pnp_port_start(pdev, 0); 507 fintek->cir_irq = pnp_irq(pdev, 0); 508 fintek->cir_port_len = pnp_port_len(pdev, 0); 509 510 fintek->cr_ip = CR_INDEX_PORT; 511 fintek->cr_dp = CR_DATA_PORT; 512 513 spin_lock_init(&fintek->fintek_lock); 514 515 pnp_set_drvdata(pdev, fintek); 516 fintek->pdev = pdev; 517 518 ret = fintek_hw_detect(fintek); 519 if (ret) 520 goto exit_free_dev_rdev; 521 522 /* Initialize CIR & CIR Wake Logical Devices */ 523 fintek_config_mode_enable(fintek); 524 fintek_cir_ldev_init(fintek); 525 fintek_config_mode_disable(fintek); 526 527 /* Initialize CIR & CIR Wake Config Registers */ 528 fintek_cir_regs_init(fintek); 529 530 /* Set up the rc device */ 531 rdev->priv = fintek; 532 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 533 rdev->open = fintek_open; 534 rdev->close = fintek_close; 535 rdev->device_name = FINTEK_DESCRIPTION; 536 rdev->input_phys = "fintek/cir0"; 537 rdev->input_id.bustype = BUS_HOST; 538 rdev->input_id.vendor = VENDOR_ID_FINTEK; 539 rdev->input_id.product = fintek->chip_major; 540 rdev->input_id.version = fintek->chip_minor; 541 rdev->dev.parent = &pdev->dev; 542 rdev->driver_name = FINTEK_DRIVER_NAME; 543 rdev->map_name = RC_MAP_RC6_MCE; 544 rdev->timeout = US_TO_NS(1000); 545 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ 546 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); 547 548 fintek->rdev = rdev; 549 550 ret = -EBUSY; 551 /* now claim resources */ 552 if (!request_region(fintek->cir_addr, 553 fintek->cir_port_len, FINTEK_DRIVER_NAME)) 554 goto exit_free_dev_rdev; 555 556 if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED, 557 FINTEK_DRIVER_NAME, (void *)fintek)) 558 goto exit_free_cir_addr; 559 560 ret = rc_register_device(rdev); 561 if (ret) 562 goto exit_free_irq; 563 564 device_init_wakeup(&pdev->dev, true); 565 566 fit_pr(KERN_NOTICE, "driver has been successfully loaded\n"); 567 if (debug) 568 cir_dump_regs(fintek); 569 570 return 0; 571 572 exit_free_irq: 573 free_irq(fintek->cir_irq, fintek); 574 exit_free_cir_addr: 575 release_region(fintek->cir_addr, fintek->cir_port_len); 576 exit_free_dev_rdev: 577 rc_free_device(rdev); 578 kfree(fintek); 579 580 return ret; 581 } 582 583 static void fintek_remove(struct pnp_dev *pdev) 584 { 585 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 586 unsigned long flags; 587 588 spin_lock_irqsave(&fintek->fintek_lock, flags); 589 /* disable CIR */ 590 fintek_disable_cir(fintek); 591 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 592 /* enable CIR Wake (for IR power-on) */ 593 fintek_enable_wake(fintek); 594 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 595 596 /* free resources */ 597 free_irq(fintek->cir_irq, fintek); 598 release_region(fintek->cir_addr, fintek->cir_port_len); 599 600 rc_unregister_device(fintek->rdev); 601 602 kfree(fintek); 603 } 604 605 static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state) 606 { 607 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 608 unsigned long flags; 609 610 fit_dbg("%s called", __func__); 611 612 spin_lock_irqsave(&fintek->fintek_lock, flags); 613 614 /* disable all CIR interrupts */ 615 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 616 617 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 618 619 fintek_config_mode_enable(fintek); 620 621 /* disable cir logical dev */ 622 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 623 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN); 624 625 fintek_config_mode_disable(fintek); 626 627 /* make sure wake is enabled */ 628 fintek_enable_wake(fintek); 629 630 return 0; 631 } 632 633 static int fintek_resume(struct pnp_dev *pdev) 634 { 635 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 636 637 fit_dbg("%s called", __func__); 638 639 /* open interrupt */ 640 fintek_enable_cir_irq(fintek); 641 642 /* Enable CIR logical device */ 643 fintek_config_mode_enable(fintek); 644 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 645 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); 646 647 fintek_config_mode_disable(fintek); 648 649 fintek_cir_regs_init(fintek); 650 651 return 0; 652 } 653 654 static void fintek_shutdown(struct pnp_dev *pdev) 655 { 656 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 657 fintek_enable_wake(fintek); 658 } 659 660 static const struct pnp_device_id fintek_ids[] = { 661 { "FIT0002", 0 }, /* CIR */ 662 { "", 0 }, 663 }; 664 665 static struct pnp_driver fintek_driver = { 666 .name = FINTEK_DRIVER_NAME, 667 .id_table = fintek_ids, 668 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, 669 .probe = fintek_probe, 670 .remove = fintek_remove, 671 .suspend = fintek_suspend, 672 .resume = fintek_resume, 673 .shutdown = fintek_shutdown, 674 }; 675 676 module_param(debug, int, S_IRUGO | S_IWUSR); 677 MODULE_PARM_DESC(debug, "Enable debugging output"); 678 679 MODULE_DEVICE_TABLE(pnp, fintek_ids); 680 MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver"); 681 682 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); 683 MODULE_LICENSE("GPL"); 684 685 module_pnp_driver(fintek_driver); 686