1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR 4 * 5 * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com> 6 * 7 * Special thanks to Fintek for providing hardware and spec sheets. 8 * This driver is based upon the nuvoton, ite and ene drivers for 9 * similar hardware. 10 */ 11 12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pnp.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/sched.h> 20 #include <linux/slab.h> 21 #include <media/rc-core.h> 22 23 #include "fintek-cir.h" 24 25 /* write val to config reg */ 26 static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg) 27 { 28 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)", 29 __func__, reg, val, fintek->cr_ip, fintek->cr_dp); 30 outb(reg, fintek->cr_ip); 31 outb(val, fintek->cr_dp); 32 } 33 34 /* read val from config reg */ 35 static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg) 36 { 37 u8 val; 38 39 outb(reg, fintek->cr_ip); 40 val = inb(fintek->cr_dp); 41 42 fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)", 43 __func__, reg, val, fintek->cr_ip, fintek->cr_dp); 44 return val; 45 } 46 47 /* update config register bit without changing other bits */ 48 static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) 49 { 50 u8 tmp = fintek_cr_read(fintek, reg) | val; 51 fintek_cr_write(fintek, tmp, reg); 52 } 53 54 /* clear config register bit without changing other bits */ 55 static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) 56 { 57 u8 tmp = fintek_cr_read(fintek, reg) & ~val; 58 fintek_cr_write(fintek, tmp, reg); 59 } 60 61 /* enter config mode */ 62 static inline void fintek_config_mode_enable(struct fintek_dev *fintek) 63 { 64 /* Enabling Config Mode explicitly requires writing 2x */ 65 outb(CONFIG_REG_ENABLE, fintek->cr_ip); 66 outb(CONFIG_REG_ENABLE, fintek->cr_ip); 67 } 68 69 /* exit config mode */ 70 static inline void fintek_config_mode_disable(struct fintek_dev *fintek) 71 { 72 outb(CONFIG_REG_DISABLE, fintek->cr_ip); 73 } 74 75 /* 76 * When you want to address a specific logical device, write its logical 77 * device number to GCR_LOGICAL_DEV_NO 78 */ 79 static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev) 80 { 81 fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO); 82 } 83 84 /* write val to cir config register */ 85 static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset) 86 { 87 outb(val, fintek->cir_addr + offset); 88 } 89 90 /* read val from cir config register */ 91 static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset) 92 { 93 return inb(fintek->cir_addr + offset); 94 } 95 96 /* dump current cir register contents */ 97 static void cir_dump_regs(struct fintek_dev *fintek) 98 { 99 fintek_config_mode_enable(fintek); 100 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 101 102 pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME); 103 pr_info(" * CR CIR BASE ADDR: 0x%x\n", 104 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) | 105 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO)); 106 pr_info(" * CR CIR IRQ NUM: 0x%x\n", 107 fintek_cr_read(fintek, CIR_CR_IRQ_SEL)); 108 109 fintek_config_mode_disable(fintek); 110 111 pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME); 112 pr_info(" * STATUS: 0x%x\n", 113 fintek_cir_reg_read(fintek, CIR_STATUS)); 114 pr_info(" * CONTROL: 0x%x\n", 115 fintek_cir_reg_read(fintek, CIR_CONTROL)); 116 pr_info(" * RX_DATA: 0x%x\n", 117 fintek_cir_reg_read(fintek, CIR_RX_DATA)); 118 pr_info(" * TX_CONTROL: 0x%x\n", 119 fintek_cir_reg_read(fintek, CIR_TX_CONTROL)); 120 pr_info(" * TX_DATA: 0x%x\n", 121 fintek_cir_reg_read(fintek, CIR_TX_DATA)); 122 } 123 124 /* detect hardware features */ 125 static int fintek_hw_detect(struct fintek_dev *fintek) 126 { 127 unsigned long flags; 128 u8 chip_major, chip_minor; 129 u8 vendor_major, vendor_minor; 130 u8 portsel, ir_class; 131 u16 vendor, chip; 132 133 fintek_config_mode_enable(fintek); 134 135 /* Check if we're using config port 0x4e or 0x2e */ 136 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL); 137 if (portsel == 0xff) { 138 fit_pr(KERN_INFO, "first portsel read was bunk, trying alt"); 139 fintek_config_mode_disable(fintek); 140 fintek->cr_ip = CR_INDEX_PORT2; 141 fintek->cr_dp = CR_DATA_PORT2; 142 fintek_config_mode_enable(fintek); 143 portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL); 144 } 145 fit_dbg("portsel reg: 0x%02x", portsel); 146 147 ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS); 148 fit_dbg("ir_class reg: 0x%02x", ir_class); 149 150 switch (ir_class) { 151 case CLASS_RX_2TX: 152 case CLASS_RX_1TX: 153 fintek->hw_tx_capable = true; 154 break; 155 case CLASS_RX_ONLY: 156 default: 157 fintek->hw_tx_capable = false; 158 break; 159 } 160 161 chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI); 162 chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO); 163 chip = chip_major << 8 | chip_minor; 164 165 vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI); 166 vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO); 167 vendor = vendor_major << 8 | vendor_minor; 168 169 if (vendor != VENDOR_ID_FINTEK) 170 fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor); 171 else 172 fit_dbg("Read Fintek vendor ID from chip"); 173 174 fintek_config_mode_disable(fintek); 175 176 spin_lock_irqsave(&fintek->fintek_lock, flags); 177 fintek->chip_major = chip_major; 178 fintek->chip_minor = chip_minor; 179 fintek->chip_vendor = vendor; 180 181 /* 182 * Newer reviews of this chipset uses port 8 instead of 5 183 */ 184 if ((chip != 0x0408) && (chip != 0x0804)) 185 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2; 186 else 187 fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1; 188 189 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 190 191 return 0; 192 } 193 194 static void fintek_cir_ldev_init(struct fintek_dev *fintek) 195 { 196 /* Select CIR logical device and enable */ 197 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 198 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); 199 200 /* Write allocated CIR address and IRQ information to hardware */ 201 fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI); 202 fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO); 203 204 fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL); 205 206 fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)", 207 fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len); 208 } 209 210 /* enable CIR interrupts */ 211 static void fintek_enable_cir_irq(struct fintek_dev *fintek) 212 { 213 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS); 214 } 215 216 static void fintek_cir_regs_init(struct fintek_dev *fintek) 217 { 218 /* clear any and all stray interrupts */ 219 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 220 221 /* and finally, enable interrupts */ 222 fintek_enable_cir_irq(fintek); 223 } 224 225 static void fintek_enable_wake(struct fintek_dev *fintek) 226 { 227 fintek_config_mode_enable(fintek); 228 fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI); 229 230 /* Allow CIR PME's to wake system */ 231 fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG); 232 /* Enable CIR PME's */ 233 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG); 234 /* Clear CIR PME status register */ 235 fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG); 236 /* Save state */ 237 fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG); 238 239 fintek_config_mode_disable(fintek); 240 } 241 242 static int fintek_cmdsize(u8 cmd, u8 subcmd) 243 { 244 int datasize = 0; 245 246 switch (cmd) { 247 case BUF_COMMAND_NULL: 248 if (subcmd == BUF_HW_CMD_HEADER) 249 datasize = 1; 250 break; 251 case BUF_HW_CMD_HEADER: 252 if (subcmd == BUF_CMD_G_REVISION) 253 datasize = 2; 254 break; 255 case BUF_COMMAND_HEADER: 256 switch (subcmd) { 257 case BUF_CMD_S_CARRIER: 258 case BUF_CMD_S_TIMEOUT: 259 case BUF_RSP_PULSE_COUNT: 260 datasize = 2; 261 break; 262 case BUF_CMD_SIG_END: 263 case BUF_CMD_S_TXMASK: 264 case BUF_CMD_S_RXSENSOR: 265 datasize = 1; 266 break; 267 } 268 } 269 270 return datasize; 271 } 272 273 /* process ir data stored in driver buffer */ 274 static void fintek_process_rx_ir_data(struct fintek_dev *fintek) 275 { 276 struct ir_raw_event rawir = {}; 277 u8 sample; 278 bool event = false; 279 int i; 280 281 for (i = 0; i < fintek->pkts; i++) { 282 sample = fintek->buf[i]; 283 switch (fintek->parser_state) { 284 case CMD_HEADER: 285 fintek->cmd = sample; 286 if ((fintek->cmd == BUF_COMMAND_HEADER) || 287 ((fintek->cmd & BUF_COMMAND_MASK) != 288 BUF_PULSE_BIT)) { 289 fintek->parser_state = SUBCMD; 290 continue; 291 } 292 fintek->rem = (fintek->cmd & BUF_LEN_MASK); 293 fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem); 294 if (fintek->rem) 295 fintek->parser_state = PARSE_IRDATA; 296 else 297 ir_raw_event_reset(fintek->rdev); 298 break; 299 case SUBCMD: 300 fintek->rem = fintek_cmdsize(fintek->cmd, sample); 301 fintek->parser_state = CMD_DATA; 302 break; 303 case CMD_DATA: 304 fintek->rem--; 305 break; 306 case PARSE_IRDATA: 307 fintek->rem--; 308 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); 309 rawir.duration = US_TO_NS((sample & BUF_SAMPLE_MASK) 310 * CIR_SAMPLE_PERIOD); 311 312 fit_dbg("Storing %s with duration %d", 313 rawir.pulse ? "pulse" : "space", 314 rawir.duration); 315 if (ir_raw_event_store_with_filter(fintek->rdev, 316 &rawir)) 317 event = true; 318 break; 319 } 320 321 if ((fintek->parser_state != CMD_HEADER) && !fintek->rem) 322 fintek->parser_state = CMD_HEADER; 323 } 324 325 fintek->pkts = 0; 326 327 if (event) { 328 fit_dbg("Calling ir_raw_event_handle"); 329 ir_raw_event_handle(fintek->rdev); 330 } 331 } 332 333 /* copy data from hardware rx register into driver buffer */ 334 static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs) 335 { 336 unsigned long flags; 337 u8 sample, status; 338 339 spin_lock_irqsave(&fintek->fintek_lock, flags); 340 341 /* 342 * We must read data from CIR_RX_DATA until the hardware IR buffer 343 * is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in 344 * the CIR_STATUS register 345 */ 346 do { 347 sample = fintek_cir_reg_read(fintek, CIR_RX_DATA); 348 fit_dbg("%s: sample: 0x%02x", __func__, sample); 349 350 fintek->buf[fintek->pkts] = sample; 351 fintek->pkts++; 352 353 status = fintek_cir_reg_read(fintek, CIR_STATUS); 354 if (!(status & CIR_STATUS_IRQ_EN)) 355 break; 356 } while (status & rx_irqs); 357 358 fintek_process_rx_ir_data(fintek); 359 360 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 361 } 362 363 static void fintek_cir_log_irqs(u8 status) 364 { 365 fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status, 366 status & CIR_STATUS_IRQ_EN ? " IRQEN" : "", 367 status & CIR_STATUS_TX_FINISH ? " TXF" : "", 368 status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "", 369 status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "", 370 status & CIR_STATUS_RX_RECEIVE ? " RXOK" : ""); 371 } 372 373 /* interrupt service routine for incoming and outgoing CIR data */ 374 static irqreturn_t fintek_cir_isr(int irq, void *data) 375 { 376 struct fintek_dev *fintek = data; 377 u8 status, rx_irqs; 378 379 fit_dbg_verbose("%s firing", __func__); 380 381 fintek_config_mode_enable(fintek); 382 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 383 fintek_config_mode_disable(fintek); 384 385 /* 386 * Get IR Status register contents. Write 1 to ack/clear 387 * 388 * bit: reg name - description 389 * 3: TX_FINISH - TX is finished 390 * 2: TX_UNDERRUN - TX underrun 391 * 1: RX_TIMEOUT - RX data timeout 392 * 0: RX_RECEIVE - RX data received 393 */ 394 status = fintek_cir_reg_read(fintek, CIR_STATUS); 395 if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) { 396 fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status); 397 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 398 return IRQ_RETVAL(IRQ_NONE); 399 } 400 401 if (debug) 402 fintek_cir_log_irqs(status); 403 404 rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT); 405 if (rx_irqs) 406 fintek_get_rx_ir_data(fintek, rx_irqs); 407 408 /* ack/clear all irq flags we've got */ 409 fintek_cir_reg_write(fintek, status, CIR_STATUS); 410 411 fit_dbg_verbose("%s done", __func__); 412 return IRQ_RETVAL(IRQ_HANDLED); 413 } 414 415 static void fintek_enable_cir(struct fintek_dev *fintek) 416 { 417 /* set IRQ enabled */ 418 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS); 419 420 fintek_config_mode_enable(fintek); 421 422 /* enable the CIR logical device */ 423 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 424 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); 425 426 fintek_config_mode_disable(fintek); 427 428 /* clear all pending interrupts */ 429 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 430 431 /* enable interrupts */ 432 fintek_enable_cir_irq(fintek); 433 } 434 435 static void fintek_disable_cir(struct fintek_dev *fintek) 436 { 437 fintek_config_mode_enable(fintek); 438 439 /* disable the CIR logical device */ 440 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 441 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN); 442 443 fintek_config_mode_disable(fintek); 444 } 445 446 static int fintek_open(struct rc_dev *dev) 447 { 448 struct fintek_dev *fintek = dev->priv; 449 unsigned long flags; 450 451 spin_lock_irqsave(&fintek->fintek_lock, flags); 452 fintek_enable_cir(fintek); 453 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 454 455 return 0; 456 } 457 458 static void fintek_close(struct rc_dev *dev) 459 { 460 struct fintek_dev *fintek = dev->priv; 461 unsigned long flags; 462 463 spin_lock_irqsave(&fintek->fintek_lock, flags); 464 fintek_disable_cir(fintek); 465 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 466 } 467 468 /* Allocate memory, probe hardware, and initialize everything */ 469 static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) 470 { 471 struct fintek_dev *fintek; 472 struct rc_dev *rdev; 473 int ret = -ENOMEM; 474 475 fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL); 476 if (!fintek) 477 return ret; 478 479 /* input device for IR remote (and tx) */ 480 rdev = rc_allocate_device(RC_DRIVER_IR_RAW); 481 if (!rdev) 482 goto exit_free_dev_rdev; 483 484 ret = -ENODEV; 485 /* validate pnp resources */ 486 if (!pnp_port_valid(pdev, 0)) { 487 dev_err(&pdev->dev, "IR PNP Port not valid!\n"); 488 goto exit_free_dev_rdev; 489 } 490 491 if (!pnp_irq_valid(pdev, 0)) { 492 dev_err(&pdev->dev, "IR PNP IRQ not valid!\n"); 493 goto exit_free_dev_rdev; 494 } 495 496 fintek->cir_addr = pnp_port_start(pdev, 0); 497 fintek->cir_irq = pnp_irq(pdev, 0); 498 fintek->cir_port_len = pnp_port_len(pdev, 0); 499 500 fintek->cr_ip = CR_INDEX_PORT; 501 fintek->cr_dp = CR_DATA_PORT; 502 503 spin_lock_init(&fintek->fintek_lock); 504 505 pnp_set_drvdata(pdev, fintek); 506 fintek->pdev = pdev; 507 508 ret = fintek_hw_detect(fintek); 509 if (ret) 510 goto exit_free_dev_rdev; 511 512 /* Initialize CIR & CIR Wake Logical Devices */ 513 fintek_config_mode_enable(fintek); 514 fintek_cir_ldev_init(fintek); 515 fintek_config_mode_disable(fintek); 516 517 /* Initialize CIR & CIR Wake Config Registers */ 518 fintek_cir_regs_init(fintek); 519 520 /* Set up the rc device */ 521 rdev->priv = fintek; 522 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 523 rdev->open = fintek_open; 524 rdev->close = fintek_close; 525 rdev->device_name = FINTEK_DESCRIPTION; 526 rdev->input_phys = "fintek/cir0"; 527 rdev->input_id.bustype = BUS_HOST; 528 rdev->input_id.vendor = VENDOR_ID_FINTEK; 529 rdev->input_id.product = fintek->chip_major; 530 rdev->input_id.version = fintek->chip_minor; 531 rdev->dev.parent = &pdev->dev; 532 rdev->driver_name = FINTEK_DRIVER_NAME; 533 rdev->map_name = RC_MAP_RC6_MCE; 534 rdev->timeout = US_TO_NS(1000); 535 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ 536 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); 537 538 fintek->rdev = rdev; 539 540 ret = -EBUSY; 541 /* now claim resources */ 542 if (!request_region(fintek->cir_addr, 543 fintek->cir_port_len, FINTEK_DRIVER_NAME)) 544 goto exit_free_dev_rdev; 545 546 if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED, 547 FINTEK_DRIVER_NAME, (void *)fintek)) 548 goto exit_free_cir_addr; 549 550 ret = rc_register_device(rdev); 551 if (ret) 552 goto exit_free_irq; 553 554 device_init_wakeup(&pdev->dev, true); 555 556 fit_pr(KERN_NOTICE, "driver has been successfully loaded\n"); 557 if (debug) 558 cir_dump_regs(fintek); 559 560 return 0; 561 562 exit_free_irq: 563 free_irq(fintek->cir_irq, fintek); 564 exit_free_cir_addr: 565 release_region(fintek->cir_addr, fintek->cir_port_len); 566 exit_free_dev_rdev: 567 rc_free_device(rdev); 568 kfree(fintek); 569 570 return ret; 571 } 572 573 static void fintek_remove(struct pnp_dev *pdev) 574 { 575 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 576 unsigned long flags; 577 578 spin_lock_irqsave(&fintek->fintek_lock, flags); 579 /* disable CIR */ 580 fintek_disable_cir(fintek); 581 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 582 /* enable CIR Wake (for IR power-on) */ 583 fintek_enable_wake(fintek); 584 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 585 586 /* free resources */ 587 free_irq(fintek->cir_irq, fintek); 588 release_region(fintek->cir_addr, fintek->cir_port_len); 589 590 rc_unregister_device(fintek->rdev); 591 592 kfree(fintek); 593 } 594 595 static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state) 596 { 597 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 598 unsigned long flags; 599 600 fit_dbg("%s called", __func__); 601 602 spin_lock_irqsave(&fintek->fintek_lock, flags); 603 604 /* disable all CIR interrupts */ 605 fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); 606 607 spin_unlock_irqrestore(&fintek->fintek_lock, flags); 608 609 fintek_config_mode_enable(fintek); 610 611 /* disable cir logical dev */ 612 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 613 fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN); 614 615 fintek_config_mode_disable(fintek); 616 617 /* make sure wake is enabled */ 618 fintek_enable_wake(fintek); 619 620 return 0; 621 } 622 623 static int fintek_resume(struct pnp_dev *pdev) 624 { 625 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 626 627 fit_dbg("%s called", __func__); 628 629 /* open interrupt */ 630 fintek_enable_cir_irq(fintek); 631 632 /* Enable CIR logical device */ 633 fintek_config_mode_enable(fintek); 634 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 635 fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); 636 637 fintek_config_mode_disable(fintek); 638 639 fintek_cir_regs_init(fintek); 640 641 return 0; 642 } 643 644 static void fintek_shutdown(struct pnp_dev *pdev) 645 { 646 struct fintek_dev *fintek = pnp_get_drvdata(pdev); 647 fintek_enable_wake(fintek); 648 } 649 650 static const struct pnp_device_id fintek_ids[] = { 651 { "FIT0002", 0 }, /* CIR */ 652 { "", 0 }, 653 }; 654 655 static struct pnp_driver fintek_driver = { 656 .name = FINTEK_DRIVER_NAME, 657 .id_table = fintek_ids, 658 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, 659 .probe = fintek_probe, 660 .remove = fintek_remove, 661 .suspend = fintek_suspend, 662 .resume = fintek_resume, 663 .shutdown = fintek_shutdown, 664 }; 665 666 module_param(debug, int, S_IRUGO | S_IWUSR); 667 MODULE_PARM_DESC(debug, "Enable debugging output"); 668 669 MODULE_DEVICE_TABLE(pnp, fintek_ids); 670 MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver"); 671 672 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); 673 MODULE_LICENSE("GPL"); 674 675 module_pnp_driver(fintek_driver); 676