1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Xilinx MIPI CSI-2 Rx Subsystem 4 * 5 * Copyright (C) 2016 - 2020 Xilinx, Inc. 6 * 7 * Contacts: Vishal Sagar <vishal.sagar@xilinx.com> 8 * 9 */ 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/v4l2-subdev.h> 20 #include <media/media-entity.h> 21 #include <media/mipi-csi2.h> 22 #include <media/v4l2-common.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-subdev.h> 26 #include "xilinx-vip.h" 27 28 /* Register register map */ 29 #define XCSI_CCR_OFFSET 0x00 30 #define XCSI_CCR_SOFTRESET BIT(1) 31 #define XCSI_CCR_ENABLE BIT(0) 32 33 #define XCSI_PCR_OFFSET 0x04 34 #define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3) 35 #define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0) 36 37 #define XCSI_CSR_OFFSET 0x10 38 #define XCSI_CSR_PKTCNT GENMASK(31, 16) 39 #define XCSI_CSR_SPFIFOFULL BIT(3) 40 #define XCSI_CSR_SPFIFONE BIT(2) 41 #define XCSI_CSR_SLBF BIT(1) 42 #define XCSI_CSR_RIPCD BIT(0) 43 44 #define XCSI_GIER_OFFSET 0x20 45 #define XCSI_GIER_GIE BIT(0) 46 47 #define XCSI_ISR_OFFSET 0x24 48 #define XCSI_IER_OFFSET 0x28 49 50 #define XCSI_ISR_FR BIT(31) 51 #define XCSI_ISR_VCXFE BIT(30) 52 #define XCSI_ISR_WCC BIT(22) 53 #define XCSI_ISR_ILC BIT(21) 54 #define XCSI_ISR_SPFIFOF BIT(20) 55 #define XCSI_ISR_SPFIFONE BIT(19) 56 #define XCSI_ISR_SLBF BIT(18) 57 #define XCSI_ISR_STOP BIT(17) 58 #define XCSI_ISR_SOTERR BIT(13) 59 #define XCSI_ISR_SOTSYNCERR BIT(12) 60 #define XCSI_ISR_ECC2BERR BIT(11) 61 #define XCSI_ISR_ECC1BERR BIT(10) 62 #define XCSI_ISR_CRCERR BIT(9) 63 #define XCSI_ISR_DATAIDERR BIT(8) 64 #define XCSI_ISR_VC3FSYNCERR BIT(7) 65 #define XCSI_ISR_VC3FLVLERR BIT(6) 66 #define XCSI_ISR_VC2FSYNCERR BIT(5) 67 #define XCSI_ISR_VC2FLVLERR BIT(4) 68 #define XCSI_ISR_VC1FSYNCERR BIT(3) 69 #define XCSI_ISR_VC1FLVLERR BIT(2) 70 #define XCSI_ISR_VC0FSYNCERR BIT(1) 71 #define XCSI_ISR_VC0FLVLERR BIT(0) 72 73 #define XCSI_ISR_ALLINTR_MASK (0xc07e3fff) 74 75 /* 76 * Removed VCXFE mask as it doesn't exist in IER 77 * Removed STOP state irq as this will keep driver in irq handler only 78 */ 79 #define XCSI_IER_INTR_MASK (XCSI_ISR_ALLINTR_MASK &\ 80 ~(XCSI_ISR_STOP | XCSI_ISR_VCXFE)) 81 82 #define XCSI_SPKTR_OFFSET 0x30 83 #define XCSI_SPKTR_DATA GENMASK(23, 8) 84 #define XCSI_SPKTR_VC GENMASK(7, 6) 85 #define XCSI_SPKTR_DT GENMASK(5, 0) 86 #define XCSI_SPKT_FIFO_DEPTH 31 87 88 #define XCSI_VCXR_OFFSET 0x34 89 #define XCSI_VCXR_VCERR GENMASK(23, 0) 90 #define XCSI_VCXR_FSYNCERR BIT(1) 91 #define XCSI_VCXR_FLVLERR BIT(0) 92 93 #define XCSI_CLKINFR_OFFSET 0x3C 94 #define XCSI_CLKINFR_STOP BIT(1) 95 96 #define XCSI_DLXINFR_OFFSET 0x40 97 #define XCSI_DLXINFR_STOP BIT(5) 98 #define XCSI_DLXINFR_SOTERR BIT(1) 99 #define XCSI_DLXINFR_SOTSYNCERR BIT(0) 100 #define XCSI_MAXDL_COUNT 0x4 101 102 #define XCSI_VCXINF1R_OFFSET 0x60 103 #define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16) 104 #define XCSI_VCXINF1R_LINECOUNT_SHIFT 16 105 #define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0) 106 107 #define XCSI_VCXINF2R_OFFSET 0x64 108 #define XCSI_VCXINF2R_DT GENMASK(5, 0) 109 #define XCSI_MAXVCX_COUNT 16 110 111 /* 112 * Sink pad connected to sensor source pad. 113 * Source pad connected to next module like demosaic. 114 */ 115 #define XCSI_MEDIA_PADS 2 116 #define XCSI_DEFAULT_WIDTH 1920 117 #define XCSI_DEFAULT_HEIGHT 1080 118 119 #define XCSI_VCX_START 4 120 #define XCSI_MAX_VC 4 121 #define XCSI_MAX_VCX 16 122 123 #define XCSI_NEXTREG_OFFSET 4 124 125 /* There are 2 events frame sync and frame level error per VC */ 126 #define XCSI_VCX_NUM_EVENTS ((XCSI_MAX_VCX - XCSI_MAX_VC) * 2) 127 128 /** 129 * struct xcsi2rxss_event - Event log structure 130 * @mask: Event mask 131 * @name: Name of the event 132 */ 133 struct xcsi2rxss_event { 134 u32 mask; 135 const char *name; 136 }; 137 138 static const struct xcsi2rxss_event xcsi2rxss_events[] = { 139 { XCSI_ISR_FR, "Frame Received" }, 140 { XCSI_ISR_VCXFE, "VCX Frame Errors" }, 141 { XCSI_ISR_WCC, "Word Count Errors" }, 142 { XCSI_ISR_ILC, "Invalid Lane Count Error" }, 143 { XCSI_ISR_SPFIFOF, "Short Packet FIFO OverFlow Error" }, 144 { XCSI_ISR_SPFIFONE, "Short Packet FIFO Not Empty" }, 145 { XCSI_ISR_SLBF, "Streamline Buffer Full Error" }, 146 { XCSI_ISR_STOP, "Lane Stop State" }, 147 { XCSI_ISR_SOTERR, "SOT Error" }, 148 { XCSI_ISR_SOTSYNCERR, "SOT Sync Error" }, 149 { XCSI_ISR_ECC2BERR, "2 Bit ECC Unrecoverable Error" }, 150 { XCSI_ISR_ECC1BERR, "1 Bit ECC Recoverable Error" }, 151 { XCSI_ISR_CRCERR, "CRC Error" }, 152 { XCSI_ISR_DATAIDERR, "Data Id Error" }, 153 { XCSI_ISR_VC3FSYNCERR, "Virtual Channel 3 Frame Sync Error" }, 154 { XCSI_ISR_VC3FLVLERR, "Virtual Channel 3 Frame Level Error" }, 155 { XCSI_ISR_VC2FSYNCERR, "Virtual Channel 2 Frame Sync Error" }, 156 { XCSI_ISR_VC2FLVLERR, "Virtual Channel 2 Frame Level Error" }, 157 { XCSI_ISR_VC1FSYNCERR, "Virtual Channel 1 Frame Sync Error" }, 158 { XCSI_ISR_VC1FLVLERR, "Virtual Channel 1 Frame Level Error" }, 159 { XCSI_ISR_VC0FSYNCERR, "Virtual Channel 0 Frame Sync Error" }, 160 { XCSI_ISR_VC0FLVLERR, "Virtual Channel 0 Frame Level Error" } 161 }; 162 163 #define XCSI_NUM_EVENTS ARRAY_SIZE(xcsi2rxss_events) 164 165 /* 166 * This table provides a mapping between CSI-2 Data type 167 * and media bus formats 168 */ 169 static const u32 xcsi2dt_mbus_lut[][2] = { 170 { MIPI_CSI2_DT_YUV422_8B, MEDIA_BUS_FMT_UYVY8_1X16 }, 171 { MIPI_CSI2_DT_YUV422_10B, MEDIA_BUS_FMT_UYVY10_1X20 }, 172 { MIPI_CSI2_DT_RGB444, 0 }, 173 { MIPI_CSI2_DT_RGB555, 0 }, 174 { MIPI_CSI2_DT_RGB565, 0 }, 175 { MIPI_CSI2_DT_RGB666, 0 }, 176 { MIPI_CSI2_DT_RGB888, MEDIA_BUS_FMT_RBG888_1X24 }, 177 { MIPI_CSI2_DT_RAW6, 0 }, 178 { MIPI_CSI2_DT_RAW7, 0 }, 179 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SRGGB8_1X8 }, 180 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SBGGR8_1X8 }, 181 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SGBRG8_1X8 }, 182 { MIPI_CSI2_DT_RAW8, MEDIA_BUS_FMT_SGRBG8_1X8 }, 183 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SRGGB10_1X10 }, 184 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SBGGR10_1X10 }, 185 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SGBRG10_1X10 }, 186 { MIPI_CSI2_DT_RAW10, MEDIA_BUS_FMT_SGRBG10_1X10 }, 187 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SRGGB12_1X12 }, 188 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SBGGR12_1X12 }, 189 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SGBRG12_1X12 }, 190 { MIPI_CSI2_DT_RAW12, MEDIA_BUS_FMT_SGRBG12_1X12 }, 191 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SRGGB16_1X16 }, 192 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SBGGR16_1X16 }, 193 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SGBRG16_1X16 }, 194 { MIPI_CSI2_DT_RAW16, MEDIA_BUS_FMT_SGRBG16_1X16 }, 195 { MIPI_CSI2_DT_RAW20, 0 }, 196 }; 197 198 /** 199 * struct xcsi2rxss_state - CSI-2 Rx Subsystem device structure 200 * @subdev: The v4l2 subdev structure 201 * @format: Active V4L2 formats on each pad 202 * @default_format: Default V4L2 format 203 * @events: counter for events 204 * @vcx_events: counter for vcx_events 205 * @dev: Platform structure 206 * @rsubdev: Remote subdev connected to sink pad 207 * @rst_gpio: reset to video_aresetn 208 * @clks: array of clocks 209 * @iomem: Base address of subsystem 210 * @max_num_lanes: Maximum number of lanes present 211 * @datatype: Data type filter 212 * @lock: mutex for accessing this structure 213 * @pads: media pads 214 * @streaming: Flag for storing streaming state 215 * @enable_active_lanes: If number of active lanes can be modified 216 * @en_vcx: If more than 4 VC are enabled 217 * 218 * This structure contains the device driver related parameters 219 */ 220 struct xcsi2rxss_state { 221 struct v4l2_subdev subdev; 222 struct v4l2_mbus_framefmt format; 223 struct v4l2_mbus_framefmt default_format; 224 u32 events[XCSI_NUM_EVENTS]; 225 u32 vcx_events[XCSI_VCX_NUM_EVENTS]; 226 struct device *dev; 227 struct v4l2_subdev *rsubdev; 228 struct gpio_desc *rst_gpio; 229 struct clk_bulk_data *clks; 230 void __iomem *iomem; 231 u32 max_num_lanes; 232 u32 datatype; 233 /* used to protect access to this struct */ 234 struct mutex lock; 235 struct media_pad pads[XCSI_MEDIA_PADS]; 236 bool streaming; 237 bool enable_active_lanes; 238 bool en_vcx; 239 }; 240 241 static const struct clk_bulk_data xcsi2rxss_clks[] = { 242 { .id = "lite_aclk" }, 243 { .id = "video_aclk" }, 244 }; 245 246 static inline struct xcsi2rxss_state * 247 to_xcsi2rxssstate(struct v4l2_subdev *subdev) 248 { 249 return container_of(subdev, struct xcsi2rxss_state, subdev); 250 } 251 252 /* 253 * Register related operations 254 */ 255 static inline u32 xcsi2rxss_read(struct xcsi2rxss_state *xcsi2rxss, u32 addr) 256 { 257 return ioread32(xcsi2rxss->iomem + addr); 258 } 259 260 static inline void xcsi2rxss_write(struct xcsi2rxss_state *xcsi2rxss, u32 addr, 261 u32 value) 262 { 263 iowrite32(value, xcsi2rxss->iomem + addr); 264 } 265 266 static inline void xcsi2rxss_clr(struct xcsi2rxss_state *xcsi2rxss, u32 addr, 267 u32 clr) 268 { 269 xcsi2rxss_write(xcsi2rxss, addr, 270 xcsi2rxss_read(xcsi2rxss, addr) & ~clr); 271 } 272 273 static inline void xcsi2rxss_set(struct xcsi2rxss_state *xcsi2rxss, u32 addr, 274 u32 set) 275 { 276 xcsi2rxss_write(xcsi2rxss, addr, xcsi2rxss_read(xcsi2rxss, addr) | set); 277 } 278 279 /* 280 * This function returns the nth mbus for a data type. 281 * In case of error, mbus code returned is 0. 282 */ 283 static u32 xcsi2rxss_get_nth_mbus(u32 dt, u32 n) 284 { 285 unsigned int i; 286 287 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) { 288 if (xcsi2dt_mbus_lut[i][0] == dt) { 289 if (n-- == 0) 290 return xcsi2dt_mbus_lut[i][1]; 291 } 292 } 293 294 return 0; 295 } 296 297 /* This returns the data type for a media bus format else 0 */ 298 static u32 xcsi2rxss_get_dt(u32 mbus) 299 { 300 unsigned int i; 301 302 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) { 303 if (xcsi2dt_mbus_lut[i][1] == mbus) 304 return xcsi2dt_mbus_lut[i][0]; 305 } 306 307 return 0; 308 } 309 310 /** 311 * xcsi2rxss_soft_reset - Does a soft reset of the MIPI CSI-2 Rx Subsystem 312 * @state: Xilinx CSI-2 Rx Subsystem structure pointer 313 * 314 * Core takes less than 100 video clock cycles to reset. 315 * So a larger timeout value is chosen for margin. 316 * 317 * Return: 0 - on success OR -ETIME if reset times out 318 */ 319 static int xcsi2rxss_soft_reset(struct xcsi2rxss_state *state) 320 { 321 u32 timeout = 1000; /* us */ 322 323 xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET); 324 325 while (xcsi2rxss_read(state, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD) { 326 if (timeout == 0) { 327 dev_err(state->dev, "soft reset timed out!\n"); 328 return -ETIME; 329 } 330 331 timeout--; 332 udelay(1); 333 } 334 335 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET); 336 return 0; 337 } 338 339 static void xcsi2rxss_hard_reset(struct xcsi2rxss_state *state) 340 { 341 if (!state->rst_gpio) 342 return; 343 344 /* minimum of 40 dphy_clk_200M cycles */ 345 gpiod_set_value_cansleep(state->rst_gpio, 1); 346 usleep_range(1, 2); 347 gpiod_set_value_cansleep(state->rst_gpio, 0); 348 } 349 350 static void xcsi2rxss_reset_event_counters(struct xcsi2rxss_state *state) 351 { 352 unsigned int i; 353 354 for (i = 0; i < XCSI_NUM_EVENTS; i++) 355 state->events[i] = 0; 356 357 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) 358 state->vcx_events[i] = 0; 359 } 360 361 /* Print event counters */ 362 static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state) 363 { 364 struct device *dev = state->dev; 365 unsigned int i; 366 367 for (i = 0; i < XCSI_NUM_EVENTS; i++) { 368 if (state->events[i] > 0) { 369 dev_info(dev, "%s events: %d\n", 370 xcsi2rxss_events[i].name, 371 state->events[i]); 372 } 373 } 374 375 if (state->en_vcx) { 376 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) { 377 if (state->vcx_events[i] > 0) { 378 dev_info(dev, 379 "VC %d Frame %s err vcx events: %d\n", 380 (i / 2) + XCSI_VCX_START, 381 i & 1 ? "Sync" : "Level", 382 state->vcx_events[i]); 383 } 384 } 385 } 386 } 387 388 /** 389 * xcsi2rxss_log_status - Logs the status of the CSI-2 Receiver 390 * @sd: Pointer to V4L2 subdevice structure 391 * 392 * This function prints the current status of Xilinx MIPI CSI-2 393 * 394 * Return: 0 on success 395 */ 396 static int xcsi2rxss_log_status(struct v4l2_subdev *sd) 397 { 398 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd); 399 struct device *dev = xcsi2rxss->dev; 400 u32 reg, data; 401 unsigned int i, max_vc; 402 403 mutex_lock(&xcsi2rxss->lock); 404 405 xcsi2rxss_log_counters(xcsi2rxss); 406 407 dev_info(dev, "***** Core Status *****\n"); 408 data = xcsi2rxss_read(xcsi2rxss, XCSI_CSR_OFFSET); 409 dev_info(dev, "Short Packet FIFO Full = %s\n", 410 data & XCSI_CSR_SPFIFOFULL ? "true" : "false"); 411 dev_info(dev, "Short Packet FIFO Not Empty = %s\n", 412 data & XCSI_CSR_SPFIFONE ? "true" : "false"); 413 dev_info(dev, "Stream line buffer full = %s\n", 414 data & XCSI_CSR_SLBF ? "true" : "false"); 415 dev_info(dev, "Soft reset/Core disable in progress = %s\n", 416 data & XCSI_CSR_RIPCD ? "true" : "false"); 417 418 /* Clk & Lane Info */ 419 dev_info(dev, "******** Clock Lane Info *********\n"); 420 data = xcsi2rxss_read(xcsi2rxss, XCSI_CLKINFR_OFFSET); 421 dev_info(dev, "Clock Lane in Stop State = %s\n", 422 data & XCSI_CLKINFR_STOP ? "true" : "false"); 423 424 dev_info(dev, "******** Data Lane Info *********\n"); 425 dev_info(dev, "Lane\tSoT Error\tSoT Sync Error\tStop State\n"); 426 reg = XCSI_DLXINFR_OFFSET; 427 for (i = 0; i < XCSI_MAXDL_COUNT; i++) { 428 data = xcsi2rxss_read(xcsi2rxss, reg); 429 430 dev_info(dev, "%d\t%s\t\t%s\t\t%s\n", i, 431 data & XCSI_DLXINFR_SOTERR ? "true" : "false", 432 data & XCSI_DLXINFR_SOTSYNCERR ? "true" : "false", 433 data & XCSI_DLXINFR_STOP ? "true" : "false"); 434 435 reg += XCSI_NEXTREG_OFFSET; 436 } 437 438 /* Virtual Channel Image Information */ 439 dev_info(dev, "********** Virtual Channel Info ************\n"); 440 dev_info(dev, "VC\tLine Count\tByte Count\tData Type\n"); 441 if (xcsi2rxss->en_vcx) 442 max_vc = XCSI_MAX_VCX; 443 else 444 max_vc = XCSI_MAX_VC; 445 446 reg = XCSI_VCXINF1R_OFFSET; 447 for (i = 0; i < max_vc; i++) { 448 u32 line_count, byte_count, data_type; 449 450 /* Get line and byte count from VCXINFR1 Register */ 451 data = xcsi2rxss_read(xcsi2rxss, reg); 452 byte_count = data & XCSI_VCXINF1R_BYTECOUNT; 453 line_count = data & XCSI_VCXINF1R_LINECOUNT; 454 line_count >>= XCSI_VCXINF1R_LINECOUNT_SHIFT; 455 456 /* Get data type from VCXINFR2 Register */ 457 reg += XCSI_NEXTREG_OFFSET; 458 data = xcsi2rxss_read(xcsi2rxss, reg); 459 data_type = data & XCSI_VCXINF2R_DT; 460 461 dev_info(dev, "%d\t%d\t\t%d\t\t0x%x\n", i, line_count, 462 byte_count, data_type); 463 464 /* Move to next pair of VC Info registers */ 465 reg += XCSI_NEXTREG_OFFSET; 466 } 467 468 mutex_unlock(&xcsi2rxss->lock); 469 470 return 0; 471 } 472 473 static struct v4l2_subdev *xcsi2rxss_get_remote_subdev(struct media_pad *local) 474 { 475 struct media_pad *remote; 476 477 remote = media_pad_remote_pad_first(local); 478 if (!remote || !is_media_entity_v4l2_subdev(remote->entity)) 479 return NULL; 480 481 return media_entity_to_v4l2_subdev(remote->entity); 482 } 483 484 static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state) 485 { 486 int ret = 0; 487 488 /* enable core */ 489 xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE); 490 491 ret = xcsi2rxss_soft_reset(state); 492 if (ret) { 493 state->streaming = false; 494 return ret; 495 } 496 497 /* enable interrupts */ 498 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE); 499 xcsi2rxss_write(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK); 500 xcsi2rxss_set(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE); 501 502 state->streaming = true; 503 504 state->rsubdev = 505 xcsi2rxss_get_remote_subdev(&state->pads[XVIP_PAD_SINK]); 506 507 ret = v4l2_subdev_call(state->rsubdev, video, s_stream, 1); 508 if (ret) { 509 /* disable interrupts */ 510 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK); 511 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE); 512 513 /* disable core */ 514 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE); 515 state->streaming = false; 516 } 517 518 return ret; 519 } 520 521 static void xcsi2rxss_stop_stream(struct xcsi2rxss_state *state) 522 { 523 v4l2_subdev_call(state->rsubdev, video, s_stream, 0); 524 525 /* disable interrupts */ 526 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK); 527 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE); 528 529 /* disable core */ 530 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE); 531 state->streaming = false; 532 } 533 534 /** 535 * xcsi2rxss_irq_handler - Interrupt handler for CSI-2 536 * @irq: IRQ number 537 * @data: Pointer to device state 538 * 539 * In the interrupt handler, a list of event counters are updated for 540 * corresponding interrupts. This is useful to get status / debug. 541 * 542 * Return: IRQ_HANDLED after handling interrupts 543 */ 544 static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data) 545 { 546 struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data; 547 struct device *dev = state->dev; 548 u32 status; 549 550 status = xcsi2rxss_read(state, XCSI_ISR_OFFSET) & XCSI_ISR_ALLINTR_MASK; 551 xcsi2rxss_write(state, XCSI_ISR_OFFSET, status); 552 553 /* Received a short packet */ 554 if (status & XCSI_ISR_SPFIFONE) { 555 u32 count = 0; 556 557 /* 558 * Drain generic short packet FIFO by reading max 31 559 * (fifo depth) short packets from fifo or till fifo is empty. 560 */ 561 for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) { 562 u32 spfifostat, spkt; 563 564 spkt = xcsi2rxss_read(state, XCSI_SPKTR_OFFSET); 565 dev_dbg(dev, "Short packet = 0x%08x\n", spkt); 566 spfifostat = xcsi2rxss_read(state, XCSI_ISR_OFFSET); 567 spfifostat &= XCSI_ISR_SPFIFONE; 568 if (!spfifostat) 569 break; 570 xcsi2rxss_write(state, XCSI_ISR_OFFSET, spfifostat); 571 } 572 } 573 574 /* Short packet FIFO overflow */ 575 if (status & XCSI_ISR_SPFIFOF) 576 dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n"); 577 578 /* 579 * Stream line buffer full 580 * This means there is a backpressure from downstream IP 581 */ 582 if (status & XCSI_ISR_SLBF) { 583 dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n"); 584 585 /* disable interrupts */ 586 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK); 587 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE); 588 589 /* disable core */ 590 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE); 591 592 /* 593 * The IP needs to be hard reset before it can be used now. 594 * This will be done in streamoff. 595 */ 596 597 /* 598 * TODO: Notify the whole pipeline with v4l2_subdev_notify() to 599 * inform userspace. 600 */ 601 } 602 603 /* Increment event counters */ 604 if (status & XCSI_ISR_ALLINTR_MASK) { 605 unsigned int i; 606 607 for (i = 0; i < XCSI_NUM_EVENTS; i++) { 608 if (!(status & xcsi2rxss_events[i].mask)) 609 continue; 610 state->events[i]++; 611 dev_dbg_ratelimited(dev, "%s: %u\n", 612 xcsi2rxss_events[i].name, 613 state->events[i]); 614 } 615 616 if (status & XCSI_ISR_VCXFE && state->en_vcx) { 617 u32 vcxstatus; 618 619 vcxstatus = xcsi2rxss_read(state, XCSI_VCXR_OFFSET); 620 vcxstatus &= XCSI_VCXR_VCERR; 621 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) { 622 if (!(vcxstatus & BIT(i))) 623 continue; 624 state->vcx_events[i]++; 625 } 626 xcsi2rxss_write(state, XCSI_VCXR_OFFSET, vcxstatus); 627 } 628 } 629 630 return IRQ_HANDLED; 631 } 632 633 /** 634 * xcsi2rxss_s_stream - It is used to start/stop the streaming. 635 * @sd: V4L2 Sub device 636 * @enable: Flag (True / False) 637 * 638 * This function controls the start or stop of streaming for the 639 * Xilinx MIPI CSI-2 Rx Subsystem. 640 * 641 * Return: 0 on success, errors otherwise 642 */ 643 static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable) 644 { 645 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd); 646 int ret = 0; 647 648 mutex_lock(&xcsi2rxss->lock); 649 650 if (enable == xcsi2rxss->streaming) 651 goto stream_done; 652 653 if (enable) { 654 xcsi2rxss_reset_event_counters(xcsi2rxss); 655 ret = xcsi2rxss_start_stream(xcsi2rxss); 656 } else { 657 xcsi2rxss_stop_stream(xcsi2rxss); 658 xcsi2rxss_hard_reset(xcsi2rxss); 659 } 660 661 stream_done: 662 mutex_unlock(&xcsi2rxss->lock); 663 return ret; 664 } 665 666 static struct v4l2_mbus_framefmt * 667 __xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss, 668 struct v4l2_subdev_state *sd_state, 669 unsigned int pad, u32 which) 670 { 671 switch (which) { 672 case V4L2_SUBDEV_FORMAT_TRY: 673 return v4l2_subdev_get_try_format(&xcsi2rxss->subdev, 674 sd_state, pad); 675 case V4L2_SUBDEV_FORMAT_ACTIVE: 676 return &xcsi2rxss->format; 677 default: 678 return NULL; 679 } 680 } 681 682 /** 683 * xcsi2rxss_init_cfg - Initialise the pad format config to default 684 * @sd: Pointer to V4L2 Sub device structure 685 * @sd_state: Pointer to sub device state structure 686 * 687 * This function is used to initialize the pad format with the default 688 * values. 689 * 690 * Return: 0 on success 691 */ 692 static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd, 693 struct v4l2_subdev_state *sd_state) 694 { 695 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd); 696 struct v4l2_mbus_framefmt *format; 697 unsigned int i; 698 699 mutex_lock(&xcsi2rxss->lock); 700 for (i = 0; i < XCSI_MEDIA_PADS; i++) { 701 format = v4l2_subdev_get_try_format(sd, sd_state, i); 702 *format = xcsi2rxss->default_format; 703 } 704 mutex_unlock(&xcsi2rxss->lock); 705 706 return 0; 707 } 708 709 /** 710 * xcsi2rxss_get_format - Get the pad format 711 * @sd: Pointer to V4L2 Sub device structure 712 * @sd_state: Pointer to sub device state structure 713 * @fmt: Pointer to pad level media bus format 714 * 715 * This function is used to get the pad format information. 716 * 717 * Return: 0 on success 718 */ 719 static int xcsi2rxss_get_format(struct v4l2_subdev *sd, 720 struct v4l2_subdev_state *sd_state, 721 struct v4l2_subdev_format *fmt) 722 { 723 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd); 724 725 mutex_lock(&xcsi2rxss->lock); 726 fmt->format = *__xcsi2rxss_get_pad_format(xcsi2rxss, sd_state, 727 fmt->pad, 728 fmt->which); 729 mutex_unlock(&xcsi2rxss->lock); 730 731 return 0; 732 } 733 734 /** 735 * xcsi2rxss_set_format - This is used to set the pad format 736 * @sd: Pointer to V4L2 Sub device structure 737 * @sd_state: Pointer to sub device state structure 738 * @fmt: Pointer to pad level media bus format 739 * 740 * This function is used to set the pad format. Since the pad format is fixed 741 * in hardware, it can't be modified on run time. So when a format set is 742 * requested by application, all parameters except the format type is saved 743 * for the pad and the original pad format is sent back to the application. 744 * 745 * Return: 0 on success 746 */ 747 static int xcsi2rxss_set_format(struct v4l2_subdev *sd, 748 struct v4l2_subdev_state *sd_state, 749 struct v4l2_subdev_format *fmt) 750 { 751 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd); 752 struct v4l2_mbus_framefmt *__format; 753 u32 dt; 754 755 mutex_lock(&xcsi2rxss->lock); 756 757 /* 758 * Only the format->code parameter matters for CSI as the 759 * CSI format cannot be changed at runtime. 760 * Ensure that format to set is copied to over to CSI pad format 761 */ 762 __format = __xcsi2rxss_get_pad_format(xcsi2rxss, sd_state, 763 fmt->pad, fmt->which); 764 765 /* only sink pad format can be updated */ 766 if (fmt->pad == XVIP_PAD_SOURCE) { 767 fmt->format = *__format; 768 mutex_unlock(&xcsi2rxss->lock); 769 return 0; 770 } 771 772 /* 773 * RAW8 is supported in all datatypes. So if requested media bus format 774 * is of RAW8 type, then allow to be set. In case core is configured to 775 * other RAW, YUV422 8/10 or RGB888, set appropriate media bus format. 776 */ 777 dt = xcsi2rxss_get_dt(fmt->format.code); 778 if (dt != xcsi2rxss->datatype && dt != MIPI_CSI2_DT_RAW8) { 779 dev_dbg(xcsi2rxss->dev, "Unsupported media bus format"); 780 /* set the default format for the data type */ 781 fmt->format.code = xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype, 782 0); 783 } 784 785 *__format = fmt->format; 786 mutex_unlock(&xcsi2rxss->lock); 787 788 return 0; 789 } 790 791 /* 792 * xcsi2rxss_enum_mbus_code - Handle pixel format enumeration 793 * @sd: pointer to v4l2 subdev structure 794 * @cfg: V4L2 subdev pad configuration 795 * @code: pointer to v4l2_subdev_mbus_code_enum structure 796 * 797 * Return: -EINVAL or zero on success 798 */ 799 static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd, 800 struct v4l2_subdev_state *sd_state, 801 struct v4l2_subdev_mbus_code_enum *code) 802 { 803 struct xcsi2rxss_state *state = to_xcsi2rxssstate(sd); 804 u32 dt, n; 805 int ret = 0; 806 807 /* RAW8 dt packets are available in all DT configurations */ 808 if (code->index < 4) { 809 n = code->index; 810 dt = MIPI_CSI2_DT_RAW8; 811 } else if (state->datatype != MIPI_CSI2_DT_RAW8) { 812 n = code->index - 4; 813 dt = state->datatype; 814 } else { 815 return -EINVAL; 816 } 817 818 code->code = xcsi2rxss_get_nth_mbus(dt, n); 819 if (!code->code) 820 ret = -EINVAL; 821 822 return ret; 823 } 824 825 /* ----------------------------------------------------------------------------- 826 * Media Operations 827 */ 828 829 static const struct media_entity_operations xcsi2rxss_media_ops = { 830 .link_validate = v4l2_subdev_link_validate 831 }; 832 833 static const struct v4l2_subdev_core_ops xcsi2rxss_core_ops = { 834 .log_status = xcsi2rxss_log_status, 835 }; 836 837 static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = { 838 .s_stream = xcsi2rxss_s_stream 839 }; 840 841 static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = { 842 .init_cfg = xcsi2rxss_init_cfg, 843 .get_fmt = xcsi2rxss_get_format, 844 .set_fmt = xcsi2rxss_set_format, 845 .enum_mbus_code = xcsi2rxss_enum_mbus_code, 846 .link_validate = v4l2_subdev_link_validate_default, 847 }; 848 849 static const struct v4l2_subdev_ops xcsi2rxss_ops = { 850 .core = &xcsi2rxss_core_ops, 851 .video = &xcsi2rxss_video_ops, 852 .pad = &xcsi2rxss_pad_ops 853 }; 854 855 static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss) 856 { 857 struct device *dev = xcsi2rxss->dev; 858 struct device_node *node = dev->of_node; 859 860 struct fwnode_handle *ep; 861 struct v4l2_fwnode_endpoint vep = { 862 .bus_type = V4L2_MBUS_CSI2_DPHY 863 }; 864 bool en_csi_v20, vfb; 865 int ret; 866 867 en_csi_v20 = of_property_read_bool(node, "xlnx,en-csi-v2-0"); 868 if (en_csi_v20) 869 xcsi2rxss->en_vcx = of_property_read_bool(node, "xlnx,en-vcx"); 870 871 xcsi2rxss->enable_active_lanes = 872 of_property_read_bool(node, "xlnx,en-active-lanes"); 873 874 ret = of_property_read_u32(node, "xlnx,csi-pxl-format", 875 &xcsi2rxss->datatype); 876 if (ret < 0) { 877 dev_err(dev, "missing xlnx,csi-pxl-format property\n"); 878 return ret; 879 } 880 881 switch (xcsi2rxss->datatype) { 882 case MIPI_CSI2_DT_YUV422_8B: 883 case MIPI_CSI2_DT_RGB444: 884 case MIPI_CSI2_DT_RGB555: 885 case MIPI_CSI2_DT_RGB565: 886 case MIPI_CSI2_DT_RGB666: 887 case MIPI_CSI2_DT_RGB888: 888 case MIPI_CSI2_DT_RAW6: 889 case MIPI_CSI2_DT_RAW7: 890 case MIPI_CSI2_DT_RAW8: 891 case MIPI_CSI2_DT_RAW10: 892 case MIPI_CSI2_DT_RAW12: 893 case MIPI_CSI2_DT_RAW14: 894 break; 895 case MIPI_CSI2_DT_YUV422_10B: 896 case MIPI_CSI2_DT_RAW16: 897 case MIPI_CSI2_DT_RAW20: 898 if (!en_csi_v20) { 899 ret = -EINVAL; 900 dev_dbg(dev, "enable csi v2 for this pixel format"); 901 } 902 break; 903 default: 904 ret = -EINVAL; 905 } 906 if (ret < 0) { 907 dev_err(dev, "invalid csi-pxl-format property!\n"); 908 return ret; 909 } 910 911 vfb = of_property_read_bool(node, "xlnx,vfb"); 912 if (!vfb) { 913 dev_err(dev, "operation without VFB is not supported\n"); 914 return -EINVAL; 915 } 916 917 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 918 XVIP_PAD_SINK, 0, 919 FWNODE_GRAPH_ENDPOINT_NEXT); 920 if (!ep) { 921 dev_err(dev, "no sink port found"); 922 return -EINVAL; 923 } 924 925 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 926 fwnode_handle_put(ep); 927 if (ret) { 928 dev_err(dev, "error parsing sink port"); 929 return ret; 930 } 931 932 dev_dbg(dev, "mipi number lanes = %d\n", 933 vep.bus.mipi_csi2.num_data_lanes); 934 935 xcsi2rxss->max_num_lanes = vep.bus.mipi_csi2.num_data_lanes; 936 937 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 938 XVIP_PAD_SOURCE, 0, 939 FWNODE_GRAPH_ENDPOINT_NEXT); 940 if (!ep) { 941 dev_err(dev, "no source port found"); 942 return -EINVAL; 943 } 944 945 fwnode_handle_put(ep); 946 947 dev_dbg(dev, "vcx %s, %u data lanes (%s), data type 0x%02x\n", 948 xcsi2rxss->en_vcx ? "enabled" : "disabled", 949 xcsi2rxss->max_num_lanes, 950 xcsi2rxss->enable_active_lanes ? "dynamic" : "static", 951 xcsi2rxss->datatype); 952 953 return 0; 954 } 955 956 static int xcsi2rxss_probe(struct platform_device *pdev) 957 { 958 struct v4l2_subdev *subdev; 959 struct xcsi2rxss_state *xcsi2rxss; 960 int num_clks = ARRAY_SIZE(xcsi2rxss_clks); 961 struct device *dev = &pdev->dev; 962 int irq, ret; 963 964 xcsi2rxss = devm_kzalloc(dev, sizeof(*xcsi2rxss), GFP_KERNEL); 965 if (!xcsi2rxss) 966 return -ENOMEM; 967 968 xcsi2rxss->dev = dev; 969 970 xcsi2rxss->clks = devm_kmemdup(dev, xcsi2rxss_clks, 971 sizeof(xcsi2rxss_clks), GFP_KERNEL); 972 if (!xcsi2rxss->clks) 973 return -ENOMEM; 974 975 /* Reset GPIO */ 976 xcsi2rxss->rst_gpio = devm_gpiod_get_optional(dev, "video-reset", 977 GPIOD_OUT_HIGH); 978 if (IS_ERR(xcsi2rxss->rst_gpio)) { 979 if (PTR_ERR(xcsi2rxss->rst_gpio) != -EPROBE_DEFER) 980 dev_err(dev, "Video Reset GPIO not setup in DT"); 981 return PTR_ERR(xcsi2rxss->rst_gpio); 982 } 983 984 ret = xcsi2rxss_parse_of(xcsi2rxss); 985 if (ret < 0) 986 return ret; 987 988 xcsi2rxss->iomem = devm_platform_ioremap_resource(pdev, 0); 989 if (IS_ERR(xcsi2rxss->iomem)) 990 return PTR_ERR(xcsi2rxss->iomem); 991 992 irq = platform_get_irq(pdev, 0); 993 if (irq < 0) 994 return irq; 995 996 ret = devm_request_threaded_irq(dev, irq, NULL, 997 xcsi2rxss_irq_handler, IRQF_ONESHOT, 998 dev_name(dev), xcsi2rxss); 999 if (ret) { 1000 dev_err(dev, "Err = %d Interrupt handler reg failed!\n", ret); 1001 return ret; 1002 } 1003 1004 ret = clk_bulk_get(dev, num_clks, xcsi2rxss->clks); 1005 if (ret) 1006 return ret; 1007 1008 /* TODO: Enable/disable clocks at stream on/off time. */ 1009 ret = clk_bulk_prepare_enable(num_clks, xcsi2rxss->clks); 1010 if (ret) 1011 goto err_clk_put; 1012 1013 mutex_init(&xcsi2rxss->lock); 1014 1015 xcsi2rxss_hard_reset(xcsi2rxss); 1016 xcsi2rxss_soft_reset(xcsi2rxss); 1017 1018 /* Initialize V4L2 subdevice and media entity */ 1019 xcsi2rxss->pads[XVIP_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 1020 xcsi2rxss->pads[XVIP_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 1021 1022 /* Initialize the default format */ 1023 xcsi2rxss->default_format.code = 1024 xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype, 0); 1025 xcsi2rxss->default_format.field = V4L2_FIELD_NONE; 1026 xcsi2rxss->default_format.colorspace = V4L2_COLORSPACE_SRGB; 1027 xcsi2rxss->default_format.width = XCSI_DEFAULT_WIDTH; 1028 xcsi2rxss->default_format.height = XCSI_DEFAULT_HEIGHT; 1029 xcsi2rxss->format = xcsi2rxss->default_format; 1030 1031 /* Initialize V4L2 subdevice and media entity */ 1032 subdev = &xcsi2rxss->subdev; 1033 v4l2_subdev_init(subdev, &xcsi2rxss_ops); 1034 subdev->dev = dev; 1035 strscpy(subdev->name, dev_name(dev), sizeof(subdev->name)); 1036 subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE; 1037 subdev->entity.ops = &xcsi2rxss_media_ops; 1038 v4l2_set_subdevdata(subdev, xcsi2rxss); 1039 1040 ret = media_entity_pads_init(&subdev->entity, XCSI_MEDIA_PADS, 1041 xcsi2rxss->pads); 1042 if (ret < 0) 1043 goto error; 1044 1045 platform_set_drvdata(pdev, xcsi2rxss); 1046 1047 ret = v4l2_async_register_subdev(subdev); 1048 if (ret < 0) { 1049 dev_err(dev, "failed to register subdev\n"); 1050 goto error; 1051 } 1052 1053 return 0; 1054 error: 1055 media_entity_cleanup(&subdev->entity); 1056 mutex_destroy(&xcsi2rxss->lock); 1057 clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks); 1058 err_clk_put: 1059 clk_bulk_put(num_clks, xcsi2rxss->clks); 1060 return ret; 1061 } 1062 1063 static int xcsi2rxss_remove(struct platform_device *pdev) 1064 { 1065 struct xcsi2rxss_state *xcsi2rxss = platform_get_drvdata(pdev); 1066 struct v4l2_subdev *subdev = &xcsi2rxss->subdev; 1067 int num_clks = ARRAY_SIZE(xcsi2rxss_clks); 1068 1069 v4l2_async_unregister_subdev(subdev); 1070 media_entity_cleanup(&subdev->entity); 1071 mutex_destroy(&xcsi2rxss->lock); 1072 clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks); 1073 clk_bulk_put(num_clks, xcsi2rxss->clks); 1074 1075 return 0; 1076 } 1077 1078 static const struct of_device_id xcsi2rxss_of_id_table[] = { 1079 { .compatible = "xlnx,mipi-csi2-rx-subsystem-5.0", }, 1080 { } 1081 }; 1082 MODULE_DEVICE_TABLE(of, xcsi2rxss_of_id_table); 1083 1084 static struct platform_driver xcsi2rxss_driver = { 1085 .driver = { 1086 .name = "xilinx-csi2rxss", 1087 .of_match_table = xcsi2rxss_of_id_table, 1088 }, 1089 .probe = xcsi2rxss_probe, 1090 .remove = xcsi2rxss_remove, 1091 }; 1092 1093 module_platform_driver(xcsi2rxss_driver); 1094 1095 MODULE_AUTHOR("Vishal Sagar <vsagar@xilinx.com>"); 1096 MODULE_DESCRIPTION("Xilinx MIPI CSI-2 Rx Subsystem Driver"); 1097 MODULE_LICENSE("GPL v2"); 1098