1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Hantro VPU codec driver 4 * 5 * Copyright 2018 Google LLC. 6 * Tomasz Figa <tfiga@chromium.org> 7 */ 8 9 #ifndef HANTRO_HW_H_ 10 #define HANTRO_HW_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/v4l2-controls.h> 14 #include <media/v4l2-ctrls.h> 15 #include <media/v4l2-vp9.h> 16 #include <media/videobuf2-core.h> 17 18 #define DEC_8190_ALIGN_MASK 0x07U 19 20 #define MB_DIM 16 21 #define TILE_MB_DIM 4 22 #define MB_WIDTH(w) DIV_ROUND_UP(w, MB_DIM) 23 #define MB_HEIGHT(h) DIV_ROUND_UP(h, MB_DIM) 24 25 #define FMT_MIN_WIDTH 48 26 #define FMT_MIN_HEIGHT 48 27 #define FMT_HD_WIDTH 1280 28 #define FMT_HD_HEIGHT 720 29 #define FMT_FHD_WIDTH 1920 30 #define FMT_FHD_HEIGHT 1088 31 #define FMT_UHD_WIDTH 3840 32 #define FMT_UHD_HEIGHT 2160 33 #define FMT_4K_WIDTH 4096 34 #define FMT_4K_HEIGHT 2304 35 36 #define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1) 37 38 struct hantro_dev; 39 struct hantro_ctx; 40 struct hantro_buf; 41 struct hantro_variant; 42 43 /** 44 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data 45 * 46 * @cpu: CPU pointer to the buffer. 47 * @dma: DMA address of the buffer. 48 * @size: Size of the buffer. 49 * @attrs: Attributes of the DMA mapping. 50 */ 51 struct hantro_aux_buf { 52 void *cpu; 53 dma_addr_t dma; 54 size_t size; 55 unsigned long attrs; 56 }; 57 58 /* Max. number of entries in the DPB (HW limitation). */ 59 #define HANTRO_H264_DPB_SIZE 16 60 61 /** 62 * struct hantro_h264_dec_ctrls 63 * 64 * @decode: Decode params 65 * @scaling: Scaling info 66 * @sps: SPS info 67 * @pps: PPS info 68 */ 69 struct hantro_h264_dec_ctrls { 70 const struct v4l2_ctrl_h264_decode_params *decode; 71 const struct v4l2_ctrl_h264_scaling_matrix *scaling; 72 const struct v4l2_ctrl_h264_sps *sps; 73 const struct v4l2_ctrl_h264_pps *pps; 74 }; 75 76 /** 77 * struct hantro_h264_dec_reflists 78 * 79 * @p: P reflist 80 * @b0: B0 reflist 81 * @b1: B1 reflist 82 */ 83 struct hantro_h264_dec_reflists { 84 struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; 85 struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; 86 struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; 87 }; 88 89 /** 90 * struct hantro_h264_dec_hw_ctx 91 * 92 * @priv: Private auxiliary buffer for hardware. 93 * @dpb: DPB 94 * @reflists: P/B0/B1 reflists 95 * @ctrls: V4L2 controls attached to a run 96 * @dpb_longterm: DPB long-term 97 * @dpb_valid: DPB valid 98 * @cur_poc: Current picture order count 99 */ 100 struct hantro_h264_dec_hw_ctx { 101 struct hantro_aux_buf priv; 102 struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; 103 struct hantro_h264_dec_reflists reflists; 104 struct hantro_h264_dec_ctrls ctrls; 105 u32 dpb_longterm; 106 u32 dpb_valid; 107 s32 cur_poc; 108 }; 109 110 /** 111 * struct hantro_hevc_dec_ctrls 112 * @decode_params: Decode params 113 * @scaling: Scaling matrix 114 * @sps: SPS info 115 * @pps: PPS info 116 * @hevc_hdr_skip_length: the number of data (in bits) to skip in the 117 * slice segment header syntax after 'slice type' 118 * token 119 */ 120 struct hantro_hevc_dec_ctrls { 121 const struct v4l2_ctrl_hevc_decode_params *decode_params; 122 const struct v4l2_ctrl_hevc_scaling_matrix *scaling; 123 const struct v4l2_ctrl_hevc_sps *sps; 124 const struct v4l2_ctrl_hevc_pps *pps; 125 u32 hevc_hdr_skip_length; 126 }; 127 128 /** 129 * struct hantro_hevc_dec_hw_ctx 130 * @tile_sizes: Tile sizes buffer 131 * @tile_filter: Tile vertical filter buffer 132 * @tile_sao: Tile SAO buffer 133 * @tile_bsd: Tile BSD control buffer 134 * @ref_bufs: Internal reference buffers 135 * @scaling_lists: Scaling lists buffer 136 * @ref_bufs_poc: Internal reference buffers picture order count 137 * @ref_bufs_used: Bitfield of used reference buffers 138 * @ctrls: V4L2 controls attached to a run 139 * @num_tile_cols_allocated: number of allocated tiles 140 */ 141 struct hantro_hevc_dec_hw_ctx { 142 struct hantro_aux_buf tile_sizes; 143 struct hantro_aux_buf tile_filter; 144 struct hantro_aux_buf tile_sao; 145 struct hantro_aux_buf tile_bsd; 146 struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES]; 147 struct hantro_aux_buf scaling_lists; 148 s32 ref_bufs_poc[NUM_REF_PICTURES]; 149 u32 ref_bufs_used; 150 struct hantro_hevc_dec_ctrls ctrls; 151 unsigned int num_tile_cols_allocated; 152 }; 153 154 /** 155 * struct hantro_mpeg2_dec_hw_ctx 156 * 157 * @qtable: Quantization table 158 */ 159 struct hantro_mpeg2_dec_hw_ctx { 160 struct hantro_aux_buf qtable; 161 }; 162 163 /** 164 * struct hantro_vp8_dec_hw_ctx 165 * 166 * @segment_map: Segment map buffer. 167 * @prob_tbl: Probability table buffer. 168 */ 169 struct hantro_vp8_dec_hw_ctx { 170 struct hantro_aux_buf segment_map; 171 struct hantro_aux_buf prob_tbl; 172 }; 173 174 /** 175 * struct hantro_vp9_frame_info 176 * 177 * @valid: frame info valid flag 178 * @frame_context_idx: index of frame context 179 * @reference_mode: inter prediction type 180 * @tx_mode: transform mode 181 * @interpolation_filter: filter selection for inter prediction 182 * @flags: frame flags 183 * @timestamp: frame timestamp 184 */ 185 struct hantro_vp9_frame_info { 186 u32 valid : 1; 187 u32 frame_context_idx : 2; 188 u32 reference_mode : 2; 189 u32 tx_mode : 3; 190 u32 interpolation_filter : 3; 191 u32 flags; 192 u64 timestamp; 193 }; 194 195 #define MAX_SB_COLS 64 196 #define MAX_SB_ROWS 34 197 198 /** 199 * struct hantro_vp9_dec_hw_ctx 200 * 201 * @tile_edge: auxiliary DMA buffer for tile edge processing 202 * @segment_map: auxiliary DMA buffer for segment map 203 * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters 204 * @cnts: vp9 library struct for abstracting hw counters access 205 * @probability_tables: VP9 probability tables implied by the spec 206 * @frame_context: VP9 frame contexts 207 * @cur: current frame information 208 * @last: last frame information 209 * @bsd_ctrl_offset: bsd offset into tile_edge 210 * @segment_map_size: size of segment map 211 * @ctx_counters_offset: hw counters offset into misc 212 * @tile_info_offset: tile info offset into misc 213 * @tile_r_info: per-tile information array 214 * @tile_c_info: per-tile information array 215 * @last_tile_r: last number of tile rows 216 * @last_tile_c: last number of tile cols 217 * @last_sbs_r: last number of superblock rows 218 * @last_sbs_c: last number of superblock cols 219 * @active_segment: number of active segment (alternating between 0 and 1) 220 * @feature_enabled: segmentation feature enabled flags 221 * @feature_data: segmentation feature data 222 */ 223 struct hantro_vp9_dec_hw_ctx { 224 struct hantro_aux_buf tile_edge; 225 struct hantro_aux_buf segment_map; 226 struct hantro_aux_buf misc; 227 struct v4l2_vp9_frame_symbol_counts cnts; 228 struct v4l2_vp9_frame_context probability_tables; 229 struct v4l2_vp9_frame_context frame_context[4]; 230 struct hantro_vp9_frame_info cur; 231 struct hantro_vp9_frame_info last; 232 233 unsigned int bsd_ctrl_offset; 234 unsigned int segment_map_size; 235 unsigned int ctx_counters_offset; 236 unsigned int tile_info_offset; 237 238 unsigned short tile_r_info[MAX_SB_ROWS]; 239 unsigned short tile_c_info[MAX_SB_COLS]; 240 unsigned int last_tile_r; 241 unsigned int last_tile_c; 242 unsigned int last_sbs_r; 243 unsigned int last_sbs_c; 244 245 unsigned int active_segment; 246 u8 feature_enabled[8]; 247 s16 feature_data[8][4]; 248 }; 249 250 /** 251 * struct hantro_postproc_ctx 252 * 253 * @dec_q: References buffers, in decoder format. 254 */ 255 struct hantro_postproc_ctx { 256 struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; 257 }; 258 259 /** 260 * struct hantro_postproc_ops - post-processor operations 261 * 262 * @enable: Enable the post-processor block. Optional. 263 * @disable: Disable the post-processor block. Optional. 264 * @enum_framesizes: Enumerate possible scaled output formats. 265 * Returns zero if OK, a negative value in error cases. 266 * Optional. 267 */ 268 struct hantro_postproc_ops { 269 void (*enable)(struct hantro_ctx *ctx); 270 void (*disable)(struct hantro_ctx *ctx); 271 int (*enum_framesizes)(struct hantro_ctx *ctx, struct v4l2_frmsizeenum *fsize); 272 }; 273 274 /** 275 * struct hantro_codec_ops - codec mode specific operations 276 * 277 * @init: If needed, can be used for initialization. 278 * Optional and called from process context. 279 * @exit: If needed, can be used to undo the .init phase. 280 * Optional and called from process context. 281 * @run: Start single {en,de)coding job. Called from atomic context 282 * to indicate that a pair of buffers is ready and the hardware 283 * should be programmed and started. Returns zero if OK, a 284 * negative value in error cases. 285 * @done: Read back processing results and additional data from hardware. 286 * @reset: Reset the hardware in case of a timeout. 287 */ 288 struct hantro_codec_ops { 289 int (*init)(struct hantro_ctx *ctx); 290 void (*exit)(struct hantro_ctx *ctx); 291 int (*run)(struct hantro_ctx *ctx); 292 void (*done)(struct hantro_ctx *ctx); 293 void (*reset)(struct hantro_ctx *ctx); 294 }; 295 296 /** 297 * enum hantro_enc_fmt - source format ID for hardware registers. 298 * 299 * @ROCKCHIP_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format 300 * @ROCKCHIP_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format 301 * @ROCKCHIP_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV) 302 * @ROCKCHIP_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY) 303 */ 304 enum hantro_enc_fmt { 305 ROCKCHIP_VPU_ENC_FMT_YUV420P = 0, 306 ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1, 307 ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2, 308 ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, 309 }; 310 311 extern const struct hantro_variant imx8mm_vpu_g1_variant; 312 extern const struct hantro_variant imx8mq_vpu_g1_variant; 313 extern const struct hantro_variant imx8mq_vpu_g2_variant; 314 extern const struct hantro_variant imx8mq_vpu_variant; 315 extern const struct hantro_variant px30_vpu_variant; 316 extern const struct hantro_variant rk3036_vpu_variant; 317 extern const struct hantro_variant rk3066_vpu_variant; 318 extern const struct hantro_variant rk3288_vpu_variant; 319 extern const struct hantro_variant rk3328_vpu_variant; 320 extern const struct hantro_variant rk3399_vpu_variant; 321 extern const struct hantro_variant rk3568_vepu_variant; 322 extern const struct hantro_variant rk3568_vpu_variant; 323 extern const struct hantro_variant sama5d4_vdec_variant; 324 extern const struct hantro_variant sunxi_vpu_variant; 325 326 extern const struct hantro_postproc_ops hantro_g1_postproc_ops; 327 extern const struct hantro_postproc_ops hantro_g2_postproc_ops; 328 329 extern const u32 hantro_vp8_dec_mc_filter[8][6]; 330 331 void hantro_watchdog(struct work_struct *work); 332 void hantro_run(struct hantro_ctx *ctx); 333 void hantro_irq_done(struct hantro_dev *vpu, 334 enum vb2_buffer_state result); 335 void hantro_start_prepare_run(struct hantro_ctx *ctx); 336 void hantro_end_prepare_run(struct hantro_ctx *ctx); 337 338 irqreturn_t hantro_g1_irq(int irq, void *dev_id); 339 void hantro_g1_reset(struct hantro_ctx *ctx); 340 341 int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx); 342 int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx); 343 void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx); 344 void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx); 345 346 dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, 347 unsigned int dpb_idx); 348 u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, 349 unsigned int dpb_idx); 350 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); 351 int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx); 352 int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); 353 int hantro_h264_dec_init(struct hantro_ctx *ctx); 354 void hantro_h264_dec_exit(struct hantro_ctx *ctx); 355 356 int hantro_hevc_dec_init(struct hantro_ctx *ctx); 357 void hantro_hevc_dec_exit(struct hantro_ctx *ctx); 358 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx); 359 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx); 360 void hantro_hevc_ref_init(struct hantro_ctx *ctx); 361 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc); 362 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr); 363 364 365 static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) 366 { 367 return (dimension + 63) / 64; 368 } 369 370 static inline size_t 371 hantro_vp9_mv_size(unsigned int width, unsigned int height) 372 { 373 int num_ctbs; 374 375 /* 376 * There can be up to (CTBs x 64) number of blocks, 377 * and the motion vector for each block needs 16 bytes. 378 */ 379 num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height); 380 return (num_ctbs * 64) * 16; 381 } 382 383 static inline size_t 384 hantro_h264_mv_size(unsigned int width, unsigned int height) 385 { 386 /* 387 * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to 388 * 448 bytes per macroblock with additional 32 bytes on 389 * multi-core variants. 390 * 391 * The H264 decoder needs extra space on the output buffers 392 * to store motion vectors. This is needed for reference 393 * frames and only if the format is non-post-processed NV12. 394 * 395 * Memory layout is as follow: 396 * 397 * +---------------------------+ 398 * | Y-plane 256 bytes x MBs | 399 * +---------------------------+ 400 * | UV-plane 128 bytes x MBs | 401 * +---------------------------+ 402 * | MV buffer 64 bytes x MBs | 403 * +---------------------------+ 404 * | MC sync 32 bytes | 405 * +---------------------------+ 406 */ 407 return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32; 408 } 409 410 static inline size_t 411 hantro_hevc_mv_size(unsigned int width, unsigned int height) 412 { 413 /* 414 * A CTB can be 64x64, 32x32 or 16x16. 415 * Allocated memory for the "worse" case: 16x16 416 */ 417 return width * height / 16; 418 } 419 420 int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx); 421 int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx); 422 void hantro_mpeg2_dec_copy_qtable(u8 *qtable, 423 const struct v4l2_ctrl_mpeg2_quantisation *ctrl); 424 int hantro_mpeg2_dec_init(struct hantro_ctx *ctx); 425 void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx); 426 427 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx); 428 int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx); 429 int hantro_vp8_dec_init(struct hantro_ctx *ctx); 430 void hantro_vp8_dec_exit(struct hantro_ctx *ctx); 431 void hantro_vp8_prob_update(struct hantro_ctx *ctx, 432 const struct v4l2_ctrl_vp8_frame *hdr); 433 434 int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx); 435 void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); 436 int hantro_vp9_dec_init(struct hantro_ctx *ctx); 437 void hantro_vp9_dec_exit(struct hantro_ctx *ctx); 438 void hantro_g2_check_idle(struct hantro_dev *vpu); 439 irqreturn_t hantro_g2_irq(int irq, void *dev_id); 440 441 #endif /* HANTRO_HW_H_ */ 442