1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright 2018 Google LLC.
6  *	Tomasz Figa <tfiga@chromium.org>
7  */
8 
9 #ifndef HANTRO_HW_H_
10 #define HANTRO_HW_H_
11 
12 #include <linux/interrupt.h>
13 #include <linux/v4l2-controls.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-vp9.h>
16 #include <media/videobuf2-core.h>
17 
18 #include "rockchip_av1_entropymode.h"
19 #include "rockchip_av1_filmgrain.h"
20 
21 #define DEC_8190_ALIGN_MASK	0x07U
22 
23 #define MB_DIM			16
24 #define TILE_MB_DIM		4
25 #define MB_WIDTH(w)		DIV_ROUND_UP(w, MB_DIM)
26 #define MB_HEIGHT(h)		DIV_ROUND_UP(h, MB_DIM)
27 
28 #define FMT_MIN_WIDTH		48
29 #define FMT_MIN_HEIGHT		48
30 #define FMT_HD_WIDTH		1280
31 #define FMT_HD_HEIGHT		720
32 #define FMT_FHD_WIDTH		1920
33 #define FMT_FHD_HEIGHT		1088
34 #define FMT_UHD_WIDTH		3840
35 #define FMT_UHD_HEIGHT		2160
36 #define FMT_4K_WIDTH		4096
37 #define FMT_4K_HEIGHT		2304
38 
39 #define NUM_REF_PICTURES	(V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1)
40 
41 #define AV1_MAX_FRAME_BUF_COUNT	(V4L2_AV1_TOTAL_REFS_PER_FRAME + 1)
42 
43 struct hantro_dev;
44 struct hantro_ctx;
45 struct hantro_buf;
46 struct hantro_variant;
47 
48 /**
49  * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
50  *
51  * @cpu:	CPU pointer to the buffer.
52  * @dma:	DMA address of the buffer.
53  * @size:	Size of the buffer.
54  * @attrs:	Attributes of the DMA mapping.
55  */
56 struct hantro_aux_buf {
57 	void *cpu;
58 	dma_addr_t dma;
59 	size_t size;
60 	unsigned long attrs;
61 };
62 
63 /* Max. number of entries in the DPB (HW limitation). */
64 #define HANTRO_H264_DPB_SIZE		16
65 
66 /**
67  * struct hantro_h264_dec_ctrls
68  *
69  * @decode:	Decode params
70  * @scaling:	Scaling info
71  * @sps:	SPS info
72  * @pps:	PPS info
73  */
74 struct hantro_h264_dec_ctrls {
75 	const struct v4l2_ctrl_h264_decode_params *decode;
76 	const struct v4l2_ctrl_h264_scaling_matrix *scaling;
77 	const struct v4l2_ctrl_h264_sps *sps;
78 	const struct v4l2_ctrl_h264_pps *pps;
79 };
80 
81 /**
82  * struct hantro_h264_dec_reflists
83  *
84  * @p:		P reflist
85  * @b0:		B0 reflist
86  * @b1:		B1 reflist
87  */
88 struct hantro_h264_dec_reflists {
89 	struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN];
90 	struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN];
91 	struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN];
92 };
93 
94 /**
95  * struct hantro_h264_dec_hw_ctx
96  *
97  * @priv:	Private auxiliary buffer for hardware.
98  * @dpb:	DPB
99  * @reflists:	P/B0/B1 reflists
100  * @ctrls:	V4L2 controls attached to a run
101  * @dpb_longterm: DPB long-term
102  * @dpb_valid:	  DPB valid
103  * @cur_poc:	Current picture order count
104  */
105 struct hantro_h264_dec_hw_ctx {
106 	struct hantro_aux_buf priv;
107 	struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
108 	struct hantro_h264_dec_reflists reflists;
109 	struct hantro_h264_dec_ctrls ctrls;
110 	u32 dpb_longterm;
111 	u32 dpb_valid;
112 	s32 cur_poc;
113 };
114 
115 /**
116  * struct hantro_hevc_dec_ctrls
117  * @decode_params: Decode params
118  * @scaling:	Scaling matrix
119  * @sps:	SPS info
120  * @pps:	PPS info
121  * @hevc_hdr_skip_length: the number of data (in bits) to skip in the
122  *			  slice segment header syntax after 'slice type'
123  *			  token
124  */
125 struct hantro_hevc_dec_ctrls {
126 	const struct v4l2_ctrl_hevc_decode_params *decode_params;
127 	const struct v4l2_ctrl_hevc_scaling_matrix *scaling;
128 	const struct v4l2_ctrl_hevc_sps *sps;
129 	const struct v4l2_ctrl_hevc_pps *pps;
130 	u32 hevc_hdr_skip_length;
131 };
132 
133 /**
134  * struct hantro_hevc_dec_hw_ctx
135  * @tile_sizes:		Tile sizes buffer
136  * @tile_filter:	Tile vertical filter buffer
137  * @tile_sao:		Tile SAO buffer
138  * @tile_bsd:		Tile BSD control buffer
139  * @ref_bufs:		Internal reference buffers
140  * @scaling_lists:	Scaling lists buffer
141  * @ref_bufs_poc:	Internal reference buffers picture order count
142  * @ref_bufs_used:	Bitfield of used reference buffers
143  * @ctrls:		V4L2 controls attached to a run
144  * @num_tile_cols_allocated: number of allocated tiles
145  */
146 struct hantro_hevc_dec_hw_ctx {
147 	struct hantro_aux_buf tile_sizes;
148 	struct hantro_aux_buf tile_filter;
149 	struct hantro_aux_buf tile_sao;
150 	struct hantro_aux_buf tile_bsd;
151 	struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES];
152 	struct hantro_aux_buf scaling_lists;
153 	s32 ref_bufs_poc[NUM_REF_PICTURES];
154 	u32 ref_bufs_used;
155 	struct hantro_hevc_dec_ctrls ctrls;
156 	unsigned int num_tile_cols_allocated;
157 };
158 
159 /**
160  * struct hantro_mpeg2_dec_hw_ctx
161  *
162  * @qtable:		Quantization table
163  */
164 struct hantro_mpeg2_dec_hw_ctx {
165 	struct hantro_aux_buf qtable;
166 };
167 
168 /**
169  * struct hantro_vp8_dec_hw_ctx
170  *
171  * @segment_map:	Segment map buffer.
172  * @prob_tbl:		Probability table buffer.
173  */
174 struct hantro_vp8_dec_hw_ctx {
175 	struct hantro_aux_buf segment_map;
176 	struct hantro_aux_buf prob_tbl;
177 };
178 
179 /**
180  * struct hantro_vp9_frame_info
181  *
182  * @valid: frame info valid flag
183  * @frame_context_idx: index of frame context
184  * @reference_mode: inter prediction type
185  * @tx_mode: transform mode
186  * @interpolation_filter: filter selection for inter prediction
187  * @flags: frame flags
188  * @timestamp: frame timestamp
189  */
190 struct hantro_vp9_frame_info {
191 	u32 valid : 1;
192 	u32 frame_context_idx : 2;
193 	u32 reference_mode : 2;
194 	u32 tx_mode : 3;
195 	u32 interpolation_filter : 3;
196 	u32 flags;
197 	u64 timestamp;
198 };
199 
200 #define MAX_SB_COLS	64
201 #define MAX_SB_ROWS	34
202 
203 /**
204  * struct hantro_vp9_dec_hw_ctx
205  *
206  * @tile_edge: auxiliary DMA buffer for tile edge processing
207  * @segment_map: auxiliary DMA buffer for segment map
208  * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters
209  * @cnts: vp9 library struct for abstracting hw counters access
210  * @probability_tables: VP9 probability tables implied by the spec
211  * @frame_context: VP9 frame contexts
212  * @cur: current frame information
213  * @last: last frame information
214  * @bsd_ctrl_offset: bsd offset into tile_edge
215  * @segment_map_size: size of segment map
216  * @ctx_counters_offset: hw counters offset into misc
217  * @tile_info_offset: tile info offset into misc
218  * @tile_r_info: per-tile information array
219  * @tile_c_info: per-tile information array
220  * @last_tile_r: last number of tile rows
221  * @last_tile_c: last number of tile cols
222  * @last_sbs_r: last number of superblock rows
223  * @last_sbs_c: last number of superblock cols
224  * @active_segment: number of active segment (alternating between 0 and 1)
225  * @feature_enabled: segmentation feature enabled flags
226  * @feature_data: segmentation feature data
227  */
228 struct hantro_vp9_dec_hw_ctx {
229 	struct hantro_aux_buf tile_edge;
230 	struct hantro_aux_buf segment_map;
231 	struct hantro_aux_buf misc;
232 	struct v4l2_vp9_frame_symbol_counts cnts;
233 	struct v4l2_vp9_frame_context probability_tables;
234 	struct v4l2_vp9_frame_context frame_context[4];
235 	struct hantro_vp9_frame_info cur;
236 	struct hantro_vp9_frame_info last;
237 
238 	unsigned int bsd_ctrl_offset;
239 	unsigned int segment_map_size;
240 	unsigned int ctx_counters_offset;
241 	unsigned int tile_info_offset;
242 
243 	unsigned short tile_r_info[MAX_SB_ROWS];
244 	unsigned short tile_c_info[MAX_SB_COLS];
245 	unsigned int last_tile_r;
246 	unsigned int last_tile_c;
247 	unsigned int last_sbs_r;
248 	unsigned int last_sbs_c;
249 
250 	unsigned int active_segment;
251 	u8 feature_enabled[8];
252 	s16 feature_data[8][4];
253 };
254 
255 /**
256  * struct hantro_av1_dec_ctrls
257  * @sequence:		AV1 Sequence
258  * @tile_group_entry:	AV1 Tile Group entry
259  * @frame:		AV1 Frame Header OBU
260  * @film_grain:		AV1 Film Grain
261  */
262 struct hantro_av1_dec_ctrls {
263 	const struct v4l2_ctrl_av1_sequence *sequence;
264 	const struct v4l2_ctrl_av1_tile_group_entry *tile_group_entry;
265 	const struct v4l2_ctrl_av1_frame *frame;
266 	const struct v4l2_ctrl_av1_film_grain *film_grain;
267 };
268 
269 struct hantro_av1_frame_ref {
270 	int width;
271 	int height;
272 	int mi_cols;
273 	int mi_rows;
274 	u64 timestamp;
275 	enum v4l2_av1_frame_type frame_type;
276 	bool used;
277 	u32 order_hint;
278 	u32 order_hints[V4L2_AV1_TOTAL_REFS_PER_FRAME];
279 	struct vb2_v4l2_buffer *vb2_ref;
280 };
281 
282 /**
283  * struct hantro_av1_dec_hw_ctx
284  * @db_data_col:	db tile col data buffer
285  * @db_ctrl_col:	db tile col ctrl buffer
286  * @cdef_col:		cdef tile col buffer
287  * @sr_col:		sr tile col buffer
288  * @lr_col:		lr tile col buffer
289  * @global_model:	global model buffer
290  * @tile_info:		tile info buffer
291  * @segment:		segmentation info buffer
292  * @film_grain:		film grain buffer
293  * @prob_tbl:		probability table
294  * @prob_tbl_out:	probability table output
295  * @tile_buf:		tile buffer
296  * @ctrls:		V4L2 controls attached to a run
297  * @frame_refs:		reference frames info slots
298  * @ref_frame_sign_bias: array of sign bias
299  * @num_tile_cols_allocated: number of allocated tiles
300  * @cdfs:		current probabilities structure
301  * @cdfs_ndvc:		current mv probabilities structure
302  * @default_cdfs:	default probabilities structure
303  * @default_cdfs_ndvc:	default mv probabilties structure
304  * @cdfs_last:		stored probabilities structures
305  * @cdfs_last_ndvc:	stored mv probabilities structures
306  * @current_frame_index: index of the current in frame_refs array
307  */
308 struct hantro_av1_dec_hw_ctx {
309 	struct hantro_aux_buf db_data_col;
310 	struct hantro_aux_buf db_ctrl_col;
311 	struct hantro_aux_buf cdef_col;
312 	struct hantro_aux_buf sr_col;
313 	struct hantro_aux_buf lr_col;
314 	struct hantro_aux_buf global_model;
315 	struct hantro_aux_buf tile_info;
316 	struct hantro_aux_buf segment;
317 	struct hantro_aux_buf film_grain;
318 	struct hantro_aux_buf prob_tbl;
319 	struct hantro_aux_buf prob_tbl_out;
320 	struct hantro_aux_buf tile_buf;
321 	struct hantro_av1_dec_ctrls ctrls;
322 	struct hantro_av1_frame_ref frame_refs[AV1_MAX_FRAME_BUF_COUNT];
323 	u32 ref_frame_sign_bias[V4L2_AV1_TOTAL_REFS_PER_FRAME];
324 	unsigned int num_tile_cols_allocated;
325 	struct av1cdfs *cdfs;
326 	struct mvcdfs  *cdfs_ndvc;
327 	struct av1cdfs default_cdfs;
328 	struct mvcdfs  default_cdfs_ndvc;
329 	struct av1cdfs cdfs_last[NUM_REF_FRAMES];
330 	struct mvcdfs  cdfs_last_ndvc[NUM_REF_FRAMES];
331 	int current_frame_index;
332 };
333 /**
334  * struct hantro_postproc_ctx
335  *
336  * @dec_q:		References buffers, in decoder format.
337  */
338 struct hantro_postproc_ctx {
339 	struct hantro_aux_buf dec_q[VB2_MAX_FRAME];
340 };
341 
342 /**
343  * struct hantro_postproc_ops - post-processor operations
344  *
345  * @enable:		Enable the post-processor block. Optional.
346  * @disable:		Disable the post-processor block. Optional.
347  * @enum_framesizes:	Enumerate possible scaled output formats.
348  *			Returns zero if OK, a negative value in error cases.
349  *			Optional.
350  */
351 struct hantro_postproc_ops {
352 	void (*enable)(struct hantro_ctx *ctx);
353 	void (*disable)(struct hantro_ctx *ctx);
354 	int (*enum_framesizes)(struct hantro_ctx *ctx, struct v4l2_frmsizeenum *fsize);
355 };
356 
357 /**
358  * struct hantro_codec_ops - codec mode specific operations
359  *
360  * @init:	If needed, can be used for initialization.
361  *		Optional and called from process context.
362  * @exit:	If needed, can be used to undo the .init phase.
363  *		Optional and called from process context.
364  * @run:	Start single {en,de)coding job. Called from atomic context
365  *		to indicate that a pair of buffers is ready and the hardware
366  *		should be programmed and started. Returns zero if OK, a
367  *		negative value in error cases.
368  * @done:	Read back processing results and additional data from hardware.
369  * @reset:	Reset the hardware in case of a timeout.
370  */
371 struct hantro_codec_ops {
372 	int (*init)(struct hantro_ctx *ctx);
373 	void (*exit)(struct hantro_ctx *ctx);
374 	int (*run)(struct hantro_ctx *ctx);
375 	void (*done)(struct hantro_ctx *ctx);
376 	void (*reset)(struct hantro_ctx *ctx);
377 };
378 
379 /**
380  * enum hantro_enc_fmt - source format ID for hardware registers.
381  *
382  * @ROCKCHIP_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format
383  * @ROCKCHIP_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format
384  * @ROCKCHIP_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV)
385  * @ROCKCHIP_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY)
386  */
387 enum hantro_enc_fmt {
388 	ROCKCHIP_VPU_ENC_FMT_YUV420P = 0,
389 	ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1,
390 	ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2,
391 	ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
392 };
393 
394 extern const struct hantro_variant imx8mm_vpu_g1_variant;
395 extern const struct hantro_variant imx8mq_vpu_g1_variant;
396 extern const struct hantro_variant imx8mq_vpu_g2_variant;
397 extern const struct hantro_variant imx8mq_vpu_variant;
398 extern const struct hantro_variant px30_vpu_variant;
399 extern const struct hantro_variant rk3036_vpu_variant;
400 extern const struct hantro_variant rk3066_vpu_variant;
401 extern const struct hantro_variant rk3288_vpu_variant;
402 extern const struct hantro_variant rk3328_vpu_variant;
403 extern const struct hantro_variant rk3399_vpu_variant;
404 extern const struct hantro_variant rk3568_vepu_variant;
405 extern const struct hantro_variant rk3568_vpu_variant;
406 extern const struct hantro_variant rk3588_vpu981_variant;
407 extern const struct hantro_variant sama5d4_vdec_variant;
408 extern const struct hantro_variant sunxi_vpu_variant;
409 
410 extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
411 extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
412 extern const struct hantro_postproc_ops rockchip_vpu981_postproc_ops;
413 
414 extern const u32 hantro_vp8_dec_mc_filter[8][6];
415 
416 void hantro_watchdog(struct work_struct *work);
417 void hantro_run(struct hantro_ctx *ctx);
418 void hantro_irq_done(struct hantro_dev *vpu,
419 		     enum vb2_buffer_state result);
420 void hantro_start_prepare_run(struct hantro_ctx *ctx);
421 void hantro_end_prepare_run(struct hantro_ctx *ctx);
422 
423 irqreturn_t hantro_g1_irq(int irq, void *dev_id);
424 void hantro_g1_reset(struct hantro_ctx *ctx);
425 
426 int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
427 int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx);
428 void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx);
429 void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx);
430 
431 dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
432 				   unsigned int dpb_idx);
433 u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx,
434 			    unsigned int dpb_idx);
435 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx);
436 int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx);
437 int hantro_g1_h264_dec_run(struct hantro_ctx *ctx);
438 int hantro_h264_dec_init(struct hantro_ctx *ctx);
439 void hantro_h264_dec_exit(struct hantro_ctx *ctx);
440 
441 int hantro_hevc_dec_init(struct hantro_ctx *ctx);
442 void hantro_hevc_dec_exit(struct hantro_ctx *ctx);
443 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
444 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
445 void hantro_hevc_ref_init(struct hantro_ctx *ctx);
446 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc);
447 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr);
448 
449 int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx);
450 void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx);
451 int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx);
452 void rockchip_vpu981_av1_dec_done(struct hantro_ctx *ctx);
453 
454 static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension)
455 {
456 	return (dimension + 63) / 64;
457 }
458 
459 static inline size_t
460 hantro_vp9_mv_size(unsigned int width, unsigned int height)
461 {
462 	int num_ctbs;
463 
464 	/*
465 	 * There can be up to (CTBs x 64) number of blocks,
466 	 * and the motion vector for each block needs 16 bytes.
467 	 */
468 	num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
469 	return (num_ctbs * 64) * 16;
470 }
471 
472 static inline size_t
473 hantro_h264_mv_size(unsigned int width, unsigned int height)
474 {
475 	/*
476 	 * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
477 	 * 448 bytes per macroblock with additional 32 bytes on
478 	 * multi-core variants.
479 	 *
480 	 * The H264 decoder needs extra space on the output buffers
481 	 * to store motion vectors. This is needed for reference
482 	 * frames and only if the format is non-post-processed NV12.
483 	 *
484 	 * Memory layout is as follow:
485 	 *
486 	 * +---------------------------+
487 	 * | Y-plane   256 bytes x MBs |
488 	 * +---------------------------+
489 	 * | UV-plane  128 bytes x MBs |
490 	 * +---------------------------+
491 	 * | MV buffer  64 bytes x MBs |
492 	 * +---------------------------+
493 	 * | MC sync          32 bytes |
494 	 * +---------------------------+
495 	 */
496 	return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
497 }
498 
499 static inline size_t
500 hantro_hevc_mv_size(unsigned int width, unsigned int height)
501 {
502 	/*
503 	 * A CTB can be 64x64, 32x32 or 16x16.
504 	 * Allocated memory for the "worse" case: 16x16
505 	 */
506 	return width * height / 16;
507 }
508 
509 static inline unsigned short hantro_av1_num_sbs(unsigned short dimension)
510 {
511 	return DIV_ROUND_UP(dimension, 64);
512 }
513 
514 static inline size_t
515 hantro_av1_mv_size(unsigned int width, unsigned int height)
516 {
517 	size_t num_sbs = hantro_av1_num_sbs(width) * hantro_av1_num_sbs(height);
518 
519 	return ALIGN(num_sbs * 384, 16) * 2 + 512;
520 }
521 
522 int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
523 int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
524 void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
525 				  const struct v4l2_ctrl_mpeg2_quantisation *ctrl);
526 int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
527 void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
528 
529 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx);
530 int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx);
531 int hantro_vp8_dec_init(struct hantro_ctx *ctx);
532 void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
533 void hantro_vp8_prob_update(struct hantro_ctx *ctx,
534 			    const struct v4l2_ctrl_vp8_frame *hdr);
535 
536 int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx);
537 void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx);
538 int hantro_vp9_dec_init(struct hantro_ctx *ctx);
539 void hantro_vp9_dec_exit(struct hantro_ctx *ctx);
540 void hantro_g2_check_idle(struct hantro_dev *vpu);
541 irqreturn_t hantro_g2_irq(int irq, void *dev_id);
542 
543 #endif /* HANTRO_HW_H_ */
544