1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Collabora, Ltd.
6  * Copyright 2018 Google LLC.
7  *	Tomasz Figa <tfiga@chromium.org>
8  *
9  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
10  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/videodev2.h>
21 #include <linux/workqueue.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/videobuf2-core.h>
25 #include <media/videobuf2-vmalloc.h>
26 
27 #include "hantro_v4l2.h"
28 #include "hantro.h"
29 #include "hantro_hw.h"
30 
31 #define DRIVER_NAME "hantro-vpu"
32 
33 int hantro_debug;
34 module_param_named(debug, hantro_debug, int, 0644);
35 MODULE_PARM_DESC(debug,
36 		 "Debug level - higher value produces more verbose messages");
37 
38 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id)
39 {
40 	struct v4l2_ctrl *ctrl;
41 
42 	ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id);
43 	return ctrl ? ctrl->p_cur.p : NULL;
44 }
45 
46 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts)
47 {
48 	struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
49 	struct vb2_buffer *buf;
50 
51 	buf = vb2_find_buffer(q, ts);
52 	if (!buf)
53 		return 0;
54 	return hantro_get_dec_buf_addr(ctx, buf);
55 }
56 
57 static const struct v4l2_event hantro_eos_event = {
58 	.type = V4L2_EVENT_EOS
59 };
60 
61 static void hantro_job_finish_no_pm(struct hantro_dev *vpu,
62 				    struct hantro_ctx *ctx,
63 				    enum vb2_buffer_state result)
64 {
65 	struct vb2_v4l2_buffer *src, *dst;
66 
67 	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
68 	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
69 
70 	if (WARN_ON(!src))
71 		return;
72 	if (WARN_ON(!dst))
73 		return;
74 
75 	src->sequence = ctx->sequence_out++;
76 	dst->sequence = ctx->sequence_cap++;
77 
78 	if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) {
79 		dst->flags |= V4L2_BUF_FLAG_LAST;
80 		v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event);
81 		v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx);
82 	}
83 
84 	v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
85 					 result);
86 }
87 
88 static void hantro_job_finish(struct hantro_dev *vpu,
89 			      struct hantro_ctx *ctx,
90 			      enum vb2_buffer_state result)
91 {
92 	pm_runtime_mark_last_busy(vpu->dev);
93 	pm_runtime_put_autosuspend(vpu->dev);
94 
95 	clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
96 
97 	hantro_job_finish_no_pm(vpu, ctx, result);
98 }
99 
100 void hantro_irq_done(struct hantro_dev *vpu,
101 		     enum vb2_buffer_state result)
102 {
103 	struct hantro_ctx *ctx =
104 		v4l2_m2m_get_curr_priv(vpu->m2m_dev);
105 
106 	/*
107 	 * If cancel_delayed_work returns false
108 	 * the timeout expired. The watchdog is running,
109 	 * and will take care of finishing the job.
110 	 */
111 	if (cancel_delayed_work(&vpu->watchdog_work)) {
112 		if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done)
113 			ctx->codec_ops->done(ctx);
114 		hantro_job_finish(vpu, ctx, result);
115 	}
116 }
117 
118 void hantro_watchdog(struct work_struct *work)
119 {
120 	struct hantro_dev *vpu;
121 	struct hantro_ctx *ctx;
122 
123 	vpu = container_of(to_delayed_work(work),
124 			   struct hantro_dev, watchdog_work);
125 	ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);
126 	if (ctx) {
127 		vpu_err("frame processing timed out!\n");
128 		ctx->codec_ops->reset(ctx);
129 		hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);
130 	}
131 }
132 
133 void hantro_start_prepare_run(struct hantro_ctx *ctx)
134 {
135 	struct vb2_v4l2_buffer *src_buf;
136 
137 	src_buf = hantro_get_src_buf(ctx);
138 	v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
139 				&ctx->ctrl_handler);
140 
141 	if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) {
142 		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
143 			hantro_postproc_enable(ctx);
144 		else
145 			hantro_postproc_disable(ctx);
146 	}
147 }
148 
149 void hantro_end_prepare_run(struct hantro_ctx *ctx)
150 {
151 	struct vb2_v4l2_buffer *src_buf;
152 
153 	if (!ctx->is_encoder && ctx->dev->variant->late_postproc) {
154 		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
155 			hantro_postproc_enable(ctx);
156 		else
157 			hantro_postproc_disable(ctx);
158 	}
159 
160 	src_buf = hantro_get_src_buf(ctx);
161 	v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
162 				   &ctx->ctrl_handler);
163 
164 	/* Kick the watchdog. */
165 	schedule_delayed_work(&ctx->dev->watchdog_work,
166 			      msecs_to_jiffies(2000));
167 }
168 
169 static void device_run(void *priv)
170 {
171 	struct hantro_ctx *ctx = priv;
172 	struct vb2_v4l2_buffer *src, *dst;
173 	int ret;
174 
175 	src = hantro_get_src_buf(ctx);
176 	dst = hantro_get_dst_buf(ctx);
177 
178 	ret = pm_runtime_resume_and_get(ctx->dev->dev);
179 	if (ret < 0)
180 		goto err_cancel_job;
181 
182 	ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks);
183 	if (ret)
184 		goto err_cancel_job;
185 
186 	v4l2_m2m_buf_copy_metadata(src, dst, true);
187 
188 	if (ctx->codec_ops->run(ctx))
189 		goto err_cancel_job;
190 
191 	return;
192 
193 err_cancel_job:
194 	hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR);
195 }
196 
197 static const struct v4l2_m2m_ops vpu_m2m_ops = {
198 	.device_run = device_run,
199 };
200 
201 static int
202 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
203 {
204 	struct hantro_ctx *ctx = priv;
205 	int ret;
206 
207 	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
208 	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
209 	src_vq->drv_priv = ctx;
210 	src_vq->ops = &hantro_queue_ops;
211 	src_vq->mem_ops = &vb2_dma_contig_memops;
212 
213 	/*
214 	 * Driver does mostly sequential access, so sacrifice TLB efficiency
215 	 * for faster allocation. Also, no CPU access on the source queue,
216 	 * so no kernel mapping needed.
217 	 */
218 	src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
219 			    DMA_ATTR_NO_KERNEL_MAPPING;
220 	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
221 	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
222 	src_vq->lock = &ctx->dev->vpu_mutex;
223 	src_vq->dev = ctx->dev->v4l2_dev.dev;
224 	src_vq->supports_requests = true;
225 
226 	ret = vb2_queue_init(src_vq);
227 	if (ret)
228 		return ret;
229 
230 	dst_vq->bidirectional = true;
231 	dst_vq->mem_ops = &vb2_dma_contig_memops;
232 	dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
233 	/*
234 	 * The Kernel needs access to the JPEG destination buffer for the
235 	 * JPEG encoder to fill in the JPEG headers.
236 	 */
237 	if (!ctx->is_encoder)
238 		dst_vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
239 
240 	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
241 	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
242 	dst_vq->drv_priv = ctx;
243 	dst_vq->ops = &hantro_queue_ops;
244 	dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer);
245 	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
246 	dst_vq->lock = &ctx->dev->vpu_mutex;
247 	dst_vq->dev = ctx->dev->v4l2_dev.dev;
248 
249 	return vb2_queue_init(dst_vq);
250 }
251 
252 static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
253 {
254 	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
255 		const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
256 
257 		if (sps->chroma_format_idc > 1)
258 			/* Only 4:0:0 and 4:2:0 are supported */
259 			return -EINVAL;
260 		if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
261 			/* Luma and chroma bit depth mismatch */
262 			return -EINVAL;
263 		if (sps->bit_depth_luma_minus8 != 0)
264 			/* Only 8-bit is supported */
265 			return -EINVAL;
266 	} else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) {
267 		const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
268 
269 		if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
270 			/* Only 8-bit and 10-bit are supported */
271 			return -EINVAL;
272 	} else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {
273 		const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;
274 
275 		/* We only support profile 0 */
276 		if (dec_params->profile != 0)
277 			return -EINVAL;
278 	}
279 	return 0;
280 }
281 
282 static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
283 {
284 	struct hantro_ctx *ctx;
285 
286 	ctx = container_of(ctrl->handler,
287 			   struct hantro_ctx, ctrl_handler);
288 
289 	vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
290 
291 	switch (ctrl->id) {
292 	case V4L2_CID_JPEG_COMPRESSION_QUALITY:
293 		ctx->jpeg_quality = ctrl->val;
294 		break;
295 	default:
296 		return -EINVAL;
297 	}
298 
299 	return 0;
300 }
301 
302 static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl)
303 {
304 	struct hantro_ctx *ctx;
305 
306 	ctx = container_of(ctrl->handler,
307 			   struct hantro_ctx, ctrl_handler);
308 
309 	switch (ctrl->id) {
310 	case V4L2_CID_STATELESS_VP9_FRAME: {
311 		int bit_depth = ctrl->p_new.p_vp9_frame->bit_depth;
312 
313 		if (ctx->bit_depth == bit_depth)
314 			return 0;
315 
316 		return hantro_reset_raw_fmt(ctx, bit_depth);
317 	}
318 	default:
319 		return -EINVAL;
320 	}
321 
322 	return 0;
323 }
324 
325 static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl)
326 {
327 	struct hantro_ctx *ctx;
328 
329 	ctx = container_of(ctrl->handler,
330 			   struct hantro_ctx, ctrl_handler);
331 
332 	switch (ctrl->id) {
333 	case V4L2_CID_STATELESS_HEVC_SPS: {
334 		const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
335 		int bit_depth = sps->bit_depth_luma_minus8 + 8;
336 
337 		if (ctx->bit_depth == bit_depth)
338 			return 0;
339 
340 		return hantro_reset_raw_fmt(ctx, bit_depth);
341 	}
342 	default:
343 		return -EINVAL;
344 	}
345 
346 	return 0;
347 }
348 
349 static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
350 	.try_ctrl = hantro_try_ctrl,
351 };
352 
353 static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
354 	.s_ctrl = hantro_jpeg_s_ctrl,
355 };
356 
357 static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = {
358 	.s_ctrl = hantro_vp9_s_ctrl,
359 };
360 
361 static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = {
362 	.try_ctrl = hantro_try_ctrl,
363 	.s_ctrl = hantro_hevc_s_ctrl,
364 };
365 
366 #define HANTRO_JPEG_ACTIVE_MARKERS	(V4L2_JPEG_ACTIVE_MARKER_APP0 | \
367 					 V4L2_JPEG_ACTIVE_MARKER_COM | \
368 					 V4L2_JPEG_ACTIVE_MARKER_DQT | \
369 					 V4L2_JPEG_ACTIVE_MARKER_DHT)
370 
371 static const struct hantro_ctrl controls[] = {
372 	{
373 		.codec = HANTRO_JPEG_ENCODER,
374 		.cfg = {
375 			.id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
376 			.min = 5,
377 			.max = 100,
378 			.step = 1,
379 			.def = 50,
380 			.ops = &hantro_jpeg_ctrl_ops,
381 		},
382 	}, {
383 		.codec = HANTRO_JPEG_ENCODER,
384 		.cfg = {
385 			.id = V4L2_CID_JPEG_ACTIVE_MARKER,
386 			.max = HANTRO_JPEG_ACTIVE_MARKERS,
387 			.def = HANTRO_JPEG_ACTIVE_MARKERS,
388 			/*
389 			 * Changing the set of active markers/segments also
390 			 * messes up the alignment of the JPEG header, which
391 			 * is needed to allow the hardware to write directly
392 			 * to the output buffer. Implementing this introduces
393 			 * a lot of complexity for little gain, as the markers
394 			 * enabled is already the minimum required set.
395 			 */
396 			.flags = V4L2_CTRL_FLAG_READ_ONLY,
397 		},
398 	}, {
399 		.codec = HANTRO_MPEG2_DECODER,
400 		.cfg = {
401 			.id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
402 		},
403 	}, {
404 		.codec = HANTRO_MPEG2_DECODER,
405 		.cfg = {
406 			.id = V4L2_CID_STATELESS_MPEG2_PICTURE,
407 		},
408 	}, {
409 		.codec = HANTRO_MPEG2_DECODER,
410 		.cfg = {
411 			.id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
412 		},
413 	}, {
414 		.codec = HANTRO_VP8_DECODER,
415 		.cfg = {
416 			.id = V4L2_CID_STATELESS_VP8_FRAME,
417 		},
418 	}, {
419 		.codec = HANTRO_H264_DECODER,
420 		.cfg = {
421 			.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
422 		},
423 	}, {
424 		.codec = HANTRO_H264_DECODER,
425 		.cfg = {
426 			.id = V4L2_CID_STATELESS_H264_SPS,
427 			.ops = &hantro_ctrl_ops,
428 		},
429 	}, {
430 		.codec = HANTRO_H264_DECODER,
431 		.cfg = {
432 			.id = V4L2_CID_STATELESS_H264_PPS,
433 		},
434 	}, {
435 		.codec = HANTRO_H264_DECODER,
436 		.cfg = {
437 			.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
438 		},
439 	}, {
440 		.codec = HANTRO_H264_DECODER,
441 		.cfg = {
442 			.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
443 			.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
444 			.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
445 			.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
446 		},
447 	}, {
448 		.codec = HANTRO_H264_DECODER,
449 		.cfg = {
450 			.id = V4L2_CID_STATELESS_H264_START_CODE,
451 			.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
452 			.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
453 			.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
454 		},
455 	}, {
456 		.codec = HANTRO_H264_DECODER,
457 		.cfg = {
458 			.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
459 			.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
460 			.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
461 			.menu_skip_mask =
462 			BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
463 			.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
464 		}
465 	}, {
466 		.codec = HANTRO_HEVC_DECODER,
467 		.cfg = {
468 			.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
469 			.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
470 			.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
471 			.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
472 		},
473 	}, {
474 		.codec = HANTRO_HEVC_DECODER,
475 		.cfg = {
476 			.id = V4L2_CID_STATELESS_HEVC_START_CODE,
477 			.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
478 			.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
479 			.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
480 		},
481 	}, {
482 		.codec = HANTRO_HEVC_DECODER,
483 		.cfg = {
484 			.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
485 			.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
486 			.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
487 			.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
488 		},
489 	}, {
490 		.codec = HANTRO_HEVC_DECODER,
491 		.cfg = {
492 			.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
493 			.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
494 			.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
495 		},
496 	}, {
497 		.codec = HANTRO_HEVC_DECODER,
498 		.cfg = {
499 			.id = V4L2_CID_STATELESS_HEVC_SPS,
500 			.ops = &hantro_hevc_ctrl_ops,
501 		},
502 	}, {
503 		.codec = HANTRO_HEVC_DECODER,
504 		.cfg = {
505 			.id = V4L2_CID_STATELESS_HEVC_PPS,
506 		},
507 	}, {
508 		.codec = HANTRO_HEVC_DECODER,
509 		.cfg = {
510 			.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
511 		},
512 	}, {
513 		.codec = HANTRO_HEVC_DECODER,
514 		.cfg = {
515 			.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
516 		},
517 	}, {
518 		.codec = HANTRO_VP9_DECODER,
519 		.cfg = {
520 			.id = V4L2_CID_STATELESS_VP9_FRAME,
521 			.ops = &hantro_vp9_ctrl_ops,
522 		},
523 	}, {
524 		.codec = HANTRO_VP9_DECODER,
525 		.cfg = {
526 			.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
527 		},
528 	},
529 };
530 
531 static int hantro_ctrls_setup(struct hantro_dev *vpu,
532 			      struct hantro_ctx *ctx,
533 			      int allowed_codecs)
534 {
535 	int i, num_ctrls = ARRAY_SIZE(controls);
536 
537 	v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls);
538 
539 	for (i = 0; i < num_ctrls; i++) {
540 		if (!(allowed_codecs & controls[i].codec))
541 			continue;
542 
543 		v4l2_ctrl_new_custom(&ctx->ctrl_handler,
544 				     &controls[i].cfg, NULL);
545 		if (ctx->ctrl_handler.error) {
546 			vpu_err("Adding control (%d) failed %d\n",
547 				controls[i].cfg.id,
548 				ctx->ctrl_handler.error);
549 			v4l2_ctrl_handler_free(&ctx->ctrl_handler);
550 			return ctx->ctrl_handler.error;
551 		}
552 	}
553 	return v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
554 }
555 
556 /*
557  * V4L2 file operations.
558  */
559 
560 static int hantro_open(struct file *filp)
561 {
562 	struct hantro_dev *vpu = video_drvdata(filp);
563 	struct video_device *vdev = video_devdata(filp);
564 	struct hantro_func *func = hantro_vdev_to_func(vdev);
565 	struct hantro_ctx *ctx;
566 	int allowed_codecs, ret;
567 
568 	/*
569 	 * We do not need any extra locking here, because we operate only
570 	 * on local data here, except reading few fields from dev, which
571 	 * do not change through device's lifetime (which is guaranteed by
572 	 * reference on module from open()) and V4L2 internal objects (such
573 	 * as vdev and ctx->fh), which have proper locking done in respective
574 	 * helper functions used here.
575 	 */
576 
577 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
578 	if (!ctx)
579 		return -ENOMEM;
580 
581 	ctx->dev = vpu;
582 	if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
583 		allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;
584 		ctx->is_encoder = true;
585 	} else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
586 		allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
587 		ctx->is_encoder = false;
588 	} else {
589 		ret = -ENODEV;
590 		goto err_ctx_free;
591 	}
592 
593 	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);
594 	if (IS_ERR(ctx->fh.m2m_ctx)) {
595 		ret = PTR_ERR(ctx->fh.m2m_ctx);
596 		goto err_ctx_free;
597 	}
598 
599 	v4l2_fh_init(&ctx->fh, vdev);
600 	filp->private_data = &ctx->fh;
601 	v4l2_fh_add(&ctx->fh);
602 
603 	hantro_reset_fmts(ctx);
604 
605 	ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);
606 	if (ret) {
607 		vpu_err("Failed to set up controls\n");
608 		goto err_fh_free;
609 	}
610 	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
611 
612 	return 0;
613 
614 err_fh_free:
615 	v4l2_fh_del(&ctx->fh);
616 	v4l2_fh_exit(&ctx->fh);
617 err_ctx_free:
618 	kfree(ctx);
619 	return ret;
620 }
621 
622 static int hantro_release(struct file *filp)
623 {
624 	struct hantro_ctx *ctx =
625 		container_of(filp->private_data, struct hantro_ctx, fh);
626 
627 	/*
628 	 * No need for extra locking because this was the last reference
629 	 * to this file.
630 	 */
631 	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
632 	v4l2_fh_del(&ctx->fh);
633 	v4l2_fh_exit(&ctx->fh);
634 	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
635 	kfree(ctx);
636 
637 	return 0;
638 }
639 
640 static const struct v4l2_file_operations hantro_fops = {
641 	.owner = THIS_MODULE,
642 	.open = hantro_open,
643 	.release = hantro_release,
644 	.poll = v4l2_m2m_fop_poll,
645 	.unlocked_ioctl = video_ioctl2,
646 	.mmap = v4l2_m2m_fop_mmap,
647 };
648 
649 static const struct of_device_id of_hantro_match[] = {
650 #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP
651 	{ .compatible = "rockchip,px30-vpu",   .data = &px30_vpu_variant, },
652 	{ .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
653 	{ .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },
654 	{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
655 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
656 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
657 	{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
658 	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
659 #endif
660 #ifdef CONFIG_VIDEO_HANTRO_IMX8M
661 	{ .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
662 	{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
663 	{ .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
664 	{ .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
665 #endif
666 #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
667 	{ .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
668 #endif
669 #ifdef CONFIG_VIDEO_HANTRO_SUNXI
670 	{ .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
671 #endif
672 	{ /* sentinel */ }
673 };
674 MODULE_DEVICE_TABLE(of, of_hantro_match);
675 
676 static int hantro_register_entity(struct media_device *mdev,
677 				  struct media_entity *entity,
678 				  const char *entity_name,
679 				  struct media_pad *pads, int num_pads,
680 				  int function, struct video_device *vdev)
681 {
682 	char *name;
683 	int ret;
684 
685 	entity->obj_type = MEDIA_ENTITY_TYPE_BASE;
686 	if (function == MEDIA_ENT_F_IO_V4L) {
687 		entity->info.dev.major = VIDEO_MAJOR;
688 		entity->info.dev.minor = vdev->minor;
689 	}
690 
691 	name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name,
692 			      entity_name);
693 	if (!name)
694 		return -ENOMEM;
695 
696 	entity->name = name;
697 	entity->function = function;
698 
699 	ret = media_entity_pads_init(entity, num_pads, pads);
700 	if (ret)
701 		return ret;
702 
703 	ret = media_device_register_entity(mdev, entity);
704 	if (ret)
705 		return ret;
706 
707 	return 0;
708 }
709 
710 static int hantro_attach_func(struct hantro_dev *vpu,
711 			      struct hantro_func *func)
712 {
713 	struct media_device *mdev = &vpu->mdev;
714 	struct media_link *link;
715 	int ret;
716 
717 	/* Create the three encoder entities with their pads */
718 	func->source_pad.flags = MEDIA_PAD_FL_SOURCE;
719 	ret = hantro_register_entity(mdev, &func->vdev.entity, "source",
720 				     &func->source_pad, 1, MEDIA_ENT_F_IO_V4L,
721 				     &func->vdev);
722 	if (ret)
723 		return ret;
724 
725 	func->proc_pads[0].flags = MEDIA_PAD_FL_SINK;
726 	func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE;
727 	ret = hantro_register_entity(mdev, &func->proc, "proc",
728 				     func->proc_pads, 2, func->id,
729 				     &func->vdev);
730 	if (ret)
731 		goto err_rel_entity0;
732 
733 	func->sink_pad.flags = MEDIA_PAD_FL_SINK;
734 	ret = hantro_register_entity(mdev, &func->sink, "sink",
735 				     &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L,
736 				     &func->vdev);
737 	if (ret)
738 		goto err_rel_entity1;
739 
740 	/* Connect the three entities */
741 	ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
742 				    MEDIA_LNK_FL_IMMUTABLE |
743 				    MEDIA_LNK_FL_ENABLED);
744 	if (ret)
745 		goto err_rel_entity2;
746 
747 	ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
748 				    MEDIA_LNK_FL_IMMUTABLE |
749 				    MEDIA_LNK_FL_ENABLED);
750 	if (ret)
751 		goto err_rm_links0;
752 
753 	/* Create video interface */
754 	func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO,
755 						  0, VIDEO_MAJOR,
756 						  func->vdev.minor);
757 	if (!func->intf_devnode) {
758 		ret = -ENOMEM;
759 		goto err_rm_links1;
760 	}
761 
762 	/* Connect the two DMA engines to the interface */
763 	link = media_create_intf_link(&func->vdev.entity,
764 				      &func->intf_devnode->intf,
765 				      MEDIA_LNK_FL_IMMUTABLE |
766 				      MEDIA_LNK_FL_ENABLED);
767 	if (!link) {
768 		ret = -ENOMEM;
769 		goto err_rm_devnode;
770 	}
771 
772 	link = media_create_intf_link(&func->sink, &func->intf_devnode->intf,
773 				      MEDIA_LNK_FL_IMMUTABLE |
774 				      MEDIA_LNK_FL_ENABLED);
775 	if (!link) {
776 		ret = -ENOMEM;
777 		goto err_rm_devnode;
778 	}
779 	return 0;
780 
781 err_rm_devnode:
782 	media_devnode_remove(func->intf_devnode);
783 
784 err_rm_links1:
785 	media_entity_remove_links(&func->sink);
786 
787 err_rm_links0:
788 	media_entity_remove_links(&func->proc);
789 	media_entity_remove_links(&func->vdev.entity);
790 
791 err_rel_entity2:
792 	media_device_unregister_entity(&func->sink);
793 
794 err_rel_entity1:
795 	media_device_unregister_entity(&func->proc);
796 
797 err_rel_entity0:
798 	media_device_unregister_entity(&func->vdev.entity);
799 	return ret;
800 }
801 
802 static void hantro_detach_func(struct hantro_func *func)
803 {
804 	media_devnode_remove(func->intf_devnode);
805 	media_entity_remove_links(&func->sink);
806 	media_entity_remove_links(&func->proc);
807 	media_entity_remove_links(&func->vdev.entity);
808 	media_device_unregister_entity(&func->sink);
809 	media_device_unregister_entity(&func->proc);
810 	media_device_unregister_entity(&func->vdev.entity);
811 }
812 
813 static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)
814 {
815 	const struct of_device_id *match;
816 	struct hantro_func *func;
817 	struct video_device *vfd;
818 	int ret;
819 
820 	match = of_match_node(of_hantro_match, vpu->dev->of_node);
821 	func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);
822 	if (!func) {
823 		v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");
824 		return -ENOMEM;
825 	}
826 
827 	func->id = funcid;
828 
829 	vfd = &func->vdev;
830 	vfd->fops = &hantro_fops;
831 	vfd->release = video_device_release_empty;
832 	vfd->lock = &vpu->vpu_mutex;
833 	vfd->v4l2_dev = &vpu->v4l2_dev;
834 	vfd->vfl_dir = VFL_DIR_M2M;
835 	vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
836 	vfd->ioctl_ops = &hantro_ioctl_ops;
837 	snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible,
838 		 funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec");
839 
840 	if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
841 		vpu->encoder = func;
842 	} else {
843 		vpu->decoder = func;
844 		v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);
845 		v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);
846 	}
847 
848 	video_set_drvdata(vfd, vpu);
849 
850 	ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
851 	if (ret) {
852 		v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");
853 		return ret;
854 	}
855 
856 	ret = hantro_attach_func(vpu, func);
857 	if (ret) {
858 		v4l2_err(&vpu->v4l2_dev,
859 			 "Failed to attach functionality to the media device\n");
860 		goto err_unreg_dev;
861 	}
862 
863 	v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,
864 		  vfd->num);
865 
866 	return 0;
867 
868 err_unreg_dev:
869 	video_unregister_device(vfd);
870 	return ret;
871 }
872 
873 static int hantro_add_enc_func(struct hantro_dev *vpu)
874 {
875 	if (!vpu->variant->enc_fmts)
876 		return 0;
877 
878 	return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
879 }
880 
881 static int hantro_add_dec_func(struct hantro_dev *vpu)
882 {
883 	if (!vpu->variant->dec_fmts)
884 		return 0;
885 
886 	return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
887 }
888 
889 static void hantro_remove_func(struct hantro_dev *vpu,
890 			       unsigned int funcid)
891 {
892 	struct hantro_func *func;
893 
894 	if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
895 		func = vpu->encoder;
896 	else
897 		func = vpu->decoder;
898 
899 	if (!func)
900 		return;
901 
902 	hantro_detach_func(func);
903 	video_unregister_device(&func->vdev);
904 }
905 
906 static void hantro_remove_enc_func(struct hantro_dev *vpu)
907 {
908 	hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
909 }
910 
911 static void hantro_remove_dec_func(struct hantro_dev *vpu)
912 {
913 	hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
914 }
915 
916 static const struct media_device_ops hantro_m2m_media_ops = {
917 	.req_validate = vb2_request_validate,
918 	.req_queue = v4l2_m2m_request_queue,
919 };
920 
921 static int hantro_probe(struct platform_device *pdev)
922 {
923 	const struct of_device_id *match;
924 	struct hantro_dev *vpu;
925 	struct resource *res;
926 	int num_bases;
927 	int i, ret;
928 
929 	vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);
930 	if (!vpu)
931 		return -ENOMEM;
932 
933 	vpu->dev = &pdev->dev;
934 	vpu->pdev = pdev;
935 	mutex_init(&vpu->vpu_mutex);
936 	spin_lock_init(&vpu->irqlock);
937 
938 	match = of_match_node(of_hantro_match, pdev->dev.of_node);
939 	vpu->variant = match->data;
940 
941 	/*
942 	 * Support for nxp,imx8mq-vpu is kept for backwards compatibility
943 	 * but it's deprecated. Please update your DTS file to use
944 	 * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead.
945 	 */
946 	if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu"))
947 		dev_warn(&pdev->dev, "%s compatible is deprecated\n",
948 			 match->compatible);
949 
950 	INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
951 
952 	vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
953 				   sizeof(*vpu->clocks), GFP_KERNEL);
954 	if (!vpu->clocks)
955 		return -ENOMEM;
956 
957 	if (vpu->variant->num_clocks > 1) {
958 		for (i = 0; i < vpu->variant->num_clocks; i++)
959 			vpu->clocks[i].id = vpu->variant->clk_names[i];
960 
961 		ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,
962 					vpu->clocks);
963 		if (ret)
964 			return ret;
965 	} else {
966 		/*
967 		 * If the driver has a single clk, chances are there will be no
968 		 * actual name in the DT bindings.
969 		 */
970 		vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);
971 		if (IS_ERR(vpu->clocks[0].clk))
972 			return PTR_ERR(vpu->clocks[0].clk);
973 	}
974 
975 	vpu->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
976 	if (IS_ERR(vpu->resets))
977 		return PTR_ERR(vpu->resets);
978 
979 	num_bases = vpu->variant->num_regs ?: 1;
980 	vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
981 				      sizeof(*vpu->reg_bases), GFP_KERNEL);
982 	if (!vpu->reg_bases)
983 		return -ENOMEM;
984 
985 	for (i = 0; i < num_bases; i++) {
986 		res = vpu->variant->reg_names ?
987 		      platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM,
988 						   vpu->variant->reg_names[i]) :
989 		      platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0);
990 		vpu->reg_bases[i] = devm_ioremap_resource(vpu->dev, res);
991 		if (IS_ERR(vpu->reg_bases[i]))
992 			return PTR_ERR(vpu->reg_bases[i]);
993 	}
994 	vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
995 	vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
996 
997 	/**
998 	 * TODO: Eventually allow taking advantage of full 64-bit address space.
999 	 * Until then we assume the MSB portion of buffers' base addresses is
1000 	 * always 0 due to this masking operation.
1001 	 */
1002 	ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
1003 	if (ret) {
1004 		dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
1005 		return ret;
1006 	}
1007 	vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
1008 
1009 	for (i = 0; i < vpu->variant->num_irqs; i++) {
1010 		const char *irq_name;
1011 		int irq;
1012 
1013 		if (!vpu->variant->irqs[i].handler)
1014 			continue;
1015 
1016 		if (vpu->variant->num_irqs > 1) {
1017 			irq_name = vpu->variant->irqs[i].name;
1018 			irq = platform_get_irq_byname(vpu->pdev, irq_name);
1019 		} else {
1020 			/*
1021 			 * If the driver has a single IRQ, chances are there
1022 			 * will be no actual name in the DT bindings.
1023 			 */
1024 			irq_name = "default";
1025 			irq = platform_get_irq(vpu->pdev, 0);
1026 		}
1027 		if (irq <= 0)
1028 			return -ENXIO;
1029 
1030 		ret = devm_request_irq(vpu->dev, irq,
1031 				       vpu->variant->irqs[i].handler, 0,
1032 				       dev_name(vpu->dev), vpu);
1033 		if (ret) {
1034 			dev_err(vpu->dev, "Could not request %s IRQ.\n",
1035 				irq_name);
1036 			return ret;
1037 		}
1038 	}
1039 
1040 	if (vpu->variant->init) {
1041 		ret = vpu->variant->init(vpu);
1042 		if (ret) {
1043 			dev_err(&pdev->dev, "Failed to init VPU hardware\n");
1044 			return ret;
1045 		}
1046 	}
1047 
1048 	pm_runtime_set_autosuspend_delay(vpu->dev, 100);
1049 	pm_runtime_use_autosuspend(vpu->dev);
1050 	pm_runtime_enable(vpu->dev);
1051 
1052 	ret = reset_control_deassert(vpu->resets);
1053 	if (ret) {
1054 		dev_err(&pdev->dev, "Failed to deassert resets\n");
1055 		goto err_pm_disable;
1056 	}
1057 
1058 	ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
1059 	if (ret) {
1060 		dev_err(&pdev->dev, "Failed to prepare clocks\n");
1061 		goto err_rst_assert;
1062 	}
1063 
1064 	ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
1065 	if (ret) {
1066 		dev_err(&pdev->dev, "Failed to register v4l2 device\n");
1067 		goto err_clk_unprepare;
1068 	}
1069 	platform_set_drvdata(pdev, vpu);
1070 
1071 	vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
1072 	if (IS_ERR(vpu->m2m_dev)) {
1073 		v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");
1074 		ret = PTR_ERR(vpu->m2m_dev);
1075 		goto err_v4l2_unreg;
1076 	}
1077 
1078 	vpu->mdev.dev = vpu->dev;
1079 	strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));
1080 	media_device_init(&vpu->mdev);
1081 	vpu->mdev.ops = &hantro_m2m_media_ops;
1082 	vpu->v4l2_dev.mdev = &vpu->mdev;
1083 
1084 	ret = hantro_add_enc_func(vpu);
1085 	if (ret) {
1086 		dev_err(&pdev->dev, "Failed to register encoder\n");
1087 		goto err_m2m_rel;
1088 	}
1089 
1090 	ret = hantro_add_dec_func(vpu);
1091 	if (ret) {
1092 		dev_err(&pdev->dev, "Failed to register decoder\n");
1093 		goto err_rm_enc_func;
1094 	}
1095 
1096 	ret = media_device_register(&vpu->mdev);
1097 	if (ret) {
1098 		v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");
1099 		goto err_rm_dec_func;
1100 	}
1101 
1102 	return 0;
1103 
1104 err_rm_dec_func:
1105 	hantro_remove_dec_func(vpu);
1106 err_rm_enc_func:
1107 	hantro_remove_enc_func(vpu);
1108 err_m2m_rel:
1109 	media_device_cleanup(&vpu->mdev);
1110 	v4l2_m2m_release(vpu->m2m_dev);
1111 err_v4l2_unreg:
1112 	v4l2_device_unregister(&vpu->v4l2_dev);
1113 err_clk_unprepare:
1114 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1115 err_rst_assert:
1116 	reset_control_assert(vpu->resets);
1117 err_pm_disable:
1118 	pm_runtime_dont_use_autosuspend(vpu->dev);
1119 	pm_runtime_disable(vpu->dev);
1120 	return ret;
1121 }
1122 
1123 static void hantro_remove(struct platform_device *pdev)
1124 {
1125 	struct hantro_dev *vpu = platform_get_drvdata(pdev);
1126 
1127 	v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);
1128 
1129 	media_device_unregister(&vpu->mdev);
1130 	hantro_remove_dec_func(vpu);
1131 	hantro_remove_enc_func(vpu);
1132 	media_device_cleanup(&vpu->mdev);
1133 	v4l2_m2m_release(vpu->m2m_dev);
1134 	v4l2_device_unregister(&vpu->v4l2_dev);
1135 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1136 	reset_control_assert(vpu->resets);
1137 	pm_runtime_dont_use_autosuspend(vpu->dev);
1138 	pm_runtime_disable(vpu->dev);
1139 }
1140 
1141 #ifdef CONFIG_PM
1142 static int hantro_runtime_resume(struct device *dev)
1143 {
1144 	struct hantro_dev *vpu = dev_get_drvdata(dev);
1145 
1146 	if (vpu->variant->runtime_resume)
1147 		return vpu->variant->runtime_resume(vpu);
1148 
1149 	return 0;
1150 }
1151 #endif
1152 
1153 static const struct dev_pm_ops hantro_pm_ops = {
1154 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1155 				pm_runtime_force_resume)
1156 	SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
1157 };
1158 
1159 static struct platform_driver hantro_driver = {
1160 	.probe = hantro_probe,
1161 	.remove_new = hantro_remove,
1162 	.driver = {
1163 		   .name = DRIVER_NAME,
1164 		   .of_match_table = of_match_ptr(of_hantro_match),
1165 		   .pm = &hantro_pm_ops,
1166 	},
1167 };
1168 module_platform_driver(hantro_driver);
1169 
1170 MODULE_LICENSE("GPL v2");
1171 MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>");
1172 MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>");
1173 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
1174 MODULE_DESCRIPTION("Hantro VPU codec driver");
1175