1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Hantro VPU codec driver 4 * 5 * Copyright (C) 2018 Collabora, Ltd. 6 * Copyright 2018 Google LLC. 7 * Tomasz Figa <tfiga@chromium.org> 8 * 9 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. 10 * Copyright (C) 2011 Samsung Electronics Co., Ltd. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/videodev2.h> 21 #include <linux/workqueue.h> 22 #include <media/v4l2-event.h> 23 #include <media/v4l2-mem2mem.h> 24 #include <media/videobuf2-core.h> 25 #include <media/videobuf2-vmalloc.h> 26 27 #include "hantro_v4l2.h" 28 #include "hantro.h" 29 #include "hantro_hw.h" 30 31 #define DRIVER_NAME "hantro-vpu" 32 33 int hantro_debug; 34 module_param_named(debug, hantro_debug, int, 0644); 35 MODULE_PARM_DESC(debug, 36 "Debug level - higher value produces more verbose messages"); 37 38 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id) 39 { 40 struct v4l2_ctrl *ctrl; 41 42 ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id); 43 return ctrl ? ctrl->p_cur.p : NULL; 44 } 45 46 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts) 47 { 48 struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx); 49 struct vb2_buffer *buf; 50 51 buf = vb2_find_buffer(q, ts); 52 if (!buf) 53 return 0; 54 return hantro_get_dec_buf_addr(ctx, buf); 55 } 56 57 static const struct v4l2_event hantro_eos_event = { 58 .type = V4L2_EVENT_EOS 59 }; 60 61 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, 62 struct hantro_ctx *ctx, 63 enum vb2_buffer_state result) 64 { 65 struct vb2_v4l2_buffer *src, *dst; 66 67 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 68 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 69 70 if (WARN_ON(!src)) 71 return; 72 if (WARN_ON(!dst)) 73 return; 74 75 src->sequence = ctx->sequence_out++; 76 dst->sequence = ctx->sequence_cap++; 77 78 if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) { 79 dst->flags |= V4L2_BUF_FLAG_LAST; 80 v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event); 81 v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx); 82 } 83 84 v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, 85 result); 86 } 87 88 static void hantro_job_finish(struct hantro_dev *vpu, 89 struct hantro_ctx *ctx, 90 enum vb2_buffer_state result) 91 { 92 pm_runtime_mark_last_busy(vpu->dev); 93 pm_runtime_put_autosuspend(vpu->dev); 94 95 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); 96 97 hantro_job_finish_no_pm(vpu, ctx, result); 98 } 99 100 void hantro_irq_done(struct hantro_dev *vpu, 101 enum vb2_buffer_state result) 102 { 103 struct hantro_ctx *ctx = 104 v4l2_m2m_get_curr_priv(vpu->m2m_dev); 105 106 /* 107 * If cancel_delayed_work returns false 108 * the timeout expired. The watchdog is running, 109 * and will take care of finishing the job. 110 */ 111 if (cancel_delayed_work(&vpu->watchdog_work)) { 112 if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done) 113 ctx->codec_ops->done(ctx); 114 hantro_job_finish(vpu, ctx, result); 115 } 116 } 117 118 void hantro_watchdog(struct work_struct *work) 119 { 120 struct hantro_dev *vpu; 121 struct hantro_ctx *ctx; 122 123 vpu = container_of(to_delayed_work(work), 124 struct hantro_dev, watchdog_work); 125 ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev); 126 if (ctx) { 127 vpu_err("frame processing timed out!\n"); 128 ctx->codec_ops->reset(ctx); 129 hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR); 130 } 131 } 132 133 void hantro_start_prepare_run(struct hantro_ctx *ctx) 134 { 135 struct vb2_v4l2_buffer *src_buf; 136 137 src_buf = hantro_get_src_buf(ctx); 138 v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, 139 &ctx->ctrl_handler); 140 141 if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) { 142 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) 143 hantro_postproc_enable(ctx); 144 else 145 hantro_postproc_disable(ctx); 146 } 147 } 148 149 void hantro_end_prepare_run(struct hantro_ctx *ctx) 150 { 151 struct vb2_v4l2_buffer *src_buf; 152 153 if (!ctx->is_encoder && ctx->dev->variant->late_postproc) { 154 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) 155 hantro_postproc_enable(ctx); 156 else 157 hantro_postproc_disable(ctx); 158 } 159 160 src_buf = hantro_get_src_buf(ctx); 161 v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, 162 &ctx->ctrl_handler); 163 164 /* Kick the watchdog. */ 165 schedule_delayed_work(&ctx->dev->watchdog_work, 166 msecs_to_jiffies(2000)); 167 } 168 169 static void device_run(void *priv) 170 { 171 struct hantro_ctx *ctx = priv; 172 struct vb2_v4l2_buffer *src, *dst; 173 int ret; 174 175 src = hantro_get_src_buf(ctx); 176 dst = hantro_get_dst_buf(ctx); 177 178 ret = pm_runtime_resume_and_get(ctx->dev->dev); 179 if (ret < 0) 180 goto err_cancel_job; 181 182 ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks); 183 if (ret) 184 goto err_cancel_job; 185 186 v4l2_m2m_buf_copy_metadata(src, dst, true); 187 188 if (ctx->codec_ops->run(ctx)) 189 goto err_cancel_job; 190 191 return; 192 193 err_cancel_job: 194 hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR); 195 } 196 197 static const struct v4l2_m2m_ops vpu_m2m_ops = { 198 .device_run = device_run, 199 }; 200 201 static int 202 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 203 { 204 struct hantro_ctx *ctx = priv; 205 int ret; 206 207 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 208 src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 209 src_vq->drv_priv = ctx; 210 src_vq->ops = &hantro_queue_ops; 211 src_vq->mem_ops = &vb2_dma_contig_memops; 212 213 /* 214 * Driver does mostly sequential access, so sacrifice TLB efficiency 215 * for faster allocation. Also, no CPU access on the source queue, 216 * so no kernel mapping needed. 217 */ 218 src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | 219 DMA_ATTR_NO_KERNEL_MAPPING; 220 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 221 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 222 src_vq->lock = &ctx->dev->vpu_mutex; 223 src_vq->dev = ctx->dev->v4l2_dev.dev; 224 src_vq->supports_requests = true; 225 226 ret = vb2_queue_init(src_vq); 227 if (ret) 228 return ret; 229 230 dst_vq->bidirectional = true; 231 dst_vq->mem_ops = &vb2_dma_contig_memops; 232 dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; 233 /* 234 * The Kernel needs access to the JPEG destination buffer for the 235 * JPEG encoder to fill in the JPEG headers. 236 */ 237 if (!ctx->is_encoder) 238 dst_vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 239 240 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 241 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 242 dst_vq->drv_priv = ctx; 243 dst_vq->ops = &hantro_queue_ops; 244 dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer); 245 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 246 dst_vq->lock = &ctx->dev->vpu_mutex; 247 dst_vq->dev = ctx->dev->v4l2_dev.dev; 248 249 return vb2_queue_init(dst_vq); 250 } 251 252 static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) 253 { 254 if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { 255 const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; 256 257 if (sps->chroma_format_idc > 1) 258 /* Only 4:0:0 and 4:2:0 are supported */ 259 return -EINVAL; 260 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) 261 /* Luma and chroma bit depth mismatch */ 262 return -EINVAL; 263 if (sps->bit_depth_luma_minus8 != 0) 264 /* Only 8-bit is supported */ 265 return -EINVAL; 266 } else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) { 267 const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; 268 269 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) 270 /* Luma and chroma bit depth mismatch */ 271 return -EINVAL; 272 if (sps->bit_depth_luma_minus8 != 0) 273 /* Only 8-bit is supported */ 274 return -EINVAL; 275 } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { 276 const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; 277 278 /* We only support profile 0 */ 279 if (dec_params->profile != 0) 280 return -EINVAL; 281 } 282 return 0; 283 } 284 285 static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) 286 { 287 struct hantro_ctx *ctx; 288 289 ctx = container_of(ctrl->handler, 290 struct hantro_ctx, ctrl_handler); 291 292 vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); 293 294 switch (ctrl->id) { 295 case V4L2_CID_JPEG_COMPRESSION_QUALITY: 296 ctx->jpeg_quality = ctrl->val; 297 break; 298 default: 299 return -EINVAL; 300 } 301 302 return 0; 303 } 304 305 static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl) 306 { 307 struct hantro_ctx *ctx; 308 309 ctx = container_of(ctrl->handler, 310 struct hantro_ctx, ctrl_handler); 311 312 switch (ctrl->id) { 313 case V4L2_CID_STATELESS_VP9_FRAME: 314 ctx->bit_depth = ctrl->p_new.p_vp9_frame->bit_depth; 315 break; 316 default: 317 return -EINVAL; 318 } 319 320 return 0; 321 } 322 323 static const struct v4l2_ctrl_ops hantro_ctrl_ops = { 324 .try_ctrl = hantro_try_ctrl, 325 }; 326 327 static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { 328 .s_ctrl = hantro_jpeg_s_ctrl, 329 }; 330 331 static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = { 332 .s_ctrl = hantro_vp9_s_ctrl, 333 }; 334 335 #define HANTRO_JPEG_ACTIVE_MARKERS (V4L2_JPEG_ACTIVE_MARKER_APP0 | \ 336 V4L2_JPEG_ACTIVE_MARKER_COM | \ 337 V4L2_JPEG_ACTIVE_MARKER_DQT | \ 338 V4L2_JPEG_ACTIVE_MARKER_DHT) 339 340 static const struct hantro_ctrl controls[] = { 341 { 342 .codec = HANTRO_JPEG_ENCODER, 343 .cfg = { 344 .id = V4L2_CID_JPEG_COMPRESSION_QUALITY, 345 .min = 5, 346 .max = 100, 347 .step = 1, 348 .def = 50, 349 .ops = &hantro_jpeg_ctrl_ops, 350 }, 351 }, { 352 .codec = HANTRO_JPEG_ENCODER, 353 .cfg = { 354 .id = V4L2_CID_JPEG_ACTIVE_MARKER, 355 .max = HANTRO_JPEG_ACTIVE_MARKERS, 356 .def = HANTRO_JPEG_ACTIVE_MARKERS, 357 /* 358 * Changing the set of active markers/segments also 359 * messes up the alignment of the JPEG header, which 360 * is needed to allow the hardware to write directly 361 * to the output buffer. Implementing this introduces 362 * a lot of complexity for little gain, as the markers 363 * enabled is already the minimum required set. 364 */ 365 .flags = V4L2_CTRL_FLAG_READ_ONLY, 366 }, 367 }, { 368 .codec = HANTRO_MPEG2_DECODER, 369 .cfg = { 370 .id = V4L2_CID_STATELESS_MPEG2_SEQUENCE, 371 }, 372 }, { 373 .codec = HANTRO_MPEG2_DECODER, 374 .cfg = { 375 .id = V4L2_CID_STATELESS_MPEG2_PICTURE, 376 }, 377 }, { 378 .codec = HANTRO_MPEG2_DECODER, 379 .cfg = { 380 .id = V4L2_CID_STATELESS_MPEG2_QUANTISATION, 381 }, 382 }, { 383 .codec = HANTRO_VP8_DECODER, 384 .cfg = { 385 .id = V4L2_CID_STATELESS_VP8_FRAME, 386 }, 387 }, { 388 .codec = HANTRO_H264_DECODER, 389 .cfg = { 390 .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, 391 }, 392 }, { 393 .codec = HANTRO_H264_DECODER, 394 .cfg = { 395 .id = V4L2_CID_STATELESS_H264_SPS, 396 .ops = &hantro_ctrl_ops, 397 }, 398 }, { 399 .codec = HANTRO_H264_DECODER, 400 .cfg = { 401 .id = V4L2_CID_STATELESS_H264_PPS, 402 }, 403 }, { 404 .codec = HANTRO_H264_DECODER, 405 .cfg = { 406 .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, 407 }, 408 }, { 409 .codec = HANTRO_H264_DECODER, 410 .cfg = { 411 .id = V4L2_CID_STATELESS_H264_DECODE_MODE, 412 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 413 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 414 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 415 }, 416 }, { 417 .codec = HANTRO_H264_DECODER, 418 .cfg = { 419 .id = V4L2_CID_STATELESS_H264_START_CODE, 420 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 421 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 422 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 423 }, 424 }, { 425 .codec = HANTRO_H264_DECODER, 426 .cfg = { 427 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, 428 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 429 .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 430 .menu_skip_mask = 431 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), 432 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 433 } 434 }, { 435 .codec = HANTRO_HEVC_DECODER, 436 .cfg = { 437 .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, 438 .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 439 .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 440 .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 441 }, 442 }, { 443 .codec = HANTRO_HEVC_DECODER, 444 .cfg = { 445 .id = V4L2_CID_STATELESS_HEVC_START_CODE, 446 .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 447 .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 448 .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 449 }, 450 }, { 451 .codec = HANTRO_HEVC_DECODER, 452 .cfg = { 453 .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, 454 .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 455 .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 456 .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 457 }, 458 }, { 459 .codec = HANTRO_HEVC_DECODER, 460 .cfg = { 461 .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, 462 .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, 463 .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 464 }, 465 }, { 466 .codec = HANTRO_HEVC_DECODER, 467 .cfg = { 468 .id = V4L2_CID_STATELESS_HEVC_SPS, 469 .ops = &hantro_ctrl_ops, 470 }, 471 }, { 472 .codec = HANTRO_HEVC_DECODER, 473 .cfg = { 474 .id = V4L2_CID_STATELESS_HEVC_PPS, 475 }, 476 }, { 477 .codec = HANTRO_HEVC_DECODER, 478 .cfg = { 479 .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, 480 }, 481 }, { 482 .codec = HANTRO_HEVC_DECODER, 483 .cfg = { 484 .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, 485 }, 486 }, { 487 .codec = HANTRO_VP9_DECODER, 488 .cfg = { 489 .id = V4L2_CID_STATELESS_VP9_FRAME, 490 .ops = &hantro_vp9_ctrl_ops, 491 }, 492 }, { 493 .codec = HANTRO_VP9_DECODER, 494 .cfg = { 495 .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, 496 }, 497 }, 498 }; 499 500 static int hantro_ctrls_setup(struct hantro_dev *vpu, 501 struct hantro_ctx *ctx, 502 int allowed_codecs) 503 { 504 int i, num_ctrls = ARRAY_SIZE(controls); 505 506 v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls); 507 508 for (i = 0; i < num_ctrls; i++) { 509 if (!(allowed_codecs & controls[i].codec)) 510 continue; 511 512 v4l2_ctrl_new_custom(&ctx->ctrl_handler, 513 &controls[i].cfg, NULL); 514 if (ctx->ctrl_handler.error) { 515 vpu_err("Adding control (%d) failed %d\n", 516 controls[i].cfg.id, 517 ctx->ctrl_handler.error); 518 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 519 return ctx->ctrl_handler.error; 520 } 521 } 522 return v4l2_ctrl_handler_setup(&ctx->ctrl_handler); 523 } 524 525 /* 526 * V4L2 file operations. 527 */ 528 529 static int hantro_open(struct file *filp) 530 { 531 struct hantro_dev *vpu = video_drvdata(filp); 532 struct video_device *vdev = video_devdata(filp); 533 struct hantro_func *func = hantro_vdev_to_func(vdev); 534 struct hantro_ctx *ctx; 535 int allowed_codecs, ret; 536 537 /* 538 * We do not need any extra locking here, because we operate only 539 * on local data here, except reading few fields from dev, which 540 * do not change through device's lifetime (which is guaranteed by 541 * reference on module from open()) and V4L2 internal objects (such 542 * as vdev and ctx->fh), which have proper locking done in respective 543 * helper functions used here. 544 */ 545 546 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 547 if (!ctx) 548 return -ENOMEM; 549 550 ctx->dev = vpu; 551 if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) { 552 allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS; 553 ctx->is_encoder = true; 554 } else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) { 555 allowed_codecs = vpu->variant->codec & HANTRO_DECODERS; 556 ctx->is_encoder = false; 557 } else { 558 ret = -ENODEV; 559 goto err_ctx_free; 560 } 561 562 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init); 563 if (IS_ERR(ctx->fh.m2m_ctx)) { 564 ret = PTR_ERR(ctx->fh.m2m_ctx); 565 goto err_ctx_free; 566 } 567 568 v4l2_fh_init(&ctx->fh, vdev); 569 filp->private_data = &ctx->fh; 570 v4l2_fh_add(&ctx->fh); 571 572 hantro_reset_fmts(ctx); 573 574 ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs); 575 if (ret) { 576 vpu_err("Failed to set up controls\n"); 577 goto err_fh_free; 578 } 579 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 580 581 return 0; 582 583 err_fh_free: 584 v4l2_fh_del(&ctx->fh); 585 v4l2_fh_exit(&ctx->fh); 586 err_ctx_free: 587 kfree(ctx); 588 return ret; 589 } 590 591 static int hantro_release(struct file *filp) 592 { 593 struct hantro_ctx *ctx = 594 container_of(filp->private_data, struct hantro_ctx, fh); 595 596 /* 597 * No need for extra locking because this was the last reference 598 * to this file. 599 */ 600 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 601 v4l2_fh_del(&ctx->fh); 602 v4l2_fh_exit(&ctx->fh); 603 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 604 kfree(ctx); 605 606 return 0; 607 } 608 609 static const struct v4l2_file_operations hantro_fops = { 610 .owner = THIS_MODULE, 611 .open = hantro_open, 612 .release = hantro_release, 613 .poll = v4l2_m2m_fop_poll, 614 .unlocked_ioctl = video_ioctl2, 615 .mmap = v4l2_m2m_fop_mmap, 616 }; 617 618 static const struct of_device_id of_hantro_match[] = { 619 #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP 620 { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, }, 621 { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, }, 622 { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, }, 623 { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, 624 { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, 625 { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, 626 { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, 627 { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, 628 #endif 629 #ifdef CONFIG_VIDEO_HANTRO_IMX8M 630 { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, 631 { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, 632 { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, 633 { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, 634 #endif 635 #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 636 { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, 637 #endif 638 #ifdef CONFIG_VIDEO_HANTRO_SUNXI 639 { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, 640 #endif 641 { /* sentinel */ } 642 }; 643 MODULE_DEVICE_TABLE(of, of_hantro_match); 644 645 static int hantro_register_entity(struct media_device *mdev, 646 struct media_entity *entity, 647 const char *entity_name, 648 struct media_pad *pads, int num_pads, 649 int function, struct video_device *vdev) 650 { 651 char *name; 652 int ret; 653 654 entity->obj_type = MEDIA_ENTITY_TYPE_BASE; 655 if (function == MEDIA_ENT_F_IO_V4L) { 656 entity->info.dev.major = VIDEO_MAJOR; 657 entity->info.dev.minor = vdev->minor; 658 } 659 660 name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name, 661 entity_name); 662 if (!name) 663 return -ENOMEM; 664 665 entity->name = name; 666 entity->function = function; 667 668 ret = media_entity_pads_init(entity, num_pads, pads); 669 if (ret) 670 return ret; 671 672 ret = media_device_register_entity(mdev, entity); 673 if (ret) 674 return ret; 675 676 return 0; 677 } 678 679 static int hantro_attach_func(struct hantro_dev *vpu, 680 struct hantro_func *func) 681 { 682 struct media_device *mdev = &vpu->mdev; 683 struct media_link *link; 684 int ret; 685 686 /* Create the three encoder entities with their pads */ 687 func->source_pad.flags = MEDIA_PAD_FL_SOURCE; 688 ret = hantro_register_entity(mdev, &func->vdev.entity, "source", 689 &func->source_pad, 1, MEDIA_ENT_F_IO_V4L, 690 &func->vdev); 691 if (ret) 692 return ret; 693 694 func->proc_pads[0].flags = MEDIA_PAD_FL_SINK; 695 func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE; 696 ret = hantro_register_entity(mdev, &func->proc, "proc", 697 func->proc_pads, 2, func->id, 698 &func->vdev); 699 if (ret) 700 goto err_rel_entity0; 701 702 func->sink_pad.flags = MEDIA_PAD_FL_SINK; 703 ret = hantro_register_entity(mdev, &func->sink, "sink", 704 &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L, 705 &func->vdev); 706 if (ret) 707 goto err_rel_entity1; 708 709 /* Connect the three entities */ 710 ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0, 711 MEDIA_LNK_FL_IMMUTABLE | 712 MEDIA_LNK_FL_ENABLED); 713 if (ret) 714 goto err_rel_entity2; 715 716 ret = media_create_pad_link(&func->proc, 1, &func->sink, 0, 717 MEDIA_LNK_FL_IMMUTABLE | 718 MEDIA_LNK_FL_ENABLED); 719 if (ret) 720 goto err_rm_links0; 721 722 /* Create video interface */ 723 func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO, 724 0, VIDEO_MAJOR, 725 func->vdev.minor); 726 if (!func->intf_devnode) { 727 ret = -ENOMEM; 728 goto err_rm_links1; 729 } 730 731 /* Connect the two DMA engines to the interface */ 732 link = media_create_intf_link(&func->vdev.entity, 733 &func->intf_devnode->intf, 734 MEDIA_LNK_FL_IMMUTABLE | 735 MEDIA_LNK_FL_ENABLED); 736 if (!link) { 737 ret = -ENOMEM; 738 goto err_rm_devnode; 739 } 740 741 link = media_create_intf_link(&func->sink, &func->intf_devnode->intf, 742 MEDIA_LNK_FL_IMMUTABLE | 743 MEDIA_LNK_FL_ENABLED); 744 if (!link) { 745 ret = -ENOMEM; 746 goto err_rm_devnode; 747 } 748 return 0; 749 750 err_rm_devnode: 751 media_devnode_remove(func->intf_devnode); 752 753 err_rm_links1: 754 media_entity_remove_links(&func->sink); 755 756 err_rm_links0: 757 media_entity_remove_links(&func->proc); 758 media_entity_remove_links(&func->vdev.entity); 759 760 err_rel_entity2: 761 media_device_unregister_entity(&func->sink); 762 763 err_rel_entity1: 764 media_device_unregister_entity(&func->proc); 765 766 err_rel_entity0: 767 media_device_unregister_entity(&func->vdev.entity); 768 return ret; 769 } 770 771 static void hantro_detach_func(struct hantro_func *func) 772 { 773 media_devnode_remove(func->intf_devnode); 774 media_entity_remove_links(&func->sink); 775 media_entity_remove_links(&func->proc); 776 media_entity_remove_links(&func->vdev.entity); 777 media_device_unregister_entity(&func->sink); 778 media_device_unregister_entity(&func->proc); 779 media_device_unregister_entity(&func->vdev.entity); 780 } 781 782 static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid) 783 { 784 const struct of_device_id *match; 785 struct hantro_func *func; 786 struct video_device *vfd; 787 int ret; 788 789 match = of_match_node(of_hantro_match, vpu->dev->of_node); 790 func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL); 791 if (!func) { 792 v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n"); 793 return -ENOMEM; 794 } 795 796 func->id = funcid; 797 798 vfd = &func->vdev; 799 vfd->fops = &hantro_fops; 800 vfd->release = video_device_release_empty; 801 vfd->lock = &vpu->vpu_mutex; 802 vfd->v4l2_dev = &vpu->v4l2_dev; 803 vfd->vfl_dir = VFL_DIR_M2M; 804 vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE; 805 vfd->ioctl_ops = &hantro_ioctl_ops; 806 snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible, 807 funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec"); 808 809 if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) { 810 vpu->encoder = func; 811 } else { 812 vpu->decoder = func; 813 v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD); 814 v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD); 815 } 816 817 video_set_drvdata(vfd, vpu); 818 819 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); 820 if (ret) { 821 v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n"); 822 return ret; 823 } 824 825 ret = hantro_attach_func(vpu, func); 826 if (ret) { 827 v4l2_err(&vpu->v4l2_dev, 828 "Failed to attach functionality to the media device\n"); 829 goto err_unreg_dev; 830 } 831 832 v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name, 833 vfd->num); 834 835 return 0; 836 837 err_unreg_dev: 838 video_unregister_device(vfd); 839 return ret; 840 } 841 842 static int hantro_add_enc_func(struct hantro_dev *vpu) 843 { 844 if (!vpu->variant->enc_fmts) 845 return 0; 846 847 return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER); 848 } 849 850 static int hantro_add_dec_func(struct hantro_dev *vpu) 851 { 852 if (!vpu->variant->dec_fmts) 853 return 0; 854 855 return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER); 856 } 857 858 static void hantro_remove_func(struct hantro_dev *vpu, 859 unsigned int funcid) 860 { 861 struct hantro_func *func; 862 863 if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) 864 func = vpu->encoder; 865 else 866 func = vpu->decoder; 867 868 if (!func) 869 return; 870 871 hantro_detach_func(func); 872 video_unregister_device(&func->vdev); 873 } 874 875 static void hantro_remove_enc_func(struct hantro_dev *vpu) 876 { 877 hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER); 878 } 879 880 static void hantro_remove_dec_func(struct hantro_dev *vpu) 881 { 882 hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER); 883 } 884 885 static const struct media_device_ops hantro_m2m_media_ops = { 886 .req_validate = vb2_request_validate, 887 .req_queue = v4l2_m2m_request_queue, 888 }; 889 890 static int hantro_probe(struct platform_device *pdev) 891 { 892 const struct of_device_id *match; 893 struct hantro_dev *vpu; 894 struct resource *res; 895 int num_bases; 896 int i, ret; 897 898 vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL); 899 if (!vpu) 900 return -ENOMEM; 901 902 vpu->dev = &pdev->dev; 903 vpu->pdev = pdev; 904 mutex_init(&vpu->vpu_mutex); 905 spin_lock_init(&vpu->irqlock); 906 907 match = of_match_node(of_hantro_match, pdev->dev.of_node); 908 vpu->variant = match->data; 909 910 /* 911 * Support for nxp,imx8mq-vpu is kept for backwards compatibility 912 * but it's deprecated. Please update your DTS file to use 913 * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead. 914 */ 915 if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu")) 916 dev_warn(&pdev->dev, "%s compatible is deprecated\n", 917 match->compatible); 918 919 INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog); 920 921 vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks, 922 sizeof(*vpu->clocks), GFP_KERNEL); 923 if (!vpu->clocks) 924 return -ENOMEM; 925 926 if (vpu->variant->num_clocks > 1) { 927 for (i = 0; i < vpu->variant->num_clocks; i++) 928 vpu->clocks[i].id = vpu->variant->clk_names[i]; 929 930 ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks, 931 vpu->clocks); 932 if (ret) 933 return ret; 934 } else { 935 /* 936 * If the driver has a single clk, chances are there will be no 937 * actual name in the DT bindings. 938 */ 939 vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL); 940 if (IS_ERR(vpu->clocks[0].clk)) 941 return PTR_ERR(vpu->clocks[0].clk); 942 } 943 944 vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true); 945 if (IS_ERR(vpu->resets)) 946 return PTR_ERR(vpu->resets); 947 948 num_bases = vpu->variant->num_regs ?: 1; 949 vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases, 950 sizeof(*vpu->reg_bases), GFP_KERNEL); 951 if (!vpu->reg_bases) 952 return -ENOMEM; 953 954 for (i = 0; i < num_bases; i++) { 955 res = vpu->variant->reg_names ? 956 platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM, 957 vpu->variant->reg_names[i]) : 958 platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0); 959 vpu->reg_bases[i] = devm_ioremap_resource(vpu->dev, res); 960 if (IS_ERR(vpu->reg_bases[i])) 961 return PTR_ERR(vpu->reg_bases[i]); 962 } 963 vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; 964 vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; 965 966 /** 967 * TODO: Eventually allow taking advantage of full 64-bit address space. 968 * Until then we assume the MSB portion of buffers' base addresses is 969 * always 0 due to this masking operation. 970 */ 971 ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); 972 if (ret) { 973 dev_err(vpu->dev, "Could not set DMA coherent mask.\n"); 974 return ret; 975 } 976 vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); 977 978 for (i = 0; i < vpu->variant->num_irqs; i++) { 979 const char *irq_name; 980 int irq; 981 982 if (!vpu->variant->irqs[i].handler) 983 continue; 984 985 if (vpu->variant->num_irqs > 1) { 986 irq_name = vpu->variant->irqs[i].name; 987 irq = platform_get_irq_byname(vpu->pdev, irq_name); 988 } else { 989 /* 990 * If the driver has a single IRQ, chances are there 991 * will be no actual name in the DT bindings. 992 */ 993 irq_name = "default"; 994 irq = platform_get_irq(vpu->pdev, 0); 995 } 996 if (irq <= 0) 997 return -ENXIO; 998 999 ret = devm_request_irq(vpu->dev, irq, 1000 vpu->variant->irqs[i].handler, 0, 1001 dev_name(vpu->dev), vpu); 1002 if (ret) { 1003 dev_err(vpu->dev, "Could not request %s IRQ.\n", 1004 irq_name); 1005 return ret; 1006 } 1007 } 1008 1009 if (vpu->variant->init) { 1010 ret = vpu->variant->init(vpu); 1011 if (ret) { 1012 dev_err(&pdev->dev, "Failed to init VPU hardware\n"); 1013 return ret; 1014 } 1015 } 1016 1017 pm_runtime_set_autosuspend_delay(vpu->dev, 100); 1018 pm_runtime_use_autosuspend(vpu->dev); 1019 pm_runtime_enable(vpu->dev); 1020 1021 ret = reset_control_deassert(vpu->resets); 1022 if (ret) { 1023 dev_err(&pdev->dev, "Failed to deassert resets\n"); 1024 goto err_pm_disable; 1025 } 1026 1027 ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); 1028 if (ret) { 1029 dev_err(&pdev->dev, "Failed to prepare clocks\n"); 1030 goto err_rst_assert; 1031 } 1032 1033 ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); 1034 if (ret) { 1035 dev_err(&pdev->dev, "Failed to register v4l2 device\n"); 1036 goto err_clk_unprepare; 1037 } 1038 platform_set_drvdata(pdev, vpu); 1039 1040 vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops); 1041 if (IS_ERR(vpu->m2m_dev)) { 1042 v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n"); 1043 ret = PTR_ERR(vpu->m2m_dev); 1044 goto err_v4l2_unreg; 1045 } 1046 1047 vpu->mdev.dev = vpu->dev; 1048 strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model)); 1049 strscpy(vpu->mdev.bus_info, "platform: " DRIVER_NAME, 1050 sizeof(vpu->mdev.bus_info)); 1051 media_device_init(&vpu->mdev); 1052 vpu->mdev.ops = &hantro_m2m_media_ops; 1053 vpu->v4l2_dev.mdev = &vpu->mdev; 1054 1055 ret = hantro_add_enc_func(vpu); 1056 if (ret) { 1057 dev_err(&pdev->dev, "Failed to register encoder\n"); 1058 goto err_m2m_rel; 1059 } 1060 1061 ret = hantro_add_dec_func(vpu); 1062 if (ret) { 1063 dev_err(&pdev->dev, "Failed to register decoder\n"); 1064 goto err_rm_enc_func; 1065 } 1066 1067 ret = media_device_register(&vpu->mdev); 1068 if (ret) { 1069 v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n"); 1070 goto err_rm_dec_func; 1071 } 1072 1073 return 0; 1074 1075 err_rm_dec_func: 1076 hantro_remove_dec_func(vpu); 1077 err_rm_enc_func: 1078 hantro_remove_enc_func(vpu); 1079 err_m2m_rel: 1080 media_device_cleanup(&vpu->mdev); 1081 v4l2_m2m_release(vpu->m2m_dev); 1082 err_v4l2_unreg: 1083 v4l2_device_unregister(&vpu->v4l2_dev); 1084 err_clk_unprepare: 1085 clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); 1086 err_rst_assert: 1087 reset_control_assert(vpu->resets); 1088 err_pm_disable: 1089 pm_runtime_dont_use_autosuspend(vpu->dev); 1090 pm_runtime_disable(vpu->dev); 1091 return ret; 1092 } 1093 1094 static int hantro_remove(struct platform_device *pdev) 1095 { 1096 struct hantro_dev *vpu = platform_get_drvdata(pdev); 1097 1098 v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name); 1099 1100 media_device_unregister(&vpu->mdev); 1101 hantro_remove_dec_func(vpu); 1102 hantro_remove_enc_func(vpu); 1103 media_device_cleanup(&vpu->mdev); 1104 v4l2_m2m_release(vpu->m2m_dev); 1105 v4l2_device_unregister(&vpu->v4l2_dev); 1106 clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); 1107 reset_control_assert(vpu->resets); 1108 pm_runtime_dont_use_autosuspend(vpu->dev); 1109 pm_runtime_disable(vpu->dev); 1110 return 0; 1111 } 1112 1113 #ifdef CONFIG_PM 1114 static int hantro_runtime_resume(struct device *dev) 1115 { 1116 struct hantro_dev *vpu = dev_get_drvdata(dev); 1117 1118 if (vpu->variant->runtime_resume) 1119 return vpu->variant->runtime_resume(vpu); 1120 1121 return 0; 1122 } 1123 #endif 1124 1125 static const struct dev_pm_ops hantro_pm_ops = { 1126 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1127 pm_runtime_force_resume) 1128 SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL) 1129 }; 1130 1131 static struct platform_driver hantro_driver = { 1132 .probe = hantro_probe, 1133 .remove = hantro_remove, 1134 .driver = { 1135 .name = DRIVER_NAME, 1136 .of_match_table = of_match_ptr(of_hantro_match), 1137 .pm = &hantro_pm_ops, 1138 }, 1139 }; 1140 module_platform_driver(hantro_driver); 1141 1142 MODULE_LICENSE("GPL v2"); 1143 MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>"); 1144 MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>"); 1145 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>"); 1146 MODULE_DESCRIPTION("Hantro VPU codec driver"); 1147