1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Collabora, Ltd.
6  * Copyright 2018 Google LLC.
7  *	Tomasz Figa <tfiga@chromium.org>
8  *
9  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
10  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/videodev2.h>
21 #include <linux/workqueue.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/videobuf2-core.h>
25 #include <media/videobuf2-vmalloc.h>
26 
27 #include "hantro_v4l2.h"
28 #include "hantro.h"
29 #include "hantro_hw.h"
30 
31 #define DRIVER_NAME "hantro-vpu"
32 
33 int hantro_debug;
34 module_param_named(debug, hantro_debug, int, 0644);
35 MODULE_PARM_DESC(debug,
36 		 "Debug level - higher value produces more verbose messages");
37 
38 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id)
39 {
40 	struct v4l2_ctrl *ctrl;
41 
42 	ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id);
43 	return ctrl ? ctrl->p_cur.p : NULL;
44 }
45 
46 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts)
47 {
48 	struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
49 	struct vb2_buffer *buf;
50 
51 	buf = vb2_find_buffer(q, ts);
52 	if (!buf)
53 		return 0;
54 	return hantro_get_dec_buf_addr(ctx, buf);
55 }
56 
57 static const struct v4l2_event hantro_eos_event = {
58 	.type = V4L2_EVENT_EOS
59 };
60 
61 static void hantro_job_finish_no_pm(struct hantro_dev *vpu,
62 				    struct hantro_ctx *ctx,
63 				    enum vb2_buffer_state result)
64 {
65 	struct vb2_v4l2_buffer *src, *dst;
66 
67 	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
68 	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
69 
70 	if (WARN_ON(!src))
71 		return;
72 	if (WARN_ON(!dst))
73 		return;
74 
75 	src->sequence = ctx->sequence_out++;
76 	dst->sequence = ctx->sequence_cap++;
77 
78 	if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) {
79 		dst->flags |= V4L2_BUF_FLAG_LAST;
80 		v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event);
81 		v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx);
82 	}
83 
84 	v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
85 					 result);
86 }
87 
88 static void hantro_job_finish(struct hantro_dev *vpu,
89 			      struct hantro_ctx *ctx,
90 			      enum vb2_buffer_state result)
91 {
92 	pm_runtime_mark_last_busy(vpu->dev);
93 	pm_runtime_put_autosuspend(vpu->dev);
94 
95 	clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
96 
97 	hantro_job_finish_no_pm(vpu, ctx, result);
98 }
99 
100 void hantro_irq_done(struct hantro_dev *vpu,
101 		     enum vb2_buffer_state result)
102 {
103 	struct hantro_ctx *ctx =
104 		v4l2_m2m_get_curr_priv(vpu->m2m_dev);
105 
106 	/*
107 	 * If cancel_delayed_work returns false
108 	 * the timeout expired. The watchdog is running,
109 	 * and will take care of finishing the job.
110 	 */
111 	if (cancel_delayed_work(&vpu->watchdog_work)) {
112 		if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done)
113 			ctx->codec_ops->done(ctx);
114 		hantro_job_finish(vpu, ctx, result);
115 	}
116 }
117 
118 void hantro_watchdog(struct work_struct *work)
119 {
120 	struct hantro_dev *vpu;
121 	struct hantro_ctx *ctx;
122 
123 	vpu = container_of(to_delayed_work(work),
124 			   struct hantro_dev, watchdog_work);
125 	ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);
126 	if (ctx) {
127 		vpu_err("frame processing timed out!\n");
128 		ctx->codec_ops->reset(ctx);
129 		hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);
130 	}
131 }
132 
133 void hantro_start_prepare_run(struct hantro_ctx *ctx)
134 {
135 	struct vb2_v4l2_buffer *src_buf;
136 
137 	src_buf = hantro_get_src_buf(ctx);
138 	v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
139 				&ctx->ctrl_handler);
140 
141 	if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) {
142 		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
143 			hantro_postproc_enable(ctx);
144 		else
145 			hantro_postproc_disable(ctx);
146 	}
147 }
148 
149 void hantro_end_prepare_run(struct hantro_ctx *ctx)
150 {
151 	struct vb2_v4l2_buffer *src_buf;
152 
153 	if (!ctx->is_encoder && ctx->dev->variant->late_postproc) {
154 		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
155 			hantro_postproc_enable(ctx);
156 		else
157 			hantro_postproc_disable(ctx);
158 	}
159 
160 	src_buf = hantro_get_src_buf(ctx);
161 	v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
162 				   &ctx->ctrl_handler);
163 
164 	/* Kick the watchdog. */
165 	schedule_delayed_work(&ctx->dev->watchdog_work,
166 			      msecs_to_jiffies(2000));
167 }
168 
169 static void device_run(void *priv)
170 {
171 	struct hantro_ctx *ctx = priv;
172 	struct vb2_v4l2_buffer *src, *dst;
173 	int ret;
174 
175 	src = hantro_get_src_buf(ctx);
176 	dst = hantro_get_dst_buf(ctx);
177 
178 	ret = pm_runtime_resume_and_get(ctx->dev->dev);
179 	if (ret < 0)
180 		goto err_cancel_job;
181 
182 	ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks);
183 	if (ret)
184 		goto err_cancel_job;
185 
186 	v4l2_m2m_buf_copy_metadata(src, dst, true);
187 
188 	if (ctx->codec_ops->run(ctx))
189 		goto err_cancel_job;
190 
191 	return;
192 
193 err_cancel_job:
194 	hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR);
195 }
196 
197 static const struct v4l2_m2m_ops vpu_m2m_ops = {
198 	.device_run = device_run,
199 };
200 
201 static int
202 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
203 {
204 	struct hantro_ctx *ctx = priv;
205 	int ret;
206 
207 	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
208 	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
209 	src_vq->drv_priv = ctx;
210 	src_vq->ops = &hantro_queue_ops;
211 	src_vq->mem_ops = &vb2_dma_contig_memops;
212 
213 	/*
214 	 * Driver does mostly sequential access, so sacrifice TLB efficiency
215 	 * for faster allocation. Also, no CPU access on the source queue,
216 	 * so no kernel mapping needed.
217 	 */
218 	src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
219 			    DMA_ATTR_NO_KERNEL_MAPPING;
220 	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
221 	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
222 	src_vq->lock = &ctx->dev->vpu_mutex;
223 	src_vq->dev = ctx->dev->v4l2_dev.dev;
224 	src_vq->supports_requests = true;
225 
226 	ret = vb2_queue_init(src_vq);
227 	if (ret)
228 		return ret;
229 
230 	dst_vq->bidirectional = true;
231 	dst_vq->mem_ops = &vb2_dma_contig_memops;
232 	dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
233 	/*
234 	 * The Kernel needs access to the JPEG destination buffer for the
235 	 * JPEG encoder to fill in the JPEG headers.
236 	 */
237 	if (!ctx->is_encoder)
238 		dst_vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
239 
240 	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
241 	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
242 	dst_vq->drv_priv = ctx;
243 	dst_vq->ops = &hantro_queue_ops;
244 	dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer);
245 	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
246 	dst_vq->lock = &ctx->dev->vpu_mutex;
247 	dst_vq->dev = ctx->dev->v4l2_dev.dev;
248 
249 	return vb2_queue_init(dst_vq);
250 }
251 
252 static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
253 {
254 	struct hantro_ctx *ctx;
255 
256 	ctx = container_of(ctrl->handler,
257 			   struct hantro_ctx, ctrl_handler);
258 
259 	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
260 		const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
261 
262 		if (sps->chroma_format_idc > 1)
263 			/* Only 4:0:0 and 4:2:0 are supported */
264 			return -EINVAL;
265 		if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
266 			/* Luma and chroma bit depth mismatch */
267 			return -EINVAL;
268 		if (sps->bit_depth_luma_minus8 != 0)
269 			/* Only 8-bit is supported */
270 			return -EINVAL;
271 	} else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) {
272 		const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
273 
274 		if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
275 			/* Only 8-bit and 10-bit are supported */
276 			return -EINVAL;
277 
278 		ctx->bit_depth = sps->bit_depth_luma_minus8 + 8;
279 	} else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {
280 		const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;
281 
282 		/* We only support profile 0 */
283 		if (dec_params->profile != 0)
284 			return -EINVAL;
285 	}
286 	return 0;
287 }
288 
289 static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
290 {
291 	struct hantro_ctx *ctx;
292 
293 	ctx = container_of(ctrl->handler,
294 			   struct hantro_ctx, ctrl_handler);
295 
296 	vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
297 
298 	switch (ctrl->id) {
299 	case V4L2_CID_JPEG_COMPRESSION_QUALITY:
300 		ctx->jpeg_quality = ctrl->val;
301 		break;
302 	default:
303 		return -EINVAL;
304 	}
305 
306 	return 0;
307 }
308 
309 static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl)
310 {
311 	struct hantro_ctx *ctx;
312 
313 	ctx = container_of(ctrl->handler,
314 			   struct hantro_ctx, ctrl_handler);
315 
316 	switch (ctrl->id) {
317 	case V4L2_CID_STATELESS_VP9_FRAME:
318 		ctx->bit_depth = ctrl->p_new.p_vp9_frame->bit_depth;
319 		break;
320 	default:
321 		return -EINVAL;
322 	}
323 
324 	return 0;
325 }
326 
327 static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
328 	.try_ctrl = hantro_try_ctrl,
329 };
330 
331 static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
332 	.s_ctrl = hantro_jpeg_s_ctrl,
333 };
334 
335 static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = {
336 	.s_ctrl = hantro_vp9_s_ctrl,
337 };
338 
339 #define HANTRO_JPEG_ACTIVE_MARKERS	(V4L2_JPEG_ACTIVE_MARKER_APP0 | \
340 					 V4L2_JPEG_ACTIVE_MARKER_COM | \
341 					 V4L2_JPEG_ACTIVE_MARKER_DQT | \
342 					 V4L2_JPEG_ACTIVE_MARKER_DHT)
343 
344 static const struct hantro_ctrl controls[] = {
345 	{
346 		.codec = HANTRO_JPEG_ENCODER,
347 		.cfg = {
348 			.id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
349 			.min = 5,
350 			.max = 100,
351 			.step = 1,
352 			.def = 50,
353 			.ops = &hantro_jpeg_ctrl_ops,
354 		},
355 	}, {
356 		.codec = HANTRO_JPEG_ENCODER,
357 		.cfg = {
358 			.id = V4L2_CID_JPEG_ACTIVE_MARKER,
359 			.max = HANTRO_JPEG_ACTIVE_MARKERS,
360 			.def = HANTRO_JPEG_ACTIVE_MARKERS,
361 			/*
362 			 * Changing the set of active markers/segments also
363 			 * messes up the alignment of the JPEG header, which
364 			 * is needed to allow the hardware to write directly
365 			 * to the output buffer. Implementing this introduces
366 			 * a lot of complexity for little gain, as the markers
367 			 * enabled is already the minimum required set.
368 			 */
369 			.flags = V4L2_CTRL_FLAG_READ_ONLY,
370 		},
371 	}, {
372 		.codec = HANTRO_MPEG2_DECODER,
373 		.cfg = {
374 			.id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
375 		},
376 	}, {
377 		.codec = HANTRO_MPEG2_DECODER,
378 		.cfg = {
379 			.id = V4L2_CID_STATELESS_MPEG2_PICTURE,
380 		},
381 	}, {
382 		.codec = HANTRO_MPEG2_DECODER,
383 		.cfg = {
384 			.id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
385 		},
386 	}, {
387 		.codec = HANTRO_VP8_DECODER,
388 		.cfg = {
389 			.id = V4L2_CID_STATELESS_VP8_FRAME,
390 		},
391 	}, {
392 		.codec = HANTRO_H264_DECODER,
393 		.cfg = {
394 			.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
395 		},
396 	}, {
397 		.codec = HANTRO_H264_DECODER,
398 		.cfg = {
399 			.id = V4L2_CID_STATELESS_H264_SPS,
400 			.ops = &hantro_ctrl_ops,
401 		},
402 	}, {
403 		.codec = HANTRO_H264_DECODER,
404 		.cfg = {
405 			.id = V4L2_CID_STATELESS_H264_PPS,
406 		},
407 	}, {
408 		.codec = HANTRO_H264_DECODER,
409 		.cfg = {
410 			.id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
411 		},
412 	}, {
413 		.codec = HANTRO_H264_DECODER,
414 		.cfg = {
415 			.id = V4L2_CID_STATELESS_H264_DECODE_MODE,
416 			.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
417 			.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
418 			.max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
419 		},
420 	}, {
421 		.codec = HANTRO_H264_DECODER,
422 		.cfg = {
423 			.id = V4L2_CID_STATELESS_H264_START_CODE,
424 			.min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
425 			.def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
426 			.max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
427 		},
428 	}, {
429 		.codec = HANTRO_H264_DECODER,
430 		.cfg = {
431 			.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
432 			.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
433 			.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
434 			.menu_skip_mask =
435 			BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
436 			.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
437 		}
438 	}, {
439 		.codec = HANTRO_HEVC_DECODER,
440 		.cfg = {
441 			.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
442 			.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
443 			.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
444 			.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
445 		},
446 	}, {
447 		.codec = HANTRO_HEVC_DECODER,
448 		.cfg = {
449 			.id = V4L2_CID_STATELESS_HEVC_START_CODE,
450 			.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
451 			.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
452 			.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
453 		},
454 	}, {
455 		.codec = HANTRO_HEVC_DECODER,
456 		.cfg = {
457 			.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
458 			.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
459 			.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
460 			.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
461 		},
462 	}, {
463 		.codec = HANTRO_HEVC_DECODER,
464 		.cfg = {
465 			.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
466 			.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
467 			.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
468 		},
469 	}, {
470 		.codec = HANTRO_HEVC_DECODER,
471 		.cfg = {
472 			.id = V4L2_CID_STATELESS_HEVC_SPS,
473 			.ops = &hantro_ctrl_ops,
474 		},
475 	}, {
476 		.codec = HANTRO_HEVC_DECODER,
477 		.cfg = {
478 			.id = V4L2_CID_STATELESS_HEVC_PPS,
479 		},
480 	}, {
481 		.codec = HANTRO_HEVC_DECODER,
482 		.cfg = {
483 			.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
484 		},
485 	}, {
486 		.codec = HANTRO_HEVC_DECODER,
487 		.cfg = {
488 			.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
489 		},
490 	}, {
491 		.codec = HANTRO_VP9_DECODER,
492 		.cfg = {
493 			.id = V4L2_CID_STATELESS_VP9_FRAME,
494 			.ops = &hantro_vp9_ctrl_ops,
495 		},
496 	}, {
497 		.codec = HANTRO_VP9_DECODER,
498 		.cfg = {
499 			.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
500 		},
501 	},
502 };
503 
504 static int hantro_ctrls_setup(struct hantro_dev *vpu,
505 			      struct hantro_ctx *ctx,
506 			      int allowed_codecs)
507 {
508 	int i, num_ctrls = ARRAY_SIZE(controls);
509 
510 	v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls);
511 
512 	for (i = 0; i < num_ctrls; i++) {
513 		if (!(allowed_codecs & controls[i].codec))
514 			continue;
515 
516 		v4l2_ctrl_new_custom(&ctx->ctrl_handler,
517 				     &controls[i].cfg, NULL);
518 		if (ctx->ctrl_handler.error) {
519 			vpu_err("Adding control (%d) failed %d\n",
520 				controls[i].cfg.id,
521 				ctx->ctrl_handler.error);
522 			v4l2_ctrl_handler_free(&ctx->ctrl_handler);
523 			return ctx->ctrl_handler.error;
524 		}
525 	}
526 	return v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
527 }
528 
529 /*
530  * V4L2 file operations.
531  */
532 
533 static int hantro_open(struct file *filp)
534 {
535 	struct hantro_dev *vpu = video_drvdata(filp);
536 	struct video_device *vdev = video_devdata(filp);
537 	struct hantro_func *func = hantro_vdev_to_func(vdev);
538 	struct hantro_ctx *ctx;
539 	int allowed_codecs, ret;
540 
541 	/*
542 	 * We do not need any extra locking here, because we operate only
543 	 * on local data here, except reading few fields from dev, which
544 	 * do not change through device's lifetime (which is guaranteed by
545 	 * reference on module from open()) and V4L2 internal objects (such
546 	 * as vdev and ctx->fh), which have proper locking done in respective
547 	 * helper functions used here.
548 	 */
549 
550 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
551 	if (!ctx)
552 		return -ENOMEM;
553 
554 	ctx->dev = vpu;
555 	if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
556 		allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;
557 		ctx->is_encoder = true;
558 	} else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
559 		allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
560 		ctx->is_encoder = false;
561 	} else {
562 		ret = -ENODEV;
563 		goto err_ctx_free;
564 	}
565 
566 	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);
567 	if (IS_ERR(ctx->fh.m2m_ctx)) {
568 		ret = PTR_ERR(ctx->fh.m2m_ctx);
569 		goto err_ctx_free;
570 	}
571 
572 	v4l2_fh_init(&ctx->fh, vdev);
573 	filp->private_data = &ctx->fh;
574 	v4l2_fh_add(&ctx->fh);
575 
576 	hantro_reset_fmts(ctx);
577 
578 	ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);
579 	if (ret) {
580 		vpu_err("Failed to set up controls\n");
581 		goto err_fh_free;
582 	}
583 	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
584 
585 	return 0;
586 
587 err_fh_free:
588 	v4l2_fh_del(&ctx->fh);
589 	v4l2_fh_exit(&ctx->fh);
590 err_ctx_free:
591 	kfree(ctx);
592 	return ret;
593 }
594 
595 static int hantro_release(struct file *filp)
596 {
597 	struct hantro_ctx *ctx =
598 		container_of(filp->private_data, struct hantro_ctx, fh);
599 
600 	/*
601 	 * No need for extra locking because this was the last reference
602 	 * to this file.
603 	 */
604 	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
605 	v4l2_fh_del(&ctx->fh);
606 	v4l2_fh_exit(&ctx->fh);
607 	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
608 	kfree(ctx);
609 
610 	return 0;
611 }
612 
613 static const struct v4l2_file_operations hantro_fops = {
614 	.owner = THIS_MODULE,
615 	.open = hantro_open,
616 	.release = hantro_release,
617 	.poll = v4l2_m2m_fop_poll,
618 	.unlocked_ioctl = video_ioctl2,
619 	.mmap = v4l2_m2m_fop_mmap,
620 };
621 
622 static const struct of_device_id of_hantro_match[] = {
623 #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP
624 	{ .compatible = "rockchip,px30-vpu",   .data = &px30_vpu_variant, },
625 	{ .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
626 	{ .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },
627 	{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
628 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
629 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
630 	{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
631 	{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
632 #endif
633 #ifdef CONFIG_VIDEO_HANTRO_IMX8M
634 	{ .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
635 	{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
636 	{ .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
637 	{ .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
638 #endif
639 #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
640 	{ .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
641 #endif
642 #ifdef CONFIG_VIDEO_HANTRO_SUNXI
643 	{ .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
644 #endif
645 	{ /* sentinel */ }
646 };
647 MODULE_DEVICE_TABLE(of, of_hantro_match);
648 
649 static int hantro_register_entity(struct media_device *mdev,
650 				  struct media_entity *entity,
651 				  const char *entity_name,
652 				  struct media_pad *pads, int num_pads,
653 				  int function, struct video_device *vdev)
654 {
655 	char *name;
656 	int ret;
657 
658 	entity->obj_type = MEDIA_ENTITY_TYPE_BASE;
659 	if (function == MEDIA_ENT_F_IO_V4L) {
660 		entity->info.dev.major = VIDEO_MAJOR;
661 		entity->info.dev.minor = vdev->minor;
662 	}
663 
664 	name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name,
665 			      entity_name);
666 	if (!name)
667 		return -ENOMEM;
668 
669 	entity->name = name;
670 	entity->function = function;
671 
672 	ret = media_entity_pads_init(entity, num_pads, pads);
673 	if (ret)
674 		return ret;
675 
676 	ret = media_device_register_entity(mdev, entity);
677 	if (ret)
678 		return ret;
679 
680 	return 0;
681 }
682 
683 static int hantro_attach_func(struct hantro_dev *vpu,
684 			      struct hantro_func *func)
685 {
686 	struct media_device *mdev = &vpu->mdev;
687 	struct media_link *link;
688 	int ret;
689 
690 	/* Create the three encoder entities with their pads */
691 	func->source_pad.flags = MEDIA_PAD_FL_SOURCE;
692 	ret = hantro_register_entity(mdev, &func->vdev.entity, "source",
693 				     &func->source_pad, 1, MEDIA_ENT_F_IO_V4L,
694 				     &func->vdev);
695 	if (ret)
696 		return ret;
697 
698 	func->proc_pads[0].flags = MEDIA_PAD_FL_SINK;
699 	func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE;
700 	ret = hantro_register_entity(mdev, &func->proc, "proc",
701 				     func->proc_pads, 2, func->id,
702 				     &func->vdev);
703 	if (ret)
704 		goto err_rel_entity0;
705 
706 	func->sink_pad.flags = MEDIA_PAD_FL_SINK;
707 	ret = hantro_register_entity(mdev, &func->sink, "sink",
708 				     &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L,
709 				     &func->vdev);
710 	if (ret)
711 		goto err_rel_entity1;
712 
713 	/* Connect the three entities */
714 	ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
715 				    MEDIA_LNK_FL_IMMUTABLE |
716 				    MEDIA_LNK_FL_ENABLED);
717 	if (ret)
718 		goto err_rel_entity2;
719 
720 	ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
721 				    MEDIA_LNK_FL_IMMUTABLE |
722 				    MEDIA_LNK_FL_ENABLED);
723 	if (ret)
724 		goto err_rm_links0;
725 
726 	/* Create video interface */
727 	func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO,
728 						  0, VIDEO_MAJOR,
729 						  func->vdev.minor);
730 	if (!func->intf_devnode) {
731 		ret = -ENOMEM;
732 		goto err_rm_links1;
733 	}
734 
735 	/* Connect the two DMA engines to the interface */
736 	link = media_create_intf_link(&func->vdev.entity,
737 				      &func->intf_devnode->intf,
738 				      MEDIA_LNK_FL_IMMUTABLE |
739 				      MEDIA_LNK_FL_ENABLED);
740 	if (!link) {
741 		ret = -ENOMEM;
742 		goto err_rm_devnode;
743 	}
744 
745 	link = media_create_intf_link(&func->sink, &func->intf_devnode->intf,
746 				      MEDIA_LNK_FL_IMMUTABLE |
747 				      MEDIA_LNK_FL_ENABLED);
748 	if (!link) {
749 		ret = -ENOMEM;
750 		goto err_rm_devnode;
751 	}
752 	return 0;
753 
754 err_rm_devnode:
755 	media_devnode_remove(func->intf_devnode);
756 
757 err_rm_links1:
758 	media_entity_remove_links(&func->sink);
759 
760 err_rm_links0:
761 	media_entity_remove_links(&func->proc);
762 	media_entity_remove_links(&func->vdev.entity);
763 
764 err_rel_entity2:
765 	media_device_unregister_entity(&func->sink);
766 
767 err_rel_entity1:
768 	media_device_unregister_entity(&func->proc);
769 
770 err_rel_entity0:
771 	media_device_unregister_entity(&func->vdev.entity);
772 	return ret;
773 }
774 
775 static void hantro_detach_func(struct hantro_func *func)
776 {
777 	media_devnode_remove(func->intf_devnode);
778 	media_entity_remove_links(&func->sink);
779 	media_entity_remove_links(&func->proc);
780 	media_entity_remove_links(&func->vdev.entity);
781 	media_device_unregister_entity(&func->sink);
782 	media_device_unregister_entity(&func->proc);
783 	media_device_unregister_entity(&func->vdev.entity);
784 }
785 
786 static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)
787 {
788 	const struct of_device_id *match;
789 	struct hantro_func *func;
790 	struct video_device *vfd;
791 	int ret;
792 
793 	match = of_match_node(of_hantro_match, vpu->dev->of_node);
794 	func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);
795 	if (!func) {
796 		v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");
797 		return -ENOMEM;
798 	}
799 
800 	func->id = funcid;
801 
802 	vfd = &func->vdev;
803 	vfd->fops = &hantro_fops;
804 	vfd->release = video_device_release_empty;
805 	vfd->lock = &vpu->vpu_mutex;
806 	vfd->v4l2_dev = &vpu->v4l2_dev;
807 	vfd->vfl_dir = VFL_DIR_M2M;
808 	vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
809 	vfd->ioctl_ops = &hantro_ioctl_ops;
810 	snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible,
811 		 funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec");
812 
813 	if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
814 		vpu->encoder = func;
815 	} else {
816 		vpu->decoder = func;
817 		v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);
818 		v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);
819 	}
820 
821 	video_set_drvdata(vfd, vpu);
822 
823 	ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
824 	if (ret) {
825 		v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");
826 		return ret;
827 	}
828 
829 	ret = hantro_attach_func(vpu, func);
830 	if (ret) {
831 		v4l2_err(&vpu->v4l2_dev,
832 			 "Failed to attach functionality to the media device\n");
833 		goto err_unreg_dev;
834 	}
835 
836 	v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,
837 		  vfd->num);
838 
839 	return 0;
840 
841 err_unreg_dev:
842 	video_unregister_device(vfd);
843 	return ret;
844 }
845 
846 static int hantro_add_enc_func(struct hantro_dev *vpu)
847 {
848 	if (!vpu->variant->enc_fmts)
849 		return 0;
850 
851 	return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
852 }
853 
854 static int hantro_add_dec_func(struct hantro_dev *vpu)
855 {
856 	if (!vpu->variant->dec_fmts)
857 		return 0;
858 
859 	return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
860 }
861 
862 static void hantro_remove_func(struct hantro_dev *vpu,
863 			       unsigned int funcid)
864 {
865 	struct hantro_func *func;
866 
867 	if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
868 		func = vpu->encoder;
869 	else
870 		func = vpu->decoder;
871 
872 	if (!func)
873 		return;
874 
875 	hantro_detach_func(func);
876 	video_unregister_device(&func->vdev);
877 }
878 
879 static void hantro_remove_enc_func(struct hantro_dev *vpu)
880 {
881 	hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
882 }
883 
884 static void hantro_remove_dec_func(struct hantro_dev *vpu)
885 {
886 	hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
887 }
888 
889 static const struct media_device_ops hantro_m2m_media_ops = {
890 	.req_validate = vb2_request_validate,
891 	.req_queue = v4l2_m2m_request_queue,
892 };
893 
894 static int hantro_probe(struct platform_device *pdev)
895 {
896 	const struct of_device_id *match;
897 	struct hantro_dev *vpu;
898 	struct resource *res;
899 	int num_bases;
900 	int i, ret;
901 
902 	vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);
903 	if (!vpu)
904 		return -ENOMEM;
905 
906 	vpu->dev = &pdev->dev;
907 	vpu->pdev = pdev;
908 	mutex_init(&vpu->vpu_mutex);
909 	spin_lock_init(&vpu->irqlock);
910 
911 	match = of_match_node(of_hantro_match, pdev->dev.of_node);
912 	vpu->variant = match->data;
913 
914 	/*
915 	 * Support for nxp,imx8mq-vpu is kept for backwards compatibility
916 	 * but it's deprecated. Please update your DTS file to use
917 	 * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead.
918 	 */
919 	if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu"))
920 		dev_warn(&pdev->dev, "%s compatible is deprecated\n",
921 			 match->compatible);
922 
923 	INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
924 
925 	vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
926 				   sizeof(*vpu->clocks), GFP_KERNEL);
927 	if (!vpu->clocks)
928 		return -ENOMEM;
929 
930 	if (vpu->variant->num_clocks > 1) {
931 		for (i = 0; i < vpu->variant->num_clocks; i++)
932 			vpu->clocks[i].id = vpu->variant->clk_names[i];
933 
934 		ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,
935 					vpu->clocks);
936 		if (ret)
937 			return ret;
938 	} else {
939 		/*
940 		 * If the driver has a single clk, chances are there will be no
941 		 * actual name in the DT bindings.
942 		 */
943 		vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);
944 		if (IS_ERR(vpu->clocks[0].clk))
945 			return PTR_ERR(vpu->clocks[0].clk);
946 	}
947 
948 	vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true);
949 	if (IS_ERR(vpu->resets))
950 		return PTR_ERR(vpu->resets);
951 
952 	num_bases = vpu->variant->num_regs ?: 1;
953 	vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
954 				      sizeof(*vpu->reg_bases), GFP_KERNEL);
955 	if (!vpu->reg_bases)
956 		return -ENOMEM;
957 
958 	for (i = 0; i < num_bases; i++) {
959 		res = vpu->variant->reg_names ?
960 		      platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM,
961 						   vpu->variant->reg_names[i]) :
962 		      platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0);
963 		vpu->reg_bases[i] = devm_ioremap_resource(vpu->dev, res);
964 		if (IS_ERR(vpu->reg_bases[i]))
965 			return PTR_ERR(vpu->reg_bases[i]);
966 	}
967 	vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
968 	vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
969 
970 	/**
971 	 * TODO: Eventually allow taking advantage of full 64-bit address space.
972 	 * Until then we assume the MSB portion of buffers' base addresses is
973 	 * always 0 due to this masking operation.
974 	 */
975 	ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
976 	if (ret) {
977 		dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
978 		return ret;
979 	}
980 	vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
981 
982 	for (i = 0; i < vpu->variant->num_irqs; i++) {
983 		const char *irq_name;
984 		int irq;
985 
986 		if (!vpu->variant->irqs[i].handler)
987 			continue;
988 
989 		if (vpu->variant->num_irqs > 1) {
990 			irq_name = vpu->variant->irqs[i].name;
991 			irq = platform_get_irq_byname(vpu->pdev, irq_name);
992 		} else {
993 			/*
994 			 * If the driver has a single IRQ, chances are there
995 			 * will be no actual name in the DT bindings.
996 			 */
997 			irq_name = "default";
998 			irq = platform_get_irq(vpu->pdev, 0);
999 		}
1000 		if (irq <= 0)
1001 			return -ENXIO;
1002 
1003 		ret = devm_request_irq(vpu->dev, irq,
1004 				       vpu->variant->irqs[i].handler, 0,
1005 				       dev_name(vpu->dev), vpu);
1006 		if (ret) {
1007 			dev_err(vpu->dev, "Could not request %s IRQ.\n",
1008 				irq_name);
1009 			return ret;
1010 		}
1011 	}
1012 
1013 	if (vpu->variant->init) {
1014 		ret = vpu->variant->init(vpu);
1015 		if (ret) {
1016 			dev_err(&pdev->dev, "Failed to init VPU hardware\n");
1017 			return ret;
1018 		}
1019 	}
1020 
1021 	pm_runtime_set_autosuspend_delay(vpu->dev, 100);
1022 	pm_runtime_use_autosuspend(vpu->dev);
1023 	pm_runtime_enable(vpu->dev);
1024 
1025 	ret = reset_control_deassert(vpu->resets);
1026 	if (ret) {
1027 		dev_err(&pdev->dev, "Failed to deassert resets\n");
1028 		goto err_pm_disable;
1029 	}
1030 
1031 	ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
1032 	if (ret) {
1033 		dev_err(&pdev->dev, "Failed to prepare clocks\n");
1034 		goto err_rst_assert;
1035 	}
1036 
1037 	ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
1038 	if (ret) {
1039 		dev_err(&pdev->dev, "Failed to register v4l2 device\n");
1040 		goto err_clk_unprepare;
1041 	}
1042 	platform_set_drvdata(pdev, vpu);
1043 
1044 	vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
1045 	if (IS_ERR(vpu->m2m_dev)) {
1046 		v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");
1047 		ret = PTR_ERR(vpu->m2m_dev);
1048 		goto err_v4l2_unreg;
1049 	}
1050 
1051 	vpu->mdev.dev = vpu->dev;
1052 	strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));
1053 	strscpy(vpu->mdev.bus_info, "platform: " DRIVER_NAME,
1054 		sizeof(vpu->mdev.bus_info));
1055 	media_device_init(&vpu->mdev);
1056 	vpu->mdev.ops = &hantro_m2m_media_ops;
1057 	vpu->v4l2_dev.mdev = &vpu->mdev;
1058 
1059 	ret = hantro_add_enc_func(vpu);
1060 	if (ret) {
1061 		dev_err(&pdev->dev, "Failed to register encoder\n");
1062 		goto err_m2m_rel;
1063 	}
1064 
1065 	ret = hantro_add_dec_func(vpu);
1066 	if (ret) {
1067 		dev_err(&pdev->dev, "Failed to register decoder\n");
1068 		goto err_rm_enc_func;
1069 	}
1070 
1071 	ret = media_device_register(&vpu->mdev);
1072 	if (ret) {
1073 		v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");
1074 		goto err_rm_dec_func;
1075 	}
1076 
1077 	return 0;
1078 
1079 err_rm_dec_func:
1080 	hantro_remove_dec_func(vpu);
1081 err_rm_enc_func:
1082 	hantro_remove_enc_func(vpu);
1083 err_m2m_rel:
1084 	media_device_cleanup(&vpu->mdev);
1085 	v4l2_m2m_release(vpu->m2m_dev);
1086 err_v4l2_unreg:
1087 	v4l2_device_unregister(&vpu->v4l2_dev);
1088 err_clk_unprepare:
1089 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1090 err_rst_assert:
1091 	reset_control_assert(vpu->resets);
1092 err_pm_disable:
1093 	pm_runtime_dont_use_autosuspend(vpu->dev);
1094 	pm_runtime_disable(vpu->dev);
1095 	return ret;
1096 }
1097 
1098 static int hantro_remove(struct platform_device *pdev)
1099 {
1100 	struct hantro_dev *vpu = platform_get_drvdata(pdev);
1101 
1102 	v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);
1103 
1104 	media_device_unregister(&vpu->mdev);
1105 	hantro_remove_dec_func(vpu);
1106 	hantro_remove_enc_func(vpu);
1107 	media_device_cleanup(&vpu->mdev);
1108 	v4l2_m2m_release(vpu->m2m_dev);
1109 	v4l2_device_unregister(&vpu->v4l2_dev);
1110 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1111 	reset_control_assert(vpu->resets);
1112 	pm_runtime_dont_use_autosuspend(vpu->dev);
1113 	pm_runtime_disable(vpu->dev);
1114 	return 0;
1115 }
1116 
1117 #ifdef CONFIG_PM
1118 static int hantro_runtime_resume(struct device *dev)
1119 {
1120 	struct hantro_dev *vpu = dev_get_drvdata(dev);
1121 
1122 	if (vpu->variant->runtime_resume)
1123 		return vpu->variant->runtime_resume(vpu);
1124 
1125 	return 0;
1126 }
1127 #endif
1128 
1129 static const struct dev_pm_ops hantro_pm_ops = {
1130 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1131 				pm_runtime_force_resume)
1132 	SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
1133 };
1134 
1135 static struct platform_driver hantro_driver = {
1136 	.probe = hantro_probe,
1137 	.remove = hantro_remove,
1138 	.driver = {
1139 		   .name = DRIVER_NAME,
1140 		   .of_match_table = of_match_ptr(of_hantro_match),
1141 		   .pm = &hantro_pm_ops,
1142 	},
1143 };
1144 module_platform_driver(hantro_driver);
1145 
1146 MODULE_LICENSE("GPL v2");
1147 MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>");
1148 MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>");
1149 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
1150 MODULE_DESCRIPTION("Hantro VPU codec driver");
1151